5
13
12
16
15
1
2
3
KFF
RT
BP5
SGND
VIN
HDRV
SW
BP10
4SYNC
11
ILIM
TPS4005xPWP
6SS/SD
7VFB
8COMP
14BOOST
LDRV 10
PGND 9
VIN
VO
+
–
+
–
UDG-03179
8
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS40054,TPS40055,TPS40057
1FEATURES CONTENTS
2• Operating Input Voltage 8 V to 40 V Device Ratings 2
• Input Voltage Feed-Forward Compensation Electrical Characteristics 3
• < 1 % Internal 0.7-V Reference Pin Descriptions 5
• Programmable Fixed-Frequency Up to 1-MHz
Voltage Mode Controller Application Information 7
• Internal Gate Drive Outputs for High-Side and Design Examples 22
Synchronous N-Channel MOSFETs Additional References 27
• 16-Pin PowerPAD™ Package (θJC = 2°C/W)
• Thermal Shutdown DESCRIPTION
The TPS4005x is a family of high-voltage, wide input
• Externally Synchronizable (8 V to 40 V), synchronous, step-down controllers.
• Programmable High-Side Sense Short-Circuit The TPS4005x family offers design flexibility with a
Protection variety of user-programmable functions, including
• Programmable Closed-Loop Soft-Start soft-start, UVLO, operating frequency, voltage feed-
forward, high-side current limit, and loop
• TPS40054 Source Only compensation.
• TPS40055 Source/Sink The TPS4005x uses voltage feed-forward control
• TPS40057 Source/Sink With VOPrebias techniques to provide good line regulation over the
wide (4:1) input voltage range, and fast response to
APPLICATIONS input line transients. Near-constant modulator gain
• Power Modules with input variation eases loop compensation. The
externally programmable current limit provides pulse-
• Networking/Telecom by-pulse current limit, as well as hiccup mode
• Industrial/Servers operation utilizing an internal fault counter for longer
duration overloads.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAPACKAGE APPLICATION OUTPUT SUPPLY MINIMUM QUANTITY DEVICE NUMBER
Tube 90 TPS40054PWP
Source Tape and Reel 2000 TPS40054PWPR
Tube 90 TPS40055PWP
Plastic HTSSOP
–40°C to 85°C Source/Sink
(PWP) Tape and Reel 2000 TPS40055PWPR
Tube 90 TPS40057PWP
Source/Sink with
prebias Tape and Reel 2000 TPS40057PWPR
DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS40054
TPS40055 UNIT
TPS40057
VFB, SS/SD, SYNC –0.3 to 6
VIN, SW –0.3 to 45
VIN Input voltage range SW, transient < 50 ns –2.5
SW, transient < 50 ns, VVIN < 14 V –5.0
KFF, with IIN(max) = – 5 mA –0.3 to 11
COMP, RT, SS/SD –0.3 to 6
Output voltage
VOrange KFF 5 mA
IOOutput current RT 200 µA
TJMaximum junction temperature (2) 150
TJOperating junction temperature range –40 to 125 °C
Tstg Storage temperature –55 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Device may shut down at junction temperatures below 150°C
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
VIN Input voltage 8 40 V
TAOperating free-air temperature –40 85 °C
THERMAL INFORMATION THERMAL METRIC(1) PWP (20 PINS) UNITS
θJA Junction-to-ambient thermal resistance 38.3
θJCtop Junction-to-case (top) thermal resistance 28.0
θJB Junction-to-board thermal resistance 9.0 °C/W
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 8.9
θJCbot Junction-to-case (bottom) thermal resistance 2.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
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SLUS593H –DECEMBER 2003–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS
TA= –40°C to 85°C, VIN = 24 Vdc, RT= 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage range, VIN 8 40 V
OPERATING CURRENT
IDD Quiescent current Output drivers not switching, VFB ≥0.75 V 1.5 3.0 mA
BP5
VBP5 Output voltage IO≤1 mA 4.7 5.0 5.2 V
OSCILLATOR/RAMP GENERATOR
fOSC Accuracy 8 V ≤VIN ≤40 V 470 520 570 kHz
VRAMP PWM ramp voltage(1) VPEAK – VVAL 2.0 V
VIH High-level input voltage, SYNC 2
VIL Low-level input voltage, SYNC 0.8 V
ISYNC Input current, SYNC 5 10 µA
Pulse width, SYNC 50 ns
VRT RT voltage 2.38 2.50 2.58 V
VFB = 0 V, fSW ≤500 kHz 85% 94%
DMAX Maximum duty cycle VFB = 0 V, 500 kHz ≤fSW ≤1 MHz(1) 80%
Minumum duty cycle VFB ≥0.75 V 0%
VKFF Feed-forward voltage 3.35 3.48 3.65 V
IKFF Feed-forward current operating range(1) (2) 20 1100 µA
SOFT START
ISS/SD Soft-start source current 1.65 2.35 2.95 µA
VSS/SD Soft-start clamp voltage 3.7 V
tDSCH Discharge time CSS/SD = 220 pF 1.6 2.2 2.8 µs
tSS/SD Soft-start time CSS/SD = 220 pF, 0 V ≤VSS/SD ≤1.6 V 115 150 215
BP10
VBP10 Output voltage IO≤1 mA 9.0 9.6 10.3 V
ERROR AMPLIFIER
8 V ≤VIN ≤40 V, TA= 25°C 0.698 0.700 0.704
VFB Feedback input voltage 8 V ≤VIN ≤40 V, 0°C ≤TA≤85°C 0.693 0.700 0.707 V
8 V ≤VIN ≤40 V, -40°C≤TA≤85°C 0.693 0.700 0.715
GBW Gain bandwidth(1) 3.0 5.0 MHz
AVOL Open loop gain 60 80 dB
IOH High-level output source current 2.0 4.0 mA
IOL Low-level output sink current 2.0 4.0
VOH High-level output voltage ISOURCE = 500 µA 3.2 3.5 V
VOL Low-level output voltage ISINK = 500 µA 0.20 0.35
IBIAS Input bias current VFB = 0.7 V 100 200 nA
(1) Ensured by design. Not production tested.
(2) IKFF increases with SYNC frequency, maximum duty cycle decreases with IKFF.
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ELECTRICAL CHARACTERISTICS (continued)
TA= –40°C to 85°C, VIN = 24 Vdc, RT= 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
ISINK Current limit sink current 8.5 10.0 11.5 µA
VILIM = 23.7 V, VSW = (VILIM – 0.5 V) 300
Propagation delay to output VILIM = 23.7 V, VSW = (VILIM – 2 V) 200 ns
tON Switch leading-edge blanking pulse time(3) 100
tOFF Off time during a fault (soft-start cycle time) 7 cycles
TA= 25°C –90 –70 –50
VOS Offset voltage SW vs. ILIM VILIM = 23.6 V, 0°C ≤TA≤85°C –120 –38 mV
VILIM = 23.6 V, -40°C ≤TA≤85°C –120 –20
OUTPUT DRIVER
tLRISE Low-side driver rise time 48 96
CLOAD = 2200 pF
tLFALL Low-side driver fall time 24 48 ns
tHRISE High-side driver rise time 48 96
CLOAD = 2200 pF (HDRV – SW)
tHFALL High-side driver fall time 36 72
VBOOST VBOOST
VOH High-level ouput voltage, HDRV IHDRV = –0.1 A (HDRV – SW) –1.5 V –1.0 V
VOL Low-level ouput voltage, HDRV IHDRV = 0.1 A (HDRV – SW) 0.75 V
VBP10 VBP10
VOH High-level ouput voltage, LDRV ILDRV = –0.1 A –1.4 V – 1.0 V
VOL Low-level ouput voltage, LDRV ILDRV = 0.1 A 0.5
Minimum controllable pulse width 100 150 ns
SS/SD SHUTDOWN
VSD Shutdown threshold voltage Outputs off 90 125 160 mV
VEN Device active threshold voltage 190 210 245
BOOST REGULATOR
VBOOST Output voltage VIN= 24.0 V 31.2 32.2 33.5 V
RECTIFIER ZERO CURRENT COMPARATOR (TPS40054 ONLY)
VSW Switch voltage LDRV output OFF –10 –5 0 mV
SW NODE
ILEAK Leakage current(3) (out of pin) 25 µA
THERMAL SHUTDOWN
Shutdown temperature(3) 165
TSD °C
Hysteresis(3) 20
UVLO
VUVLO KFF programmable threshold voltage RKFF = 28.7 kΩ6.95 7.50 7.95
VDD UVLO, fixed 7.2 7.5 7.9 V
VDD UVLO, hysteresis 0.46
(3) Ensured by design. Not production tested.
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ILIM
VIN
BOOST
HDRV
SW
BP10
LDRV
PGND
KFF
RT
BP5
SYNC
SGND
SS/SD
VFB
COMP
Thermal Pad
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
Table 1. PIN DESCRIPTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the SW voltage. A
BOOST 14 O 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.
5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an
BP5 3 O external DC load of 1 mA or less.
10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
BP10 11 O ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the VFB
COMP 8 O pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to improve large
signal transient response.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
HDRV 13 O (MOSFET off).
Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a voltage
ILIM 16 I drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to the voltage
drop (VIN – SW) across the high-side MOSFET during conduction.
A resistor is connected from this pin to VIN to program the amount of voltage feed-forward and UVLO level. The
KFF 1 I current fed into this pin is internally divided and used to control the slope of the PWM ramp.
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground (MOSFET
LDRV 10 O off).
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the
PGND 9 lower MOSFET(s).
RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
SGND 5 Signal ground reference for the device.
Soft-start programming and shutdown pin. A capacitor connected from this pin to ground programs the soft-start time.
The capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS/SD pin is
used as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is
SS/SD 6 I approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately 1.55 V. The
controller is considered shut down when VSS/SD is 125 mV or less. The internal circuitry is enabled when VSS/SD is 210
mV or greater. When VSS/SD is less than approximately 0.85 V, the outputs cease switching and the output voltage
(VO) decays while the internal circuitry remains active.
This pin is connected to the switched node of the converter and used for overcurrent sensing. The TPS40054 also
SW 12 I uses this pin for zero current sensing.
Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master frequency.
SYNC 4 I If synchronization is not used, connect this pin to SGND.
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
VFB 7 I voltage, 0.7 V.
VIN 15 I Supply voltage for the device.
PWP PACKAGE (TOP VIEW)
A. For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.
B. PowerPAD™ heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
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1
2
Ramp Generator
13
10
14
N-channel
Driver
12
9
1115
4
5
BP10
BP10
7
16
3-bit up/down
Fault Counter
7
Fault
CLK
7CLK
3 7
BP5
7
Restart
7
7
Fault
CL
S Q
QR
7CLK
CL
SW
7SW
S Q
QR
7
HDRV
LDRV
PGND
BOOST
BP10
VIN
SYNC
RT
KFF
BP5
VFB
ILIM
SGND
Zero Current Detector
(TPS40054 Only)
N-channel
Driver
10V Regulator
71V5REF
7+
6
07VREF
7
7
Restart
SS/SD
8COMP
+
Overtemperature
+
Soft Start
CLK
Oscillator
7
7
7
07VREF
1V5REF
3V5REF
Reference
Voltages
7
BP5
UDG-08118
tSTART
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
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SIMPLIFIED BLOCK DIAGRAM
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( ) ( )
KFF IN(min) KFF T
R V V 58.14 R 1340= - ´ ´ + W
VPEAK
VVALLEY
tON1 > tON2 and D1> D2
t2
tON2
t1
tON1
VIN
RAMP
COMP
SW
D =
tON
tUDG-08119
RT+ǒ1
fSW 17.82 10*6*17ǓkW
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
APPLICATION INFORMATION
The TPS40054/55/57 family of devices allows the user to optimize the PWM controller to the specific application.
The TPS40057 is safe for pre-biased outputs, not turning on the synchronous rectifier until the high-side FET has
already started switching.
The TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters
and ensures that one converter does not sink current from another converter. This controller also emulates a
non-synchronous buck converter at light loads where the inductor current goes discontinuous. At continuous
output inductor currents the controller operates as a synchronous buck converter to optimize efficiency.
The TPS40055 operates in two quadrants, sourcing and sinking output current.
SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)
The TPS4005x has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
master clock to the ramp generator circuit. The switching frequency, fSW in kHz, of the clock oscillator is set by a
single resistor (RT) to ground. The clock frequency is related to RT, in kΩby Equation 1 and the relationship is
charted in Figure 2.
(1)
PROGRAMMING THE RAMP GENERATOR CIRCUIT
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).
Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle
The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (RKFF) pulled up to VIN. RKFF is related to RT, and the
minimum input voltage, VIN(min) through the following:
where
• VIN(min) is the ensured minimum start-up voltage (the actual start-up voltage is nominally about 10% lower at
25°C)
• RTis the timing resistance in kΩ
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100
0
200
300
400
500
600
200 400 600 800 1000100
700
300 500 700 900
FEED-FORWARD IMPEDANCE
vs
SWITCHING FREQUENCY
RKFF - Feed-Forward Impedance - kΩ
fSW - Switching Frequency - kHz
VIN = 25 V
VIN = 15 V
VIN = 9 V
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
www.ti.com
• VKFF is the voltage at the KFF pin (typical value is 3.48 V) (2)
The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 3.
For low-input voltage and high duty-cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltage. For more information on large duty cycle operation, refer to Application Note
(SLUA310), Effect of Programmable UVLO on Maximum Duty Cycle.
Figure 2. Figure 3.
UVLO OPERATION
The TPS4005x uses variable (user-programmable) UVLO protection. See the Programming the Ramp Generator
section for more information on setting the UVLO voltage. The UVLO circuit holds the soft-start low until the input
voltage has exceeded the user-programmable undervoltage threshold.
The TPS4005x uses the feed-forward pin, KFF, as a user-programmable low-line UVLO detection. This variable
low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An undervoltage
condition exists if the TPS4005x receives a clock pulse before the ramp has reached 90% of its full amplitude.
The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF pin. The
KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF resistor
can be referenced to the oscillator frequency as descibed in Equation 2.
The programmable UVLO function uses a three-bit counter to prevent spurious shut-downs or turn-ons due to
spikes or fast line transients. When the counter reaches a total of seven counts in which the ramp duration is
shorter than the clock cycle, a powergood signal is asserted and a soft-start initiated, and the upper and lower
MOSFETS are turned off.
Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).
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10
0.2
0
2015 25 30 4035
0.4
1.0
0.8
1.2
0.6
VUVLO – Undervoltage Lockout Threshold – V
VUVLO – Hysteresis – V
UDG-02132
Clock
PWM RAMP
PowerGood
VIN
UVLO Threshold
1 2 3 4 5 6 7 1 2 3 4 5 6 71 2
TPS40054
TPS40055
TPS40057
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SLUS593H –DECEMBER 2003–REVISED JULY 2012
Figure 4. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start-up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With RTchosen to select the operating frequency and RKFF chosen to
select the start-up voltage, the approximate amount of hysteresis voltage is shown in Figure 5.
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
HSYTERESIS
Figure 5.
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1
2
3
4
16
15
14
13
ILIM
VIN
BOOST
HDRV
KFF
RT
BP5
SYNC
TPS4005xPWP
5
6
7
8
12
11
10
9
SW
BP10
LDRV
PGND
SGND
SS
VFB
COMP DA
1N914, 1N4150
Type Signal Diode
PGND
RA
499 kW
CA
47 pF
RKFF
71.5 kW
UDG-08102
( )
( )
f
A
A SW
8 3.48
C
R 7.9
-
=´ ´
( )
( )
()
KFF
A
IN min
R 8 3.48
R 495 k 499 k
0.1 V 3.48
´ -
= = W = W
´ -
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
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Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This
applies to applications which have high impedance on the input voltage line or which have excessive ringing on
the VIN line. The input voltage impedance can cause the input voltage to sag enough at start up to cause a
UVLO shutdown and subsequent restart. Excessive ringing can also affect the voltage seen by the device and
cause a UVLO shutdown and restart. A simple external circuit provides a selectable amount of hysteresis to
prevent the nuisance UVLO shutdown.
Assuming a hysteresis current of 10% IKFF, and the peak detector charges to 8 V and VIN(min) = 10 V, the value of
RAis calculated by Equation 3 using a RKFF = 71.5 kΩ.
(3)
CAis chosen to maintain the peak voltage between switching cycles in order to keep the capacitor charge from
drooping 0.1 V (from 8 V to 7.9 V).
(4)
The value of CAmay calculate to less than 10 pF, but some standard value up to 47 pF works adequately. The
diode can be a small-signal switching diode or Schottky rated for more then 20 V. Figure 6 illustrates a typical
implementation using a small switching diode.
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the
nominal start up voltage.
Figure 6. Hysteresis for Programmable UVLO
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L+ǒVIN *VOǓ VO
VIN DI fSW (Henries)
2 4 6 8 1210
VIN – Input Voltage – V
2
1
5
4
6
3
VBP5 – BP5 Voltage – V
110°C
– 55°C
25°C
2 4 6 8 1210
VIN – Input Voltage – V
2
0
8
6
10
4
VBP10 – BP10 Voltage – V
110°C
– 55°C
25°C
1
7
5
9
3
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SLUS593H –DECEMBER 2003–REVISED JULY 2012
BP5 AND BP10 INTERNAL VOLTAGE REGULATORS
Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure 7
and Figure 8. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10
regulation characteristics is also based on the load presented by switching the external MOSFETs.
INPUT VOLTAGE INPUT VOLTAGE
vs vs
BP5 VOLTAGE BP10 VOLTAGE
Figure 7. Figure 8.
SELECTING THE INDUCTOR VALUE
The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is
physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater
number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the
load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in
Equation 5.
where
• VOis the output voltage
•ΔI is the peak-to-peak inductor current (5)
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CO+
L ƪǒIOHǓ2*ǒIOLǓ2ƫ
ƪǒVfǓ2*ǒViǓ2ƫ(Farads)
V2+ƪǒVfǓ2*ǒViǓ2ƫǒVolts2Ǔ
EC+1
2 C V2(Joules)
I2+ƪǒIOHǓ2*ǒIOLǓ2ƫǒ(Amperes)2Ǔ
EL+1
2 L I2(Joules)
O SW
1
V I ESR
8 C f
æ ö
æ ö
D = D ´ +
ç ÷
ç ÷
ç ÷
´ ´
è ø
è ø
TPS40054
TPS40055
TPS40057
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CALCULATING THE OUTPUT CAPACITANCE
The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.
The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst-case output
ripple is described in Equation 6.
where
• COis the output capacitance
• ESR is the equivalent series resistance of the output capacitance (6)
The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During a
step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.
Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
Equation 7.
(7)
where
• IOH is the output current under heavy load conditions
• IOL is the output current under light load conditions (8)
Energy in the capacitor is described in Equation 9.
(9)
where
where
• Vfis the final peak capacitor voltage
• Viis the initial capacitor voltage (10)
Substituting Equation 8 into Equation 7, then substituting Equation 10 into Equation 9, then setting Equation 9
equal to Equation 7, and then solving for COyields the capacitance described in Equation 11.
(11)
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( )
SS / SD
SS / SD START
FB
I
C t F
V
æ ö
= ´
ç ÷
è ø
tSTART w2p L CO
Ǹ(seconds)
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PROGRAMMING SOFT START
The TPS4005x uses a closed-loop soft-start system to ensure a controlled ramp of the output during startup. The
reference voltage used for the startup is derived in the following manner. A capacitor (CSS/SD) is connected to the
SS/SD pin. There is a ramped voltage generated at this pin by charging CSS/SD with a current source. A value of
0.85 V is subtracted from the voltage at the SS/SSD pin and is applied to a non-inverting input of the error
amplifier. This is the effective soft-start ramp voltage, VSSRMP. The error amplifier also has the 0.7-V reference
(VFB) voltage applied to a non-inverting input. The structure of the error amplifier input stage is such that the
lower of VFB or VSSRMP becomes the dominant voltage that the error amplifier uses to regulate the FB pin. This
provides a clean, closed-loop startup while VSSRMP is lower than VFB and a precision reference regulated supply
as VSSRMP climbs above VFB. To ensure a controlled ramp-up of the output voltage, the soft-start time should be
greater than the L-COtime constant as described in Equation 12.
where
• tSTART is the startup ramp time in s (12)
There is a direct correlation between tSTART and the input current required during start-up. The faster tSTART, the
higher the input current required during start-up. This relationship is described in more detail in the section titled,
Programming the Current Limit which follows. The soft-start capacitance, CSS/SD, is described in Equation 13.
For applications in which the VIN supply ramps up slowly (typically between 50 ms and 100 ms), it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the VIN supply transitions between 6 V and 7 V.
where
• ISS/SD is the soft-start charge current (typical value is 2.35 μA)
• VFB is the feedback reference voltage (typical value is 0.7 V) (13)
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UDG-02136
HDRV
CLOCK
VVIN-VSW
SS
7 CURRENT LIMIT TRIPS
(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP) 7 SOFT-START CYCLES
VILIM
tBLANKING
( )
O O
ILIM LOAD
START
C V
I I A
t
æ ö
´
= +
ç ÷
è ø
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PROGRAMMING CURRENT LIMIT
The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.
The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM
is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 9 for typical overcurrent
protection waveforms.
The minimum current limit setpoint (IILIM) is calculated in Equation 14.
where
• ILOAD is the load current at start-up (14)
Figure 9. Typical Current Limit Protection Waveforms
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D+VO
VIN
+VC
VSor VO
VC
+VIN
VS
( )
()( )
()
KFF KFF
IN min T dummy
R V V 58.14 R 1340= - ´ ´ + W
( ) ( )
T dummy 6
SYNC
1
R 17 k
f 17.82 10-
æ ö
ç ÷
= - W
ç ÷
´ ´
è ø
( ) ( )
3
OC OS
DS on max
ILIM
SINK SINK
I R V 42.86 10
R
1.12 I I
-
é ù
ë û
´ + ´
= + W
´
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SLUS593H –DECEMBER 2003–REVISED JULY 2012
The current limit programming resistor (RILIM) is calculated using Equation 15. Care must be taken in choosing
the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level,
the minimum value of ISINK and the maximum value of VOS must be used. The main purpose is hard fault
protection of the power switches.
where
• ISINK is the current into the ILIM pin and is 8.5 μA, minimum
• IOC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current
• VOS is the overcurrent comparator offset and is –20 mV, maximum (15)
SYNCHRONIZING TO AN EXTERNAL SUPPLY
The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the
frequency programmed by RT.
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a dummy value
for RTthat would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the
design.
where
• fSYNC is the synchronizing frequency in kHz (16)
Use the value of RT(dummy) to calculate the value for RKFF.
where
• RT(dummy) is in kΩ(17)
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The generic modulator gain is described in Figure 10. Duty cycle, D, varies from 0 to 1 as the control
voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS. Also, for a synchronous
buck converter, D = VO/ VIN. To get the control voltage to output voltage modulator gain in terms of the input
voltage and ramp voltage,
(18)
With the voltage feedforward function, the ramp slope is proportional to the input voltage. Therefore the
moderator DC gain is independent to the change of input voltage.
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100 1 k 10 k 100 k
Switching Frequency (Hz)
Modulator Gain (dB)
ESR Zero, +1
AMOD = VIN(min)/VRAMP
L-C Filter, –2
Resultant, –1
D= VC/VS
VS
VC
fC+fSW
4(Hertz)
BIAS
O
0.7 R1
R
V 0.7
´
= W
-
fZ+1
2p ESR CO(Hertz)
fLC +1
2p L CO
Ǹ(Hertz)
( ) ( ) ( )
IN min IN min
MOD MOD dB
RAMP RAMP
V V
A or A 20 log
V V
æ ö æ ö
ç ÷ ç ÷
= = ´
ç ÷ ç ÷
è ø è ø
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For the TPS4005x, with VIN(min) being the minimum input voltage required to cause the ramp excursion to reach
the maximum ramp amplitude of VRAMP, the modulator dc gain is shown in Equation 19.
(19)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in Equation 20.
(20)
There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 21.
(21)
Calculate the value of RBIAS to set the output voltage, VO.
(22)
The maximum crossover frequency (0 dB loop gain) is set by Equation 23.
(23)
Typically, fCis selected to be close to the midpoint between the L-COdouble pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (–40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 11 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.
Figure 10. PWM Modulator Relationships Figure 11. Modulator Gain vs Switching Frequency
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( ) ( )
2
LC
MOD
MOD f
CMOD f
f1
A A and G
f A
æ ö
= ´ =
ç ÷
è ø
fC+1
2p R1 C2 G(Hertz)
( )
P2
1
f Hz
2 R3 C3
=p ´ ´
( )
P1
1
f Hz
2 R2 C2
=p ´ ´
( )
Z2
1
f Hz
2 R1 C3
=p ´ ´
( )
Z1
1
f Hz
2 R2 C1
=p ´ ´
+
R1
RBIAS
R3
C3
C2
(optional)
C1 R2
78
VREF
VOCOMP
VFB
UDG-08103
GAIN
180 °
-90 °
-270 °
PHASE
+1
-1
-1
0dB
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A Type III topology, shown in Figure 12, has two zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 13. The two zeros are used to compensate the L-CO
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to
roll-off the overall gain at higher frequencies.
Figure 12. Type III Compensation Configuration Figure 13. Type III Compensation Gain and Phase
The poles and zeros for a Type III network are described in Equation 24 through Equation 27.
(24)
(25)
(26)
(27)
The value of R1 is somewhat arbitrary, but influences other component values. A value between 50 kΩand
100 kΩusually yields reasonable values.
The unity gain frequency is described in Equation 28.
where
• G is the reciprocal of the modulator gain at fC(28)
The modulator gain as a function of frequency at fC, is described in Equation 29.
(29)
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CBP10 +ǒQgHS )QgSRǓ
DV(Farads)
CBOOST +Qg
DV(Farads)
R2(MIN) +VC (max)
ISOURCE (min)
+3.5 V
2 mA +1750 W
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Minimum Load Resistance
Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.
(30)
CALCULATING THE BOOST AND BP10 BYPASS CAPACITOR
The BOOST capacitance provides a local, low impedance source for the high-side driver. The BOOST capacitor
should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BOOST capacitance is
described in Equation 31.
(31)
The 10-V reference pin, BP10V provides energy for both the synchronous MOSFET and the high-side MOSFET
via the BOOST capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 32.
(32)
dv/dt INDUCED TURN-ON
MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the
MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise. If the gate-to-source
voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through
currents. Therefore, the SR MOSFET should be chosen so that the QGD charge is smaller than the QGS charge.
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PT+ǒTJ*TAǓ
qJA (Watts)
UDG-02139
∆I
ANTI-CROSS
CONDUCTION SYNCHRONOUS
RECTIFIER ON
BODY DIODE
CONDUCTION
BODY DIODE
CONDUCTION
HIGH SIDE ON
ID1
ID2
IO
SW
0
}
d 1-d
PSW(fsw) +ǒVIN IOUT tSWǓ fSW (Watts)
IRMS +IOUT d
ǸǒARMSǓ
PCOND +ǒIRMSǓ2 RDS(on) ǒ1)TCR ƪTJ*25OCƫǓ(Watts)
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HIGH-SIDE MOSFET POWER DISSIPATION
The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The
high-side MOSFET conduction losses are defined by Equation 33.
where
• TCRis the temperature coefficient of the MOSFET RDS(on) (33)
The TCRvaries depending on MOSFET technology and manufacturer, but typically ranges between 3500
ppm/°C and 7000 ppm/°C.
The IRMS current for the high-side MOSFET is described in Equation 34.
(34)
The switching losses for the high-side MOSFET are descibed in Equation 35.
where
• IOis the DC output current
• tSW is the switching rise time, typically < 20 ns
• fSW is the switching frequency (35)
Typical switching waveforms are shown in Figure 14.
Figure 14. Inductor Current and SW Node Waveforms
The maximum allowable power dissipation in the MOSFET is determined by Equation 36.
where
• PT= PCOND + PSW(fsw) (W)
•θJA is the package thermal impedance (36)
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PT+TJ*TA
qJA (Watts)
qJA +36.515OCńW
PT+ǒ2 Qg fSW )IQǓ VIN (Watts)
PT+ǒ2 PD
VDR )IQǓ VIN (Watts)
PD+Qg VDR fSW (Wattsńdriver)
PSR +PDC )PRR )PCOND (Watts)
PRR +0.5 QRR VIN fSW (Watts)
PDC +2 IO VF tDELAY fSW (Watts)
IRMS +IO 1*d
ǸǒAmperesRMSǓ
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SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION
The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction
losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be defined
using Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in Equation 37.
(37)
The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross
conduction delay time. The body diode conduction losses are described by Equation 38.
where
• VFis the body diode forward voltage
• tDELAY is the delay time just before the SW node rises (38)
The 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and
once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recover
from a forward bias to a reverse blocking state. The reverse recovery losses are described in Equation 39.
where
• QRR is the reverse recovery charge of the body diode (39)
The QRR is not always described in a MOSFET data sheet, but may be obtained from the MOSFET vendor. The
total synchronous rectifier MOSFET power dissipation is described in Equation 40.
(40)
TPS4005x POWER DISSIPATION
The power dissipation in the TPS4005x is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance, ( refer to PowerPAD Thermally Enhanced Package [2] ) can be calculated
from Equation 41.
(41)
And the total power dissipation in the TPS4005x, assuming the same MOSFET is selected for both the high-side
and synchronous rectifier, is described in Equation 42.
(42)
or
where
• IQis the quiescent operating current (neglecting drivers) (43)
The maximum power capability of the PowerPad package is dependent on the layout as well as air flow. The
thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow,
(44)
The maximum allowable package power dissipation is related to ambient temperature by Equation 45.
(45)
Substituting Equation 38 into Equation 43 and solving for fSW yields the maximum operating frequency for the
TPS4005x. The result is described in Equation 46.
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( )
( )
J A
Q
JA IN
SW
T T I
V
f Hz
2 Qg
æ ö
æ ö
-
ç ÷
-
ç ÷
ç ÷
q ´
ç ÷
è ø
=ç ÷
´
ç ÷
ç ÷
è ø
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
(46)
LAYOUT CONSIDERATIONS
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The θJA specified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a lowest thermal impedance of 40°C/W requires one square inch of 2-ounce
copper on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please
refer to the selected MOSFET's data sheet for more information regarding proper mounting.
GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS
The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that
circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if
possible. The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling
capacitor (BP10), and the input capacitor should be connected to PGND plane at the input capacitor.
Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.
Component placement should ensure that bypass capacitors (BP10 and BP5) are located as close as possible to
their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW).
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TJ+ǒPCOND )PSWǓ qJA )TA+(0.129 )1.152) 40 )85 +136OC
PSW(fsw) +ǒVIN IO tSWǓ fSW +24 V 8 A 20 ns 300 kHz +1.152 W
PCOND +2.932 0.008 (1)0.007 (150 *25)) +0.129 W
IRMS +IO d
Ǹ+8 0.135
Ǹ+2.93 A
DI+IO 2 0.2 +8 2 0.2 +3.2 A
fSW +0.135
400 ns +337 kHz
( )
( )
( )
( )
O min
IN max
O min ON
SW
SW SW ON
IN max
V
V
Vt1
or f
V t t t
æ ö
æ ö
ç ÷
ç ÷
ç ÷
ç ÷
æ ö æ ö è ø
ç ÷
ç ÷ = = =
ç ÷ ç ÷
ç ÷ è ø
è ø ç ÷
ç ÷
è ø
( )
( )
( )
( )
O min O max
MIN MAX
IN max IN min
V V
3.234 3.366
D 0.135 D 0.337
V 24 V 10
= = = = = =
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DESIGN EXAMPLE
• Input voltage: 10 Vdc to 24 Vdc
• Output voltage: 3.3 V ±2% (3.234 ≤VO≤3.366)
• Output current: 8 A (maximum, steady state), 10 A (surge, 10 ms duration, 10% duty cycle maximum)
• Output ripple: 33 mVPP at 8 A
• Output load response: 0.3 V ≥10% to 90% step load change, from 1 A to 7 A
• Operating temperature: -40°C to 85°C
• fSW = 300 kHz
1. Calculate maximum and minimum duty cycles
(47)
2. Select switching frequency
The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater
than 300 ns (see Electrical Characteristics Table ). Therefore:
(48)
Using 400 ns to provide margin,
(49)
Since the oscillator can vary by 10%, decrease fSW, by 10%
fSW = 0.9 × 337 kHz = 303 kHz
and therefore choose a frequency of 300 kHz.
3. Select ΔI
In this case ΔI is chosen so that the converter enters discontinuous mode at 20% of nominal load.
(50)
4. Calculate the high-side MOSFET power losses
Power losses in the high-side MOSFET (Si7860DP) at 24-VIN where switching losses dominate can be calculated
from Equation 51.
(51)
Substituting Equation 34 into Equation 33 yields
(52)
and from Equation 35, the switching losses can be determined.
(53)
The MOSFET junction temperature can be found by substituting Equation 52 and Equation 53 into Equation 36:
(54)
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CO+
2.9 m ǒ(8 A)2*(1 A)2Ǔ
ǒ(3.3)2*(3.0)2Ǔ+97 mF
( ) ( )
KFF IN(min) T
R V 3.48 58.14 R 1340 72.8k use71.5k= - ´ ´ + = W \ W
RT+ǒ1
fSW 17.82 10*6*17ǓkW+170 kWNuse 169 kW
L+(24 *3.3 V) 3.3 V
24 V 3.2 A 300 kHz +2.96 mH
TJ+PSR qJA )TA+(1.322) 40 )85 +139oC
PSR +PRR )PCOND )PDC +0.108 )0.83 )0.384 +1.322 W
PRR +0.5 QRR VIN fSW +0.5 30 nC 24 V 300 kHz +0.108 W
PDC +2 IO VFD tDELAY fSW +2 8.0 A 0.8 V 100 ns 300 kHz +0.384
( )
( )
2
COND
P 7.44 0.008 1 0.007 150 25 0.83 W= ´ ´ + ´ - =
IRMS +IO 1*d
Ǹ+8 1*0.135
Ǹ+7.44 ARMS
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5. Calculate synchronous rectifier losses
The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery
losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead
time associated with the anti-cross conduction delay.
The IRMS current through the synchronous rectifier from Equation 37:
(55)
The synchronous MOSFET conduction loss from Equation 33 is:
(56)
The body diode conduction loss from Equation 38 is:
(57)
The body diode reverse recovery loss from Equation 39 is:
(58)
The total power dissipated in the synchronous rectifier MOSFET from Equation 40 is:
(59)
The junction temperature of the synchronous rectifier at 85°C is:
(60)
In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.
6. Calculate the inductor value
The inductor value is calculated from Equation 5.
(61)
A 2.9-µH Coev DXM1306-2R9 or 2.6-µH Panasonic ETQ-P6F2R9LFA can be used.
7. Setting the switching frequency
The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RTcan be found from
Equation 1, with fSW in kHz.
(62)
8. Programming the ramp generator circuit
The PWM ramp is programmed through a resistor (RKFF) from the KFF pin to VIN. The ramp generator also
controls the input UVLO voltage. For an undervoltage level of 10 V, RKFF can be calculated from Equation 2:
(63)
9. Calculating the output capacitance (CO)
In this example the output capacitance is determined by the load response requirement of ΔV = 0.3 V for a 1-A
to 8-A step load. COcan be calculated using Equation 11:
(64)
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Product Folder Link(s): TPS40054 TPS40055 TPS40057
G+1
AMOD(f)
+1
0.304 +3.29
AMOD(f) +AMOD ǒfLC
fCǓ2
+5 ǒ4.93 kHz
20 kHz Ǔ2
+0.304
fZ+1
2p ESR CO
+1
2p 0.006 360 mF+73.7 kHz
fLC +1
2pL CO
Ǹ+1
2p2.9 mH 360 mF
Ǹ+4.93 kHz
AMOD +10
2+5.0 AMOD(dB) +20 log (5)+14 dB
3
ILIM 6 6
14 0.0104 0.020 42.86 10
R 18.24 k 18.7k
1.12 8.5 10 8.5 10
-
- -
´ - ´
= + = W @ W
´ ´ ´
ILIM
360 F 3.3 V
I 8.0 A 9.2 A
1 ms
m ´
> + =
SS / SD
2.35 A
C 1ms 3.36nF 3300pF
0.7 V
m
= ´ = @
ESR 10.3 m - 4.3m 6.0 m= W W = W
1
33mV 3.2 A ESR
8 97 F 300kHz
æ ö
æ ö
= +
ç ÷
ç ÷
ç ÷
´ m ´
è ø
è ø
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
www.ti.com
Using Equation 6 calculate the ESR required to meet the output ripple requirements.
(65)
(66)
For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used.
10. Calculate the soft-start capacitor (CSS/SD)
This design requires a soft-start time (tSTART) of 1 ms. CSS/SD can be calculated using Equation 13:
(67)
11. Calculate the current limit resistor (RILIM)
The current limit set point depends on tSTART, VO,COand ILOAD at start-up as shown in Equation 14. For this
design,
(68)
For this design, add IILIM (9.2 A) to one-half the ripple current (1.6 A) and increase this value by 30% to allow for
tolerances. This yields a overcurrent setpoint (IOC) of 14 A. RDS(on) is increased 30% (1.3 × 0.008) to allow for
MOSFET heating. Using Equation 15 to calculate RILIM.
(69)
12. Calculate loop compensation values
Calculate the DC modulator gain (AMOD) from Equation 19:
(70)
Calculate the output filter L-COpoles and COESR zeros from Equation 20 and Equation 21:
(71)
and
(72)
Select the close-loop 0 dB crossover frequency, fC. For this example fC= 20 kHz.
Select the double zero location for the Type III compensation network at the output filter double pole at 4.93 kHz.
Select the double pole location for the Type III compensation network at the output capacitor ESR zero at
73.7 kHz.
The amplifier gain at the crossover frequency of 20 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 29:
(73)
And also from Equation 29:
(74)
24 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS40054 TPS40055 TPS40057
CBP(10 V) +QgHS )QgSR
DV+2 Qg
DV+36 nC
0.5 V +72 nF
CBOOST +Qg
DV+18 nC
0.5 V +36 nF
RBIAS +0.7 V R1
VO*0.7 V +0.7 V 100kW
3.3 V *0.7 V +26.9 kW, choose 26.7 kW
fZ1 +1
2p R2 C1 NC1 +1
2p 97.6 kW 4.93 kHz +331 pF, choose 330 pF
fP1 +1
2p R2 C2 NR2 +1
2p 22 pF 73.3 kHz +98.2 kW, choose 97.6 kW
fC+1
2p R1 C2 GNC2 +1
2p 100 kW 3.29 20 kHz +24.2 pF, choose 22 pF
fP2 +1
2p R3 C3 NR3 +1
2p 330 pF 73.3 kHz +6.55 kW, choose 6.49 kW
fZ2 +1
2p R1 C3 NC3 +1
2p 100 kW 4.93 kHz +323 pF, choose 330 pF
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
Choose R1 = 100 kΩ
The poles and zeros for a type III network are described in Equation 24 through Equation 28.
(75)
(76)
(77)
(78)
(79)
Calculate the value of RBIAS from Equation 22 with R1 = 100 kΩ.
(80)
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage
droop on the BOOST pin from Equation 31 is:
(81)
and the BP10V capacitance from Equation 32 is
(82)
For this application, a 0.1-µF capacitor is used for the BOOST bypass capacitor and a 1.0-µF capacitor is used
for the BP10V bypass.
DESIGN EXAMPLE SUMMARY
Figure 15 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the
design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST
to get sufficient gate drive for the upper MOSFET. As seen in Figure 7, the BP10 output is about 6 V with the
input at 8 V so the upper MOSFET gate drive may be less than 5 V.
A schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may
be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.
TPS40054-Q1, TPS40055-Q1 and TPS40057-Q1 automotive qualified versions TPS40055-EP Enhanced product
4.5 to 18V controller with power good TPS40195 4.5 to 18V controller with synchronization power good
TPS40200 Wide input non-synchronous DC-DC controller
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS40054 TPS40055 TPS40057
1
2
3
4
16
15
14
13
ILIM
VIN
BOOST
HDRV
KFF
RT
BP5
SYNC
TPS4005xPWP
5
6
7
8
12
11
10
9
SW
BP10
LDRV
PGND
SGND
SS/SD
VFB
COMP
18.7 kW
RKFF
71.5 kW
1.0 mF
0.1 mF
2.9 mH
R3
6.49 kW
C3
330 pF
R1
100 kW
RBIAS
26.7 kW
180 mF
VO
+
–
CSS/SD
3300 pF
C1
330 pF
RT
169 kW
VIN
+
Si7860
330 mF
22 mF
50 V
C2
22 pF PWP
100 pF
1.0 mF
1.0 kW
R2
97.6 kW
Si7860
*optional
330 mF
22 mF
50 V
180 mF
–
1.0 mF
UDG-08117
TPS40054
TPS40055
TPS40057
SLUS593H –DECEMBER 2003–REVISED JULY 2012
www.ti.com
Figure 15. 24-V to 3.3-V at 8-A DC-to-DC Converter Design Example
26 Submit Documentation Feedback Copyright © 2003–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS40054 TPS40055 TPS40057
TPS40054
TPS40055
TPS40057
www.ti.com
SLUS593H –DECEMBER 2003–REVISED JULY 2012
ADDITIONAL REFERENCES
RELATED DEVICES
The following devices have characteristics similar to the TPS40054/5/7 and may be of interest.
Table 2. RELATED DEVICES
DEVICE DESCRIPTION
TPS40055-EP Enhanced performance TPS40055.
TPS40054-Q1
TPS40057-Q1 Automotive qualified versions of the TPS5005x series.
TPS40055-Q1
TPS40192 4.5-V to 18-V Controller with Synchronization Power Good
TPS40193
TPS40200 Wide-Input Non-Synchronous DC-DC Controller
REFERENCES
1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.
2. PowerPAD Thermally Enhanced Package Texas Instruments, Semiconductor Group, Technical Brief
(SLMA002)REVISION HISTORY
Changes from Revision F (SEPTEMBER 2008) to Revision G Page
• Deleted errors in schematic. ................................................................................................................................................. 1
• Changed ILIM to IILIM (corrected typographical error) ........................................................................................................... 14
• Added clarity to Loop Compensation section ..................................................................................................................... 15
• Changed VIN(UVLO) to VIN(min) in two places (corrected typographic errors) ......................................................................... 16
• Changed corrected Equation 46 ......................................................................................................................................... 21
• Changed corrected Equation 56 ......................................................................................................................................... 23
• Changed corrected Equation 67 ......................................................................................................................................... 24
• Changed corrected Equation 69 ......................................................................................................................................... 24
• Changed corrected reference designator values in Figure 15 ............................................................................................ 26
Changes from Revision G (SEPTEMBER 2011) to Revision H Page
• Added the Thermal Information table ................................................................................................................................... 2
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
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PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS40054PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40054PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40054PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40054PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40055PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40055PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40055PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40055PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40057PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40057PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40057PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40057PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jul-2012
Addendum-Page 2
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS40055 :
•Enhanced Product: TPS40055-EP
NOTE: Qualified Version Definitions:
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS40054PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS40055PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TPS40057PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40054PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS40055PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
TPS40057PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Jul-2012
Pack Materials-Page 2
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