W83194R-81 - Winbond Electronics Corporation America

W83194R-81

Publication Release Date: May 17, 2005

i Revision A1

Table of Content-

1. GENERAL DESCRINPTION....................................................................................................... 1

2. PRODUCT FEATURES .............................................................................................................. 1

3. BLOCK DIAGRAM ...................................................................................................................... 2

4. PIN CONFIGURATION...............................................................................................................2

5. PIN DESCRIPTION..................................................................................................................... 3

5.1 Crystal I/O ....................................................................................................................... 3

5.2 CPU, SDRAM, PCI Clock Outputs ................................................................................ 3

5.3 I2C Control Interface....................................................................................................... 4

5.4 Fixed Frequency Outputs ............................................................................................... 4

5.5 Power Pins......................................................................................................................5

6. FREQUENCY SELECTION BY HARDWARE ............................................................................ 5

7. CPU 3.3#_2.5 BUFFER SELECTION......................................................................................... 6

8. FUNTION DESCRIPTION .......................................................................................................... 6

8.1 POWER MANAGEMENT FUNCTIONS ......................................................................... 6

8.2 2-WIRE I2C CONTROL INTERFACE ............................................................................ 7

8.3 SERIAL CONTROL REGISTERS .................................................................................. 7

8.3.1 Register 0: CPU Frequency Select Register....................................................................8

8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)...............................................9

8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive) .................................................9

8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)...........................................9

8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)........................10

8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive).................................................10

8.3.7 Register 6: Winbond Chip ID Register (Read Only)......................................................10

9. SPECIFICATIONS .................................................................................................................... 11

9.1 ABSOLUTE MAXIMUM RATINGS ............................................................................... 11

9.2 AC CHARACTERISTICS.............................................................................................. 11

9.3 DC CHARACTERISTICS.............................................................................................. 12

9.4 BUFFER CHARACTERISTICS .................................................................................... 13

9.4.1 TYPE 1 BUFFER FOR CPU (0:2) .................................................................................13

9.4.2 TYPE 2 BUFFER FOR IOAPIC .....................................................................................13

9.4.3 TYPE 3 BUFFER FOR REF(0:2), 24MHZ, 48MHZ .......................................................14

9.4.4 TYPE 4 BUFFER FOR SDRAM(0:12) ...........................................................................14

9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4, F).........................................................................14

W83194R-81

- ii -

10. POWER MANAGEMENT TIMING ............................................................................................ 15

10.1 CPU_STOP# Timing Diagram...................................................................................... 15

10.2 PCI_STOP# Timing Diagram........................................................................................ 15

11. ORDERING INFORMATION .................................................................................................... 16

12. HOW TO READ THE TOP MARKING...................................................................................... 16

13. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 17

14. REVISION HISTORY ................................................................................................................18

W83194R-81

Publication Release Date: May 17, 2005

- 1 - Revision A1

1. GENERAL DESCRINPTION

The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required

for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16

different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth

transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency with CPU

clocks.

The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each

clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce

EMI.

The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF

loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as

maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide

better than 0.5V /ns slew rate.

2. PRODUCT FEATURES

• Supports Pentium, Pentium Pro, AMD and Cyrix CPUs with I2C.

• 3 CPU clocks

• 13 SDRAM clocks for 3 DIMMs

• 6 PCI synchronous clocks.

• Optional single or mixed supply:

(Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or

(Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V)

• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns

• SDRAM frequency synchronous or asynchronous to CPU clocks

• Smooth frequency switch with selections from 66 to 133mhz(including 90MHz)

• I

2C 2-Wire serial interface and I2C read back

• 0.25%, 0.5% center type spread spectrum to reduce EMI

• Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

• MODE pin for power Management

• 48 MHz for USB

• 24 MHz for super I/O

• 48-pin SSOP package

W83194R-81

- 2 -

3. BLOCK DIAGRAM

PLL2

XTAL

OSC

Spread

Spectrum

PLL1

LATCH

POR STOP

÷2

Contro

l Logic

Config

. Reg.

STOP

PCI

clock

Divder

48MHz

SIO

REF(0:2)

CPUCLK(0:2

)

SDRAM(0:12

)

PCICLK(0:4)

PCICLK_F

Xin

Xout

*FS(0:2) 3

*MODE

CPU_STOP#

PCI_STOP#

*SDAT

*SCLK

CPU3.3_2.5#

CPU_STOP#

PCI_STOP#

*SD_SEL#

SEL24_14#

SDRAM_STOP#

PD#

IOAPIC

4. PIN CONFIGURATION

Vdd

REF0/ *MODE

Vss

Xin

Xout

Vddq4

PCICLK_F/ *FS1

PCICLK0/ *FS2

Vss

PCICLK1

PCICLK2

PCICLK3

PCICLK4

Vddq4

SDRAM12

Vss

*CPU_STOP#/SDRAM11

*PCI_STOP#/SDRAM10

Vddq3

*SDRAM_STOP#/SDRAM 9

*PD#/SDRAM 8

Vss

*SDATA

*SDCLK

Vddq2

IOAPIC

REF1/ *SD_SEL#

Vss

REF2/CPU3.3_2.5#

CPUCLK0

Vddq2b

CPUCLK1

CPUCLK

Vss

SDRAM 0

SDRAM 1

SDRAM 2

Vddq3

SDRAM 3

Vss

SDRAM 4

SDRAM 5

SDRAM 6

SDRAM 7

Vss

Vddq3

48MHz/*FS0

SIO/*SEL24_14#

W83194R-81

Publication Release Date: May 17, 2005

- 3 - Revision A1

5. PIN DESCRIPTION

IN - Input

OUT - Output

I/O - Bi-directional Pin

# - Active Low

* - Internal 250kΩ pull-up

5.1 Crystal I/O

SYMBOL PIN I/O FUNCTION

Xin 4 IN

Crystal input with internal loading capacitors and

feedback resistors.

Xout 5 OUT Crystal output at 14.318MHz nominally.

5.2 CPU, SDRAM, PCI Clock Outputs

SYMBOL PIN I/O FUNCTION

CPUCLK [ 0:2 ] 40,41,43 OUT

Low skew (< 250ps) clock outputs for host

frequencies such as CPU, Chipset and Cache.

Vddq2b is the supply voltage for these outputs.

SDRAM11/

*CPU_STOP# 17 I/O

If MODE =1 (default), then this pin is a SDRAM

clock buffered output of the crystal. If MODE = 0 ,

then this pin is CPU_STOP# input used in power

management mode for synchronously stopping the

all CPU clocks.

SDRAM10/

*PCI_STOP# 18 I/O

If MODE = 1 (default), then this pin is a SDRAM

clock output. If MODE = 0 , then this pin is

PCI_STOP # and used in power management

mode for synchronously stopping the all PCI clocks.

SDRAM9/

*SDRAM_STOP# 20 I/O

If MODE = 1 (default), then this pin is a SDRAM

clock output. If MODE = 0 , then this pin is

SDRAM_STOP # and used in power management

mode for stopping the all SDRAM clocks.

SDRAM8/ *PD# 21 I/O

If MODE = 1 (default), then this pin is a SDRAM

clock output. If MODE = 0 , then this pin is PD #

and used to power down the device into a power

down state.

SDRAM[0:7],

SDRAM12

28,29,31,32,3

4, 35,37,38,15 O SDRAM clock outputs which have the same

frequency as CPU clocks.

PCICLK_F/ *FS1 7 I/O

Latched input for FS1 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

Free running PCI clock during normal operation.

W83194R-81

- 4 -

5.2 CPU, SDRAM, PCI Clock Outputs, continued

SYMBOL PIN I/O FUNCTION

PCICLK 0 / *FS2 8 I/O

Latched input for FS2 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks.

PCI clock during normal operation.

PCICLK [ 1:4 ] 10,11,12,13 OUT Low skew (< 250ps) PCI clock outputs.

5.3 I2C Control Interface

SYMBOL PIN I/O FUNCTION

*SDATA 23 I/O Serial data of I2C 2-wire control interface

*SDCLK 24 IN Serial clock of I2C 2-wire control interface

5.4 Fixed Frequency Outputs

SYMBOL PIN I/O FUNCTION

IOAPIC 47 O 2.5V fixed 14.318MHz

REF0 / *MODE 2 I/O

3.3V, 14.318MHz reference clock output.

Internal 250kΩ pull-up.

Function select pin.

REF1 /*SD_SEL# 46 I/O

3.3V, 14.318MHz reference clock output

Internal 250kΩ pull-up.

Latched input at Power On selects the frequencies

for clock outputs.

REF2 / CPU3.3#_2.5

44 I/O

Internal 250kΩ pull-up.

Latched input for CPU3.3#_2.5 at initial power up.

Reference clock during normal operation.

Latched high - Vddq2b = 2.5V

Latched low - Vddq2b = 3.3V

SIO / *SEL24_14# 25 I/O

*SEL24_14# controls the frequency of SIO. If logic

0 at power on, SIO=14.318. If logic 1, SIO=24MHz

for super I/O.

48MHz / *FS0 26 I/O

Internal 250kΩ pull-up.

Latched input for FS0 at initial power up for H/W

selecting the output frequency of CPU, SDRAM and

PCI clocks. 48MHz output for USB during normal

operation.

W83194R-81

Publication Release Date: May 17, 2005

- 5 - Revision A1

5.5 Power Pins

SYMBOL PIN FUNCTION

Vdd 1 Power supply for REF0 crystal and core logic.

Vddq2 48 Power supply for REF1,IOAPIC output, 2.5V.

Vddq2b 42

Power supply for REF2, CPUCLK[0:2], either 2.5V or

3.3V.

Vddq3 19, 30, 36 Power supply for SDRAM and 48/24MHz outputs.

Vddq4 6,14 Power supply for PCICLK outputs.

Vss 3,9,16,22,27,

33,39,45 Circuit Ground.

6. FREQUENCY SELECTION BY HARDWARE

SD_SEL FS2 FS1 FS0 CPU

(MHZ)

SDRAM

(MHZ) PCI (MHZ) REF (MHZ)

IOAPIC

0 0 0 0 66.70 100.05 33.35 14.318

0 0 0 1 90 90 30 14.318

0 0 1 0 95.25 63.4 31.7 14.318

0 0 1 1 100.2 66.8 33.4 14.318

0 1 0 0 100 75 30 14.318

0 1 0 1 112 74.7 37.3 14.318

0 1 1 0 124 82.7 31 14.318

0 1 1 1 133.3 88.9 33.3 14.318

1 0 0 0 66.8 66.8 33.4 14.318

1 0 0 1 75 75 30 14.318

1 0 1 0 83.3 83.3 33.32 14.318

1 0 1 1 95.25 95.25 31.7 14.318

1 1 0 0 100.2 100.2 33.4 14.318

1 1 0 1 112 112 37.3 14.318

1 1 1 0 124 124 31 14.318

1 1 1 1 133.3 133.3 33.3 14.318

W83194R-81

- 6 -

7. CPU 3.3#_2.5 BUFFER SELECTION

CPU 3.3#_2.5 ( PIN 44 ) INPUT LEVEL CPU OPERATE AT

1 VDD = 2.5V

0 VDD = 3.3V

8. FUNTION DESCRIPTION

8.1 POWER MANAGEMENT FUNCTIONS

All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,

external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure

correct pulse widths. When MODE=0, pins 17, 18, 20 and 21 are inputs (PCI_STOP#),

(CPU_STOP#), (SDRAM_STOP#), (PD#). when MODE=1, these functions are not available. A

particular clock could be enabled as both the 2-wire serial control interface and one of these pins

indicate that it should be enabled.

The W83194R-81 may be disabled in the low state according to the following table in order to reduce

power consumption. All clocks are stopped in the low state, but maintain a valid high period on

transitions from running to stop. The CPU and PCI clocks transform between running and stop by

waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after

which high levels of the output are either enabled or disabled.

Mode pin-power management input

MODE(PIN2) PIN17 PIN18 PIN20 PIN21

0 (Input) CPU_STOP# PCI_STOP# SDRAM_STOP# PD#

1 (Output) SDRAM11 SDRAM10 SDRAM9 SDRAM8

PD# CPU_STOP# PCI_STOP# SDRAM

_STOP# PCI [0:4] SDRAM

[0:12] CPU[1:2] XTAL &

VCOS

0 X X X Low Low Low Low

1 X X X Running Running Running Running

1 1 1 1 Running Running Running Running

1 1 1 0 Running Running Running Running

1 1 0 1 Low Running Running Running

1 1 0 0 Low Low Running Running

1 0 1 1 Running Running Low Running

1 0 1 0 Running Low Low Running

1 0 0 1 Low Running Low Running

1 0 0 0 Low Low Low Running

W83194R-81

Publication Release Date: May 17, 2005

- 7 - Revision A1

8.2 2-WIRE I2C CONTROL INTERFACE

The clock generator is a slave I2C component which can be read back the data stored in the latches

for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire

control interface allows each clock output individually enabled or disabled. On power up, the

W83194R-81 initializes with default register settings, and then itptional to use the 2-wire control

interface.

The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high

during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA

while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-

high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data

is always sent as complete 8-bit bytes followed by an acknowledge generated.

Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code

checking [0000 0000], and byte count checking. After successful reception of each byte, an

acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to

write to internal I2C registers after the string of data. The sequence order is as follows:

Bytes sequence order for I2C controller :

Clock Address

A(6:0) & R/W Ack 8 bits dummy

Command code Ack 8 bits dummy

Byte count Ack Byte0,1,2...

until Stop

Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :

Clock Address

A(6:0) & R/W Ack Byte 0 Ack Ack Byte2, 3, 4...

until Stop

Byte 1

8.3 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the @PowerUp column gives the state at true power

up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte

Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in

these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,

the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.

W83194R-81

- 8 -

8.3.1 Register 0: CPU Frequency Select Register

BIT @POWERUP PIN DESCRIPTION

7 0 -

0 = ±0.25% Spread Spectrum Modulation

1 = ±0.5% Spread Spectrum Modulation

6 0 - SSEL2 ( Frequency table selection by software via I2C)

5 0 - SSEL1 ( Frequency table selection by software via I2C)

4 0 - SSEL0 ( Frequency table selection by software via I2C)

3 0 -

0 = Selection by hardware

1 = Selection by software I2C - Bit 6:4 and Bit2

2 0 - SSEL3 (Frequency table selection by software via I2C )

1 0 -

0 = Normal

1 = Spread Spectrum enabled

0 0 -

0 = Running

1 = Tristate all outputs

Frequency table selection by software via I2C

SSEL3 SSEL2 SSEL1 SSEL0 CPU

(MHZ)

SDRAM

(MHZ) PCI (MHZ) REF (MHZ)

IOAPIC

0 0 0 0

66.70 100.05 33.35 14.318

0 0 0 1 90 90 30

14.318

0 0 1 0

95.25 63.4 31.7 14.318

0 0 1 1

100.2 66.8 33.4 14.318

0 1 0 0 100 75 30

14.318

0 1 0 1 112 74.7 37.3

14.318

0 1 1 0 124 82.7 31 14.318

0 1 1 1

133.3 88.9 33.3 14.318

1 0 0 0

66.8 66.8 33.4 14.318

1 0 0 1 75 75 30

14.318

1 0 1 0

83.3 83.3 33.32

14.318

1 0 1 1

95.25 95.25 31.7 14.318

1 1 0 0

100.2 100.2 33.4 14.318

1 1 0 1 112 112 37.3

14.318

1 1 1 0 124 124 31 14.318

1 1 1 1

133.3 133.3 33.3 14.318

W83194R-81

Publication Release Date: May 17, 2005

- 9 - Revision A1

8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP PIN DESCRIPTION

7 1 - Reserved

6 1 - Reserved

5 1 - Reserved

4 1 - Reserved

3 1 40 CPUCLK2 (Active / Inactive)

2 1 41 CPUCLK1 (Active / Inactive)

1 1 43 CPUCLK0 (Active / Inactive)

0 - - Latched FS0#

8.3.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP PIN DESCRIPTION

7 - - Latched FS1#

6 1 7 PCICLK_F (Active / Inactive)

5 1 - Reserved

4 1 13 PCICLK4 (Active / Inactive)

3 1 12 PCICLK3 (Active / Inactive)

2 1 11 PCICLK2 (Active / Inactive)

1 1 10 PCICLK1 (Active / Inactive)

0 1 8 PCICLK0 (Active / Inactive)

8.3.4 Register 3: SDRAM Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP PIN DESCRIPTION

7 1 28 SDRAM7 (Active / Inactive)

6 1 29 SDRAM6 (Active / Inactive)

5 1 31 SDRAM5 (Active / Inactive)

4 1 32 SDRAM4 (Active / Inactive)

3 1 34 SDRAM3 (Active / Inactive)

2 1 35 SDRAM2 (Active / Inactive)

1 1 37 SDRAM1 (Active / Inactive)

0 1 38 SDRAM0 (Active / Inactive)

W83194R-81

- 10 -

8.3.5 Register 4: Additional SDRAM Clock Register (1 = Active, 0 = Inactive)

BIT @POWERUP PIN DESCRIPTION

7 1 - Reserved

6 1 25 24/14MHz(Active / Inactive)

5 1 26 48MHz(Active / Inactive)

4 1 15 SDRAM12 (Active / Inactive)

3 1 17 SDRAM11 (Active / Inactive)

2 1 18 SDRAM10 (Active / Inactive)

1 1 20 SDRAM9 (Active / Inactive)

0 1 21 SDRAM8 (Active / Inactive)

8.3.6 Register 5: Peripheral Control (1 = Active, 0 = Inactive)

BIT @POWERUP PIN DESCRIPTION

7 1 - Reserved

6 - - Latched FS2#

5 1 - Reserved

4 1 47 IOAPIC (Active / Inactive)

3 - - Latched SD_SEL

2 1 44 REF2 (Active / Inactive)

1 1 46 REF1 (Active / Inactive)

0 1 2 REF0 (Active / Inactive)

8.3.7 Register 6: Winbond Chip ID Register (Read Only)

BIT @POWERUP PIN DESCRIPTION

7 0 - Winbond Chip ID

6 1 - Winbond Chip ID

5 0 - Winbond Chip ID

4 1 - Winbond Chip ID

3 0 - Winbond Chip ID

2 1 - Winbond Chip ID

1 0 - Winbond Chip ID

0 0 - Winbond Chip ID

W83194R-81

Publication Release Date: May 17, 2005

- 11 - Revision A1

9. SPECIFICATIONS

9.1 ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in this table may cause permanent damage to the device.

Precautions should be taken to avoid application of any voltage higher than the maximum rated

voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs

must always be tied to an appropriate logic voltage level (Ground or Vdd).

SYMBOL PARAMETER RATING

Vdd , VIN Voltage on any pin with respect to GND - 0.5 V to + 7.0 V

TSTG Storage Temperature - 65°C to + 150°C

TB Ambient Temperature - 55°C to + 125°C

TA Operating Temperature 0°C to + 70°C

9.2 AC CHARACTERISTICS

Vddq4 = Vdd = Vddq3 = 3.3V

5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0

C to +70

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Output Duty Cycle 45 50 55 % Measured at 1.5V

CPU/SDRAM to PCI

Offset tOFF 1 4 ns

15 pF Load Measured at

1.5V

Skew (CPU-CPU), (PCI-

PCI), (SDRAM-SDRAM) tSKEW 250 ps

15 pF Load Measured at

1.5V

CPU/SDRAM

Cycle to Cycle Jitter tCCJ ±250 ps

CPU/SDRAM

Absolute Jitter tJA 500 ps

Jitter Spectrum 20 dB

Bandwidth from Center BWJ 500 KHz

Output Rise (0.4V ~ 2.0V)

& Fall (2.0V ~0.4V) Time

tTLH

tTHL

0.4 1.6 ns

15 pF Load on CPU and

PCI outputs

Overshoot/Undershoot

Beyond Power Rails Vover 1.5 V

22 Ω at source of 8 inch

PCB run to 15 pF load

Ring Back Exclusion VRBE 2.1 V

Ring Back must not

enter this range.

W83194R-81

- 12 -

9.3 DC CHARACTERISTICS

Vddq4 = Vdd = Vddq3 = 3.3V

5 %, Vddq2=Vddq2b = 2.375V~2.9V , TA = 0

C to +70

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Input Low Voltage VIL 0.8

Vdc

Input High Voltage VIH 2.0

Vdc

Input Low Current IIL -66

µA

Input High Current IIH 5

µA

Output Low Voltage

IOL = 4 mA VOL 0.4

Vdc All outputs

Output High Voltage

IOH = 4mA VOH 2.4

Vdc All outputs using 3.3V

power

Tri-State leakage

Current Ioz 10

µA

Dynamic Supply Current

for Vdd + Vddq3 Idd3 mA

CPU = 66.6 MHz

PCI = 33.3 Mhz with load

Dynamic Supply Current

for Vddq2 + Vddq2b Idd2 mA

Same as above

CPU Stop Current

for Vdd + Vddq3 ICPUS3 mA

Same as above

CPU Stop Current

for Vddq2 + Vddq2b ICPUS2 mA

Same as above

PCI Stop Current

for Vdd + Vddq3 IPD3 mA

W83194R-81

Publication Release Date: May 17, 2005

- 13 - Revision A1

9.4 BUFFER CHARACTERISTICS

9.4.1 TYPE 1 BUFFER FOR CPU (0:2)

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Pull-Up Current Min IOH(min) -27 mA Vout = 1.0 V

Pull-Up Current Max IOH(max) -27 mA Vout = 2.0V

Pull-Down Current Min IOL(min) mA Vout = 1.2 V

Pull-Down Current Max IOL(max) 27 mA Vout = 0.3 V

Rise/Fall Time Min

Between 0.4 V and 2.0 V TRF(min) 0.4 ns 10 pF Load

Rise/Fall Time Max

Between 0.4 V and 2.0 V TRF(max) 1.6 ns 20 pF Load

9.4.2 TYPE 2 BUFFER FOR IOAPIC

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Pull-Up Current Min IOH(min) mA Vout = 1.4 V

Pull-Up Current Max IOH(max) -29 mA Vout = 2.7V

Pull-Down Current Min IOL(min) mA Vout = 1.0 V

Pull-Down Current Max IOL(max) 28 mA Vout = 0.2 V

Rise/Fall Time Min

Between 0.7 V and 1.7 V TRF(min) 0.4 ns 10 pF Load

Rise/Fall Time Max

Between 0.7 V and 1.7 V TRF(max) 1.8 ns 20 pF Load

W83194R-81

- 14 -

9.4.3 TYPE 3 BUFFER FOR REF(0:2), 24MHZ, 48MHZ

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Pull-Up Current Min IOH(min) -29 mA Vout = 1.0 V

Pull-Up Current Max IOH(max) -23 mA Vout = 3.135V

Pull-Down Current Min IOL(min) 29 mA Vout = 1.95 V

Pull-Down Current Max IOL(max) mA Vout = 0.4 V

Rise/Fall Time Min

Between 0.8 V and 2.0 V TRF(min) 1.0 ns 10 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V TRF(max) 4.0 ns 20 pF Load

9.4.4 TYPE 4 BUFFER FOR SDRAM(0:12)

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Pull-Up Current Min IOH(min) mA Vout = 1.65V

Pull-Up Current Max IOH(max) -46 mA Vout = 3.135V

Pull-Down Current Min IOL(min) mA Vout = 1.65 V

Pull-Down Current Max IOL(max) 53 mA Vout = 0.4 V

Rise/Fall Time Min

Between 0.8 V and 2.0 V TRF(min) 0.5 ns 20 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V TRF(max) 1.3 ns 30 pF Load

9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4, F)

PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS

Pull-Up Current Min IOH(min) -33 mA Vout = 1.0 V

Pull-Up Current Max IOH(max) -33 mA Vout = 3.135 V

Pull-Down Current Min IOL(min) 30 mA Vout = 1.95 V

Pull-Down Current Max IOL(max) 38 mA Vout = 0.4 V

Rise/Fall Time Min

Between 0.8 V and 2.0 V TRF(min) 0.5 ns 15 pF Load

Rise/Fall Time Max

Between 0.8 V and 2.0 V TRF(max) 2.0 ns 30 pF Load

W83194R-81

Publication Release Date: May 17, 2005

- 15 - Revision A1

10. POWER MANAGEMENT TIMING

10.1 CPU_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

CPU_STOP#

CPUCLK[0:3]

SDRAM

For synchronous Chipset, CPU_STOP# pin is a synchronous “active low ”input pin used to stop the

CPU clocks for low power operation. This pin is asserted synchronously by the external control logic

at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the

CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output

with full pulse width. In this case, CPU locks on latency“ is less than 2 CPU clocks and locks off

latency is less then 2 CPU clocks.

10.2 PCI_STOP# Timing Diagram

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK_F

PCI_STOP#

PCICLK[0:4]

1212

For synchronous Chipset, PCI_STOP# pin is a synchronous ctive low” input pin used to stop the

PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic

at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the

PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output

with full pulse width. In this case, PCI locks on latency“ is less than 1 PCI clocks and locks off

latency is less then 1 PCI clocks.

W83194R-81

- 16 -

11. ORDERING INFORMATION

Part Number Package Type Production Flow

W83194R-81 48 PIN SSOP Commercial, 0°C to +70°C

12. HOW TO READ THE TOP MARKING

W 8 3 1 9 4 R - 8 1

2 8 0 5 1 2 3 4

8 1 4 G B B

1st line: Winbond logo and the type number: W83194R-81

2nd line: Tracking code 2 8051234

2: wafers manufactured in Winbond FAB 2

8051234: wafer production series lot number

3rd line: Tracking code 814 G B B

814: packages made in '98, week 14

G: assembly house ID; A means ASE, S means SPIL, G means GR

BB: IC revision

All the trade marks of products and companies mentioned in this data sheet

belong to their respective owners.

W83194R-81

Publication Release Date: May 17, 2005

- 17 - Revision A1

13. PACKAGE DRAWING AND DIMENSIONS

W83194R-81

- 18 -

14. REVISION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 May 17, 2005 18 ADD Important Notice

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Headquarters

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

Winbond Electronics Corporation America

2727 North First Street, San Jose,

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

Winbond Electronics (H.K.) Ltd.

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

FAX: 852-27552064

Unit 9-15, 22F, Millennium City,

TEL: 852-27513100

Please note that all data and specifications are subject to change without notice.

ll the trade marks of products and companies mentioned in this data sheet belong to their respective owner

Winbond Electronics (Shanghai) Lt

200336 China

FAX: 86-21-62365998

27F, 2299 Yan An W. Rd. Shanghai,

TEL: 86-21-62365999

Winbond Electronics Corporation Japan

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

FAX: 81-45-4781800

7F Daini-ueno BLDG, 3-7-18

TEL: 81-45-4781881

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.