ISSI IS71VPCF16XS04 (R) 3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package (MCP) -- 16 Mbit Simultaneous Operation Flash PRELIMINARY Memory and 4 Mbit Static RAM INFORMATION JUNE 2002 MCP FEATURES * Power supply voltage 2.7V to 3.3V * High performance: * Over 100,000 write/erase cycles * Low supply voltage (Vccf 2.5V) inhibits writes * WP/ACC input pin: If VIL, allows protection of boot sectors If VIH, allows removal of boot sector protection If Vacc, program time is reduced by 40% Flash: 85ns maximum access time SRAM: 85ns maximum access time * Package: 69-ball BGA * Operating Temperature: -25C to +85C * Boot sector: Top or Bottom FLASH FEATURES * Power Dissipation: SRAM FEATURES (4 Mb density) * Power Dissipation: Read Current at 1 Mhz: 7 mA maximum Read Current at 5 Mhz: 18 mA maximum Sleep Mode: 5 A maximum * Simultaneous Read and Write Operations: Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank * Low-Power Mode: A period of no activity causes flash to enter a lowpower state * Erase Suspend/Resume: Suspends of erase activity to allow a read in the same bank. * Sector Erase Architecture: 8 words of 4k size and 31 words of 32K size (16 Mbit) Any combination of sectors, or the entire flash can be simultaneously erased * Erase Algorithms: Automatically preprograms/erases the flash memory entirely, or by sector * Program Algorithms: Automatically writes and verifies data at specified address * Hidden ROM Region: 64KB with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence * Data Polling and Toggle Bit: Allow for detection of program or erase cycle completion * Ready-Busy output (RY/BY): Detection of program or erase cycle completion Operating: 40 mA maximum Standby: 7 A maximum * * * * Chip Selects: CE1s, CE2s Power down feature using CE1s, or CE2s Data retention supply voltage: 1.5 to 3.3 volt Byte data control: LBs (DQ0-DQ7), UBs (DQ8-DQ15) -- in x16 mode GENERAL DESCRIPTION The flash and SRAM MCP is available in 16 Mbit Flash/4 Mbit SRAM having a data bus of either x8 or x16. The 16 Mbit flash is composed of 1,048,576 words of 16 bits or 2,097,152 bytes of 8 bits. The 4Mb SRAM has 262,144 words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0DQ7 handle the x8 format, while lines DQ0-DQ15 handle the x16 format. The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations. The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer. The 16 Mbit flash/4 Mbit SRAM is offered in a 69-ball BGA package. The flash is compatible with the JEDEC Flash command set standard . The flash access time is 85ns and the SRAM access time is 85ns. The Flash architecture is composed of two banks which allows simultaneous operation on each. Optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. Both operations would then be operating simultaneously, with zero latency. Copyright (c) 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) MCP BLOCK DIAGRAM VCCf GND A0-A19 RY/BY A0-A19 A-1 WP/ACC RESET CEf I/Of 16-MBIT Flash Memory DQ0-DQ15/A-1 VCCS GND A0-A17 DQ0-DQ15/A-1 SA LBs UBs WE OE CE1s CE2s I/Os 4-MBIT Static RAM LOGIC SYMBOL 21 A0-A19, A-1 SA CEf RY/BY CE1s CE2s OE WE 16 or 8 DQ0-DQ15 WP/ACC RESET UBs LBs I/Of I/Os 2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH MEMORY BLOCK DIAGRAM VCC OE GND A0-A19 BYTE Upper Bank Address Upper Bank Y-Decoder Latches and Control Logic RY/BY A0-A19 X-Decoder A0-A19 RESET WE CE BYTE DQ0-DQ15 DQ0-DQ15 Status STATE CONTROL & COMMAND REGISTER Control WP/ACC DQ0-DQ15 DQ0-DQ15 A0-A19 A0-A19 Lower Bank Address Lower Bank Y-Decoder Latches and Control Logic X-Decoder OE BYTE FLASH BANK ORGANIZATION Organization Type Bank 1 Size Bank 2 Size Boot Block Type H 0.5Mb 15.5Mb Top Type J Type K Type L Type M 2Mb 4Mb 8Mb 0.5Mb 14Mb 12Mb 8Mb 15.5Mb Top Top Top Bottom Type N Type P Type Q 2Mb 4Mb 8Mb 14Mb 12Mb 8Mb Bottom Bottom Bottom Note: For device part number, see Part Number Logic Diagram or Ordering Information Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 3 ISSI IS71VPCF16XS04 (R) PIN CONFIGURATION (16 Mb Flash and 4 Mb SRAM) 69 BALL FBGA (Top View) 1 A NC B NC 2 3 A7 4 12345678901234 12345678901234 12345678901234 12345678901234 LB 12345678901234 12345678901234 12345678901234 12345678901234 12345678901234 12345678901234 UB 12345678901234 12345678901234 C A3 A6 D A2 A5 A18 5 6 NC NC WP/ACC 123456789012345 WE 7 A8 A11 RESET A19 A12 A15 RY/BY NC A9 A13 NC A14 12345678901234 12345678901234 12345678901234 12345678901234 12345678901234 SA 12345678901234 12345678901234 NC NC A16 NC A1 A4 A17 A10 F NC A0 GND DQ1 DQ6 CEf OE DQ9 DQ3 DQ0 DQ10 VCCf DQ8 DQ2 DQ11 H J K NC 10 123456789012345 123456789012345 123456789012345 123456789012345 CE2s 123456789012345 NC 12345678901234 12345678901234 12345678901234 12345678901234 CE1s 12345678901234 12345678901234 9 NC E G 8 NC DQ4 123456789012345 123456789012345 123456789012345 123456789012345 VCCs 123456789012345 123456789012345 1234567890123 1234567890123 1234567890123 1234567890123 I/Os 1234567890123 1234567890123 DQ13 DQ15/A-1 I/Of DQ12 DQ7 GND DQ5 DQ14 NC NC 1234 1234 1234 1234 Shared Flash only SRAM only PIN DESCRIPTIONS 4 A0-A17 Address Inputs, Common LBs Lower-byte Control(DQ0-DQ7), SRAM A18-A19, A-1 Address Inputs, Flash UBs Upper-byte Control (DQ8-DQ15), SRAM DQ0-DQ15/A-1 Data Inputs/Outputs WP/ACC Write Protect/Acceleration Pin, Flash RESET Reset RY/BY Ready/Busy Output CE1s, CE2s Chip Selects, SRAM SA High Order Address Pin, SRAM (x8) I/Of I/O Configuration, Flash NC No Connection CEf Chip Enable Input, Flash Vccf Power, Flash OE Output Enable Input Vccs Power, SRAM WE Write Enable Input GND Ground I/Os I/O Configuration, SRAM Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) DEVICE BUS OPERATIONS User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM= Word Mode: I/Os = Vccs) OPERATION(1,3) Full Standby Output Disable Read from Flash(2) Write to Flash Read from SRAM Write to SRAM CEf CE1s H H H H L L L L L L H H H H H H X Temporary Sector Group Unprotection(4) Flash Hardware X Reset X Boot Block Sector X Write Protection CE2s OE WE SA(6) LBs UBs H X L L H X H X H X L L L L L L X X L H H X L X L X L H H H H H H X X X H X H H L L H H L L L X X X X X X H X H H H H L L H H H L L L X X X X X X X X X X X X X X X X X X X X X H X X X X X X L H L L H L X H X X X L X X X X X X X X X X X X X RESET WP/ACC(5) DQ0-DQ7 DQ8-DQ15 X X X H X X X X X X L L H L L H X High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT DIN DIN DOUT High-Z DOUT DIN High-Z DIN X High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT DIN DIN DOUT DOUT High-Z DIN DIN High-Z X VID(8) X X X X X X X X X X X X X X X X X X X X High-Z High-Z X High-Z High-Z X L L X X X L H H H H H H H H H H H H H H H H Notes: 1. 2. 3. 4. 5. Any operations not indicated this column are inhibited. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. It is also used for the extended sector group protections. WP/ACC = VIL: protection of boot sectors. WP/ACC = VIH: removal of boot sectors protection. WP/ACC = VACC (9V): Program time will reduce by 40%. 6. SA: Don't care or open. 7. L = VIL, H = VIH, X = VIL or VIH. 8. See DC CHARACTERISTICS. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 5 ISSI IS71VPCF16XS04 (R) DEVICE BUS OPERATIONS User Bus Operations (Flash=BYTE mode: I/Of = GND, SRAM= Word Mode: I/Os = Vccs) CEf CE1s OPERATION(1,3) Full Standby CE2s DQ15/A-1 OE WE SA(6) LBs UBs DQ0-DQ7 DQ8-DQ15 RESET WP/ACC(5) H H X X X X X X X High-Z High-Z H X H X L X X X X X X High-Z High-Z H X H L H X H H X X X High-Z High-Z H X H L H X X X X H H High-Z High-Z H X L H X A-1 H H X X X High-Z High-Z H X L X L A-1 H H X X X High-Z High-Z H X L H X A-1 L H X X X DOUT DOUT H X L X L A-1 L H X X X DOUT DOUT H X L H X A-1 H L X X X DIN DIN H X L X L A-1 H L X X X DIN DIN H X H L H X L H X L L DOUT DOUT H X H H L L H H X X L L H H X X H L L H High-Z DOUT DOUT High-Z H H X X H L H X X L X L L DIN DIN H X H H L L H H X X X X L L X X H L L H High-Z DIN DIN High-Z H H X X Temporary Sector Group Unprotection(4) X X X X X X X X X X X VID(8) X Flash Hardware Reset X X H X X L X X X X X X X X X X X X High-Z High-Z High-Z High-Z L L X X Boot Block Sector Write Protection X X X X X X X X X X X X L Output Disable Read from Flash (2) Write to Flash Read from SRAM Write to SRAM Notes: 1. 2. 3. 4. 5. Any operations not indicated this column are inhibited.. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. It is also used for the extended sector group protections. WP/ACC = VIL: protection of boot sectors. WP/ACC = VIH: removal of boot sectors protection. WP/ACC = VACC (9V): Program time will reduce by 40%. 6. SA: Don't care or open. 7. L = VIL, H = VIH, X = VIL or VIH. 8. See DC CHARACTERISTICS. 6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) DEVICE BUS OPERATIONS User Bus Operations (Flash=WORD mode: I/Of = Vccf, SRAM= Byte Mode: I/Os = GND CEf CE1s OPERATION(1,3) Full Standby CE2s OE WE SA LBs(6) UBs(6) DQ0-DQ7 DQ8-DQ15 RESET WP/ACC(5) H H X X X X X X High-Z High-Z H X H X L X X X X X High-Z High-Z H X H L H H H X X X High-Z High-Z H X H L H X X X H H High-Z High-Z H X L H X H H X X X High-Z High-Z H X L X L H H X X X High-Z High-Z H X L H X L H X X X DOUT DOUT H X L X L L H X X X DOUT DOUT H X L H X H L X X X DIN DIN H X L X L H L X X X DIN DIN H X H L H L H SA X X DOUT High-Z H X Write to SRAM H Temporary Sector X Group Unprotection(4) L X H X X X L X SA X X X X X DIN X High-Z X H VID(8) X X Flash Hardware Reset X X H X X L X X X X X X X X X X High-Z High-Z High-Z High-Z L L X X Boot Block Sector Write Protection X X X X X X X X X X X L Output Disable (2) Read from Flash Write to Flash Read from SRAM Notes: 1. Any operations not indicated this column are inhibited.. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. 4. It is also used for the extended sector group protections. 5. WP/ACC = VIL: protection of boot sectors. WP/ACC = VIH: removal of boot sectors protection. WP/ACC = VACC (9V): Program time will reduce by 40%. 6. LBs, UBs: Don't care or open. 7. L = VIL, H = VIH, X = VIL or VIH. 8. See DC CHARACTERISTICS. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 7 ISSI IS71VPCF16XS04 (R) DEVICE BUS OPERATIONS User Bus Operations (Flash=Byte mode: I/Of = GND, SRAM= Byte Mode: I/Os = GND) OPERATION(1,3) Full Standby CEf CE1s CE2s DQ15/A-1 OE WE SA LBs UBs (6) (6) DQ0-DQ7 DQ8-DQ15 RESET WP/ACC(5) H H X X X X X X X High-Z High-Z H X H X L X X X X X X High-Z High-Z H X H L H X H H X X X High-Z High-Z H X H L H X X X X H H High-Z High-Z H X L H X A-1 H H X X X High-Z High-Z H X L X L A-1 H H X X X High-Z High-Z H X L H X A-1 L H X X X DOUT DOUT H X L X L A-1 L H X X X DOUT DOUT H X L H X A-1 H L X X X DIN DIN H X L X L A-1 H L X X X DIN DIN H X H L H X L H SA X X DOUT High-Z H X Write to SRAM H Temporary Sector X Group Unprotection(4) L X H X X X X X L X SA X X X X X DIN X High-Z X H VID(8) X X Flash Hardware Reset X X H X X L X X X X X X X X X X X X High-Z High-Z High-Z High-Z L L X X Boot Block Sector Write Protection X X X X X X X X X X X X L Output Disable Read from Flash(2) Write to Flash Read from SRAM Notes: 1. 2. 3. 4. 5. Any operations not indicated this column are inhibited. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once. It is also used for the extended sector group protections. WP/ACC = VIL: protection of boot sectors. WP/ACC = VIH: removal of boot sectors protection. WP/ACC = VACC (9V): Program time will reduce by 40%. 6. LBs, UBs: Don't care or open. 7. L = VIL, H = VIH, X = VIL or VIH. 8. See DC CHARACTERISTICS. 8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH - TOP BOOT SECTOR ADDRESS Type Type H Sector Sector Address A19-A12 Sector Size (x8) KB/KW Address Range L K Type J Bank2 Bank2 Bank2 Bank2 SA0 00000xxx 64/32 000000h-00FFFFh 000000h-007FFFh Bank2 Bank2 Bank2 Bank2 SA1 00001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh Bank2 Bank2 Bank2 Bank2 SA2 00010xxx 64/32 020000h-02FFFFh 010000h-017FFFh Bank2 Bank2 Bank2 Bank2 SA3 00011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh Bank2 Bank2 Bank2 Bank2 SA4 00100xxx 64/32 040000h-04FFFFh 020000h-027FFFh Bank2 Bank2 Bank2 Bank2 SA5 00101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh Bank2 Bank2 Bank2 Bank2 SA6 00110xxx 64/32 060000h-06FFFFh 030000h-037FFFh Bank2 Bank2 Bank2 Bank2 SA7 00111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh Bank2 Bank2 Bank2 Bank2 SA8 01000xxx 64/32 080000h-08FFFFh 040000h-047FFFh Bank2 Bank2 Bank2 Bank2 SA9 01001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh Bank2 Bank2 Bank2 Bank2 SA10 01010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh Bank2 Bank2 Bank2 Bank2 SA11 01011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh Bank2 Bank2 Bank2 Bank2 SA12 01100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh Bank2 Bank2 Bank2 Bank2 SA13 01101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh Bank2 Bank2 Bank2 Bank2 SA14 01110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh Bank2 Bank2 Bank2 Bank2 SA15 01111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh Bank1 Bank2 Bank2 Bank2 SA16 10000xxx 64/32 100000h-10FFFFh 080000h-087FFFh Bank1 Bank2 Bank2 Bank2 SA17 10001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh Bank1 Bank2 Bank2 Bank2 SA18 10010xxx 64/32 120000h-12FFFFh 090000h-097FFFh Bank1 Bank2 Bank2 Bank2 SA19 10011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh Bank1 Bank2 Bank2 Bank2 SA20 10100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh Bank1 Bank2 Bank2 Bank2 SA21 10101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh Bank1 Bank2 Bank2 Bank2 SA22 10110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh Bank1 Bank2 Bank2 Bank2 SA23 10111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh Bank1 Bank1 Bank2 Bank2 SA24 11000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh Bank1 Bank1 Bank2 Bank2 SA25 11001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh Bank1 Bank1 Bank2 Bank2 SA26 11010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh Bank1 Bank1 Bank2 Bank2 SA27 11011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh Bank1 Bank1 Bank1 Bank2 SA28 11100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh Bank1 Bank1 Bank1 Bank2 SA29 11101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh Type Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 (x16) Address Range 9 ISSI IS71VPCF16XS04 (R) FLASH - TOP BOOT SECTOR ADDRESS (Continued) K Type J Type H Sector Sector Address A19-A12 Bank1 Bank1 Bank1 Bank2 SA30 11110xxx 64/32 1E0000h-1EFFFFh F0000h-F7FFFh Bank1 Bank1 Bank1 Bank1 SA31 11111000 8/4 1F0000h-1F1FFFh F8000h-F8FFFh Bank1 Bank1 Bank1 Bank1 SA32 11111001 8/4 1F2000h-1F3FFFh F9000h-F9FFFh Bank1 Bank1 Bank1 Bank1 SA33 11111010 8/4 1F4000h-1F6FFFh FA000h-FAFFFh Bank1 Bank1 Bank1 Bank1 SA34 11111011 8/4 1F6000h-1F7FFFh FB000h-FBFFFh Bank1 Bank1 Bank1 Bank1 SA35 11111100 8/4 1F8000h-1F9FFFh FC000h-FCFFFh Bank1 Bank1 Bank1 Bank1 SA36 11111101 8/4 1FA000h-1FBFFFh FD000h-FDFFFh Bank1 Bank1 Bank1 Bank1 SA37 11111110 8/4 1FC000h-1FDFFFh FE000h-FEFFFh Bank1 Bank1 Bank1 Bank1 SA38 11111111 8/4 1FE000h-1FFFFFh FF000h-FFFFFh Type Type L Sector Size (x8) KB/KW Address Range (x16) Address Range Note: The address range is A19:A-1 in byte mode (I/Of=VIL ) or A19:A0 in word mode (I/Of=VIH ). The bank address bits are A19-A15 for Type H, A19 - A17 for Type J, and A19 and A18 for Type K, and A19 for Type L. FLASH - TOP BOOT SECURITY SECTOR ADDRESSES (Hidden-ROM) Device Types H, J, K, L 10 Sector Address A19-A12 Size KB/KW (x8) Address Range (x16) Address Range 11111xxx 64/32 1F0000h-1FFFFFh F8000h-FFFFFh Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH - BOTTOM BOOT SECTOR ADDRESS P Type N Type M Sector Sector Address A19-A12 Sector Size (x8) KB/KW Address Range Bank 1 Bank1 Bank1 Bank1 SA0 00000000 8/4 000000h-001FFFh 000000h-000FFFh Bank1 Bank1 Bank1 Bank1 SA1 00000001 8/4 002000h-003FFFh 001000h-001FFFh Bank1 Bank1 Bank1 Bank1 SA2 00000010 8/4 004000h-005FFFh 002000h-002FFFh Bank1 Bank1 Bank1 Bank1 SA3 00000011 8/4 006000h-007FFFh 003000h-003FFFh Bank1 Bank1 Bank1 Bank1 SA4 00000100 8/4 008000h-009FFFh 004000h-004FFFh Bank1 Bank1 Bank1 Bank1 SA5 00000101 8/4 00A000h-00BFFFh 005000h-005FFFh Bank1 Bank1 Bank1 Bank1 SA6 00000110 8/4 00C000h-00DFFFh 006000h-006FFFh Bank1 Bank1 Bank1 Bank1 SA7 00000111 8/4 00E000h-00FFFFh 007000h-007FFFh Bank1 Bank1 Bank1 Bank2 SA8 00001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh Bank1 Bank1 Bank1 Bank2 SA9 00010xxx 64/32 020000h-02FFFFh 010000h-017FFFh Bank1 Bank1 Bank1 Bank2 SA10 00011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh Bank1 Bank1 Bank2 Bank2 SA11 00100xxx 64/32 040000h-04FFFFh 020000h-027FFFh Bank1 Bank1 Bank2 Bank2 SA12 00101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh Bank1 Bank1 Bank2 Bank2 SA13 00110xxx 64/32 060000h-06FFFFh 030000h-037FFFh Bank1 Bank1 Bank2 Bank2 SA14 00111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh Bank1 Bank2 Bank2 Bank2 SA15 01000xxx 64/32 080000h-08FFFFh 040000h-047FFFh Bank1 Bank2 Bank2 Bank2 SA16 01001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh Bank1 Bank2 Bank2 Bank2 SA17 01010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh Bank1 Bank2 Bank2 Bank2 SA18 01011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh Bank1 Bank2 Bank2 Bank2 SA19 01100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh Bank1 Bank2 Bank2 Bank2 SA20 01101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh Bank1 Bank2 Bank2 Bank2 SA21 01110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh Bank1 Bank2 Bank2 Bank2 SA22 01111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh Bank2 Bank2 Bank2 Bank2 SA23 10000xxx 64/32 100000h-10FFFFh 080000h-087FFFh Bank2 Bank2 Bank2 Bank2 SA24 10001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh Bank2 Bank2 Bank2 Bank2 SA25 10010xxx 64/32 120000h-12FFFFh 090000h-097FFFh Bank2 Bank2 Bank2 Bank2 SA26 10011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh Bank2 Bank2 Bank2 Bank2 SA27 10100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh Bank2 Bank2 Bank1 Bank2 SA28 10101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh Bank2 Bank2 Bank1 Bank2 SA29 10110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh Type Type Q Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 (x16) Address Range 11 ISSI IS71VPCF16XS04 (R) FLASH - BOTTOM BOOT SECTOR ADDRESS (Continued) Sector Sector Address A19-A12 Sector Size (x8) KB/KW Address Range P Bank2 Bank2 Bank2 Bank2 SA30 10111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh Bank2 Bank2 Bank2 Bank2 SA31 11000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh Bank2 Bank2 Bank2 Bank2 SA32 11001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh Bank2 Bank2 Bank2 Bank2 SA33 11010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh Bank2 Bank2 Bank2 Bank2 SA34 11011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh Bank2 Bank2 Bank2 Bank2 SA35 11100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh Bank2 Bank2 Bank2 Bank2 SA36 11101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh Bank2 Bank2 Bank2 Bank2 SA37 11110xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh Bank2 Bank2 Bank2 Bank2 SA38 11111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh Q Type Type M Type N Type (x16) Address Range Note: The address range is A19:A-1 in byte mode (I/Of=VIL ) or A19:A0 in word mode (I/Of=VIH ). The bank address bits are A19-A15 for Type M, A19 - A17 for Type N, and A19 - A18 for Type P, and A19 for Type Q. FLASH - BOTTOM BOOT SECURITY SECTOR ADDRESSES (Hidden-ROM) Device Types M,N,P,Q 12 Sector Address A19-A12 Size KB/KW (x8) Address Range (x16) Address Range 00000xxx 64/32 000000h-00FFFFh 00000h-07FFFh Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) SECTOR GROUP ADDRESS (TYPE H, TYPE J, TYPE K, TYPE L) (Top Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 SGA1 0 0 0 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 SGA8 1 1 1 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 X X X SA0 X X X SA1 to SA3 X X X X X X X X X X X X X X X X X X SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 X X X SA28 to SA30 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 13 ISSI IS71VPCF16XS04 (R) SECTOR GROUP ADDRESS (TYPE M, TYPE N, TYPE P, TYPE Q) (Bottom Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 1 1 1 SA7 0 1 1 0 X X X SA8 to SA10 1 1 SGA8 0 0 0 SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 0 0 0 1 X X X SA35 to SA37 1 0 1 1 X X X SA38 SGA15 SGA16 14 1 1 1 1 1 1 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH MEMORY AUTOSELECT CODES Type A12 to A19 A6 A1 A0 A-1(1) Code (HEX) Manufacturer's Code X VIL VIL VIL VIL 04h Byte X VIL VIL VIH VIL 36h Word X VIL VIL VIH X 2236h Byte X VIL VIL VIH VIL 39h Word X VIL VIL VIH X 2239h Byte X VIL VIL VIH VIL 2Dh Word X VIL VIL VIH X 222Dh Byte X VIL VIL VIH VIL 2Eh Word X VIL VIL VIH X 222Eh Byte X VIL VIL VIH VIL 28h Word X VIL VIL VIH X 2228h Byte X VIL VIL VIH VIL 2Bh Word X VIL VIL VIH X 222Bh Byte X VIL VIL VIH VIL 33h Word X VIL VIL VIH X 2233h Byte X VIL VIL VIH VIL 35h Word X VIL VIL VIH X 2235h Sector VIL VIH VIL VIL 01h(2) TYPE H Device ID TYPE M Device ID TYPE J Device ID TYPE N Device ID TYPE K Device ID TYPE P Device ID TYPE L Device ID TYPE Q Device ID Sector Group Protect Group Address Note: 1. A-1 is only used for Byte mode. 2. Output 01h at protected sector address and output 00h at unprotected sector address. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 15 ISSI IS71VPCF16XS04 (R) FLASH MEMORY COMMAND DEFINITIONS Command Sequence Bus Bus Write Cycle Req'd Read / Reset First Bus Cycle Second Bus Write Cycle Third Bus Write Cycle Addr. Data Addr. Data Addr. XXXH F0H -- -- -- Fourth Bus Read/Write Data Addr. Data -- -- -- Fifth Bus Cycle Addr. Sixth Bus Cycle Data Addr. Data -- -- -- -- Read / Reset * 1 Word Byte 1 555H AAAH AAH 2AAH 555H 55H 555H AAAH F0H RA RD -- -- -- -- Autoselect Word Byte 3 555H AAAH AAH 2AAH 555H 55H (BA) 555H (BA) AAAH 90H -- -- -- -- -- -- Program Word Byte 3 555H AAAH AAH 2AAH 555H 55H 555H AAAH A0H PA PD -- -- -- -- Chip Erase Word Byte 4 555H AAAH AAH 2AAH 555H 55H 555H AAAH 80H 555H AAAH AAH 2AAH 555H 55H 555H AAAH 10H Sector Erase Word Byte 6 555H AAAH AAH 2AAH 555H 55H 555H AAAH 80H 555H AAAH AAH 2AAH 555H 55H SA 30H Sector Erase Suspend Word Byte 1 BA B0H -- -- -- -- -- -- -- -- -- -- Sector Erase Resume Word Byte 1 BA 30H -- -- -- -- -- -- -- -- -- -- Set to Fast Mode Word Byte 3 555H AAH AAH 2AAH 555H 55H 555H AAAH 20H -- -- -- -- -- -- Fast Program * 2 Word Byte 2 XXXH A0H PA PD -- -- -- -- -- -- -- -- Reset from Fast Mode * 2 Word Byte 2 BA 90H XXXH F0H*6 -- -- -- -- -- -- -- -- Extended Sector Group Protection *3 Word Byte 4 XXXH 60H SPA 60H SPA 40H SPA SD -- -- -- -- Query * 4 Word Byte 1 55H AAH 98h -- -- -- -- -- -- -- -- -- -- Hidden-ROM Entry Word Byte 3 555H AAAH AAh 2AAH 555H 55H 555H AAAH 88H -- -- -- -- -- -- Hidden-ROM Program *5 Hidden-ROM Erase *5 Word Byte 4 555H AAAH AAH 2AAH 555H 55H 555H AAAH A0H PA PD -- -- -- -- Word Byte 6 555H AAAH AAH 2AAH 555H 55H 555H AAAH 80H 555H AAAH AAH 2AAH 555H 55H HRA 30H Hidden-Rom Exit *5 Word Byte 4 555H AAAH AAH 2AAH 555H 55H (HRBA) 555H 90H (HRBA) AAAH XXXH 00H -- -- -- -- Note: *1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid during Fast Mode. *3: This command is valid while RESET=VID. *4: The valid Address is A0 to A6. *5: This command is valid during Hi-ROM mode. *6: The data "00h" is also acceptable. 16 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 Address bits A12 to A19 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA),and Bank Address (BA). Bus operations are defined in "Device Bus Operations". RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19 , A18 , A17 , A16 , A15 , A14 , A13 , and A12 will uniquely select any sector. BA = Bank address (A15 to A19 ) SPA = Sector group address to be protected. Set sector group address (SGA) and (A6 , A1 , A0 ) = (0, 1, 0) for protect; or SGA and (A6, A1, A0) = (1,1,0) for unprotect. (R) Type M, Type N, Type P, Type Q (Bottom Boot Type) Word mode: 000000h to 007FFFh Byte mode: 000000h to 00FFFFh HRBA = Bank address of the Hidden-ROM area Type H, Type J, Type K, Type L (Top Boot Type) : A15 = A16 = A17 = A18 = A19 = 1 Type M, Type N, Type P, Type Q (Bottom Boot Type) : A15 = A16 = A17 = A18 = A19 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. The system should generate the following address patterns; Word mode : 555h or 2AAh to addresses A0 to A10 Byte mode : AAAh or 555h to addresses A-1 and A0 to A10 HRA= Address of the Hidden-ROM area Type H, Type J, Type K, Type L (Top Boot Type) Word mode: 0F8000h to 0FFFFFh Byte mode: 1F0000h to 1FFFFFh MCP ABSOLUTE MAXIMUM RATINGS(1,2,3) Symbol Parameter TBIAS Temperature Under Bias TSTG Storage Temperature PD Power Dissipation IOUT Output Current (per I/O) VIN, VOUT Voltage Relative to GND for Data, Address and Control Pins Value -25 to +85 -55 to +125 1.6 100 -0.3 to VCCf + 0.4 -0.3 to VCCs + 0.4 Unit C C W mA V V VIN RESET(5) -0.5 TO +13.0 V VIN WP/ACC -0.5 TO +10.5 V -0.3 to 4.0 V (6) VCCf/VCCs Voltage on Vcc Supply Relative to GND(4) Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 4. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. 5. Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pin may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. 6. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0V for periods of up to 20 ns, when VCCf is applied. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 17 ISSI IS71VPCF16XS04 (R) MCP OPERATING RANGE Range Industrial Ambient Temperature -25C to +85C VCCF,VCCS 2.7-3.3V STANDARD VOLTAGE RANGE VCC = 2.7-3.3 V Max Access Time CE Access OE Access FLASH MEMORY 70 85 70 85 30 40 SRAM 70 85 70 85 35 45 UNITS ns ns ns CAPACITANCE(1) Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 11 14 pF COUT Output Capacitance VOUT = 0V 12 16 pF CIN2 Control Pin Capacitance VIN = 0V 14 16 pF CIN3 WP/ACC Pin Capacitance VIN = 0V 17 20 pF Notes: 1. Test conditions: TA = 25C, f = 1 MHz 18 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) MCP DC CHARACTERISTICS Symbol Parameter Test Conditions Min. Max. Unit ILI ILO VIL Input Leakage Output Leakage Input Low Level VIN=VSS to VCCf, VCCs VOUT=VSS to VCCf, VCCs -1.0 -1.0 -0.2 1.0 1.0 0.5 A A V VIH Input High Level 2.4 VCC + 0.3(2) V VID Voltage for Sector Protection, and Temporary Sector Unprotection (RESET)(1) 11.5 12.5 V VACC Voltage for Program Acceleration ( WP/ACC)(1) 8.5 9.5 V VOL Output Low Level VCCf = VCCf min., VCCS=VCCS min. IOL = 1.0mA -- 0.45 V VOH Output High Level VCCf = VCCf min., VCCS=VCCS min. IOH = -0.5mA 2.4 -- V VLKO Flash Low Vccf 2.3 2.5 V Notes: 1. Applicable for only VCCf applying. 2. VCC indicates lower of VCCf or VCCs. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 19 ISSI IS71VPCF16XS04 (R) FLASH DC CHARACTERISTICS Symbol Parameter ILIT RESET Inputs Leakage Current ILIA ACC Inputs Leakage Current FLASH Vcc (1) ICC1f Active Current (Read) ICC2f ICC3f ICC4f ICC5f ISB1f Test Conditions Min. VCCf=VCCf max., VCCs=VCCs max. -- RESET = 12.5V VCCf=VCCf max., VCCs=VCCs max. -- WP/ACC = Vacc max. CEf=VIL tCycle = 5Mhz Byte -- OE=VIH tCycle = 5Mhz Word -- tCycle = 1Mhz Byte -- tCycle = 1Mhz Word -- FLASH Vcc Active(2) CEf=VIL -- Current(Program/Erase) OE=VIH FLASH Vcc Active(4) CEf=VIL Byte -- Current OE=VIH Word (Read-While-Program) FLASH Vcc Active(4) CEf=VIL Byte -- Current OE=VIH Word (Read-While-Erase) FLASH Vcc Active CEf=VIL -- Current OE=VIH (Erase-Suspend-Program) FLASH Vcc VCCf = Vcc max, CEf= VCCf = + 0.3V -- Standby Current RESET, CEf, WP/ACC = VCCf = + 0.3V Max. 35 Unit A 20 A 13 15 7 7 35 mA 48 50 mA 48 50 mA 35 mA 5 A mA ISB2f FLASH Vcc Standby Current (RESET) VCCf = Vcc max, RESET= VSS = + 0.3V WP/ACC = VCCf = + 0.3V -- 5 A ISB3f FLASH Vcc(3) Standby Current (Auto Sleep Mode) VCCf = Vcc max. CEf, = VSS = + 0.3V RESET, WP/ACC = VCCf = + 0.3V VIN = VCCf + 0.3V OR VSS + 0.3V -- 5 A Notes: 1. 2. 3. 4. 20 The ICC current listed includes both the DC operating current and the frequency dependent component. ICC active while Embedded Algorithm (program or erase) is in progress. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.. Embedded Algorithm (program or erase) is in progress. (@5 MHz) Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) AC CHARACTERISTICS - CE TIMING JEDEC Symbol Standard Symbol Condition Min Unit CE Recover Time -- tCCR -- 0 ns CE Hold Time -- tCHOLD -- 3 ns Parameter TIMING DIAGRAM FOR ALTERNATING SRAM TO FLASH CEf tCCR tCCR CE1s WE tCHOLD tCCR tCHOLD tCCR CE2s Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 21 ISSI IS71VPCF16XS04 (R) FLASH READ ONLY SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter Min. tRC Cycle Time 70 tACC Address to Output Delay -- tCE Chip Enable to Output Delay tOE Max. Min. Max. Unit 85 -- ns 70 -- 85 ns -- 70 -- 85 ns Output Enable to Output Delay -- 30 -- 35 ns tDF Chip Enable to Output High-Z -- 25 -- 30 ns tDF Output Enable to Output High-Z -- 25 -- 30 ns tOH Output Hold Time from Addresses, CEf or OE, Whichever Occurs First 0 -- 0 -- ns tREADY RESET Pin Low to Read Mode -- 20 -- 20 s FLASH AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 22 Unit 0V to 3.0V 5 ns 1.5V 1 TTL gate and 30pF Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH READ CYCLE tRC Address Stable ADDRESS tACC CEf tDF tOE OE tOEH WE DQ tCE High-Z Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 tOH Output valid High-Z 23 ISSI IS71VPCF16XS04 (R) FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM tRC Address Stable ADDRESS tACC CEf tRH tRP RESET tRH tCE tOH DQ 24 High-Z Output valid Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH ERASE/PROGRAM OPERATION CHARACTERISTICS (Over Operating Range) Symbol tWC tAS tASO tAH tAHT tDS tDH tOES tOEH tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH1 tWHWH2 tVCS Note: Parameter Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Output Enable Hold Time Toggle and Data Polling CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Word Programming Operation Sector Erase Operation (1) VCCf Setup Time -70 ns Min. Max. -85ns Min. Max. Unit 70 0 12 - 85 0 15 - ns ns ns 45 0 - 45 0 - ns ns 30 0 0 0 10 - 35 0 0 0 10 - ns ns ns ns ns 20 20 0 0 0 0 0 0 30 30 25 25 50 12 15 0.7 - 20 20 0 0 0 0 0 0 35 35 30 30 50 15 20 1 - ns ns ns ns ns ns ns ns ns ns ns ns s s s s 1. This does not include the preprogramming time. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 25 ISSI IS71VPCF16XS04 (R) FLASH ERASE/PROGRAM OPERATION CHARACTERISTICS (Continued) (Over Operating Range) Symbol tVLHT tVIDR tVACCA tRB tRP tEOE tRH tBUSY tTOW tSPD -70 ns Min. Max. Parameter (2) Voltage Transition Time Rise Time to VID(2) Rise Time to VACC Recovery Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time (3) Erase Suspend Transition Time (4) 4 500 500 0 500 200 50 - 70 90 20 -85ns Min. Max. Unit 4 500 500 0 500 200 50 - 85 90 20 s ns ns ns ns ns ns ns s s Note: 2. This timing is for Sector Protection Operation. 3. The time between writes must be less than "tTOW " otherwise that command will not be accepted and erasure will start. A time-out or "tTOW " from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command(s). 4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD " to suspend the erase operation. 26 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH WRITE CYCLE (WE Control) Data Polling 3rd Bus Cycle 555h ADDRESS PA PA tWC tAS tSH tRC CEf tCS OE tGHWL tCH tWP tWPH tDS tDH tCE tOE tWHWH1 WE DQ A0h tDF PD DQ7 Dout tOH Dout Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x16 mode (the addresses differ from x8 mode, i.e. AAAh). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 27 ISSI IS71VPCF16XS04 (R) FLASH WRITE CYCLE (CEf Control) Data Polling 3rd Bus Cycle 555h ADDRESS CEf PA tWC tWS OE tGHEL tAS PA tAH tWH tCP tCPH tDS tDH tWHWH1 WE DQ PD A0h DQ7 Dout Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the x16 mode (the addresses differ from x8 mode, i.e. AAAh). 28 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS 555h ADDRESS 2AAh 555h 555h 2AAh SA* tWC tAS tAH CEf tCH tCS OE tWP tWPH tGHWL WE tDS tDH AAh DQ 30h for Sector Erase 55h 80h AAh 55h 10h/ 30h tVCS Vccf *SA is the sector address for Sector Erase. Address = 555h for Chip Erase. Note: These waveforms are for the x16 mode (the addresses differ from x8 mode: AAAh, 555h, AAAh, AAAh, 555h, SA*). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 29 ISSI IS71VPCF16XS04 (R) FLASH AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALOGRITHM OPERATIONS CEf tCH OE tOE tDF tOEH WE DQ tCEf DQ7 Data In DQ7 = Valid Data High - Z tWHWH1 or 2 DQ0/DQ6 Data In DQ0 to DQ6 = Output Flag DQ0 to DQ6 Valid Data High - Z tEOE tBUSY RY/BY *DQ7 = Valid Data (the device has completed the Embedded operation.) 30 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH AC WAVEFORMS FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS ADDRESS tAHT tASO CEf tAHT tAS tCEPH WE tOEH tOEH tOEPH OE tDH DQ6/DQ2 Data tOE Toggle Data tCEf* Toggle Data Toggle Data Toggle Data Output Valid tBUSY RY/BY * DQ6 stops toggling (the device has completed the Embedded operation). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 31 ISSI IS71VPCF16XS04 (R) FLASH BACK-TO-BACK READ/WRITE TIMING DIAGRAM Read ADDRESS tWC Read tRC Command tRC Command BA1 BA2 (555h) BA1 BA2 (PA) tAS tWC Read tRC Read tRC BA1 BA2 (PA) tACC tAH tAS tCE tAHT CEf tCEPH tOE OE tGHWL tWP tDF tOEH WE tDS DQ Valid Output Valid Input (A0h) tDH tDF Valid Output Valid Input Valid Output Status (PD) Note: This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2. 32 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH RY/BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS CEf The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY FLASH RESET RY/BY TIMING DIAGRAM WE RESET tRP tRB RY/BY tREADY Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 33 ISSI IS71VPCF16XS04 (R) FLASH TEMPORARY SECTOR GROUP UNPROTECTION VCCf VIDR tVLHT tVCS VID VIH RESET CEf WE tVLHT RY/BY Program or Erase Command Sequence tVLHT Unprotection Period 34 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) FLASH ACCELERATED PROGRAM VCCf tVCS tVACCR tVLHT VACC VIH WP/ACC CEf WE tVLHT RY/BY Program Command Sequence tVLHT Acceleration Period Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 35 ISSI IS71VPCF16XS04 (R) FLASH EXTENDED SECTOR GROUP PROTECTION Vccf tVCS VLHT RESET tWC tWC VIDR SGAX SGAX ADDRESS SGAY A0 A1 A6 CEf OE tWP TIME-OUT WE tOE Data 60h 60h 40h 01h 60h SGAx: Sector Group Address to be protected. SGAy: Next Group Sector Address to be protected UNPROTECTION: Implement with A6 = 1, A1 = 1, A0 = 0. Time-out approximately 15 ms. TIME-OUT : Time-Out window = 250 s (Min.) 36 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) SRAM POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC Vcc Dynamic Operating Supply Current ICC1 Operating Supply Current ISB CMOS Standby Current (CMOS Inputs) Test Conditions VCCS = Max., IOUT = 0 mA, f = fMAX VCCS = Max., IOUT = 0 mA, f = 0 VCCS = Max., CE1s VCCS - 0.2V, CE2s 0.2V, VIN VCCS - 0.2V, or VIN 0.2V, f = 0 Min. -- Max. 40 Unit mA -- 8 mA -- 7 A Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. SRAM READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 70 ns Symbol Parameter Min. Max. 85ns Min. Max. Unit tRC Read Cycle Time 70 -- 85 -- ns tAA Address Access Time -- 70 -- 85 ns tOHA Output Hold Time 10 -- 10 -- ns tACE1 CE1s Access Time -- 70 -- 85 ns OE Access Time -- 35 -- 45 ns OE to High-Z Output -- 25 -- 35 ns tLZOE(2) OE to Low-Z Output 5 -- 5 -- ns (2) tHZCE1 CE1s to High-Z Output 0 25 0 35 ns tLZCE1 (2) CE1s to Low-Z Output 10 -- 10 -- ns tBA LBs, UBs Access Time -- 70 -- 85 ns tHZB LBs, UBs to High-Z Output 0 25 0 50 ns tLZB LBs, UBs to Low-Z Output 0 -- 0 -- ns tDOE tHZOE (2) Notes: 1. See SRAM AC TEST CONDITIONS. 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 37 ISSI IS71VPCF16XS04 (R) SRAM AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 3.0V 5 ns 1.5V 1 TTL gate and 30pF AC WAVEFORMS SRAM READ CYCLE NO. 1(1,2) (Address Controlled) (CE1S = OE = VIL, UBs or LBs = VIL) tRC ADDRESS tAA tOHA DOUT 38 PREVIOUS DATA VALID tOHA DATA VALID Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) AC WAVEFORMS SRAM READ CYCLE NO. 2(1,3) (CE1S, OE, AND UBs/ LBs Controlled) tRC ADDRESS tAA tOHA OE tDOE CE1s tHZOE tLZOE tACE1/tACE2 CE2s tLZCE1/ tLZCE2 tHZCE1 LBs, UBs tBA tHZB tLZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, UBs, or LBs = VIL. 3. Address is valid prior to or coincident with CE1 LOW transition. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 39 ISSI IS71VPCF16XS04 (R) WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 70ns Symbol Parameter Min. Max. 85ns Min. Max. Unit tWC Write Cycle Time 70 -- 85 -- ns tSCE1 tAW CE1s to Write End 60 -- 70 -- ns Address Setup Time to Write End 60 -- 70 -- ns tHA tSA Address Hold from Write End 0 -- 0 -- ns Address Setup Time 0 -- 0 -- ns tPWB tPWE LBs,UBs Valid to End of Write 60 -- 70 -- ns WE Pulse Width 50 -- 60 -- ns tSD tHD Data Setup to Write End 30 -- 35 -- ns Data Hold from Write End 0 -- 0 -- ns WE LOW to High-Z Output -- 25 -- 35 ns WE HIGH to Low-Z Output 0 -- 0 -- ns tHZWE tLZWE(3) (3) Notes: 1. See SRAM AC TEST CONDITIONS. 2. The internal write time is defined by the overlap of CE1 LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 40 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) AC WAVEFORMS SRAM WRITE CYCLE NO. 1(1,2) (CE1S Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCE1 CE1s tSCE2 CE2s tAW tPWE(4) WE LBs, UBs tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE1s and WE inputs and at least one of the LBs and UBs inputs being in the LOW state. 2. WRITE = (CE1s) [ (LBs) = (UBs) ] (WE). Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 41 ISSI IS71VPCF16XS04 (R) AC WAVEFORMS SRAM WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCE1 CE1s tSCE2 CE2s tAW tPWE1, 2 WE LBs, UBs tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 42 tHD DATA-IN VALID Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) AC WAVEFORMS SRAM WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCE1 CE1s tSCE2 CE2s tAW tPWE1, 2 WE LBs, UBs tSA DOUT DATA UNDEFINED t HZWE tLZWE HIGH-Z tSD DIN DATA-IN VALID Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 tHD 43 ISSI IS71VPCF16XS04 (R) WRITE CYCLE NO. 4 (UBs/LBs Controlled, CE1s is LOW, CE2s is HIGH) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA t HA t HA t SA WE UBs, LBs t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps 44 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) SRAM DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.3 V IDR Data Retention Current Vcc = 1.5V, CS1 Vcc - 0.2V -- 7 A tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 -- ns Recovery Time See Data Retention Waveform tRC -- ns SRAM DATA RETENTION WAVEFORM (CE1 Controlled) tSDR Data Retention Mode tRDR VCC 2.7V 2.5V VDR CE1s GND CE1s VCC - 0.2V Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 45 ISSI IS71VPCF16XS04 (R) MINI BALL GRID ARRAY - 69-Ball BGA PACKAGE CODE: F - 8.0 mm x 11.0 mm Body, 0.8 mm Ball Pitch o 0.45 + 0.10/-0.05 (73X) 1 2 3 4 5 6 7 8 9 10 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K A B C D E F G H J K e D D1 e E1 E A1 A SEATING PLANE Symbol Min. Typ. Max. Units A -- -- 1.40 mm A1 0.28 0.38 0.48 mm D 11.50 11.00 11.10 mm D1 -- 7.20 -- mm E 7.90 8.00 8.10 mm E1 -- 7.20 -- mm e -- 0.80 -- mm 46 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 ISSI IS71VPCF16XS04 (R) PART NUMBER LOGIC IS 71 X XX F XX X S XX -- XXXX X X ISSI Prefix Product Family: Flash/SRAM MCP Voltage : V = 3.0 Center Voltage SRAM Data Bus Width: 08, 16, or PC (pin configurable) Flash Label Flash Density (Mbit) Flash Organization : A = Type A - Top Boot Block (Bank1: 4Mbit, Bank2: 28Mbit) B = Type B - Top Boot Block (Bank1: 8Mbit, Bank2: 24Mbit) C = Type C - Top Boot Block (Bank1: 16Mbit, Bank2: 16Mbit) D = Type D - Bottom Boot Block (Bank1: 4Mbit, Bank2: 28Mbit) E = Type E - Bottom Boot Block (Bank1: 8Mbit, Bank2: 24Mbit) F = Type F - Bottom Boot Block (Bank1: 16Mbit, Bank2: 16Mbit) G = User Configurable Bank Grouping H = Type H - Top Boot Block (Bank1: 0.5Mbit, Bank2: 15.5Mbit) J = Type J - Top Boot Block (Bank1: 2Mbit, Bank2: 14Mbit) K = Type K - Top Boot Block (Bank1: 4Mbit, Bank2: 12Mbit) L = Type L - Top Boot Block (Bank1: 8Mbit, Bank2: 8Mbit) M = Type M - Bottom Boot Block (Bank1: 0.5Mbit, Bank2: 15.5Mbit) N = Type N - Bottom Boot Block (Bank1: 2Mbit, Bank2: 14Mbit) P = Type P - Bottom Boot Block (Bank1: 4Mbit, Bank2: 12Mbit) Q = Type Q - Bottom Boot Block (Bank1: 8Mbit, Bank2: 8Mbit) SRAM Label SRAM Density (Mbit) Speed : 8570 = 85ns Flash, 70ns SRAM 7070 = 70ns Flash, 70ns SRAM 8585 = 85ns Flash, 85ns SRAM 7085 = 70ns Flash, 85ns SRAM Package: A = 101-ball BGA B = 73-ball BGA F = 69-ball BGA Temperature Grade: Blank = Commercial I = Industrial Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02 47 ISSI IS71VPCF16XS04 (R) ORDERING INFORMATION Industrial Range: -25C to +85C Order Part No. SRAM Data Bus Boot Section Flash Bank Flash Speed Organization (ns) SRAM Speed (ns) Package IS71VPCF16HS04-8585FI 8/16 Top 0.5Mb, 15.5Mb 85 85 69-ball BGA IS71VPCF16JS04-8585FI 8/16 Top 2Mb, 14Mb 85 85 69-ball BGA IS71VPCF16KS04-8585FI 8/16 Top 4Mb, 12Mb 85 85 69-ball BGA IS71VPCF16LS04-8585FI 8/16 Top 8Mb, 8Mb 85 85 69-ball BGA IS71VPCF16MS04-8585FI 8/16 Bottom 0.5Mb, 15.5Mb 85 85 69-ball BGA IS71VPCF16NS04-8585FI 8/16 Bottom 2Mb, 14Mb 85 85 69-ball BGA IS71VPCF16PS04-8585FI 8/16 Bottom 4Mb, 12Mb 85 85 69-ball BGA IS71VPCF16QS04-8585FI 8/16 Bottom 8Mb, 8Mb 85 85 69-ball BGA 48 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00C 06/14/02