GS816018/32/36BT-250/200/150 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs * FT pin for user-configurable flow through or pipeline operation * Single Cycle Deselect (SCD) operation * 2.5 V or 3.3 V +10%/-10% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 100-lead TQFP package * RoHS-compliant 100-lead TQFP package available Functional Description Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Ne w De sig Applications The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. ct Features 250 MHz-150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O n-- Di sco nt inu ed Pr od u 100-Pin TQFP Commercial Temp Industrial Temp No t Re co m me nd ed for Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.05 9/2008 Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816018/32/36BT operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -250 -200 -150 Unit tKQ tCycle 2.5 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x32/x36) 295 345 245 285 200 225 mA mA tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 225 255 200 220 185 205 mA mA 1/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 n-- Di sco nt inu ed Pr od u ct A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816018B 100-Pin TQFP Pinout NC NC NC Ne w me nd ed for A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC De sig VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.05 9/2008 2/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 n-- Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816032B 100-Pin TQFP Pinout NC DQC DQC VDDQ Ne w me nd ed for NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.05 9/2008 3/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 n-- Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS816036B 100-Pin TQFP Pinout DQPC DQC DQC VDDQ Ne w me nd ed for DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA A A A A1 A0 NC NC VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either VDD or VSS. These pins can also be left floating. Rev: 1.05 9/2008 4/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 TQFP Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O n-- Di sco nt inu ed Pr od u ct Symbol Data Input and Output pins NC No Connect BW I Byte Write--Writes all enabled bytes; active low BA, BB, BC, BD I Byte Write Enable for DQA, DQB Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable--Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I G I ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I LBO I VDD I VSS I VDDQ I Chip Enable; active high De sig Output Enable; active low me nd ed for Ne w Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground No t Re co m Output driver power supply Rev: 1.05 9/2008 5/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 GS816018/32/36B Block Diagram Register D Q A0 A0 D0 Q0 A1 D1 Q1 Counter Load n-- Di sco nt inu ed Pr od u A1 ct A0-An A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q Register D D 36 Q BB 36 D Ne w D Q Register BD Q Register D De sig Q BC Q Register D Register 4 Register me nd ed for D Q Register E1 E2 E3 D Q Register FT G 1 Power Down No t ZZ Q Re co m D Control DQx1-DQx9 Note: Only x36 version shown for simplicity. Rev: 1.05 9/2008 6/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Byte Write Truth Table GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L H H H Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 n-- Di sco nt inu ed Pr od u ct Function 2, 3 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x32 and x36 versions. Rev: 1.05 9/2008 7/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Synchronous Truth Table E1 None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X H Read Cycle, Begin Burst External R L Read Cycle, Begin Burst External R L Write Cycle, Begin Burst External W L Read Cycle, Continue Burst Next CR X Read Cycle, Continue Burst Next CR H Write Cycle, Continue Burst Next CW Write Cycle, Continue Burst Next CW Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Current ADSP ADSC ADV W DQ3 H X L X X High-Z L X X L X X High-Z X H L X X X High-Z L X L X X X High-Z X X X L X X High-Z H L L X X X Q H L H L X F Q H L H L X T D X X H H L F Q X X X H L F Q X X X H H L T D H X X X H L T D X X X H H H F Q H X X X H H F Q X X X H H H T D H X X X H H T D Ne w me nd ed for Write Cycle, Suspend Burst E3 X De sig Deselect Cycle, Power Down E2 ct Operation n-- Di sco nt inu ed Pr od u State Address Diagram Used Key No t Re co m Notes: 1. X = Don't Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.05 9/2008 8/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Simplified State Diagram ct X W R R R First Write CR De sig CW Ne w W First Read X CR R R X Burst Write me nd ed for Simple Burst Synchronous Operation Simple Synchronous Operation W X n-- Di sco nt inu ed Pr od u Deselect Burst Read X CR CW CR No t Re co m Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.05 9/2008 9/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Simplified State Diagram with G ct X W R W X n-- Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.05 9/2008 10/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins -0.5 to 4.6 V VDDQ Voltage in VDDQ Pins -0.5 to 4.6 VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n-- Di sco nt inu ed Pr od u ct Symbol V -0.5 to VDDQ +0.5 V -0.5 to VDD +0.5 V +/-20 mA +/-20 mA 1.5 W -55 to 125 o -55 to 125 o C C De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage Ne w Power Supply Voltage Ranges VDD3 3.0 3.3 3.6 V VDD2 2.3 2.5 2.7 V me nd ed for 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. Rev: 1.05 9/2008 11/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ -0.3 -- 0.8 V 1,3 n-- Di sco nt inu ed Pr od u Parameter ct VDDQ3 Range Logic Levels Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Parameter Symbol Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD -- VDD + 0.3 V 1 VDD Input Low Voltage VIL -0.3 -- 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD -- VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage -0.3 -- 0.3*VDD V 1,3 De sig Min. Ne w VDDQ2 Range Logic Levels VILQ me nd ed for Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 C 2 Ambient Temperature (Industrial Range Versions) TA -40 25 85 C 2 Re co m Parameter No t Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. Rev: 1.05 9/2008 12/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 50% tKC VDD +1.5 V VSS n-- Di sco nt inu ed Pr od u 50% ct 50% VDD VSS - 2.0 V 50% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF AC Test Conditions Conditions Input high level VDD - 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output load me nd ed for Output reference level Ne w Parameter De sig Note: These parameters are sample tested. VDDQ/2 Fig. 1 Output Load 1 DQ No t Re co m Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. 50 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.05 9/2008 13/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD -1 uA 1 uA ZZ Input Current IIN1 VDD VIN VIH 0 V VIN VIH FT Input Current IIN2 Output Leakage Current IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA VDD VIN VIL 0 V VIN VIL -100 uA -1 uA 1 uA 1 uA Output Disable, VOUT = 0 to VDD -1 uA 1 uA IOH = -8 mA, VDDQ = 2.375 V 1.7 V -- IOH = -8 mA, VDDQ = 3.135 V 2.4 V -- IOL = 8 mA -- 0.4 V No t Re co m me nd ed for Ne w De sig n-- Di sco nt inu ed Pr od u -1 uA -1 uA Rev: 1.05 9/2008 14/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Operating Currents -250 Operating Current -40 to 85C 0 to 70C -40 to 85C Pipeline IDD IDDQ 305 40 315 40 255 30 265 30 205 20 215 20 mA Flow Through IDD IDDQ 235 20 245 20 205 15 215 15 190 15 200 15 mA Pipeline IDD IDDQ 275 20 285 20 230 15 240 15 185 15 195 15 mA Flow Through IDD IDDQ 215 10 225 10 190 10 200 10 175 10 185 10 mA Pipeline ISB 40 50 40 50 40 50 mA Flow Through ISB 40 50 40 50 40 50 mA Pipeline IDD 85 90 75 80 60 65 mA Flow Through IDD 60 65 50 55 50 55 mA Mode (x32/ x36) Device Selected; All other inputs VIH or VIL Output open Symbol 0 to 70C (x18) Standby Current ZZ VDD - 0.2 V Deselect Current Device Deselected; All other inputs VIH or VIL -- -- ct Test Conditions -150 -40 to 85C n-- Di sco nt inu ed Pr od u Parameter -200 0 to 70C Unit No t Re co m me nd ed for Ne w De sig Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Rev: 1.05 9/2008 15/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 AC Electrical Characteristics -150 Min Max Min Max 4.0 -- 5.0 -- Min Max ct tKC -200 n-- Di sco nt inu ed Pr od u Clock Cycle Time -250 Unit 6.7 -- ns Clock to Output Valid tKQ -- 2.5 -- 3.0 -- 3.8 ns Clock to Output Invalid tKQX 1.5 -- 1.5 -- 1.5 -- ns Clock to Output in Low-Z tLZ1 1.5 -- 1.5 -- 1.5 -- ns Setup time tS 1.2 -- 1.4 -- 1.5 -- ns Hold time tH 0.2 -- 0.4 -- 0.5 -- ns Clock Cycle Time tKC 5.5 -- 6.5 -- 7.5 -- ns Clock to Output Valid tKQ -- 5.5 -- 6.5 -- 7.5 ns Clock to Output Invalid tKQX 2.0 -- 2.0 -- 2.0 -- ns 1 Clock to Output in Low-Z tLZ 2.0 -- 2.0 -- 2.0 -- ns Setup time tS 1.5 -- 1.5 -- 1.5 -- ns Hold time tH 0.5 -- 0.5 -- 0.5 -- ns Clock HIGH Time tKH 1.3 -- 1.3 -- 1.5 -- ns 1.5 -- 1.5 -- 1.7 -- ns 1.5 2.5 1.5 3.0 1.5 3.0 ns -- 2.5 -- 3.0 -- 3.8 ns 0 -- 0 -- 0 -- ns Clock LOW Time tKL Clock to Output in High-Z tHZ1 G to Output Valid tOE G to output in Low-Z tOLZ1 G to output in High-Z ZZ setup time tOHZ1 -- 2.5 -- 3.0 -- 3.8 ns 2 5 -- 5 -- 5 -- ns 2 1 -- 1 -- 1 -- ns tZZR 20 -- 20 -- 20 -- ns tZZS tZZH me nd ed for ZZ hold time De sig Flow Through Symbol Ne w Pipeline Parameter ZZ recovery No t Re co m Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.05 9/2008 16/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Pipeline Mode Timing Cont Cont Deselect Write B Single Read Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC CK ADSP tS tH Deselect Burst Read ADSC initiated read ADSC tS tH ADV tS tH A0-An Read C ct Read A n-- Di sco nt inu ed Pr od u Begin A B tS GW tS C tH De sig BW tH tS tS tH E1 tH E2 tS tH E3 tOE tS tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) No t DQa-DQd E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC Re co m G me nd ed for tS Deselected with E1 Ne w Ba-Bd Rev: 1.05 9/2008 17/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC ct tKH n-- Di sco nt inu ed Pr od u CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0-An A B C tS tH tS tH BW Ba-Bd tS E1 tS tH E2 tS tH E3 E2 and E3 only sampled with ADSC Re co m G tH tS tOE tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa-DQd Deselected with E1 me nd ed for tH Ne w tS tH De sig GW Rev: 1.05 9/2008 18/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n-- Di sco nt inu ed Pr od u ct Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC tKL CK Setup Hold ADSP De sig ADSC tZZS Ne w ZZ tZZR tZZH me nd ed for Application Tips No t Re co m Single and Dual Cycle Deselect SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.05 9/2008 19/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 TQFP Package Drawing (Package T) A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 -- 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch -- 0.65 -- L Foot Length 0.45 0.60 0.75 L1 Lead Length -- 1.00 -- Y Coplanarity Lead Angle n-- Di sco nt inu ed Pr od u Min. Nom. Max e b A2 Y De sig A1 0.10 0 -- 7 E1 E No t Re co m me nd ed for Ne w Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. D D1 Description c Pin 1 Symbol L1 ct L Rev: 1.05 9/2008 20/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 TA3 250/5.5 C TQFP 200/6.5 C TQFP 150/7.5 C TQFP 250/5.5 C TQFP 200/6.5 C TQFP 150/7.5 C TQFP 250/5.5 C TQFP 200/6.5 C TQFP 150/7.5 C TQFP 250/5.5 I TQFP 200/6.5 I TQFP 150/7.5 I TQFP 250/5.5 I TQFP 200/6.5 I Pipeline/Flow Through TQFP 150/7.5 I GS816036BT-250I Pipeline/Flow Through TQFP 250/5.5 I 512K x 36 GS816036BT-200I Pipeline/Flow Through TQFP 200/6.5 I 512K x 36 GS816036BT-150I Pipeline/Flow Through TQFP 150/7.5 I 1M x 18 GS816018BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 1M x 18 GS816018BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 1M x 18 GS816018BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 512K x 32 GS816032BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 512K x 32 GS816032BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 512K x 32 GS816032BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 512K x 36 GS816036BGT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 C 512K x 36 GS816036BGT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 C 512K x 36 GS816036BGT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 C 1M x 18 GS816018BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I Part Number1 Type Package 1M x 18 GS816018BT-250 Pipeline/Flow Through TQFP 1M x 18 GS816018BT-200 Pipeline/Flow Through 1M x 18 GS816018BT-150 Pipeline/Flow Through 512K x 32 GS816032BT-250 Pipeline/Flow Through 512K x 32 GS816032BT-200 Pipeline/Flow Through 512K x 32 GS816032BT-150 Pipeline/Flow Through 512K x 36 GS816036BT-250 Pipeline/Flow Through 512K x 36 GS816036BT-200 Pipeline/Flow Through 512K x 36 GS816036BT-150 Pipeline/Flow Through 1M x 18 GS816018BT-250I Pipeline/Flow Through 1M x 18 GS816018BT-200I Pipeline/Flow Through 1M x 18 GS816018BT-150I Pipeline/Flow Through 512K x 32 GS816032BT-250I Pipeline/Flow Through 512K x 32 GS816032BT-200I Pipeline/Flow Through 512K x 32 GS816032BT-150I 512K x 36 me nd ed for Ne w De sig n-- Di sco nt inu ed Pr od u Org ct Speed2 (MHz/ns) Re co m Ordering Information for GSI Synchronous Burst RAMs No t 1M x 18 GS816018BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816018BT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.05 9/2008 21/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS816018BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 512K x 32 GS816032BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 512K x 32 GS816032BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I 512K x 32 GS816032BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I 512K x 36 GS816036BGT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/5.5 I 512K x 36 GS816036BGT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/6.5 I n-- Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 512K x 36 GS816036BGT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816018BT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.05 9/2008 22/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology GS816018/32/36BT-250/200/150 18Mb Sync SRAM Datasheet Revision History Types of Changes Format or Content Page;Revisions;Reason Content 8160xxB_r1_01; 8160xxB_r1_02 Content 8160xxB_r1_02; 8160xxB_r1_03 Content 8160xxB_r1_03; 8160xxB_r1_04 Content 8160xxB_r1_04; 8160xxB_r1_05 Content * Updated overshoot/undershoot information * Added 300 MHz speed bin * Removed 300 MHz speed bin * Added Status column to Ordering Information table * Changed Pb-free to RoHS-compliant * Updated Truth Tables (pg. 7,8) * Updated for MP status No t Re co m me nd ed for Ne w De sig 8160xxB_r1; 8160xxB_r1_01 n-- Di sco nt inu ed Pr od u * Creation of new datasheet 8160xxB_r1 ct DS/DateRev. Code: Old; New Rev: 1.05 9/2008 23/23 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. (c) 2004, GSI Technology