Data Sheet
V1.1 2011-09
Microcontrollers
16-Bit
Architecture
XE161FL, XE161HL
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Econo Line
Edition 2011-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
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Data Sheet
V1.1 2011-09
Microcontrollers
16-Bit
Architecture
XE161FL, XE161HL
16-Bit Single-Chip
Real Time Signal Controller
XE166 Family / Econo Line
XE161FL, XE161HL
XE166 Family / Econo Line
Data Sheet V1.1, 2011-09
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
XE161xL Data Sheet
Revision History: V1.1 2011-09
Previous Versions: V1.0
Page Subjects (major changes since last revision)
9Removed the note on exposed pad connection to VSS pin, which is not
relevant for VQFN48 package.
43 USIC “QSPI” protocol shortcut removed due to ambiguity (interpreted as
Queued SPI or Quad SPI).
62 Updated definition of Stopover mode and power consumption parameters
section.
66 Updated ADC parameters section.
72 Relaxed the conditions for short-term deviation of internal clock source
frequency ΔfINT
72 Added startup time from power-on tSPO.
83 Added the minimum PLL free running frequency. Reduced the min/max
bandwidth.
90 SSC Slave Mode timing parameter, t14, for upper voltage is updated.
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XE161FL, XE161HL
XE166 Family / Econo Line
Table of Contents
Data Sheet 1 V1.1, 2011-09
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Memory Checker Module (MCHK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7 Capture/Compare Unit (CC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 Capture/Compare Units CCU6x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.11 A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.12 Universal Serial Interface Channel Modules (USIC) . . . . . . . . . . . . . . . . . 42
3.13 MultiCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.14 System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.15 Window Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.16 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.17 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.18 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.19 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.1.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Voltage Range definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.3 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.1 DC Parameters for Upper Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.2 DC Parameters for Lower Voltage Area . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.4 Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.6 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.7 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table of Contents
XE161FL, XE161HL
XE166 Family / Econo Line
Table of Contents
Data Sheet 2 V1.1, 2011-09
4.7.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.7.2 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.7.2.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.7.2.2 Wakeup Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.7.2.3 Selecting and Changing the Operating Frequency . . . . . . . . . . . . . . 83
4.7.3 External Clock Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.7.4 Pad Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.7.5 Synchronous Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.7.6 Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.1 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.2 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.3 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
Data Sheet 3 V1.1, 2011-09
16-Bit Single-Chip
Real Time Signal Controller
XE161xL (XE166 Family)
1 Summary of Features
For a quick overview and easy reference, the features of the XE161 xL are summarized
here.
• High-performance CPU with five-stage pipeline and MPU
– 12.5 ns instruction cycle @ 80 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16 × 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for cod e and data
– 1,024 Bytes on-chip special function registe r area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
• Interrupt system with 16 priority levels providing 64 interrupt nodes
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 12.5 ns
• Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
• Clock generation from internal or external clock sources,
using on-ch i p PL L or p rescaler
• Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
• On-chip memory modules
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– 6 Kbytes on-chip data SRAM (DSRAM)
– 4 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 160 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC) for Flash
memory and through parity for RAMs
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
Data Sheet 4 V1.1, 2011-09
• On-Chip Peripheral Modules
– Synchronizable 12-bit A/D Converte r with up to 10 channels,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– 16-channel general purpose capture/compare unit (CC2)
– Two capture/compare units for flexible PWM signal generation (CCU6x)
– Multi-functional general purpose timer unit with 5 timers
– Up to 4 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 32 message objects
(Full CAN/Basic CAN) on 2 CAN nodes and gateway functionality
– On-chip system timer and on-chip real time clock
• Single power supply from 3.0 V to 5.5 V
• Power reduction and wake-up modes with flexible power management
• Programmable window watchdog timer and oscillator watchdog
• Up to 33 general purpose I/O lines
• On-chip bootstrap loaders
• Supported by a full range of development tools including C compilers, macro-
assembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
• On-chip debug support via Device Access Port (DAP), Single-Pin DAP (SPD) or
JTAG interface
• 48-pin Green VQFN package, 0.5 mm (10.7 mil) pitch
Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. This ordering co de identifies:
• the function set of the corresponding product type
• the temperature range1):
– SAF-…: -40°C to 85°C
– SAK-…: -40°C to 125°C
• the package and the type of delivery.
For ordering codes for the XE161xL please contact your sales representative or local
distributor.
1) Not all derivatives are offered in all temperatu re ranges.
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
Data Sheet 5 V1.1, 2011-09
1.1 Device Types
The following XE161xL device types are available and can be ordered through Infineon’s
direct and/or distribution channels.
Table 1 Synopsis of XE161x L Device Types
Derivative1)
1) x is a placeholder for available speed grade in MHz. Can be 66 or 80.
Flash
Memory2)
2) Specific information about the on-chip Flash memory in Table 3.
PSRAM
DSRAM3)
3) All derivatives additionally provide 2 Kbytes DPRAM.
Capt./Comp.
Modules ADC4)
Chan.
4) Specific information about the ava ilable channels in Table 5.
Interfaces4)
XE161FL-12FxV 96 Kbytes 4 Kbytes
6 Kbytes CC2
CCU60/3 10 2 CAN Nodes,
4 Serial Chan.
XE161HL-12FxV 96 Kbytes 4 Kbytes
6 Kbytes CC2
CCU60/3 10 4 Serial Chan.
XE161FL-20FxV 160 Kbytes 4 Kbytes
6 Kbytes CC2
CCU60/3 10 2 CAN Nodes,
4 Serial Chan.
XE161HL-20FxV 160 Kbytes 4 Kbytes
6 Kbytes CC2
CCU60/3 10 4 Serial Chan.
XE161FL, XE161HL
XE166 Family / Econo Line
Summary of Features
Data Sheet 6 V1.1, 2011-09
1.2 Definition of Feature Variants
The XE161xL types are offered with several Flash memory sizes. Table 3 and Table 4
describe the location of the avai lable Flash memory.
The XE161xL types are offered with different interface options. Table 5 lists the available
channels for each option.
Table 3 Continuous Flash Memory Ranges
Total Flash Size 1st Range1)
1) The uppermost 4-Kbyte sector of the first Flash segment is reserved for int ernal use (C0’F000H to C0’FFFFH).
2nd Range 3rd Range
160 Kbytes C0’0000H …
C0’EFFFH
C1’0000H …
C2’0FFFH
C4’0000H …
C4’7FFFH
96 Kbytes C0’0000H …
C0’EFFFH
C1’0000H …
C1’0FFFH
C4’0000H …
C4’7FFFH
Table 4 Flash Memory Module All ocation (in Kbytes)
Total Flash Size Flash 01)
1) The uppermost 4-Kbyte sector of the first Flas h segment is reserved for intern al use (C0’F000H to C0’FFFFH).
Flash 1
160 128 32
96 64 32
Table 5 Interface Channel Association
Total Number Available Channels / Message Objects
10 ADC0 channels CH0, CH2, CH3, CH4, CH8, CH9, CH16, CH17, CH19,
CH20
2 CAN nodes CAN0, CAN1
32 message objects
4 serial channels U0C0, U0C1, U1C0, U1C1
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 7 V1.1, 2011-09
2 General Device Information
The XE161xL series (16-Bit Single-Chip
Real Time Signal Controller) is a part of the Infineon XE166 Family of full-feature single-
chip CMOS microcontrollers. These devices extend the functionality and performance of
the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They
combine high CPU performance (up to 80 million instructions per second) with extended
peripheral functionality and enhanced IO capabilities. Optimized peripherals can be
adapted flexibly to meet the application requirements. These derivatives utilize clock
generation via PLL and internal or external clock sources. On-chip memory modules
include program Flash, program RAM, and data RAM.
Figure 1 XE161xL Logic Symbol
MC_XY_LOGSYMB48
Port 2
12 bit
Port 6
3 bit
V
AGND
(1)
V
AREF
(1)
V
DDPB
(3)
V
SS
(3)
V
DDIM
(2)
XTAL1
XTAL2
Port 10
12 bit
Port 5
6 bit
via Port Pins
SPD/DAP/
JTAG
1 / 2 / 4 bit
TRST Debug
2 bit
TESTM
PORST
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 8 V1.1, 2011-09
2.1 Pin Configuration and Definit ion
The pins of the XE161xL are described in detai l in Table 6, which includes all altern ate
functions. For further explanat ions please refer to the footnotes at the end of the table.
The following figure summarizes all pins, showing their locations on the four sides of the
package.
Figure 2 XE161xL Pin Configuration (top view)
MC_XY_PIN48
12
11
10
9
8
7
6
5
4
3
2
136
35
34
33
32
31
30
29
28
27
26
25
VQFN48
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P5.3
P5.2
V
DDPB
TESTM
P6.3
P6.1
V
AGND
V
AREF
P6.0
P5.0
P2.6
P2.7
P2.8
P10.4
P10.0
P10.3
P10.2
P10.1
P10.5
P10.6
P10.7
P10.12
PORST
V
DDIM
XTAL2
P10.9
P10.8
V
DDPB
P2.2
P2.1
P2.0
V
DDPB
P2.3
P5.8
P5.9
V
DDIM
P2.5
P2.4
XTAL1
TRST
P5.4
P2.9
P2.10
P2.13
P10.10
V
SS
V
SS
V
SS
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 9 V1.1, 2011-09
Key to Pin Definitions
•Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00B, output O1 is selected by 1x01B, etc.
Output signal OH is controlled by hardware.
•Type: Indicates the pad type and its power supply domain (B, M).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DA: Digital IO and analog input
– In: Input only pad
– PS: Power supply pad
Table 6 Pin Definitions and Functions
Pin Symbol Ctrl. Type Function
1 TESTM IIn/BTestmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to VDDPB).
An internal pullup device will hold this pin high
when nothing is driving it.
2TRST IIn/BTest-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XE161xL’s debug system.
In this case, pin TRST must be driven low once to
reset the debug system.
An internal pulldown device will hold this pin low
when nothing is driving it.
3 P6.3 O0 / I St/B Bit 3 of Port 6, General Purpose Input/Output
CCU63_COU
T62 O1 St/B CCU63 Channel 2 Output
T3OUT O2 St/B GPT12E Timer T3 Toggle Latch Output
U1C1_SELO
0O3 St/B USIC1 Channel 1 Select/Control 0 Output
U1C1_DX2D I St/B USIC1 Channel 1 Shift Control Input
ADC0_REQT
RyF ISt/BExternal Request Trigger Input for ADC0/1
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 10 V1.1, 2011-09
4 P6.1 O0 / I DA/B Bit 1 of Port 6, General Purpose Input/Output
ADC0_CH17 I DA/B Analog Input Channel 17 for ADC0
EMUX1 O1 DA/B External Analog MUX Control Output 1 (ADC0)
T3OUT O2 DA/B GPT12E Timer T3 Toggle Latch Output
U1C1_DOUT O3 DA/B USIC1 Channel 1 Shift Data Output
ADC0_REQT
RyE IDA/BExternal Request Trigge r In put for ADC0
CCU63_CTR
APB IDA/BCCU63 Emergency Trap Inpu t
U1C1_DX0A I DA/B USIC1 Channel 1 Shift Data Input
ESR1_6 I DA/B ESR1 Trigger Input 6
5 P6.0 O0 / I DA/B Bit 0 of Port 6, General Purpose Input/Output
ADC0_CH16 I DA/B Analog Input Channel 16 for ADC0
EMUX0 O1 DA/B External Analog MUX Control Output 0 (ADC0)
CCU63_COU
T61 O2 DA/B CCU63 Channel 1 Output
BRKOUT O3 DA/B OCDS Break Signal Output
ADC0_REQG
TyG IDA/BExternal Request Gate Input for ADC0
U1C1_DX0E I DA/B USIC1 Channel 1 Shift Data Input
10 P5.0 I In/B Bit 0 of Port 5, General Purpo se Input
ADC0_CH0 I In/B Analog Input Channel 0 for ADC0
11 P5.2 I In/B Bit 2 of Port 5, General Purpo se Input
ADC0_CH2 I In/B Analog Input Channel 2 for ADC0
TDI_A I In/B JTAG Test Da ta In put
12 P5.3 I In/B Bit 3 of Port 5, General Purpo se Input
ADC0_CH3 I In/B Analog Input Channel 3 for ADC0
T3INA I In/B GPT12E Timer T3 Count/Ga te Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 11 V1.1, 2011-09
13 P5.4 I In/B Bit 4 of Port 5, General Purpo se Input
ADC0_CH4 I In/B Analog Input Channel 4 for ADC0
CCU63_T12
HRB IIn/BExternal Run Control Input for T12 of CCU63
T3EUDA I In/B G PT12E Timer T3 External Up/Down Control
Input
TMS_A I In/B JTAG Test Mode Selection Input
14 P5.8 I In/B Bit 8 of Port 5, General Purpo se Input
ADC0_CH8 I In/B Analog Input Channel 8 for ADC0
CCU6x_T12H
RC IIn/BExternal Run Control Input for T12 of CCU60/3
CCU6x_T13H
RC IIn/BExternal Run Control Input for T13 of CCU60/3
15 P5.9 I In/B Bit 9 of Port 5, General Purpo se Input
ADC0_CH9 I In/B Analog Input Channel 9 for ADC0
CC2_T7IN I In/B CAPCOM2 Timer T7 Count Input
16 P2.0 O0 / I DA/B Bit 0 of Port 2, General Purpose Input/Output
CCU63_CC6
0O2 DA/B CCU63 Channel 0 Output
RxDC0C I DA/B CAN Node 0 Receive Data Input
CCU63_CC6
0INB IDA/BCCU63 Channel 0 Input
ADC0_CH19 I DA/B Analog Input Channel 19 for ADC0
T5INB I DA/B GPT12E Timer T5 Count/Gate Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 12 V1.1, 2011-09
17 P2.1 O0 / I DA/B Bit 1 of Port 2, General Purpose Input/Output
TxDC0 O1 DA/B CAN Node 0 Transmit Data Output
CCU63_CC6
1O2 DA/B CCU63 Channel 1 Output
CCU63_CC6
1INB IDA/BCCU63 Channel 1 Input
ADC0_CH20 I DA/B Analog Input Channel 20 for ADC0
T5EUDB I DA/B GPT12E Timer T5 External Up/Down Contro l
Input
ESR1_5 I DA/B ESR1 Trigger Input 5
ERU_0A0 I DA/B External Request Unit Channel 0 Input A0
21 P2.2 O0 / I St/B Bit 2 of Port 2, General Purpose Input/Output
TxDC1 O1 St/B CAN Node 1 Transmit Data Output
CCU63_CC6
2O2 St/B CCU63 Channel 2 Output
CCU63_CC6
2INB ISt/BCCU63 Channel 2 Input
ESR2_5 I St/B ESR2 Trigger Input 5
ERU_1A0 I St/B External Request Unit Channel 1 Input A0
22 P2.3 O0 / I St/B Bit 3 of Port 2, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
CCU63_COU
T63 O2 St/B CCU63 Channel 3 Output
CC2_CC16 O3 / I St/B CAPCOM2 CC16IO Capture Inp./ Compare Out.
ESR2_0 I St/B ESR2 Trigger Input 0
U0C0_DX0E I St/B USIC0 Channel 0 Shift Data Input
U0C1_DX0D I St/B USIC0 Channel 1 Shift Data Input
RxDC0A I St/B CAN Node 0 Receive Data Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 13 V1.1, 2011-09
23 P2.4 O0 / I St/B Bit 4 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
TxDC0 O2 St/B CAN Node 0 Transmit Data Output
CC2_CC17 O3 / I St/B CAPCOM2 CC17IO Capture Inp./ Compare Out.
ESR1_0 I St/B ESR1 Trigger Input 0
U0C0_DX0F I St/B USIC0 Channel 0 Shift Data Input
RxDC1A I St/B CAN Node 1 Receive Data Input
24 P2.5 O0 / I St/B Bit 5 of Port 2, General Purpose Input/Output
U0C0_SCLK
OUT O1 St/B USIC0 Channel 0 Shift Clock Output
TxDC0 O2 St/B CAN Node 0 Transmit Data Output
CC2_CC18 O3 / I St/B CAPCOM2 CC18IO Capture Inp./ Compare Out.
U0C0_DX1D I St/B USIC0 Channel 0 Shift Clock Input
ESR1_10 I St/B ESR1 Trigger Input 10
25 P2.6 O0 / I St/B Bit 6 of Port 2, General Purpose Input/Output
U0C0_SELO
0O1 St/B USIC0 Channel 0 Select/Control 0 Output
U0C1_SELO
1O2 St/B USIC0 Channel 1 Select/Control 1 Output
CC2_CC19 O3 / I St/B CAPCOM2 CC19IO Capture Inp./ Compare Out.
CLKIN1 I St/B Clock Signal Input 1
U0C0_DX2D I St/B USIC0 Channel 0 Shift Control Input
RxDC0D I St/B CAN Node 0 Receive Data Input
ESR2_6 I St/B ESR2 Trigger Input 6
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 14 V1.1, 2011-09
26 P2.7 O0 / I St/B Bit 7 of Port 2, General Purpose Input/Output
U0C1_SELO
0O1 St/B USIC0 Channel 1 Select/Control 0 Output
U0C0_SELO
1O2 St/B USIC0 Channel 0 Select/Control 1 Output
CC2_CC20 O3 / I St/B CAPCOM2 CC20IO Capture Inp./ Compare Out.
U0C1_DX2C I St/B USIC0 Channel 1 Shift Control Input
ESR2_7 I St/B ESR2 Trigger Input 7
RxDC1C I St/B CAN Node 1 Receive Data Input
U1C0_DX0A I St/B USIC1 Channel 0 Shift Data Input
27 P2.8 O0 / I St/B Bit 8 of Port 2, General Purpose Input/Output
U0C1_SCLK
OUT O1 St/B USIC0 Channel 1 Shift Clock Output
EXTCLK O2 St/B Programmable Clock Signal Output
CC2_CC21 O3 / I St/B CAPCOM2 CC21IO Capture Inp./ Compare Out.
U0C1_DX1D I St/B USIC0 Channel 1 Shift Clock Input
28 P2.9 O0 / I St/B Bit 9 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
TxDC1 O2 St/B CAN Node 1 Transmit Data Output
CC2_CC22 O3 / I St/B CAPCOM2 CC22IO Capture Inp./ Compare Out.
C1 I St/B Configuration Pin 1
TCK_A I St/B DAP0/J TAG Clock Input
29 P2.10 O0 / I St/B Bit 10 of Port 2, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
U0C0_SELO
3O2 St/B USIC0 Channel 0 Select/Control 3 Output
CC2_CC23 O3 / I St/B CAPCOM2 CC23IO Capture Inp./ Compare Out.
U0C1_DX0E I St/B USIC0 Channel 1 Shift Data Input
CAPINA I St/B GPT12E Register CAPREL Capture Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 15 V1.1, 2011-09
30, P2.13 O0 / I St/B Bit 13 of Port 2, General Purpose Input/Output
U1C1_DOUT O1 St/B USIC1 Channel 1 Shift Data Output
CCU63_COU
T60 O2 St/B CCU63 Channel 0 Output
U1C1_DX0B I St/B USIC1 Channel 1 Shift Data Input
U1C0_DX0B I St/B USIC1 Channel 0 Shift Data Input
31 P10.0 O0 / I St/B Bit 0 of Port 10, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
CCU60_CC6
0O2 St/B CCU60 Channel 0 Output
CCU60_CC6
0INA ISt/BCCU60 Channel 0 Input
ESR1_2 I St/B ESR1 Trigger Input 2
U0C0_DX0A I St/B USIC0 Channel 0 Shift Data Input
U0C1_DX0A I St/B USIC0 Channel 1 Shift Data Input
U1C1_DX0C I St/B USIC1 Channel 1 Shift Data Input
32 P10.1 O0 / I St/B Bit 1 of Port 10, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
CCU60_CC6
1O2 St/B CCU60 Channel 1 Output
CCU60_CC6
1INA ISt/BCCU60 Channel 1 Input
U0C0_DX0B I St/B USIC0 Channel 0 Shift Data Input
U0C0_DX1A I St/B USIC0 Channel 0 Shift Clock Input
33 P10.2 O0 / I St/B Bit 2 of Port 10, General Purpose Input/Output
U0C0_SCLK
OUT O1 St/B USIC0 Channel 0 Shift Clock Output
CCU60_CC6
2O2 St/B CCU60 Channel 2 Output
CCU60_CC6
2INA ISt/BCCU60 Channel 2 Input
U0C0_DX1B I St/B USIC0 Channel 0 Shift Clock Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 16 V1.1, 2011-09
34 P10.3 O0 / I St/B Bit 3 of Port 10, General Purpose Input/Output
CCU60_COU
T60 O2 St/B CCU60 Channel 0 Output
U0C0_DX2A I St/B USIC0 Channel 0 Shift Control Input
U0C1_DX2A I St/B USIC0 Channel 1 Shift Control Input
RxDC1D I St/B CAN Node 1 Receive Data Input
35 P10.4 O0 / I St/B Bit 4 of Port 10, General Purpose Input/Output
U0C0_SELO
3O1 St/B USIC0 Channel 0 Select/Control 3 Output
CCU60_COU
T61 O2 St/B CCU60 Channel 1 Output
U0C0_DX2B I St/B USIC0 Channel 0 Shift Control Input
U0C1_DX2B I St/B USIC0 Channel 1 Shift Control Input
ESR1_9 I St/B ESR1 Trigger Input 9
36 P10.5 O0 / I St/B Bit 5 of Port 10, General Purpose Input/Output
U0C1_SCLK
OUT O1 St/B USIC0 Channel 1 Shift Clock Output
CCU60_COU
T62 O2 St/B CCU60 Channel 2 Output
U0C1_DX1B I St/B USIC0 Channel 1 Shift Clock Input
37 P10.6 O0 / I St/B Bit 6 of Port 10, General Purpose Input/Output
U0C0_DOUT O1 St/B USIC0 Channel 0 Shift Data Output
U1C0_DOUT O2 St/B USIC1 Channel 0 Shift Data Output
U1C0_SELO
0O3 St/B USIC1 Channel 0 Select/Control 0 Output
U0C0_DX0C I St/B USIC0 Channel 0 Shift Data Input
U1C0_DX2D I St/B USIC1 Channel 0 Shift Control Input
CCU6x_CTR
APA ISt/BCCU60/CCU63 Emergency Trap Input
U1C0_DX0F I St/B USIC1 Channel 0 Shift Data Input
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 17 V1.1, 2011-09
38 P10.7 O0 / I St/B Bit 7 of Port 10, General Purpose Input/Output
U0C1_DOUT O1 St/B USIC0 Channel 1 Shift Data Output
CCU60_COU
T63 O2 St/B CCU60 Channel 3 Output
CCU63_COU
T61 O3 St/B CCU63 Channel 1 Output
U0C1_DX0B I St/B USIC0 Channel 1 Shift Data Input
CCU60_CCP
OS0A ISt/BCCU60 Position Input 0
T4INB I St/B GPT12E Timer T4 Count/Gate Input
39 P10.8 O0 / I St/B Bit 8 of Port 10, General Purpose Input/Output
U0C0_MCLK
OUT O1 St/B USIC0 Channel 0 Master Clock Output
U0C1_SELO
0O2 St/B USIC0 Channel 1 Select/Control 0 Output
U1C0_SCLK
OUT O3 St/B USIC1 Channel 0 Shift Clock Output
CCU60_CCP
OS1A ISt/BCCU60 Position Input 1
U0C0_DX1C I St/B USIC0 Channel 0 Shift Clock Input
BRKIN_B ISt/BOCDS Break Signal Input
T3EUDB I St/B GPT12E Timer T3 External Up/Down Control
Input
U1C0_DX1A I St/B USIC1 Channel 0 Shift Clock Input
ESR2_11 I St/B ESR2 Trigger Input 11
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 18 V1.1, 2011-09
40 P10.9 O0 / I St/B Bit 9 of Port 10, General Purpose Input/Output
U0C0_SELO
4O1 St/B USIC0 Channel 0 Select/Control 4 Output
U0C1_MCLK
OUT O2 St/B USIC0 Channel 1 Master Clock Output
TxDC1 O3 St/B CAN Node 1 Transmit Data Output
CCU60_CCP
OS2A ISt/BCCU60 Position Input 2
TCK_B I St/B DAP0/J TAG Clock Input
T3INB I St/B GPT12E Timer T3 Count/Gate Input
44 P10.10 O0 / I St/B Bit 10 of Port 10, General Purpose Input/Output
U0C0_SELO
0O1 St/B USIC0 Channel 0 Select/Control 0 Output
CCU60_COU
T63 O2 St/B CCU60 Channel 3 Output
U1C0_DOUT O3 St/B USIC1 Channel 0 Shift Data Output
U0C0_DX2C I St/B USIC0 Channel 0 Shift Control Input
TDI_B I St/B JTAG Test Data Input
U0C1_DX1A I St/B USIC0 Channel 1 Shift Clock Input
45 P10.12 O0 / I St/B Bit 12 of Port 10, General Purpose Input/Output
U1C0_DOUT O1 St/B USIC1 Channel 0 Shift Data Output
U0C0_DOUT O2 St/B USIC0 Channel 0 Shift Data Output
CCU63_COU
T62 O3 St/B CCU63 Channel 2 Output
TDO_A OH St/B DAP1/JTAG Test Data Output
SPD_0 I/OH St/B SPD Input/Output
C0 I St/B Configuration Pin 0
U0C0_DX0D I St/B USIC0 Channel 0 Shift Data Input
U1C0_DX0C I St/B USIC1 Channel 0 Shift Data Input
U1C0_DX1E I St/B USIC1 Channel 0 Shift Clock Input
46 XTAL2 O Sp/M Crystal Oscillator Amplifier Output
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 19 V1.1, 2011-09
47 XTAL1 I Sp/M Crystal Oscillator Amplifier Inpu t
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Voltages on XTAL1 must comply to the core
supply voltage VDDIM.
ESR2_9 I St/B ESR2 Trigger Input 9
48 PORST IIn/BPower On Reset Input
A low level at this pin resets the XE161xL
completely. A spike filter suppresses input pulses
<10 ns. Input pulses >100 ns safely pass the filter.
The minimum durati on for a safe recognition
should be 120 ns.
An internal pullup device will hold this pin high
when nothing is driving it.
8VAREF - PS/B Reference Voltage for A/D Converters ADC0
9VAGND - PS/B Reference Ground for A/D Converters ADC0
18,
43 VDDIM - PS/M Digital Core Supply Voltage for Domain M
Decouple with a ceramic capacitor, see Data
Sheet for details.
All VDDIM pins must be connected to each other.
7,
20,
41
VDDPB - PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
VDDP/VSS pin pairs as close as possible to the pins.
6,
19,
42
VSS - PS/-- Digital Ground
All VSS pins must be connected to the ground-line
or ground-plane.
Table 6 Pin Definitions and Functions (cont’d)
Pin Symbol Ctrl. Type Function
XE161FL, XE161HL
XE166 Family / Econo Line
General Device Information
Data Sheet 20 V1.1, 2011-09
2.2 Identification Registers
The identification registers describe the current version of the XE161xL and of its
modules.
Table 7 XE161xL Identification Registers
Short Name Value Address Notes
SCU_IDMANUF 1820H00’F07EH
SCU_IDCHIP 2801H00’F07CH
SCU_IDMEM 3028H00’F07AH
SCU_IDPROG 1313H00’F078H
JTAG_ID 001D’6083H---
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 21 V1.1, 2011-09
3 Functional Description
The architecture of the XE161xL combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent op eration of several subsystems of the XE161xL.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XE161xL.
Figure 3 Block Diagram
DPRAM
CPU
PMU
DMU
ADC0
Module
8-/10-/
12-Bit
RTC
MCHK
Interrupt & PEC
LXBUS
Controller
DSRAM
System Functions
Cl o ck, Re se t, P o we r
Control
OCDS
D ebug Supp ort
Interrupt Bus
Peripher al D ata Bus
Analog and D i git al General Purp os e I O (G PI O) Port s
MC_L-SERIES_BLOCKDIAGRAM
GPT
5
Timers
CC2
Module
16
Chan.
LXBus
WWD
Multi
CAN
CCU6x
Modules
3+1
Chan.
each
USICx
Modules
2
Chan.
each
PSRAM
Flash Memory
IMB
MAC Unit
MPU
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 22 V1.1, 2011-09
3.1 Memory Subsystem and Organization
The memory space of the XE161xL is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8 XE161xL Memory Map 1)
Address Area Start Loc. End Loc. Area Size2) Notes
IMB register space FF’FF00HFF’FFFFH256 bytes
Reserved F0’0000HFF’FEFFH< 1 Mbyte Minus IMB
registers.
Reserved for EPSRAM E8’1000HEF’FFFFH508 Kbytes Mirrors EPSRAM
Emulated PSRAM E8’0000HE8’0FFFHup to 4 Kbytes With Flash timing.
Reserved for PSRAM E0’1000HE7’FFFFH508 Kbytes Mirrors PSRAM
PSRAM E0’0000HE0’0FFFHup to 4 Kbytes Program SRAM.
Reserved for Flash C4’8000HDF’FFFFH176 0 Kbytes
Flash 1 C4’0000HC4’7FFFH32 Kbytes
Reserved for Flash C2’1000HC3’FFFFH124 Kbytes
Flash 0 C0’0000HC2’0FFFH132 Kbytes3)
External memory area 40’0000HBF’FFFFH8 Mbytes
External IO area4) 21’0000H3F’FFFFH1984 Kbytes
Reserved 20’B800H20’FFFFH18 Kbytes
USIC0-1 alternate regs. 20’B000H20’B7FFH2 Kbytes Accessed via
LXBus Controller
MultiCAN alternate regs. 20’8000H20’AFFFH12 Kbytes Accessed via
LXBus Controller
Reserved 20’5000H20’7FFFH12 Kbytes
USIC0-1 registers 20’4000H20’4FFFH4 Kbytes Accessed via
LXBus Controller
MultiCAN registers 20’0000H20’3FFFH16 Kbytes Accessed via
LXBus Controller
External memory area 01’0000H1F’FFFFH1984 Kbytes
SFR area 00’FE00H00’FFFFH0.5 Kbytes
Dual-port RAM
(DPRAM) 00’F600H00’FDFFH2 Kbytes
Reserved for DPRAM 00’F200H00’F5FFH1 Kbytes
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 23 V1.1, 2011-09
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Po rti ons of the o n-chip DPR AM an d th e
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These inclu de peripheral s on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
4 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or data.
The PSRAM is accessed via the PMU and is optimized for code fetches. A section of the
PSRAM with programmable size can be write-protected.
ESFR area 00’F000H00’F1FFH0.5 Kbytes
XSFR area 00’E000H00’EFFFH4 Kbytes
Data SRAM (DSRAM) 00’C800 H00’DFFFH6 Kbytes
Reserved for DSRAM 00’8000H00’C7FFH18 Kbytes
External memory area 00’0000H00’7FFFH32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicat ed, see column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for int ernal use (C0’F000H to C0’FFFFH).
4) Several pipeline optimizations are not active within the external IO area.
Table 8 XE161xL Memory Map (cont’d)1) (cont’d)
Address Area Start Loc. End Loc. Area Size2) Notes
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 24 V1.1, 2011-09
6 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for genera l purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XE166 Family. In order to ensure
upward compatibility they should either not be accessed or written with zeros.
The on-chip Flash memory stores code, constant data, and control data. The
160 Kbytes of on-chip Flash memory consist of 1 module of 32 Kbytes (preferably for
data storage) and 1 module of 128 Kbytes. Each module is organized in 4-Kbyte sectors.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The co mplete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with pr otected and efficien t writing algorithms for pr ogramming and erasing .
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.6.
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bi t e rro r and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application agai nst such soft errors.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 25 V1.1, 2011-09
3.2 Central Processing Unit (CPU)
The core of the CPU consists of a 5-stage execution pipeline with a 2-stage instru ction-
fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply and
accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply-and-divide uni t, a bit-mask generator, and a barrel
shifter.
Figure 4 CPU Block Diagram
DPRAM
CPU
IPIP
RF
R0
R1
GPRs
R14
R15
R0
R1
GPRs
R14
R15
IFU
Injection/
Exception
Handler
ADU
MAC
mca04917_x.vsd
CPUCON1
CPUCON2
CSP IP
Return
Stack
FIFO
Branch
Unit
Prefetch
Unit VECSEG
TFR
+/-
IDX0
IDX1
QX0
QX1
QR0
QR1 DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
MRW
MCW
MSW
MAL
+/-
MAH
Multiply
Unit
ALU
Division Unit
Multiply Unit
Bit-Mask-Gen.
Barrel-Shifter
+/-
MDC
PSW
MDH
ZEROS
MDL
ONES
R0
R1
GPRs
R14
R15
CP
WB
Buffer
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
R0
R1
GPRs
R14
R15
PMU
DMU
DSRAM
EBC
Peripherals
PSRAM
Flash/ROM
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 26 V1.1, 2011-09
With this hardware most XE161xL instructions are executed in a single machine cycle of
12.5 ns @ 80-MHz CPU clock. For example, shift and rotate instructions are always
processed during one machine cycle, no matter how many bits are shifted. Also,
multiplication and most MAC instructions execute in one cycle. All multiple-cycle
instructions have been optimized so that they can be executed very fast; for example, a
32-/16-bit division i s started within 4 cycles while the remaining cycle s are executed in
the background. Another pipel ine optimization, the branch target prediction, eliminates
the execution time of branch instructions if the prediction was correct.
The CPU has a register conte xt consisting of up to three register b anks with 16 word-
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware im plementation can be be st utilize d by the
programmer with the highly efficient XE161xL instruction set. This includes the following
instruction classes:
• Standard Arithmetic Instructions
• DSP-Oriented Arithmetic Instructions
• Logical Instructions
• Boolean Bit Manipulation Instructions
• Compare and Loop Control Instructions
• Shift and Rotate Instructions
• Prioritize Instruction
• Data Movement Instructions
• System Stack Instructions
• Jump and Call Instructions
• Return Instructions
• System Control Instructions
• Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate ad dressing modes are provided to
specify the required operands.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 27 V1.1, 2011-09
3.3 Memory Protection Unit (MPU)
The XE161xL’s Memory Protection Unit (MPU) protects user-specified memory areas
from unauthorized read, write, or instruction fe tch accesses. The MPU can protect the
whole address space including the peripheral area. This completes established
mechanisms such as the register security mechanism or stack overrun/underrun
detection.
Four Protection Levels support flexible system programming where operating system,
low level drivers, and applications run on separate levels. Each protection level permits
different access restrictions for instructions and/or data.
Every access is checked (if the MPU is enabled) and an access violating the permission
rules will be marked as invalid and leads to a protection trap.
A set of protection registers for each protection level sp ecifies the address ranges and
the access permissions. Applications requiring more than 4 protection levels can
dynamically re-pro gra m th e pr otection register s.
3.4 Memory Checker Module (MCHK)
The XE161xL’s Memory Checker Modul e calcul ates a checksum (fractional polynomial
division) on a block of data, often called Cyclic Redundancy Code (CRC). It is based on
a 32-bit linear feedback shift register and may, therefore, also be used to generate
pseudo-random numbers.
The Memory Checker Module is a 16-bit parallel input signature compression circuitry
which enables error detection within a block of data stored in memory, registers, or
communicated e.g. via serial communication lines. It reduces the probability of error
masking due to repeated error patterns by calculating the signature of blocks of data.
The polynomial used for operation is configurable, so most of the commonly used
polynomials may be used. Also, the block size for generating a CRC result is
configurable via a local counter. An interrupt may be generated if testing the current data
block reveals an error.
An autonomous CRC compare circuitry is included to enable redundant error detection,
e.g. to enable higher safety integrity levels.
The Memory Checker Module provides enhanced fault detection (beyond parity or ECC)
for data and instructions in volatile and non volatile memories. This is especially
important for the safety and reliability of embedded systems.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 28 V1.1, 2011-09
3.5 Interrupt System
The architecture of the XE161xL supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroll er. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Using a standard interrupt service the current program execution is suspended and a
branch to the interrupt vector table is perfo rmed. Wi th th e PEC just one cycle is ‘stolen ’
from the current CPU activity to perform t he PEC service. A PEC service implies a single
byte or word data transfer between any two memory locations with an additional
increment of either the PEC source pointer, the destination pointer, or both. An individual
PEC transfer counter is implicitly decremented for each PEC service except when
performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source-related vector location. PEC services
are particularly well suited to supporting the transmission or reception of blocks of data.
The XE161xL has eight PEC channels, each with fast interrupt-driven data transfer
capabilities.
With a minimum interrupt response time of 7/111) CPU clocks, the XE161xL can react
quickly to the occurrence of non-deterministic events.
Interrupt Nodes and Source Selection
The interrupt system provides 64 physical nodes with separate control register
containing an interrupt reque st flag, an interrupt enable flag and a n interrupt priority bit
field. Most interrupt sources are assigned to a dedicated node. A particular subset of
interrupt sources shares a set of nodes. The source selection can be programmed using
the interrupt source selection (ISSR) registers.
External Request Unit (ERU)
A dedicated External Request Unit (ERU) is provided to route and preprocess selected
on-chip peripheral and external interrupt requests. The ERU features 4 programmable
input channels with event trigger l ogic (ETL) a routing matrix and 4 output ga ting units
(OGU). The ETL features rising ed ge, falling edg e, or both ed ges event detectio n. The
OGU combines the detected interrupt events and provides filtering capabilities
depending on a programmable pattern match or miss.
Trap Processing
The XE161xL provides efficient mechanisms to identify and process exceptions or error
conditions that arise during run-time, the so-called ‘Hardware Traps’. A hardware trap
causes an immediate system reaction similar to a standard interrupt service (branching
1) Depending if the jump cache is used or not.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 29 V1.1, 2011-09
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in th e trap flag register (TFR ). Unl ess anoth er hig her-prior ity trap se rvice
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6 On-Chip Debug Support (OCDS)
The On-Chip Debug Suppo rt system built into the XE161xL provides a broad range of
debug and emulation features. User software running on the XE161xL can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. T his
consists of the 2-pin Device Access Port (DAP) or of th e 1-pin Single Pin DAP (SPD) or
of the JTAG port conforming to IEEE-1149. The debug interface can be completed with
an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (SPD, DAP or JTAG). In ad dition the OCDS system can be controlled
by the CPU, e.g. by a monitor program. An injection interface allows the execution of
OCDS-generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XE166 Family emulation device.
The SPD interfa ce uses o ne interface sign al, DAP in terface u ses two in terface sig nals,
the JTAG interface uses four interface signals, to communicate with external circuitry.
The debug interface can be amended wi th two optional break lines.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 30 V1.1, 2011-09
3.7 Capture/Compare Unit (CC2)
The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of one system clock cycle (eight cycles in
staggered mode). The CAPCOM unit is typically used to handle high-speed I/O tasks
such as pulse and waveform generation, pulse width modulation (PWM), digital to
analog (D/A) conversion, software timing, or time recording with respect to external
events.
Two 16-bit timers with reload registers provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs allow event scheduling for the capture/compare registers relative to external
events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer and
programmed for capture or compare function.
All registers have each one port pin associated with it which serves as an input pin for
triggering the capture function, or as an output pin to indicate the occurrence of a
compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an external event at the port pin which is associated with this
register. In addition, a specific interrupt request for this capture/compare register is
generated. Either a positive, a negative, or both a positive and a negative external signal
transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes
are continuously compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the selected compare mode.
Table 9 Compare Modes
Compare Modes Function
Mode 0 Interrupt-only compare mode;
Several compare interrupts per timer period are possib le
Mode 1 Pin toggles on each compare match;
Several compare events per timer period are possible
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 31 V1.1, 2011-09
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
register in response to an exte rnal event at the port pin associ ated with this register. In
addition, a specific interrupt request for this capture/compare register is generated.
Either a positive, a negative, or both a positive and a ne gative external sign al transition
at the pin can be selected as the triggering event.
The contents of all registers selected for one of the five compare modes are continuously
compared with the contents of the allocated timers.
When a match occurs between the timer value and the value in a capture/compare
register, specific actions will be taken based on the compare mode selected.
Mode 2 Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode Generates single edges or pulses;
Can be used with any compare mode
Table 9 Compare Modes (cont’d)
Compare Modes Function
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 32 V1.1, 2011-09
Figure 5 CAPCOM Unit Block Diagram
Sixteen
16-bit
Capture/
Compare
Registers
Mode
Control
(Capture
or
Compare)
T7
Input
Control
T8
Input
Control
MC_CAPCOM2_BLOCKDIAG
CC16IRQ
CC31IRQ
CC17IRQ
T7IRQ
T8IRQ
CC16IO
CC17IO
T7IN
T6OUF
f
CC
T6OUF
f
CC
Reload Reg.
T7REL
Timer T7
Timer T8
Reload Reg.
T8REL
CC31IO
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 33 V1.1, 2011-09
3.8 Capture/Compare Units CCU6x
The XE161xL types feature the CCU60 and CCU63 units.
CCU6 is a high-reso lution capture and compare unit with app lication-specific modes. It
provides inputs to start the timers synchronously, an important feature in devices with
several CCU6 modules.
The module provides two independent timers (T12, T13), that can be used for PWM
generation, especially for AC motor control. Additionally, special control modes for block
commutation and multi-phase machines are sup ported.
Timer 12 Features
• Three capture/compare channels, where each channel can be used either as a
capture or as a compare channel.
• Supports generation of a three-phase PW M (six outputs, indivi dual signa ls for high-
side and low-side switches)
• 16-bit resolution, maximum count frequency = peripheral clock
• Dead-time control for each channel to avoid short circuits in the power stage
• Concurrent update of the required T12/13 registers
• Center-aligned and edge-align ed PWM can be generated
• Single-shot mode supported
• Many interrupt request sources
• Hysteresis-like control mode
• Automatic start on a HW event (T12HR, for synchronization purposes)
Timer 13 Features
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock
• Can be synchronized to T12
• Interrupt generation at period match and compare match
• Single-shot mode supported
• Automatic start on a HW event (T13HR, for synchronization purposes)
Additional Features
• Block commutation for brushless DC drives implemented
• Position detection via Hall sensor patte rn
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP)
• Control modes for multi-channel AC drives
• Output levels can be selected and adapted to the power stage
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 34 V1.1, 2011-09
Figure 6 CCU6 Block Diagram
Timer T12 can work in capture and/or compare mode for its three channels. The modes
can also be combined . Timer T13 can work in compare mode only. Th e multi-channel
control unit generates output patte rns that can be modulated by timer T12 and/or timer
T13. The modulation sources can be selected and combined for signal modulation.
mc_ccu6_blockdiagram.vsd
C hannel 0
C hannel 1
C hannel 2
T12 Dead-
time
Control
Input / Output Control
CC62
COUT62
CC61
COUT61
CC60
COUT60
COUT63
CTRAP
C hannel 3T13
CCPOS0
1
1
1
2221
start
compare
capt ure
3
Multi-
channel
Control
Trap
Control
compare
compare
compare
compare
1
trap input
CCPOS1
CCPOS2
out put select
out put select
3
Ha ll input
CCU6 Module Kernel
fSYS
Interrupts
TxHR
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 35 V1.1, 2011-09
3.9 General Purpose Timer (GPT12E) Unit
The GPT12E unit is a very flexible multif unctional timer/counter structu re which ca n be
used for many different timing tasks such as event timing and counting, pulse width and
duty cycle measurements, pulse generatio n, or pulse multiplication.
The GPT12E unit incorporates five 16-bit timers organized in two separate modules,
GPT1 and GPT2. Each timer in each module may either operate independently in a
number of different modes or be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for
one of four basic modes of operation: Timer, Gated Timer, Counter, and Incremental
Interface Mode. In Timer Mode, the input clock for a timer is derived from the system
clock and divided by a programmab le prescale r. C ounter Mo de a llows timer clocki ng i n
reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is control led by the ‘gate’ level on an e xternal input pin. Fo r these
purposes each timer has one associated port pin (TxIN) which serves as a gate or clock
input. The maximum resolution of the timers in module GPT1 is 4 system clock cycles.
The counting direction (up/down) for each timer can be programmed by software or
altered dynamically by an external signal on a port pin (TxEUD), e.g. to facilitate position
tracking.
In Incremental Interface Mode the GPT1 timers can be directly connected to the
incremental position sensor signals A and B through their respective inputs TxIN and
TxEUD. Direction and counting signals are internally derived from these two input
signals, so that the contents of the respective timer Tx corresponds to the sensor
position. The third position sensor signal T OP0 can be connected to an interrupt input.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out
monitoring of external hardware components. It may also be used internally to clock
timers T2 and T4 for measuring long time periods with high resolution.
In addition to the basic operating modes, T2 and T4 may be configured as reload or
capture register for timer T3. A timer used as capture or reload register is stopped. Th e
contents of timer T3 is captured into T2 or T 4 in response to a sign al at the associated
input pin (TxIN). Timer T3 is re loaded with th e contents of T2 or T4, trigge red either by
an external signal or a selectab le state transition of its toggle latch T3OTL. When both
T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL
with the low and high times of a PWM signal, this signal can be con tinuously generated
without software intervention.
Note: Signals T2IN, T2EUD, T4EUD, T6OUT, T6IN and T6EUD are not connected to
pins.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 36 V1.1, 2011-09
Figure 7 Block Diagram of GPT1
MC_GPT_BLOCK1
Aux. Timer T2
2
n
:1
T2
Mode
Control
Capture
U/D
Basic Clock
f
GPT
T3CON.BPS1
T3OTL T3OUT
Toggle
Latch
T2IN
T2EUD Reload
Core Timer T3
T3
Mode
Control
T3IN
T3EUD U/D
Interrupt
Request
(T3IRQ)
T4
Mode
Control
U/D
Aux. Timer T4
T4EUD
T4IN Reload
Capture
Interrupt
Request
(T4IRQ)
Interrupt
Request
(T2IRQ)
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 37 V1.1, 2011-09
With its maximum resolution of 2 system clock cycles, the GPT2 module provides
precise event control and time measurement. It includes two timers (T5, T6) and a
capture/reload register (CAPREL). Both timers can be clocked with an input clock which
is derived from the CPU clock via a programmable prescaler or with external signals. The
counting direction (up/dow n) for each timer can be programmed by software or altered
dynamically with an extern al signal on a port pin (TxEUD). Conc atenation of the timers
is supported with the output toggle latch (T6OTL) of timer T6, which changes its state on
each timer overflow/underflow.
The state of this latch may be used to clock timer T5, and/or it may be output on pin
T6OUT. The overflows/underflows of timer T6 can also be used to clock the CAPCOM2
timers and to initiate a reload from the CAPREL register.
The CAPREL register can capture the contents of timer T5 based on an external signal
transition on the corresponding port pin (CAPIN); timer T5 may optionally be cleared
after the capture procedure. This allows the XE161xL to measure absolute time
differences or to perform pulse multiplication without software overhead.
The capture trigger (timer T5 to CAPREL) can also be generated upon transitions of
GPT1 timer T3 inputs T3IN and/or T3EUD. This is especially advantageous when T3
operates in Incremental Interface Mode.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 38 V1.1, 2011-09
Figure 8 Block Diagram of GPT2
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 39 V1.1, 2011-09
3.10 Real Time Clock
The Real Time Clock (RTC) module of the XE161xL can be clocked with a clock signal
selected from internal sources or external sources (pins).
The RTC basically consists of a chain of divider blocks:
• Selectable 32:1 and 8:1 dividers (on - off)
• The reloadable 16-bit timer T14
• The 32-bit RTC timer block (accessible via registers RTCH and RTCL) consisting of:
– a reloadable 10-bit timer
– a reloadable 6-bit timer
– a reloadable 6-bit timer
– a reloadable 10-bit timer
All timers count up. Each timer can generate an interrupt request. All requests are
combined to a common node request.
Figure 9 RTC Block Diagram
Note: The registers associated with the RTC are only affected by a power reset.
CNT-Register
REL-Register
10 Bits6 Bits6 Bits10 Bi tsT14
MCB05568B
T14-Register
Interrupt Sub Node RTCINT
MUX
32
PRE
RUN
CNT
INT3
CNT
INT2
CNT
INT1
CNT
INT0
f
CNT
f
RTC
T14REL 10 Bits6 Bi ts6 Bi ts10 Bi ts
:
MUX
8:
REFCLK
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 40 V1.1, 2011-09
The RTC module can be used fo r different purposes:
• System clock to determine the current time and date
• Cyclic time-based interrupt, to provide a system time tick independent of CPU
frequency and other resources
• 48-bit timer for long-term measurements
• Alarm interrupt at a defined time
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 41 V1.1, 2011-09
3.11 A/D Converters
For analog signal measurement, a 12-bit A/D converters (ADC0) with 10 multiplexed
input channels and a sample and hold circuit have been integrated on-chip. Conversions
use the successive approximation meth od. The sample time (to charge the capacitors)
and the conversion time are programmable so that they can be adjusted to the external
circuit. The A/D converters can also operate in 8-bit and 10-bit conversion mode, further
reducing the conversion time.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequence s provid e a high deg ree of programmabi lity to meet
the application requirements.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically. For applications that require fewer analog input
channels, the remaini ng channel inputs can be used as digital input port pins.
The A/D converters of the XE161xL support two types of request sources which can be
triggered by several intern al and external events.
• Parallel requests are acti vated at the same time and then exe cuted in a predefined
sequence.
• Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing that sequence. All requests are arbitrated according to the priority
level assigned to them.
Data reduction features reduce the number of required CPU access operations allowing
the precise evaluation of analog inputs (high conversion rate) even at a low CPU speed.
Result data can be reduced by limit checking or accumulation of results. Two cascadable
filters build the hardware to generate a configurable moving average.
The Peripheral Event Controlle r (PEC) can be used to control the A/D con verters or to
automatically store conversion results to a table in memory for later evalua tion, without
requiring the overhead of entering and exiting interrupt routines for ea ch data transfer.
Each A/D converter contains eight result registers which can be concatenated to build a
result FIFO. Wait-for-read mode can be enabled for each result register to prevent the
loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise,
those pins used for analog input can be disconnected from the digital input stages. This
can be selected for each pin separately with the Port x Digital Input Disable registers.
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Broken wire detection for each channel and a multiplexer test mode provide information
to verify the proper operation of the analog signal sources (e.g. a sensor system).
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 42 V1.1, 2011-09
3.12 Universal Serial Interface Channel Modules (USIC)
The XE161xL features the USIC modules USIC0 and USIC1. Each module provides two
serial communication channels.
The Universal Serial Interface Ch annel (USI C) module is based on a g eneric data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during run time.
Figure 10 General Structure of a USIC Module
The regular structure of the USIC module brings the following advantag es:
• Higher flexibility through configuration with same look-and-feel for data management
• Reduced complexity for low-level dr ivers serving different protocols
• Wide range of protocols with improved performances (baud rate, buffer handling)
USIC_basic.vsd
Bus In ter face
DBU
0
DBU
1
Control 0
Control 1
DSU
0
DSU
1
PPP_A
PPP_B
PPP_C
PPP_D
PPP_A
PPP_B
PPP_C
PPP_D
Pin Routing Shell
Buffer & Sh ift Structure Proto col Prepro cessors Pin sBus
fsys Fractional
Dividers Ba u d rate
Generators
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 43 V1.1, 2011-09
Target Protocols
Each USIC channel can rece ive and transmit data frames with a selectable data wo rd
width from 1 to 16 bits in each of the following protocols:
•UART (asynchronous serial channel)
– module capability: maximum baud rate = fSYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
•LIN Support (Local Interconnect Network)
– module capability: maximum baud rate = fSYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
•SSC/SPI (synchronous serial channel with or without data buffer)
– module capability: maximum baud rate = fSYS / 2, limited by loop delay
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
•IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
•IIS (Inter-IC Sound Bus)
– module capability: maximum baud rate = fSYS / 2
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum achievable baud rate can be
limited. Please note that there may be additional delays, such as internal or
external propagation delays and driver delays (e.g. for collision detection in UART
mode, for IIC, etc.).
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 44 V1.1, 2011-09
3.13 MultiCAN Module
The MultiCAN module contains two ind epen dently op erating CAN nodes with Ful l-CAN
functionality which are able to exchange Data and Remote Frames using a gateway
function. Transmission and reception of CAN frames is handled in accordance with CAN
specification V2.0 B (active). Each CAN node can receive and transmit standard frames
with 11-bit identifiers as well as extended frames with 29-bit identifiers.
The two CAN nodes share a common set of message objects. Each message object can
be individually allocated to either of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects can be combined to build
gateways between the CAN nodes or to set up a FIFO buffer.
The message objects are organized in double-chained linked lists, where each CAN
node has its own list of message objects. A CAN node stores frames only into message
objects that are allocated to its own message object list and it transmits only messages
belonging to this message object list. A powerful, command-driven list controller
performs all message object list operations.
Figure 11 Block Diagram of MultiCAN Module
mc_multican_block.vsd
M ultiCA N M odule K ernel
Interrupt
Control
f
CAN
Port
Control
CAN Co ntrol
Message
Object
Buffer
CAN
Node 0
Linked
List
Control
Clock
Control
Address
Decoder
CAN
Node n
TXDCn
RXDCn
TXDC0
RXDC0
...
...
...
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 45 V1.1, 2011-09
MultiCAN Features
• CAN functionality conforming to CAN specification V2.0 B active for each CAN node
(compliant to ISO 11898)
• Independent CAN nodes
• Set of independent message objects (shared by the CAN nodes)
• Dedicated control registers for each CAN node
• Data transfer rate up to 1 Mbit/s, individually programmable for each node
• Flexible and powerful me ssage transfer control and error handling capabiliti es
• Full-CAN functionality for message objects:
– Can be assigned to one of the CAN nodes
– Configurable as transmit or receive objects, or as message buffer FIFO
– Handle 11-bit or 29-bit identifiers with programmable acceptance mask for filtering
– Remote Monitoring Mode, and frame counter for monitoring
• Automatic Gateway Mode support
• 16 individually programmable interrupt nodes
• Analyzer mode for CAN bus monitoring
3.14 System Timer
The System Timer consists of a progra mmable prescaler and two concatenated timers
(10 bits and 6 bits). Both timers can generate in terrupt requests. Th e clock source can
be selected and the timers can also run during power reduction modes.
Therefore, the System Timer enables the software to maintain the current time for
scheduling functions or for the implem entation of a clock.
3.15 Window Watchdog Timer
The Window Watchdog Timer is one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Window Watchdog Timer is always enabled after an application reset of the chip. It
can be disabled and enabled at any time by executing the instructions DISWDT and
ENWDT respectively. The software has to service the Window Watchdog Timer before
it overflows. If this is not the case because of a hardware or software failure, the Window
Watchdog Timer overflows, generating a reset request.
The Window Watchdog Timer has a ‘programmable window boundary’, it disallows
refresh during the Window Watchdog Timer’s count-up. A refresh during this window-
boundary will cause the Window W atchdog Timer to also generate a reset request.
The Window Watchdog Timer is a 16-bit timer clocked with either the system clock or the
independent wake-up oscillator clock, divided by 16,384 or 256. The Window Watchdog
Timer register is set to a prespecified reload value (stored in WDTREL) in order to allow
further variation of the monitored time interval. Each time it is serviced by the application
software, the Window Watchdog Timer is reloaded.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 46 V1.1, 2011-09
When clocked by fSYS = 80 MHz, time intervals between 12.5 ns and 13.4 s can be
monitored.
When clocked by fWU = 500 kHz, time intervals between 2.0 µs and 2147.5 s can be
monitored.
The default Watchdog Timer interval afte r power-up is 0.13 s (@ fWU = 500 kHz).
3.16 Clock Genera ti on
The Clock Generation Unit can generate the system clock signal fSYS for the XE161xL
from a number of external or internal clock sou rce s:
• External clock signals with pad voltage or core volta ge levels
• External crystal or resonator using the on-chip oscillator
• On-chip clock source for operation without crystal/resonator
• Wake-up clock (ultra-low-power) to further reduce power consumpti on
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.7.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on the EXTCL K pin.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 47 V1.1, 2011-09
3.17 Parallel Ports
The XE161xL provides up to 3 3 I/O lines which are organ ized into 3 input/outpu t ports
and 1 input port. All port lines are bit-addressable, and all input/output lines can be
individually (bit-wise) configured via port control registers. This configuration selects the
direction (input/output), push/pull or open-drain operation, activation of pull devices, and
edge characteristics (shape) and driver characteristics (output current) of the port
drivers. The I/O ports are true bidirectional ports which are switched to high impedance
state when configured as inputs. During the internal reset, all port pins are configured as
inputs without pull devices active.
All port lines have alternate input or output functions associated with them. These
alternate functions can be programmed to be assigned to various port pins to support the
best utilization for a given appli cation. For thi s reason, certain functions app ear several
times in Table 10.
All port lines that are not used for alternate functions may be used as general purpose
I/O lines.
Table 10 Summary of the XE161xL’s Ports
Group Width I/O Connected Modules
P2 12 I/O Analog in puts, ADC, CAN, CC2, CCU6, DAP/JTAG,
GPT12E, SCU, USIC
P5 6 I Analog inputs, CCU6 , JTAG, GPT12E, CC2
P6 3 I/O Analog inputs, ADC, CCU6, JTAG, GPT12E, USIC
P10 12 I/O CAN, CCU6, GPT12E, DAP/JTAG, SPD, USIC
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 48 V1.1, 2011-09
3.18 Power Management
The XE161xL provides the means to control the power it cons umes either at a given time
or averaged over a certain duration.
Two mechanisms can be used (and partly in parallel):
•Clock Generation Management controls the frequency of internal and external
clock signals. Clock signals for currently inactive parts of logic are disabled
automatically. The user can drastically reduce the consumed power by reducing th e
XE161xL system clock frequency.
External circuits can be controlled using the programmable frequency output
EXTCLK.
•Peripheral Manageme nt permits temporary disabling of perip heral modules. Each
peripheral can be disabled and enabled separately. The CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally with signals
generated by the external system, or internally by the on-chip wake-up timer. This
supports intermittent operation of the XE161xL by generating cyclic wake-up signals.
Full performance is available to quickly react to action requests while the intermittent
sleep phases greatly reduce the average system powe r consumption.
Note: When selecting the suppl y voltage and the clock sou rce and generation meth od,
the required parameters must be carefully written to the respective bit fields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the inte nded operation of power supply system and cloc k system.
Please refer to the Programmer’s Guide.
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 49 V1.1, 2011-09
3.19 Instruction Set Summary
Table 11 lists th e instructions of the XE161xL.
The addressing mode s that can be used with a specific in struction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11 Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise exclusive OR, (word/byte operands) 2 / 4
BCLR/BSET Clear/Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bi t 4
BFLDH/BFLDL Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR 2
SHL/SHR Shift left/right direct word GPR 2
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 50 V1.1, 2011-09
ROL/ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS/Z Move byte operand to word op. with sign/zero extension 2 / 4
JMPA/I/R Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
JB(C) Jump relative if direct bit is set (an d clear bit) 4
JNB(S) Jump relative if direct bit is not set (and set bit) 4
CALLA/I/R Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call
absolute subroutine 4
TRAP Call interrupt service routine vi a immediate trap number 2
PUSH/POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and upda te
register with word operand 4
RET(P) Return from intra-segment subroutine
(and pop direct word register from system stack) 2
RETS Return from inter-segment subroutine 2
RETI Return from interrupt service subroutine 2
SBRK Software Break 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Unused instruction1) 4
SRVWDT Service Watchdog Timer 4
DISWDT/ENWDT Disable/Enable Watchdog Timer 4
EINIT End-of-Initialization Regi ster Lock 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
Table 11 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XE161FL, XE161HL
XE166 Family / Econo Line
Functional Des cription
Data Sheet 51 V1.1, 2011-09
NOP Null operation 2
CoMUL/CoMAC Multiply (and accumulate) 4
CoADD/CoSUB Add/Subtract 4
Co(A)SHR (Arithmetic) Shift right 4
CoSHL Shift left 4
CoLOAD/STORE Load accumulator/Store MAC register 4
CoCMP Compare 4
CoMAX/MIN Maximum/Minimum 4
CoABS/CoRND Absolute value/Round accumu lator 4
CoMOV Data move 4
CoNEG/NOP Negate accumulator/Null operation 4
1) The Enter Power Down Mode instruction is not used in the XE161xL, due to the enhanced power control
scheme. PWRDN will be correctly decoded, but will trigger no action.
Table 11 Instruction Set Summary (cont’d)
Mnemonic Description Bytes
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 52 V1.1, 2011-09
4 Electrical Parameters
The operating range for the XE161xL is defined by its ele c trical parameters. For proper
operation the specified limits must be respected when integrating the device in its target
environment.
4.1 General Parameters
These parameters are valid for all subsequent descriptions, unless otherwise noted.
Note: Stresses above the values li sted under “Absolute Ma ximum Ratings” may cause
permanent damage to the device. This is a stress rating only. Functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for an extended time may affect device reliability.
During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the
voltage on VDDP pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximu m ratings.
Table 12 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Output current on a pin
when high value is driven IOH SR -15 −−mA
Output current on a pin
when low value is driven IOL SR −−15 mA
Overload current IOV SR -5 −5mA 1)
1) Overload condition occu rs if the input voltage VIN is out of the absolute maximum rating range. In this case the
current must be limited to the listed values by desi gn measures.
Absolute sum of overload
currents Σ|IOV|
SR −−30 mA 1)
Junction Te mp erature TJ SR -40 −150 °C
Storage Temperature TST SR -65 −150 °C
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR -0.5 −6.0 V
Voltage on any pin with
respect to ground (Vss) VIN SR -0.5 −VDDP +
0.5 VVIN≤VDDP(max)
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 53 V1.1, 2011-09
4.1.1 Operating Conditions
The following operating conditions must not be exceeded to ensure correct operation of
the XE161xL. All parameters specified in the following secti ons re fe r to the se operatin g
conditions, unless otherwise noticed.
Note: Typical parameter values refer to room temperature and nomina l supply voltage,
minimum/maximum parameter values also include conditions of
minimum/maximum temperature and minimum/maximum supply voltage.
Additional details are described where applicable.
Table 13 Operating Conditions
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Voltage Regulator Buffer
Capacitanc e fo r DMP_M CEVRM
SR 1.0 −4.7 μF 1)2)
External Load
Capacitance CL SR −203) −pF pin out
driver= default
4)
System frequency fSYS SR −−80 MHz 5)
Overload current for
analog inputs6) IOVA SR -2 −5 mA not subject to
production test
Overload current for digital
inputs6) IOVD SR -5 −5 mA not subject to
production test
Overload current coupling
factor for analog inputs7) KOVA
CC −2.5 x
10-4 1.5 x
10-3 -IOV< 0 mA; not
subject to
production test
−1.0 x
10-6 1.0 x
10-4 -IOV> 0 mA; not
subject to
production test
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 54 V1.1, 2011-09
Overload current coupling
factor for digital I/O pins KOVD
CC −1.0 x
10-2 3.0 x
10-2 IOV< 0 mA; not
subject to
production test
−1.0 x
10-4 5.0 x
10-3 IOV> 0 mA; not
subject to
production test
Absolute sum of overload
currents Σ|IOV|
SR −−50 mA not su bj e c t to
production test
Digital core supply voltage
for domain M8) VDDIM
CC −1.5 −V
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0 −5.5 V
Digital ground voltage VSS SR −0−V
1) To ensure the stability of t he voltage r egulators th e EVRs must be b uffered with cer amic capacitors. Separa te
buffer capacitors with the recomended values shall be connected as close as possible to each VDDIM pin to
keep the resistance of the board tracks below 2 Ohm. Connect all VDDIM pins together. The minimum
capacitance value is required for proper operation under all conditions (e.g. temperature). Higher values
slightly increase the startu p time.
2) Use one Capacitor for each pin.
3) This is the reference load. For bigger capacitive loads, use the derating factors listed in the PAD properties
section.
4) The timing is valid for pin drivers operating in default curren t mode (se lected af ter reset) . Reducing the o utput
current may lead to increased delays or reduced driving capability (CL).
5) The operating frequency range may be reduced for specific device types. This is indicated in the device
designation (...FxxL). 66 MHz devices are marked ...F66L.
6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range: VOV > VIHmax (IOV > 0) or VOV < VILmin ((IOV < 0). The absolute sum of input
overload currents on all pins may not exceed 50 mA. The supply voltages must remain within the specified
limits. Proper operation under overload conditions depends on the application. Overload conditions must not
occur on pin XTAL1.
7) An overload current (IOV) through a pin injects a certain error current (IINJ) into the adjacent pins. This error
current adds to the respective pins lea kage current (IOZ). The amount of error current depends on the overload
current and is defined by the overlo ad coupl ing facto r KOV. The polarity of the in jected erro r curren t is inverse
compared to the pola rity of the overl oad current that pr oduces it.The t otal current through a pin is | ITOT| = |IOZ|
+ (|IOV| KOV). The additional error current may distort the input voltage on analog inputs.
Table 13 Operating Conditions (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 55 V1.1, 2011-09
4.2 Voltage Range definit ions
The XE161xL timing depends on the supply voltage. If such a dependency exists the
timing values are given for 2 voltage areas commonly used. The voltage areas are
defined in the following tables.
4.2.1 Parameter Interpretation
The parameters listed in the following include both the characteristics of the XE161xL
and its demands on the system. To aid in correctly interpreting the parameters when
evaluating them for a design, they are marked accordingly in the column “Symbol”:
CC (Controller Characteristics):
The logic of the XE161xL provides signals with the specified characteristics.
SR (System Requirement):
The external system must provide signals with the specified characteristics to the
XE161xL.
8) Value is controlled by on-chip regulator.
Table 14 Upper Voltage Range Definition
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 4.5 5.0 5.5 V
Table 15 Lower Voltage Ra nge Definition
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage for
IO pads and voltage
regulators
VDDP SR 3.0 3.3 4.5 V
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 56 V1.1, 2011-09
4.3 DC Parameters
These parameters are static or average values th at may be exceeded during switching
transitions (e.g. output current).
The XE161xL can operate within a wide supply voltage range from 3.0 V to 5.5 V.
However, during operation this supply voltage must remain within 10 percent of the
selected nominal supply voltage. It cannot vary across the full operating voltage range.
Because of the supply voltage restriction and because electrical behavior depends on
the supply voltage, the parame ters are specified separately for the uppe r and the lower
voltage range.
During operation, the supply voltages may only change with a maximum speed of
dV/dt < 1 V/ms.
Leakage current is strongly dependent on the operating temperature and the voltage
level at the respective pin. The maximum values in the following tables apply under worst
case conditions, i.e. maximum temperature and an input level equal to the supply
voltage.
The value for the leakage current in an application can be determined by using the
respective leakage derating formula (see tables) with values from that application.
The pads of the XE161xL are designed to operate in various driver modes. The DC
parameter specifications refer to the pad current limits specifi ed in Section 4.7.4.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 57 V1.1, 2011-09
Pullup/Pulldown Device Behavior
Most pins of the XE161xL feature pullup or pulldown devices. For some special pins
these are fixed; for the port pins they can be selected by the application.
The specified curre nt values indicate how to load the respective pin dependin g on the
intended signal level. Figure 12 shows the current paths.
The shaded resistors shown in the figure may be required to compensate system pull
currents that do not match the given limit values.
Figure 12 Pullup/Pulldown Current Definition
MC_XC2X_PULL
V
DDP
V
SS
Pullup
Pulldown
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 58 V1.1, 2011-09
4.3.1 DC Parameters for Upper Voltage Area
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 16 is valid under the following conditions: VDDP≤5.5 V; VDDPtyp. 5 V; VDDP≥4.5 V
Table 16 DC Characteristics for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Pin capacitance (digital
inputs/outputs). CIO CC −−10 pF not subject to
production test
Input Hysteresis1) HYS CC 0.11 x
VDDP
−−VRS=0Ohm
Absolute input leakage
current on pins of analog
ports2)
|IOZ1|
CC −10 200 nA VIN>VSS ;
VIN<VDDP
Absolute input leakage
current for all other pins.
2)3)
|IOZ2|
CC −0.2 5 μATJ≤110 °C;
VIN>VSS ;
VIN<VDDP
−0.2 10 μATJ≤150 °C;
VIN>VSS ;
VIN<VDDP
Pull Level Force Current4) |IPLF| SR 220 −−μAVIN≥VIHmin
(pulldown_ena
bled);
VIN≤VILmax
(pullup_enable
d)
Pull Level Keep Current5) |IPLK|
SR −−30 μAVIN≥VIHmin
(pullup_enable
d);
VIN≤VILmax
(pulldown_ena
bled)
Input high voltage (all
except XTAL1) VIH SR 0.7 x
VDDP
−VDDP +
0.3 V
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 59 V1.1, 2011-09
Input low voltage
(all except XTAL1) VIL SR -0.3 −0.3 x
VDDP
V
Output High voltage6) VOH CC VDDP -
1.0 −−VIOH≥IOHmax
VDDP -
0.4 −−VIOH≥IOHnom 7)
Output Low Voltage6) VOL CC −−0.4 V IOL≤IOLnom 8)
−−1.0 V IOL≤IOLmax
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respecti ve supply vo ltage due to ground bouncing ( VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional erro r current (IINJ) will flow if an overload curre nt flows through an adjacent pin.
Please refer to the defini tion of the overload coupling factor KOV.
3) The given values are worst -case val ues. In production test , this l eakage current i s only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current t hrough this pin to change the default pin leve l driven by the enable d pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Table 16 DC Characteristics for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 60 V1.1, 2011-09
4.3.2 DC Parameters for Lowe r V o lta g e Ar ea
Keeping signal levels within the limits specified in this table ensures operation without
overload conditions. For signal levels outside these specifications, also refer to the
specification of the overload current IOV.
Note: Operating Conditions apply.
Table 17 is valid under the following conditions: VDDP≥3.0 V; VDDPtyp. 3.3 V;
VDDP≤4.5 V
Table 17 DC Characteristics for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Pin capacitance (digital
inputs/outputs). CIO CC −−10 pF not subject to
production test
Input Hysteresis1) HYS CC 0.07 x
VDDP
−−VRS=0Ohm
Absolute input leakage
current on pins of analog
ports2)
|IOZ1|
CC −10 200 nA VIN>VSS ;
VIN<VDDP
Absolute input leakage
current for all other pins.
2)3)
|IOZ2|
CC −0.2 2 μATJ≤110 °C;
VIN>VSS ;
VIN<VDDP
−0.2 6 μATJ≤150 °C;
VIN>VSS ;
VIN<VDDP
Pull Level Force Current4) |IPLF| SR 150 −−μAVIN≥VIHmin
(pulldown_ena
bled);
VIN≤VILmax
(pullup_enable
d) ;
Pull Level Keep Current5) |IPLK|
SR −−10 μAVIN≥VIHmin
(pullup_enable
d);
VIN≤VILmax
(pulldown_ena
bled)
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 61 V1.1, 2011-09
Input high voltage (all
except XTAL1) VIH SR 0.7 x
VDDP
−VDDP +
0.3 V
Input low voltage
(all except XTAL1) VIL SR -0.3 −0.3 x
VDDP
V
Output High voltage6) VOH CC VDDP -
1.0 −−VIOH≥IOHmax
VDDP -
0.4 −−VIOH≥IOHnom 7)
Output Low Voltage6) VOL CC −−0.4 V IOL≤IOLnom 8)
−−1.0 V IOL≤IOLmax
1) Not subject to production test - verified by design/characterization. Hysteresis is implemented to avoid
metastable states and switching due to internal ground bounce. It cannot suppress switching due to external
system noise under all conditions.
2) If the input voltage exceeds the respecti ve supply vo ltage due to ground bouncing ( VIN < VSS) or supply ripple
(VIN > VDDP), a certain amount of current may flow through the protection diodes. This current adds to the
leakage current. An additional erro r current (IINJ) will flow if an overload curre nt flows through an adjacent pin.
Please refer to the defini tion of the overload coupling factor KOV.
3) The given values are worst -case val ues. In production test , this l eakage current i s only tested at 125 °C; other
values are ensured by correlation. For derating, please refer to the following descriptions: Leakage derating
depending on temperature (TJ = junction temperature [°C]): IOZ = 0.05 x e(1.5 + 0.028 x TJ>) [μA]. For example, at
a temperature of 95 °C the resulting leakage current is 3.2 μA. Leakage derating depending on voltage level
(DV = VDDP - VPIN [V]): IOZ = IOZtempmax - (1.6 x DV) (μA]. This voltage derating formula is an approximation
which applies for maximum temperature.
4) Drive the indicated minimum current t hrough this pin to change the default pin leve l driven by the enable d pull
device.
5) Limit the current through this pin to the indicated value so that the enabled pull device can keep the default
pin level.
6) The maximum deliverable output current of a port driver depends on the selected output driver mode. This
specification is not valid for outputs which are switched to open drain mode. In this case the respective output
will float and the voltage is determined by the external circuit.
7) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
8) As a rule, with decreasing output current the output levels approach the respective supply level (VOL->VSS,
VOH->VDDP). However, only the levels for nominal output currents are verified.
Table 17 DC Characteristics for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 62 V1.1, 2011-09
4.3.3 Power Consumption
The power consumed by the XE161xL depends on several factors such as supply
voltage, operating frequency, active circuits, and operating temperature. The power
consumption specified here consists of two components:
• The switching current IS depends on the device ac tivity
• The leakage current ILK depends on the device temperature
To determine the actual power consumption, always both components, switching current
IS and leakage current ILK must be added:
IDDP = IS + ILK.
Note: The power consumption values are not subject to production test. They are
verified by design/characterization.
To determine the total power consumption for dimensioning the external power
supply, also the pad driver currents must be con sidered.
The given power consumption parameters and their values refer to specific operating
conditions:
•Active mode:
Regular operation, i.e. periphe rals are active, code executio n out of Flash.
•Stopover mode:
Crystal oscillator and PLL stopped, Flash switched off, clock in most parts of domain
DMP_M stopped.
Note: The maximum values cover the complete specified operating range of all
manufactured devices.
The typical values refer to average devices under typical conditions, such as
nominal supply voltage, room temperature, application-oriented activity.
After a power reset, the decoupling capacitors for VDDIM are charged with the
maximum possible current.
For additional information, please refer to Section 5.2, Thermal Considerations.
Note: Operating Conditions apply.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 63 V1.1, 2011-09
Active Mode Power Supply Current
The actual power supply current in active mode not only depends on the system
frequency but also on the configuration of the XE161xL’s subsystem.
Besides the power consumed by the device logic the power supply pins also provide the
current that flows through the pin outp ut drive r s.
A small current is consumed because the drivers’ input stages are switched.
Table 18 Switching Pow e r Consumption
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Power supply current
(active) with all peripherals
active and EVVRs on
ISACT
CC −6 + 0.5
x fSYS1)
1) fSYS in MHz
8 +
0.75 x
fSYS1)
mA power_mode=
active ;
voltage_range=
both 2)3)4)
2) The pad supply voltage pins (VDDPB) provide the input current for the on-chip EVVRs and the current
consumed by the pin output drivers. A small current is consumed because the drivers input stages are
switched.
3) Please consider the additio nal conditions described in section "Active Mode Power Supply Current".
4) The pad supply voltage only has a minor influence on this parameter.
Power supply current in
stopover mode, EVVRs on ISSO CC −0.7 2.0 mA power_mode=
stopover ;
voltage_range=
both
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 64 V1.1, 2011-09
Figure 13 Supply Current in Active Mode as a Functio n of Freq ue ncy
Note: Operating Conditions apply.
Table 19 Leakage Power Consumption
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Leakage supply current1)2)
1) The supply current caused by leakage depends mainly on the junction temperature and the supply voltage.
The temperature difference between the junction temperature TJ and the ambient temperature TA must be
taken into account. As this fr actio n of the suppl y current does n ot dep end on device a ctivit y, i t must b e added
to other power consumption values.
2) All inputs (including pins configur ed as input s) are set at 0 V to 0 .1 V or at VDDP - 0.1 V to VDDP and all output s
(including pins configured as outputs) are disconne cted.
ILK1 CC −0.03 0.04 mA TJ=25°C
−0.4 1.1 mA TJ=85°C
−1.7 4.9 mA TJ=125°C
−3.5 10.7 mA TJ=150°C
MC_XC2XL_IS
fSYS [MHz]
IS[mA]
10
20
40
20 40 80
60
50
60
70
ISACTtyp
ISACTmax
30
80
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 65 V1.1, 2011-09
Leakage Power Consumption Calculation
The leakage power consumption can be calculated according to the following formulas:
ILK1 = 470,000 + e-α with α = 5000 / (273 + B×TJ)
Parameter B must be replaced by
• 1.0 for typical values
• 1.3 for maximum values
Figure 14 Leakage Suppl y Current as a Function of Te mperature
MC_XC2XL_ILKN
TJ [°C]
ILK [mA]
2
6
10
0 50 150
100-50
4
8
12 ILK1max
ILK1typ
125
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 66 V1.1, 2011-09
4.4 Analog/Digital Converter Parameters
These parameters describe the conditions for optimum ADC performance .
Note: Operating Conditions apply.
Table 20 ADC Parameters for All Voltage Ranges
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Switched capacitance at
an analog input CAINSW
CC −9 20 pF not subject to
production test
1)
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
Total capacitance at an
analog input CAINT
CC −20 30 pF not subject to
production test
1)
Switched capacitance at
the reference input CAREFSW
CC −15 30 pF not subject to
production test
1)
Total capacitance at the
reference input CAREFT
CC −20 40 pF not subject to
production test
1)
Broken wire detection
delay against VAGND2) tBWG CC −−503)
Broken wire detection
delay against VAREF2) tBWR CC −−504)
Conversion time for 8-bit
result2) tc8 CC (10 + STC x tADCI + 2 x
tSYS
Conversion time for 10-bit
result2) tc10 CC (1 2 + STC x tADCI + 2 x
tSYS
Conversion time for 12-bit
result2) tc12 CC (1 6 + STC x tADCI + 2 x
tSYS
Analog reference ground VAGND
SR VSS -
0.05 −1.5 V
Analog input voltage
range VAIN SR VAGND −VAREF V 5)
Analog reference voltage VAREF
SR VAGND
+ 1.0 −VDDPB
+ 0.05 V
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 67 V1.1, 2011-09
2) This parameter includes the sample time (also the additional sample time specified by STC), the time to
determine the digital result and the time to load the result register with the conversion result. Values for the
basic clock tADCI depend on programming.
3) The broken wire detection delay against VAGND is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 500 µs. Result below 10% (66H)
4) The broken wire detection delay against VAREF is measured in numbers of consecutive precharge cycles at a
conversion rate of not more than 10 µs. This function is influenced by leakage current, in particular at high
temperature. Resul t above 80% (332H)
5) VAIN may exceed VAGND or VAREF up to the a bsolute maximum rat ings. However, the conversion r esult in the se
cases will be X000H or X3FFH, respectively.
Table 21 ADC Parameters for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input resistance of the
selected analog channel RAIN CC −0.9 1.5 kOh
mnot subject to
production test
1)
Input resistance of the
reference input RAREF
CC −0.5 1 kOh
mnot subject to
production test
1)
Differential Non-Linearity
Error2)3)4)5) |EADNL|
CC −2.5 5.0 LSB
Gain Error2)3)4)5) |EAGAIN|
CC −2.5 6.0 LSB
Integral Non-
Linearity2)3)4)5) |EAINL|
CC −2.0 4.0 LSB
Offset Error2)3)4)5) |EAOFF|
CC −2.0 4.0 LSB
Analog clock frequency fADCI SR 2 −20 MHz Std. re ference
input (VAREF)
2−17.5 MHz Alt. re ference
input (CH0)
Total Unadjusted Error3)4) |TUE|
CC −2.5 5.5 LSB 6)7)
Wakeup time from analog
powerdown, fast mode tWAF CC −−7.0 μs
Wakeup time from analog
powerdown, slow mode tWAS CC −−11.5 μs
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 68 V1.1, 2011-09
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,
DNL, INL, Gain and Offset errors increase also by the factor 1/k.
5) If the analog reference voltage is > VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage r ange. The specified TUE i s valid only if the ab solute sum of input overlo ad currents on an alog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
Table 22 ADC Parameters for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input resistance of the
selected analog channel RAIN CC −1.4 2.5 kOh
mnot subject to
production test
1)
Input resistance of the
reference input RAREF
CC −1.0 2.0 kOh
mnot subject to
production test
1)
Differential Non-Linearity
Error2)3)4)5) |EADNL|
CC −2.5 5.5 LSB
Gain Error2)3)4)5) |EAGAIN|
CC −3.0 8.0 LSB
Integral Non-
Linearity2)3)4)5) |EAINL|
CC −2.5 7.5 LSB
Offset Error2)3)4)5) |EAOFF|
CC −2.0 5.5 LSB
Analog clock frequency fADCI SR 2 −16.7 MHz Std. reference
input (VAREF)
2−12.1 MHz Alt. re ference
input (CH0)
Total Unadjusted Error3)4) |TUE|
CC −2.5 7.5 LSB 6)7)
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 69 V1.1, 2011-09
Figure 15 Equivalent Circuitry for Analog Inputs
Sample time and conversion time of the XE161xL’ s A/D converters are progra mmable.
The timing abo ve can be calculated using Table 23.
The limit values for fADCI must not be exceeded when selecting the prescaler value.
Wakeup time from analog
powerdown, fast mode tWAF CC −−8.5 μs
Wakeup time from analog
powerdown, slow mode tWAS CC −−15.0 μs
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and VDDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below VDDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,
DNL, INL, Gain and Offset errors increase also by the factor 1/k.
5) If the analog reference voltage is > VDDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at VAREF = VDDPB = 3.3 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage r ange. The specified TUE i s valid only if the ab solute sum of input overlo ad currents on an alog
port pins (see IOV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
Table 22 ADC Parameters for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
A/D Converter
MCS05570
R
Source
V
AIN
C
Ext
C
AINT
C
AINS
-
R
AIN, On
C
AINS
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 70 V1.1, 2011-09
Converter Timing Example A:
Converter Timing Example B:
Table 23 A/D Converter Computatio n Table
GLOBCTR.5-0
(DIVA) A/D Converter
Analog Clock fADCI
INPCRx.7-0
(STC) Sample Time1)
tS
1) The selected sample time is doubled if broken wire detection is active (due to the presa m pling phase).
000000BfSYS 00HtADCI × 2
000001BfSYS / 2 01HtADCI × 3
000010BfSYS / 3 02HtADCI × 4
:fSYS / (DIVA+1) : tADCI × (STC+2)
111110BfSYS / 63 FEHtADCI × 256
111111BfSYS / 64 FFHtADCI × 257
Assumptions: fSYS = 80 MHz (i.e. tSYS = 12.5 ns), DIVA = 03H, STC = 00H
Analog clock fADCI = fSYS / 4 = 20 MHz, i.e. tADCI = 50 ns
Sample time tS= tADCI × 2 = 100 ns
Conversion 12-bit:
tC12 = 16 × tADCI + 2 × tSYS = 16 × 50 ns + 2 × 12.5 ns = 0.825 μs
Conversion 10-bit:
tC10 = 12 × tADCI + 2 × tSYS = 12 × 50 ns + 2 × 12.5 ns = 0.625 μs
Conversion 8-bit:tC8 = 10 × tADCI + 2 × tSYS = 10 × 50 ns + 2 × 12.5 ns = 0.525 μs
Assumptions: fSYS = 66 MHz (i.e. tSYS = 15.2 ns), DIVA = 03H, STC = 00H
Analog clock fADCI = fSYS / 4 = 16.5 MHz, i.e. tADCI = 60.6 ns
Sample time tS= tADCI × 2 = 121.2 ns
Conversion 12-bit:
tC12 = 16 × tADCI + 2 × tSYS = 16 × 60.6 ns + 2 × 15.2 ns = 1.0 μs
Conversion 10-bit:
tC10 = 12 × tADCI + 2 × tSYS = 12 × 60.6 ns + 2 × 15.2 ns = 0.758 μs
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 71 V1.1, 2011-09
Conversion 8-bit:tC8 = 10 × tADCI + 2 × tSYS = 10 × 60 .6 ns + 2 × 15.2 ns = 0.636 μs
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 72 V1.1, 2011-09
4.5 System Parameters
The following parameters specify several aspects which are important when integrating
the XE161xL into an application system.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 24 Various System Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Short-term deviation of
internal clock source
frequency1)
1) The short-term frequency deviation refers to a timeframe of a few hours and is me asured relative to t he current
frequency at the be ginni ng of t he r especti ve ti meframe. This pa rameter i s use fu l to det ermi ne a time span f or
re-triggering a LIN synchron i zation.
ΔfINT CC -1 −1%ΔTJ = ≤ 10°C
Internal clock source
frequency fINT CC 4.8 5.0 5.2 MHz
Wakeup clock source
frequency2)
2) This parameter is tested for the fastest and the slowest selection. The medium selections are not subject to
production test - verified by design/characterization.
fWU CC 400 −700 kHz FREQSEL= 00
210 −390 kHz FREQSEL= 01
140 −260 kHz FREQSEL= 10
110 −200 kHz FREQSEL= 11
Startup time from power-
on with code execution
from Flash
tSPO CC 1.4 1.9 2.4 ms fWU = 500 kHz
Startup time from stopover
mode with code execution
from PSRAM
tSSO CC 11 /
fWU3)
3) fWU in MHz.
−12 /
fWU3) μs
Core voltage (PVC)
supervision level VPVC CC VLV -
0.03 VLV VLV +
0.074) V 5)
Supply watchdog (SWD)
supervision level VSWD
CC VLV -
0.106) VLV VLV +
0.15 V voltage_range=
lower 5)
VLV -
0.15 VLV VLV +
0.15 V voltage_range=
upper 5)
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 73 V1.1, 2011-09
Conditions for tSPO Timing Measurement
The time required for the transition from Power-On to Base mode is called tSPO. It is
measured under the following conditions:
Precondition: The pad supply is valid, i.e. VDDPB is above 3.0 V and remains above 3.0 V
even though the XE161xL is starting up. No debugger is attached.
Start condition: Power on reset is removed (PORST = 1).
End condition: External pin toggle caused by first user instruction executed from Flash
after startup.
Conditions for tSSO Timing Measurement
The time required for the transition from Stopover to Stopover Waked-Up mode is
called tSSO. It is measured under the following conditions:
Precondition: The Stopover mode has been entered using the procedure defined in the
Programmer’s Guide.
Start condition: Pin toggle on ESR pin triggering the startup sequence.
End condition: External pin toggle caused by first user instruction executed from PSRAM
after startup.
4) This value includes a hysteresis of approximately 50 mV for rising voltage.
5) VLV = selected SWD voltage level
6) The limit VLV - 0.10 V is valid for the OK1 level. The limit for the OK2 level is VLV - 0.15 V.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 74 V1.1, 2011-09
Coding of bit fields LEVxV in SWD and PVC Configuration Registers
Table 25 Coding of bit fields LEVxV in Register SWDCO N0
Code Default Voltage Level Notes1)
1) The indicated default levels are selected automatically after a power reset.
0000B2.9 V
0001B3.0 V LEV1V: reset request
0010B3.1 V
0011B3.2 V
0100B3.3 V
0101B3.4 V
0110B3.6 V
0111B4.0 V
1000B4.2 V
1001B4.5 V LEV2V: no request
1010B4.6 V
1011B4.7 V
1100B4.8 V
1101B4.9 V
1110B5.0 V
1111B5.5 V
Table 26 Coding of bit fields LEVxV in Registers PVCyCO N z
Code Default Voltage Level Notes1)
000B0.95 V
001B1.05 V
010B1.15 V
011B1.25 V
100B1.35 V LEV1V: reset request
101B1.45 V LEV2V: interrupt request2)
110B1.55 V
111B1.65 V
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 75 V1.1, 2011-09
1) The indicated default levels are selected automatically after a power reset.
2) Due to variations of the tolerance of both the Embedded Voltage Regulators (EVR) and PVC levels, this
interrupt can be triggered inadvertently, even though the core voltage is within the normal range. It is,
therefore, recommended not to use this warning level.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 76 V1.1, 2011-09
4.6 Flash Memory Parameters
The XE161xL is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XE161xL’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 27 Flas h Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Parallel Flash module
program/erase limit
depending on Flash read
activity
NPP SR −−21) NFL_RD≤1
−−12) NFL_RD>1
Flash erase endurance
for security pages NSEC SR 10 −−cycle
stRET≥20 years
Flash wait states3) NWSFLASH
SR 1−− fSYS≤8MHz
2−− fSYS≤13 MHz
3−− fSYS≤17 MHz
4−− fSYS>17MHz
Erase time per
sector/page tER CC −74) 8.0 ms
Programming time per
page tPR CC −34) 3.5 ms
Data retention time tRET CC 20 −−year
sNER≤1,000 cycl
es
Drain disturb limit NDD SR 32 −−cycle
s
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 77 V1.1, 2011-09
Access to the XE161xL Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Number of erase cycles NER SR −−15000 cycle
stRET≥5 years;
Valid for up to
64 user
selected
sectors (data
storage)
−−1000 cycle
stRET≥20 years
1) All Flash module(s) can be erased/pro grammed while code is executed and/or dat a is read from only one Flash
module or from PSRAM. The Flash module that deliver s code/data can, of course, not be erased/programmed.
2) Flash module 1 can be erased/programmed while code is execut ed and/or data is read from Flash module 0.
3) Value of IMB_IMBCTRL.WSFLASH.
4) Programming and erase times dep end on the internal Flash clock source. The control state machine needs a
few system clock cycles. This increases the stated durations noticably only at extremely low system clock
frequencies.
Table 27 Flas h Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 78 V1.1, 2011-09
4.7 AC Parameters
These parameters descri be the dynamic behavior of the XE161xL.
4.7.1 Testing Waveforms
These values are used for characterization and production testing (except pin XTAL1).
Figure 16 Inp ut Ou tput Waveforms
Figure 17 Floating Waveforms
MCD05556C
0.3 VDDP
In p u t S ign a l
(driven by teste r)
O utput Signal
(measured)
Hold time
Ou tp u t d e la y O utput delay
H o ld time
Output tim ings refer to the rising edge of CLKO UT.
In p u t timin g s a re c a lcu la te d fro m th e time , wh e n th e in p u t s ig n a l re a c h e s
VIH or VIL, re sp e c tively .
0.2 VDDP
0.8 VDDP
0.7 VDDP
MCA05565
Timing
Reference
Points
V
Load + 0.1 V
V
Load - 0.1 V
V
OH - 0.1 V
V
OL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV
change from load voltage occurs, but begins to float when a 100 mV
change from the loaded
V
OH /
V
OL level occu rs (
I
OH /
I
OL = 20 mA).
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 79 V1.1, 2011-09
4.7.2 Definition of Internal Timing
The internal operation of the XE161xL is contro lled by the internal system clock fSYS.
Because the system clock signal fSYS can be generated from a nu mber of internal and
external sources using different mech anisms, the duration of the system clock periods
(TCSs) and their variation (as well as the derived external timing) depend on the
mechanism used to generate fSYS. This must be considered when calculating the timing
for the XE161xL.
Figure 18 Generation Mechanisms for the System Clock
Note: The example of PLL operation shown in Figure 18 uses a PLL factor of 1:4; the
example of prescaler operation uses a divider factor of 2:1.
The specification of the external timing (AC Characteristics) depends on the period of the
system clock (TCS).
MC_XC2X_CLOCKGEN
Phase Locked Loop Operation (1:N)
f
IN
Di rect Clock Dri ve (1:1)
Prescaler Op eratio n ( N :1)
f
SYS
f
IN
f
SYS
f
IN
f
SYS
TCS
TCS
TCS
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 80 V1.1, 2011-09
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11B), the system clock is
derived directly from the input clock signal CLKIN1:
fSYS = fIN.
The frequency of fSYS is the same as the freq uency of fIN. In this case the hi gh and low
times of fSYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL11) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY =
1B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source throu gh the output prescaler K1 (= K1DIV+1):
fSYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of fSYS equals the freque ncy of fOSC. In
this case the high and low times of fSYS are determined by the duty cycle of the input
clock fOSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
fSYS = fOSC / 1024.
4.7.2.1 Phase Locked Loop (PLL)
When PLL operation is sele cted (SYSCON0.CLKSEL = 10B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (fSYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of fSYS so that it is
locked to fIN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage VDDIM.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 81 V1.1, 2011-09
The timing in the AC Characteristics refers to TCSs. Timing must be calculated using the
minimum TCS possible under the give n circumstances.
The actual minimum value for TCS depends on the jitter of the PLL. Because the PLL is
constantly adjusting its output frequency to correspond to the input frequency (from
crystal or oscillator), the accumulated jitter is limited. This means that the relative
deviation for periods of more than one TCS is lower than for a single TCS (see formulas
and Figure 19).
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal fSYS. The number of VCO cycles
is K2 ×T, where T is the number of consecutive fSYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (fSYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T × TCS the accumulated jitter DT is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
fSYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97 × [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63 × [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 82 V1.1, 2011-09
Figure 19 Approximated Accumulated PLL Jitter
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed CL=20pF.
The maximum peak-to-peak noise on the pad supply voltage (measured between
VDDPB pin and VSS pin) is limited to a peak-to-pea k voltage of VPP = 50 mV. This
can be achieved by appropriate blocking of the supply voltage as close as possible
to the supply pins and using PCB supply and ground planes.
PLL frequency band selection
Different frequency bands can be selected for the VCO so that the operation of the PLL
can be adjusted to a wide range of input and output freq uencies:
MC_XC2X_JITTER
Cycles
T
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
D
T
20 40 60 80 100
ns fSYS = 66 M Hz
1
fVCO = 132 M Hz
fVCO = 66 MHz
±9 fSYS = 33 M Hz
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 83 V1.1, 2011-09
4.7.2.2 Wakeup Clock
When wakeup operation is selected (SYSCON0.CLKSEL = 00B), the system clock is
derived from the low-frequency wakeup clock source:
fSYS = fWU.
In this mode, a basic functionality can be maintained without requiring an external clock
source and while minimizing the power consump tion.
4.7.2.3 Selecting and Changing the Operating Frequency
When selecting a clock source and the clock generation method, the required
parameters must be carefully written to the respective bit fields, to avoid unintended
intermediate states.
Many applications change the frequen cy of the system clock (fSYS) during operation in
order to optimize system performance and power consumption. Changing the operating
frequency also changes the switching curren ts, which influ ences the power supply.
To ensure proper o peration of the on-chip EVRs while the y generate the core voltage,
the operating frequency shall only be changed in certain steps. This prevents overshoots
and undershoots of the supply voltage.
To avoid the indicated p roblems, recommen ded sequences are pro vided which en sure
the intended operation of the clock system interacting with the power system.
Please refer to the Programmer’s Guide.
Table 28 System PLL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VCO output frequency fVCO CC 50 −110 MHz VCOSEL=00
B;
VCOmode=
controlled
10 − 40 MHz VCOSEL=00
B;
VCOmode=free
running
100 −160 MHz VCOSEL=01
B;
VCOmode=
controlled
20 −80 MHz VCOSEL=01
B;
VCOmode=free
running
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 84 V1.1, 2011-09
4.7.3 External Clock Input Parameters
These parameters specify the external clock generation for the XE161xL. The clock can
be generated in two ways:
• By connecting a crystal or ceramic resonator to pins XTAL1/XTAL2.
• By supplyi ng an external clock signal. This clock signal can be suppl ied either to
pin XTAL1 (core voltage domain) or to pin CLKIN1 (IO voltage domain).
If connected to CLKIN1, the input signal must reach the defined input levels VIL and VIH.
If connected to XTAL1, a minimum amplitude VAX1 (peak-to-peak voltage) is sufficient for
the operation of the on-chip oscillator.
Note: The given clock timing parameters (t1
…
t4) are only valid for an external clock
input signa l .
Note: Operating Conditions apply.
Table 29 External Clock Input Characteristics
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Oscillator frequency fOSC SR 4 −40 MHz Input= Clock
Signal
4−16 MHz Input= Crystal
or Resonator
XTAL1 input current
absolute value |IIL| CC −−20 μA
Input clock high time t1 SR 6 −−ns
Input clock low time t2 SR 6 −−ns
Input clock rise time t3 SR −88ns
Input clock fall time t4 SR −88ns
Input voltage amplitude on
XTAL11)
1) The amplitude voltage VAX1 refers to the offset voltage VOFF. This offset voltage must be stable during the
operation and the resulting voltage peaks must remain within the limits defined by VIX1.
VAX1 SR 0.3 x
VDDIM
−−VfOSC≥4MHz;
fOSC≤16 MHz
0.4 x
VDDIM
−−VfOSC≥16 MHz;
fOSC≤25 MHz
0.5 x
VDDIM
−−VfOSC≥25 MHz;
fOSC≤40 MHz
Input voltage range limits
for signal on XTAL1 VIX1 SR -1.7 +
VDDIM
−1.7 V 2)
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 85 V1.1, 2011-09
Note: For crystal/resonator operation, it is strongly recommended to measure the
oscillation allowance (negative resistance) in the final target system (layout) to
determine th e op ti mu m parameters for oscillator operation.
The manufacturers of crystals and ceramic resonators offer an oscillator
evaluation service. This evaluation checks the crystal/resonator specification
limits to ensure a reliable oscillatior operation.
Figure 20 External Clock Drive XTAL1
2) Overload conditions must not occur on pin XTAL1.
MC_EXTCLOCK
t
1
t
2
t
OSC
= 1/f
OSC
t
3
t
4
V
OFF
V
AX1
0.1 VAX1
0.9 VAX1
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 86 V1.1, 2011-09
4.7.4 Pad Properties
The output pad drivers of the XE161xL can operate i n several user-selectable modes.
Strong driver mode allows controlling external components requiring higher currents
such as power bridges or LEDs. Reducing th e driving power of an output pad reduces
electromagnetic emissions (EME). In strong driver mode, selecting a slower edge
reduces EME.
The dynamic behavior, i.e. th e rise time and fall time, depends on the applied external
capacitance that must be charged and discharged. Timing values are given for a
capacitance of 20 pF, unless otherwise noted.
In general, the performance of a pad driver depends on the available supply voltage
VDDP. Therefore the following tables list the pad parameters for the upper voltage range
and the lower voltage range, respectively.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 30 is valid under the following conditions: VDDP≤5.5 V; VDDPtyp. 5 V; VDDP≥4.5 V
Table 30 Standard Pad Parameters for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Maximum output driver
current (absolute value)1) IOmax
CC −−3.0 mA Driver_Strength
=Medium
−−5.0 mA Driver_Strength
=Strong
−−0.5 mA Driver_Strength
=Weak
Nominal output driver
current (absolute value) IOnom
CC −−1.0 mA Driver_Strength
=Medium
−−1.6 mA Driver_Strength
=Strong
−−0.25 mA Driver_Strength
=Weak
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 87 V1.1, 2011-09
Rise and Fall times (10% -
90%) tRF CC −−38 +
0.6 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Medium
−−1 +
0.45 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Soft
−−16 +
0.45 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Slow
−−200 +
2.5 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Weak
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-
IOH) must remain below 25 mA.
Table 31 Standard Pad Parameters for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Maximum output driver
current (absolute value)1) IOmax
CC −−1.8 mA Driver_Strength
=Medium
−−3.0 mA Driver_Strength
=Strong
−−0.3 mA Driver_Strength
=Weak
Table 30 Standard Pad Parameters for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 88 V1.1, 2011-09
Nominal output driver
current (absolute value) IOnom
CC −−0.8 mA Driver_Strength
=Medium
−−1.0 mA Driver_Strength
=Strong
−−0.15 mA Driver_Strength
=Weak
Rise and Fall times (10% -
90%) tRF CC −−73 +
0.85 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Medium
−−6 + 0.6
x CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Soft
−−33 +
0.6 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Strong;
Driver_Edge=
Slow
−−385 +
3.25 x
CL
ns CL≥20 pF;
CL≤100 pF;
Driver_Strength
=Weak
1) The total output current that may be drawn at a given time must be limited to protect the supply rails from
damage. For any group of 16 neighboring output pins, the total output current in each direction (ΣIOL and Σ-
IOH) must remain below 25 mA.
Table 31 Standard Pad Parameters for Lower Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 89 V1.1, 2011-09
4.7.5 Synchronous Serial Interface Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 32 is valid under the following conditions: CL=20pF; SSC=master;
voltage_range= upper
Table 32 USIC SSC Master Mode Timing for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tSYS -
81)
1) tSYS = 1 / fSYS
−−ns
Slave select output SELO
inactive afte r la st
SCLKOUT receive edge
t2 CC tSYS -
61) −−ns
Data output DOUT valid
time t3 CC -6 −9ns
Receive data input setup
time to SCLKOUT receive
edge
t4 SR 31 −−ns
Data input DX0 hold time
from SCLKOUT re cei ve
edge
t5 SR -4 −−ns
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 90 V1.1, 2011-09
Table 33 is valid under the following conditions: CL=20pF; SSC=master;
voltage_range= lower
Table 34 is valid under the following conditions: CL=20pF; SSC= slave ;
voltage_range= upper
Table 33 USIC SSC Master Mode Timing for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tSYS -
101)
1) tSYS = 1 / fSYS
−−ns
Slave select output SELO
inactive afte r la st
SCLKOUT receive edge
t2 CC tSYS -
91) −−ns
Data output DOUT valid
time t3 CC -7 −11 ns
Receive data input setup
time to SCLKOUT receive
edge
t4 SR 40 −−ns
Data input DX0 hold time
from SCLKOUT re cei ve
edge
t5 SR -5 −−ns
Table 34 USIC SSC Slave Mode Timing for Upper Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Select input DX2 setup to
first clock input DX1
transmit edg e 1)
t10 SR 10 −−ns
Select input DX2 hold after
last clock input DX1
receive edg e1)
t11 SR 7 −−ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR 7 −−ns
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 91 V1.1, 2011-09
Table 35 is valid under the following conditions: CL=20pF; SSC= slave ;
voltage_range= lower
Data input DX0 hold time
from clock input DX1
receive edg e1)
t13 SR 5 −−ns
Data output DOUT valid
time t14 CC 7 −33 ns
1) These input timings are valid f or asynchronous input signal ha ndling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 35 USIC SSC Slave Mode Timing for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Select input DX2 setup to
first clock input DX1
transmit edg e 1)
1) These input timings are valid f or asynchronous input signal ha ndling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
t10 SR 10 −−ns
Select input DX2 hold after
last clock input DX1
receive edg e1)
t11 SR 7 −−ns
Receive data input setup
time to shift clock receive
edge1)
t12 SR 7 −−ns
Data input DX0 hold time
from clock input DX1
receive edg e1)
t13 SR 5 −−ns
Data output DOUT valid
time t14 CC 8 −41 ns
Table 34 USIC SSC Slave Mode Timing for Upper Voltage Range (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 92 V1.1, 2011-09
Figure 21 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration where the slave select signal
is low-active and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock Output
SCLKOUT
Data Output
DOUT
t
3
t
3
t
5
Data
valid
t
4
First Tran smit
Edge
Data Input
DX0
Select Output
SELOx
Active
Master Mode Timing
S lave Mode Ti ming
t
11
t
10
Clock Input
DX1
Data Output
DOUT
t
14
t
14
Data
valid
Data Input
DX0
Select Input
DX2
Active
t
13
t
12
Tr a nsmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Receive
Edge Last Receive
Edge
InactiveInactive
T ransmit
Edge
InactiveInactive
First Transmit
Edge Receive
Edge Transmit
Edge Last Recei ve
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLKC FG = 00
B
. Also valid for for SCLKCFG = 01
B
with inver ted SCLKOUT signal.
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 93 V1.1, 2011-09
4.7.6 Debug Interface Timing
The debugger can communicate with the XE161xL via 1-pin SPD interface, via the 2-pin
DAP interface or via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 36 is valid under the following conditions: CL= 20 pF; voltage_ra nge= upper
Table 36 DAP Interface Timing for Upp er Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAP0 clock period t11 SR 1001)
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
−−ns
DAP0 high time t12 SR 8 −−ns
DAP0 low time t13 SR 8 −−ns
DAP0 clock rise time t14 SR −−4ns
DAP0 clock fall time t15 SR −−4ns
DAP1 setup to DAP0
rising edge t16 SR 6 −−ns pad_type= stan
dard
DAP1 hold after DAP0
rising edge t17 SR 6 −−ns pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t19 CC 92 95 −ns pad_type= stan
dard
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 94 V1.1, 2011-09
Table 37 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Figure 22 Test Clock Timing (DAP0)
Table 37 DAP Interface Timi ng for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DAP0 clock period t11 SR 1001)
1) The debug interface cannot operate faster than the overall system, therefore t11 ≥ tSYS.
−−ns
DAP0 high time t12 SR 8 −−ns
DAP0 low time t13 SR 8 −−ns
DAP0 clock rise time t14 SR −−4ns
DAP0 clock fall time t15 SR −−4ns
DAP1 setup to DAP0
rising edge t16 SR 6 −−ns pad_type= stan
dard
DAP1 hold after DAP0
rising edge t17 SR 6 −−ns pad_type= stan
dard
DAP1 valid per DAP0
clock period2)
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t19 CC 87 92 −ns pad_type= stan
dard
MC_DAP0
0.9
VDDP
0.5
VDDP
t
11
t
12
t
13
0.1
VDDP
t
15
t
14
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 95 V1.1, 2011-09
Figure 23 DAP Timing Host to Device
Figure 24 DAP Timing Device to Host
Note: The transmission timing is determined by the receiving debugger by evaluating the
sync-request synchronization pattern telegram.
t
16
t
17
DAP0
DAP1
MC_DAP1_RX
DAP1
MC_DAP1_TX
t
11
t
19
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 96 V1.1, 2011-09
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not sub j ect to p roduction test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 38 is valid un der the following conditions: CL= 20 pF; voltage_range= upper
Table 38 JTAG Interface Timing for Upper Volta ge Ra nge
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1 SR 1001)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
−−ns 2)
2) Under typical conditions, the JTAG interface can operate at transfer rates up to 10 MHz.
TCK high time t2 SR 16 −−ns
TCK low time t3 SR 16 −−ns
TCK clock rise time t4 SR −−8ns
TCK clock fall time t5 SR −−8ns
TDI/TMS setup to TCK
rising edge t6 SR 6 −−ns
TDI/TMS hold after TCK
rising edge t7 SR 6 −−ns
TDO valid from TCK falling
edge (propagation delay)3)
3) The falling edge on TCK is used to generate the TDO timing.
t8 CC −29 32 ns
TDO high impedance to
valid output from TCK
falling edge4)3)
4) The setup time for TDO is given implicitly by the TCK cycle time.
t9 CC −29 32 ns
TDO valid output to high
impedance from TCK
falling edge3)
t10 CC −29 32 ns
TDO hold after TCK falling
edge3) t18 CC 5 −−ns
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 97 V1.1, 2011-09
Table 39 is valid under the following conditions: CL= 20 pF; voltage_range= lower
Table 39 JTAG Interface Timing for Lower Voltage Range
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1 SR 1001)
1) The debug interface cannot operate faster than the overall system, therefore t1 ≥ tSYS.
−−ns
TCK high time t2 SR 16 −−ns
TCK low time t3 SR 16 −−ns
TCK clock rise time t4 SR −−8ns
TCK clock fall time t5 SR −−8ns
TDI/TMS setup to TCK
rising edge t6 SR 6 −−ns
TDI/TMS hold after TCK
rising edge t7 SR 6 −−ns
TDO valid from TCK falling
edge (propagation delay)2)
2) The falling edge on TCK is used to generate the TDO timing.
t8 CC −39 43 ns
TDO high impedance to
valid output from TCK
falling edge3)2)
3) The setup time for TDO is given implicitly by the TCK cycle time.
t9 CC −39 43 ns
TDO valid output to high
impedance from TCK
falling edge2)
t10 CC −39 43 ns
TDO hold after TCK falling
edge2) t18 CC 5 −−ns
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 98 V1.1, 2011-09
Figure 25 Test Clock Timing (TCK)
Figure 26 JTAG Timing
MC_JTAG_TCK
0.9
VDDP
0.5
VDDP
t
1
t
2
t
3
0.1
VDDP
t
5
t
4
t6t7
t6t7
t9t8t10
TCK
TMS
TDI
TDO
MC_JTAG
t18
XE161FL, XE161HL
XE166 Family / Econo Line
Electrical Parameters
Data Sheet 99 V1.1, 2011-09
Debug via SPD
The SPD interface will work with standard SPD tools having a sample/output clock
frequency deviation of +/- 5% or less.
Note: For further details please refer to application note AP24004 in section SPD Timing
Requirements.
Note: Operating Conditions apply.
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
Data Sheet 100 V1.1, 2011-09
5 Package and Reliability
The XE166 Family devices use the package type:
• PG-VQFN (Plastic Green - Very Thin Profile Quad Flat Non-Leaded Packag e)
The following specifications must be regarded to ensure proper integration of the
XE161xL in its target environment.
5.1 Packaging
These parameters specify the packaging rather than the silicon.
Note: To improve the EMC behavior, it is recommended to con nect the exposed pad to
the board ground, independent of the thermal require ments.
Board layout examples are given in an applica tion note.
Package Compatibility Considerations
The XE161xL is a member of the XE166 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
Table 40 Package Parameters (PG-VQFN-48-54)
Parameter Symbol Limit Values Unit Notes
Min. Max.
Exposed Pad Dimension Ex × Ey – 5.2 x 5.2 mm –
Power Dissipation PDISS –0.7W–
Thermal resistance
Junction-Ambient RΘJA – 73 K/W No thermal via,
2-layer1)
1) Device mounted on a 2-layer JEDEC board (according to JESD 51-3) without thermal vias; exposed pad not
soldered.
49 K/W No thermal via,
4-layer2)
2) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) without thermal vias; exposed pad not
soldered.
43 K/W 4-layer, no pad3)
3) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad not
soldered.
34 K/W 4-layer, pad4)
4) Device mounted on a 4-layer JEDEC board (according to JESD 51-7) with thermal vias; exposed pad soldered
to the board.
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
Data Sheet 101 V1.1, 2011-09
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Pad (if present) may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
Data Sheet 102 V1.1, 2011-09
Package Outlines
Figure 27 PG-VQFN-48-54 (Plastic Green Thin Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
0.9 MAX.
SEATING PLANE
Index Marking
+0.03
0.4 x 45˚
(0.65)
Index Marking
13
12
24
25
48
1
(5.2)
37
36
7
±0.1
A
6.8
6.8
48x
0.08
(0.2)
0.05 MAX.
C
7±0.1
B
11 x 0.5 = 5.5
0.5
0.5
11 x 0.5 = 5.5
0.4±0.07
(6.2)
(6.2)
(5.2)
0.23
0.26
0.15
M
±0.05
±0.03
48x
0.1 A B C
PG-VQFN-48-15, -19, -20, -22, -24, -48, -51, -52, -53, -55, -56-PO V12
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
Data Sheet 103 V1.1, 2011-09
5.2 Thermal Considerations
When operating the XE161xL in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting the rma l
damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
XE161FL, XE161HL
XE166 Family / Econo Line
Package and Reliability
Data Sheet 104 V1.1, 2011-09
5.3 Quality Declarations
The operation lifetime of the XE161xL depends on the operating temperature. The
lifetime decreases with increasing temperature as shown in Table 42.
Table 41 Quality Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Operation lifetime tOP CC −−20 a See Table 42
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR −−2000 V EIA/JESD22-
A114-B
Moisture sensitivity level MSL CC −−3−JEDEC
J-STD-020C
Table 42 Lifetime Dependency on Temperature
Operating Time Operating Temper ature
20 a TJ ≤ 110°C
95 500 h TJ = 120°C
68 500 h TJ = 125°C
49 500 h TJ = 130°C
26 400 h TJ = 140°C
14 500 h TJ = 150°C
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