3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) IDT71V016SA Features Description The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs and automotive applications. The IDT71V016 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA. 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times -- Automotive: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball Plastic FBGA packages Functional Block Diagram OE A0 - A15 Output Enable Buffer Address Buffers Row / Column Decoders I/O15 CS 8 Chip Enable Buffer High Byte I/O Buffer 8 I/O8 WE Write Enable Buffer 16 64K x 16 Memory Array Sense Amps and Write Drivers I/O7 8 Low Byte I/O Buffer 8 I/O0 BHE Byte Enable Buffers BLE 6818 drw 01 DECEMBER 2004 1 (c)2004 Integrated Device Technology, Inc. DSC-6818/00 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 BHE C S I/O0 6 39 BLE 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 VDD 11 34 VSS VSS 12 33 VDD I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC SO44-1 SO44-2 SOJ/TSOP Top View 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O8 BHE A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VDD E VDD I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 6818 tbl 02a FBGA (BF48-1) Top View Pin Description 6818 drw 02 Truth Table(1) CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATA OUT High Byte Read L L H L L DATAOUT DATA OUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled Function 6818 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 2 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings (1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to VSS -0.5 to VDD+0.5 V Temperature Under Bias TBIAS Junction Temperature Page TJ Recommended Operating Temperature and Supply Voltage -40C to +125C 0V See Below Automotive Grade 2 -40C to +105C 0V See Below Automotive Grade 3 -40C to +85C 0V See Below -40 to +150 C Automotive Grade 4 0C to +70C 0V See Below -65 to +150 o C 1.25 IOUT DC Output Current 50 6818 tbl 04 Recommended DC Operating Conditions W mA Symbol 6818 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter V DD Supply Voltage Vss Ground VIH VIL Capacitance Input High Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 2.0 ____ (1) Input Low Voltage VDD+0.3 V 0.8 V ____ -0.3 V (1) 6818 tbl 05 NOTE: 1. Refer to maximum overshoot/undershoot diagram below. The measured voltage at device pin should not exceed half sinusoidal wave with 2V peak and half period of 2ns. (TA = +25C, f = 1.0MHz, SOJ/TSOP package) Parameter(1) I/O Capacitance Automotive Grade 1 C Power Dissipation CI/O VDD o PT Input Capacitance VSS -55 to +125 Storage Temperature CIN Temperature o TSTG Symbol Grade Conditions Max. Unit V IN = 3dV 6 pF V OUT = 3dV 7 pF Maximum Overshoot/Undershoot 6818 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. VIH +2V 2ns VIL 2ns -2V DC Electrical Characteristics 6818 drw 12 (VDD = Min. to Max., Automotive Temperature Ranges) Symbol |ILI| |ILO| Parameter Input Leakage Current Output Leakage Current Test Conditions Automotive Temperature Grade IDT71V016SA Min. Max. 1 and 2 ___ 5 3 and 4 ___ 1 1 and 2 ___ 5 3 and 4 ___ 1 VDD = Max., VIN = VSS to VDD VDD = Max., CS = VIH, VOUT = VSS to VDD Unit A A V OL Output Low Voltage IOL = 8mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VDD = Min. 2.4 ___ V 6818 tbl 07 6.42 3 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (1,2) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD - 0.2V, Automotive Temperature Ranges) 71V016SA12 Parameter 71V016SA15 Automotive Grade 71V016SA20 Automotive Grade Automotive Grade Unit Symbol ICC Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(3) 1 2 3 and 4 1 2 3 and 4 1 2 3 and 4 Max. 110 100 90 80 80 80 80 80 80 Typ.(4) 75 75 75 70 70 70 70 70 70 mA ISB Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(3) 45 45 35 35 35 30 30 30 30 mA ISB1 Full Standby Power Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(3) 5 5 2 5 5 2 5 5 2 mA 6818 tbl 8 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and V DD - 0.2V (High). 3. fMAX = 1/t RC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 4. Typical values are measured at 3.3V, 25C and with equal read and write cycles. These parameter is guaranteed by device characterization but is not production tested. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figure 1, 2 and 3 6818 tbl 09 3.3V AC Test Loads DATA OUT +1.5V I/O Z0 = 50W 5pF* 50 W 320 W 350 W *Including jig and scope capacitance. 30pF Figure 2. AC Test Load 6818 drw 03 (for t CLZ, tOLZ, tCHZ, tOHZ , tOW, and tWHZ) Figure 1. AC Test Load Figure 3. Output Capacitive Derating 6.42 4 6818 drw 04 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) AC Electrical Characteristics Commercial and Industrial Temperature Ranges (VDD = Min. to Max., Automotive Temperature Ranges) 71V016SA12 Symbol Parameter 71V016SA15 71V016SA20 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 ____ 15 ____ 20 ____ ns tAA Address Access Time ____ 12 ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 12 ____ 15 ____ 20 ns tCLZ(1,2) Chip Select Low to Output in Low-Z 4 ____ 5 ____ 5 ____ ns tCHZ(1,2) Chip Select High to Output in High-Z ____ 6 ____ 6 ____ 8 ns Output Enable Low to Output Valid ____ 6 ____ 6 ____ 8 ns 1 ____ 1 ____ 1 ____ ns ____ 6 ____ 6 ____ 8 ns tOE (1,2) tOLZ Output Enable Low to Output in Low-Z tOHZ(1,2) Output Enable High to Output in High-Z tOH Output Hold from Address Change 4 -- 4 -- 4 -- ns tBE Byte Enable Low to Output Valid -- 6 -- 6 ____ 8 ns tBLZ(1,2) Byte Enable Low to Output in Low-Z 1 ____ 1 ____ 1 ____ ns ____ 6 ____ 6 ____ 8 ns 0 ____ 0 ____ 0 ____ ns (1,2) tBHZ Byte Enable High to Output in High-Z tPU(3) Chip Select Low toPower Up tPD(3) Chip Select High toPower Down ____ 12 ____ 15 ____ 20 ns Write Cycle Time 12 ____ 15 ____ 20 ____ ns ns WRITE CYCLE tWC tAW Address Valid to End of Write 8 ____ 10 ____ 12 ____ tCW Chip Select Low to End of Write 8 ____ 10 ____ 12 ____ ns tBW Byte Enable Low to End of Write 9 ____ 10 ____ 12 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns 0 ____ 0 ____ 0 ____ ns 8 ____ 10 ____ 12 ____ ns 6 ____ 8 ____ 9 ____ ns 0 ____ 0 ____ 0 ____ ns 3 ____ 3 ____ ns ____ 6 ____ 8 ns Address Hold from End of Write tWR tWP Write Pulse Width tDW Data Valid to End of Write tDH Data Hold Time (1,2) tOW Write Enable High to Output in Low-Z 3 ____ tWHZ(1,2) Write Enable Low to Output in High-Z ____ 6 NOTES: 1. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ, and tWHZ is less than tOW for any given device. 2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 3. This parameter is guaranteed by design and not production tested. 6818 tbl 10 Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH tOH DATAOUT DATAOUT VALID PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 6818 drw 06 6.42 5 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) tRC ADDRESS tAA tOH OE tOHZ tOE tOLZ (3) (3) CS tCLZ (3) tACS (2) tCHZ (3) BHE, BLE (2) tBE tBLZ tBHZ (3) (3) DATAOUT ICC VDD Supply ISB Current DATA OUT VALID tPD tPU 6818 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW C S tCW (2) tCHZ (5) tBW BHE , BLE tWR WE tAS (5) (5) tWHZ tOW DATAOUT tBHZ tWP PREVIOUS DATA VALID (3) (5) DATA VALID tDW DATAIN tDH DATAIN VALID 6818 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + t DW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 6 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW C S tAS tCW (2) tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 6818 drw 09 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) tWC ADDRESS tAW C S tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 6818 drw 10 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + t DW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 7 IDT71V016SA, 3.3V CMOS Static RAM for Automotive Applications 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71V016 Device Type SA XX XXX Power Speed Package X X X Process/ Tape & Reel Temperature Range 8 1 2 3 4 G Automotive Grade 1 (-40C to +125C) Automotive Grade 2 (-40C to +105C) Automotive Grade 3 (-40C to +85C) Automotive Grade 4 (0C to +70C) Restricted hazardous substance device Y PH BF 400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2) 7.0 x 7.0 mm FBGA (BF48-1) 12 15 20 Speed in nanoseconds 6818 drw 11 6.42 8 IDT71V016SA, 3.3V CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Datasheet Document History Rev 0 Date 12/17/04 Page p. 1-8 Description Released Automotive datasheet CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 9 for Tech Support: ipchelp@idt.com 800-345-7015