MC100LVEL56DWG - ON SEMICONDUCTOR

November, 2008 − Rev. 12

1Publication Order Number:

MC100LVEL56/D

MC100LVEL56

3.3V ECL Dual Differential

2:1 Multiplexer

Description

The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The

differential data path makes the device ideal for multiplexing low skew

clock or other skew sensitive signals.

The device features both individual and common select inputs to

address both data path and random logic applications.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs are

left open the D input will pull down to VEE, The D input will bias

around VCC/2 forcing the Q output LOW.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB and

VCC via a 0.01 mF capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

Features

•580 ps Typical Propagation Delays

•Separate and Common Select

•The 100 Series Contains Temperature Compensation

•PECL Mode Operating Range:

VCC = 3.0 V to 3.8 V with VEE = 0 V

•NECL Mode Operating Range:

VCC = 0 V with VEE = −3.0 V to −3.8 V

•Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL

•Q Output will Default LOW with Inputs Open or at VEE

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

*For additional marking information, refer to

Application Note AND8002/D.

MARKING DIAGRAM*

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

SO−20 WB

DW SUFFIX

CASE 751D

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

100LVEL56

AWLYYWWG

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MC100LVEL56

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D0bD0b D1aVBBO

1718 16 15 14 13 12

43 56789

SEL0 SEL1 VCC Q1 Q1 VEE

D0a

1920

VCC Q0

D1aD0a

COM_SEL

VBB1 D1bD1b

10 1 0

Table 1. PIN DESCRIPTION

D0a* − D1a*

D0a* − D1a* ECL Input Data a Invert

FUNCTION

ECL Input Data a

D0b* − D1b*

D0b* − D1b* ECL Input Data b Invert

ECL Input Data b

SEL0* − SEL1*

COM_SEL* ECL Common Select Input

ECL Indiv. Select Input

VBB0, VBB1

Q0 − Q1 ECL True Outputs

Output Reference Voltage

Q0 − Q1 ECL Inverted Outputs

VCC Positive Supply

VEE Negative Supply

SEL0

Table 2. TRUTH TABLE

Q0,

SEL1

COM_SEL

Q1,

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Figure 1. 20−Lead Package (Top View) and Logic Diagram

* Pins will default LOW when left open.

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 KW

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 200 V

> 4 kV

Moisture Sensitivity, (Note 1)

Pb (Indefinite Time Out of Drypack)

Pb−Free

Level 1

Level 3

Flammability Rating

Oxygen Index

UL 94 V−0 @ 0.125 in

28 to 34

Transistor Count 147

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MC100LVEL56

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Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V

VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

6 to 0

−6 to 0

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−20 WB

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SO−20 WB 30 to 35 °C/W

Tsol Wave Solder Pb

Pb−Free

t2 to 3 sec @ 248°C

t2 to 3 sec @ 260°C

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 5. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 24 20 24 20 24 mA

VOH Output HIGH Voltage (Note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV

VOL Output LOW Voltage (Note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV

VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV

VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV

VBB Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 4)

Vpp < 500 mV

Vpp y 500 mV

1.3

1.5

2.9

1.2

1.4

2.9

1.2

1.4

2.9

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current Dn

0.5

−600

0.5

−600

0.5

−600

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP(min)

and 1 V.

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Table 6. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 20 24 20 24 20 24 mA

VOH Output HIGH Voltage (Note 6) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV

VOL Output LOW Voltage (Note 6) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV

VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV

VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV

VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V

VIHCMR Input HIGH Voltage Common Mode

Range (Differential) (Note 7)

Vpp < 500 mV

Vpp y 500 mV

−2.0

−1.8

−0.4

−2.1

−1.9

−0.4

−2.1

−1.9

−0.4

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current Dn

0.5

−600

0.5

−600

0.5

−600

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.

7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input

signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin

and 1 V.

Table 7. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 8)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Toggle Frequency

(See Figure 2, Fmax/JITTER)

1 GHz

tPLH

tPHL

Propagation Delay to Output

SEL

COMSEL

400

430

600

730

420

440

620

740

440

450

640

750

tSKEW Within−Device Skew (Note 9) 40 80 40 80 40 80 ps

tSKEW Duty Cycle Skew (Note 10) 100 100 100 ps

tJITTER Random Clock Jitter (RMS) 1.5 ps

VPP Input Swing (Note 11) 150 1000 150 1000 150 1000 mV

Output Rise/Fall Times Q

(20% − 80%)

200 540 200 540 200 540 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

8. VEE can vary ±0.3 V.

9. Within-device skew is defined as identical transitions on similar paths through a device.

10.Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point

of the outputs.

11. VPP(min) is minimum input swing for which AC parameters are guaranteed.

MC100LVEL56

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100

200

300

400

500

600

700

800

900

1000

0 250 500 750 1000 1250 1500 1750 2000

(JITTER)

Figure 2. Fmax/Jitter

FREQUENCY (MHz)

OUTPUT VOLTAGE (mV amplitude)

JITTER (ps RMS)

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

MC100LVEL56

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ORDERING INFORMATION

Device Package Shipping†

MC100LVEL56DW SO−20 WB 38 Units / Rail

MC100LVEL56DWG SO−20 WB

(Pb−Free)

38 Units / Rail

MC100LVEL56DWR2 SO−20 WB 1000 / Tape & Reel

MC100LVEL56DWR2G SO−20 WB

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100LVEL56

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PACKAGE DIMENSIONS

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

SO−20 WB

DW SUFFIX

CASE 751D−05

ISSUE G

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent

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applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC100LVEL56/D

ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).

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