4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC AD7605-4 Data Sheet FEATURES GENERAL DESCRIPTION 4 simultaneously sampled inputs True bipolar analog input ranges: 10 V (maximum), 5 V (maximum) Single 5 V analog supply and 2.5 V to 5 V VDRIVE (nominal) Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 M analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 16-bit ADC with 300 kSPS on all channels Flexible parallel/serial interface Serial peripheral interface (SPI)/QSPI/MICROWIRE/DSP compatible Performance 7 kV ESD rating on analog input pins Standby mode: 25 mW (typical) 64-lead LQFP package The AD7605-41 is a 4-channel, 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS). The device contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7605-4 operates from a single 5 V supply and can accommodate 10 V and 5 V true bipolar input signals while sampling at throughput rates of up to 300 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to 16.5 V. The AD7605-4 has 1 M analog input impedance, regardless of sampling frequency. The single-supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7605-4 is SPI, QSPITM, MICROWIRETM, and digital signal processor (DSP) compatible. APPLICATIONS Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions Power line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) Resolution (Bits) 18 16 14 Single-Ended Inputs AD7608 AD7606 AD7606-6 AD7606-4 AD7605-4 AD7607 True Differential Inputs AD7609 No. of Simultaneous Sampling Channels 8 8 6 4 4 8 FUNCTIONAL BLOCK DIAGRAM AVCC V1 CLAMP V1GND CLAMP V2 CLAMP V2GND CLAMP V3 CLAMP V3GND CLAMP V4 CLAMP V4GND CLAMP 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB 1M RFB SECONDORDER LPF AVCC REGCAP REGCAP REFCAPB REFCAPA 2.5V LDO T/H 2.5V LDO REFIN/REFOUT SECONDORDER LPF SECONDORDER LPF SECONDORDER LPF T/H T/H 2.5V REF 4:1 MUX SERIAL 16-BIT SAR T/H PARALLEL/ SERIAL INTERFACE REF SELECT AGND DB7/DOUTA DB8/DOUTB RD/SCLK CS PAR/SER/BYTE SEL VDRIVE CONTROL INPUTS AGND CONVST A CONVST B RESET RANGE DB0 TO DB15/BYTESEL BUSY FRSTDATA 13503-001 CLK OSC AD7605-4 PARALLEL Figure 1. Protected by U.S. Patent No. 8,072,360 B2. Rev. 0 1 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7605-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Transfer Function ............................................................. 19 Applications ....................................................................................... 1 Internal/External Reference ...................................................... 20 General Description ......................................................................... 1 Typical Connection Diagram ................................................... 21 Functional Block Diagram .............................................................. 1 Power-Down Modes .................................................................. 21 Revision History ............................................................................... 2 Conversion Control ................................................................... 22 Specifications..................................................................................... 3 Applications Information .............................................................. 23 Timing Specifications .................................................................. 5 Parallel Interface (PAR/SER/BYTE SEL = 0).......................... 23 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 Parallel Byte (PAR/SER/BYTE SEL = 1, DB15/BYTE SEL = 1) ................................................................ 23 ESD Caution .................................................................................. 9 Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 24 Pin Configuration and Function Descriptions ........................... 10 Reading During Conversion ..................................................... 24 Typical Performance Characteristics ........................................... 13 Layout Guidelines....................................................................... 25 Terminology .................................................................................... 17 Outline Dimensions ....................................................................... 27 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 27 Converter Details........................................................................ 18 Analog Input ............................................................................... 18 REVISION HISTORY 9/2016--Revision 0: Initial Version Rev. 0 | Page 2 of 27 Data Sheet AD7605-4 SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 300 kSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) (SINAD) Ratio Dynamic Range Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Channel-to-Channel Isolation ANALOG INPUT FILTER Full Power Bandwidth tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity Integral Nonlinearity Total Unadjusted Error (TUE) Positive Full-Scale (PFS) Error Drift Matching Bipolar Zero Code Error Drift Matching Negative Full-Scale (NFS) Error Drift Matching Test Conditions/Comments fIN = 1 kHz sine wave, unless otherwise noted 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range Min Typ Max 86.5 86 86.5 90 89 90 dB dB dB 86 89 90.5 90 -107 -108 dB dB dB dB dB -95 Unit fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 160 kHz -110 -106 -95 dB dB dB -3 dB, 10 V range -3 dB, 5 V range -0.1 dB, 10 V range -0.1 dB, 5 V range 10 V range 5 V range 23 15 10 5 11 15 kHz kHz kHz kHz s s No missing codes 10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range 10 V range 5 V range External reference Internal reference External reference Internal reference 10 V range 5 V range Rev. 0 | Page 3 of 27 16 0.5 0.5 6 12 8 8 2 7 5 16 1 3 10 5 1 6 8 8 4 8 5 16 0.99 2 32 32 40 6 12 8 22 32 32 40 Bits LSB1 LSB LSB LSB LSB LSB ppm/C ppm/C LSB LSB LSB LSB V/C V/C LSB LSB LSB LSB ppm/C ppm/C LSB LSB AD7605-4 Parameter ANALOG INPUT Input Voltage Range Analog Input Current Input Capacitance Input Impedance REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input Voltage High (VINH) Low (VINL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output Voltage High (VOH) Low (VOL) Floating State Leakage Current Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE Total Current, ITOTAL Normal Mode Static Operational Standby Mode Shutdown Mode Power Dissipation Normal Mode Static Operational Standby Mode Shutdown Mode 1 Data Sheet Test Conditions/Comments Min RANGE = 1 RANGE = 0 Input voltage (VIN) = 10 V VIN = 5 V Typ Max Unit 10 5 V V A A pF M 2.525 1 V A pF V 9 2.5 5 1 2.475 REF SELECT = 1 REFIN/REFOUT 2.5 7.5 2.49 to 2.505 10 ppm/C 0.7 x VDRIVE 0.3 x VDRIVE 2 5 ISOURCE = 100 A ISINK = 100 A VDRIVE - 0.2 0.2 1 5 16 Twos complement All four channels included 2 1 300 Per channel, all four channels included 2.5 V to 5 V nominal Digital inputs = 0 V or VDRIVE 4.75 2.3 fSAMPLE = 300 kSPS fSAMPLE = 300 kSPS LSB means least significant bit. With a 5 V input range, 1 LSB = 152.58 V. With a 10 V input range, 1 LSB = 305.175 V. Rev. 0 | Page 4 of 27 20 V V A pF V V A pF Bits s s kSPS 5 5.25 5.25 V V 10 12 5 2 12 15.2 8 6 mA mA mA A 52 71 25 10 61 80 42 31.5 mW mW mW W Data Sheet AD7605-4 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. Note that throughout this data sheet, multifunction pins, such as RD/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, RD, when only that function is relevant. Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE VINL = 0.1 x VDRIVE and VINH = 0.9 x VDRIVE Logic Input Levels Min Typ Max VINL = 0.3 x VDRIVE and VINH = 0.7 x VDRIVE Logic Input Levels Min Typ Max Unit 3.33 3.33 s tCONV tWAKE-UP STANDBY 2 2.08 100 2 2.08 100 s s tWAKE-UP SHUTDOWN Internal Reference 30 30 ms External Reference 13 13 ms tRESET t1 t2 t3 t4 t5 50 t11 t12 t13 0.5 0.5 ns ns ns ns ns ms 25 25 ns 25 25 0 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 50 40 45 25 25 0 25 25 ns 0 0 0 0 ns ns 16 21 25 32 15 22 19 24 30 37 15 22 ns ns ns ns ns ns 16 20 25 30 19 24 30 37 ns ns ns ns 16 21 25 32 19 24 30 37 ns ns ns ns t14 Rev. 0 | Page 5 of 27 Description See Figure 2 and Figure 3 1/throughput rate, parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines Conversion time STBY rising edge to CONVST x rising edge; powerup time from standby mode; not shown in Figure 2 or Figure 3 Not shown in Figure 2 or Figure 3 STBY rising edge to CONVST x rising edge; powerup time from shutdown mode STBY rising edge to CONVST x rising edge; powerup time from shutdown mode RESET high pulse width CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A and CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high See Figure 4, Figure 5, and Figure 7 CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width; CS and RD linked Delay from CS until DB15 to DB0 three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V AD7605-4 Parameter t15 t16 t17 Data Sheet VINL = 0.1 x VDRIVE and VINH = 0.9 x VDRIVE Logic Input Levels Min Typ Max 6 6 22 VINL = 0.3 x VDRIVE and VINH = 0.7 x VDRIVE Logic Input Levels Min Typ Max 6 6 22 Unit ns ns ns 23.5 17 14.5 11.5 20 15 12.5 10 MHz MHz MHz MHz 15 20 30 18 23 35 ns ns ns 17 23 27 34 20 26 32 39 ns ns ns ns ns ns ns ns SERIAL READ OPERATION fSCLK t18 t19 t20 t21 t22 t23 0.4 x tSCLK 0.4 x tSCLK 7 0.4 x tSCLK 0.4 x tSCLK 7 22 22 FRSTDATA OPERATION t24 15 20 25 30 18 23 30 35 ns ns ns ns 15 20 25 30 18 23 30 35 ns ns ns ns 16 20 25 30 19 23 30 35 ns ns ns ns 19 24 22 29 ns ns 17 22 24 20 27 29 ns ns ns t25 t26 t27 t28 t29 Rev. 0 | Page 6 of 27 Description Data hold time after RD falling edge CS to DB15 to DB0 hold time Delay from CS rising edge to DB15 to DB0 threestate enabled See Figure 6 Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled See Figure 4 and Figure 7 Delay from CS falling edge until FRSTDATA threestate disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25V VDRIVE = 2.3 V to 2.7V CS rising edge until FRSTDATA three-state enabled Data Sheet AD7605-4 Timing Diagrams t5 CONVST A, CONVST B tCYCLE CONVST A, CONVST B t2 t3 tCONV t1 BUSY t4 CS t7 13503-002 tRESET RESET Figure 2. CONVST x Timing--Reading After a Conversion t5 CONVST A, CONVST B tCYCLE CONVST A, CONVST B t2 t3 tCONV t1 BUSY t6 CS t7 13503-003 tRESET RESET Figure 3. CONVST x Timing--Reading During a Conversion CS t8 FRSTDATA INVALID t24 V1 t26 t15 t14 V2 V3 t17 V4 t27 t29 Figure 4. Parallel Mode, Separate CS and RD Pulses t12 CS AND RD t16 t13 DATA: DB15 TO DB0 V1 V2 V3 t17 V4 FRSTDATA Figure 5. CS and RD, Linked Parallel Mode Rev. 0 | Page 7 of 27 13503-004 DATA: DB15 TO DB0 t16 t13 13503-005 RD t9 t11 t10 AD7605-4 Data Sheet CS t21 SCLK t19 t18 DOUTA, DOUTB t20 DB15 t22 DB14 DB13 t23 DB1 DB0 t25 t29 13503-006 t28 FRSTDATA Figure 6. Serial Read Operation CS t8 t9 t10 t16 t13 DATA: DB7 TO DB0 INVALID HIGH BYTE V1 t26 FRSTDATA t24 t14 t15 LOW BYTE V1 HIGH BYTE V4 t27 Figure 7. Parallel Byte Mode Read Operation Rev. 0 | Page 8 of 27 t17 LOW BYTE V4 t29 13503-007 RD t11 Data Sheet AD7605-4 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. THERMAL RESISTANCE Table 4. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN/REFOUT to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Pb/Sn Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow ESD All Pins Except Analog Inputs Analog Input Pins Only 1 Rating -0.3 V to +7 V -0.3 V to AVCC + 0.3 V 16.5 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVCC + 0.3 V 10 mA -40C to +85C -65C to +150C 150C 240 (+0)C 260 (+0)C JA is the natural convection junction to ambient thermal resistance, measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 5. Thermal Resistance Package Type ST-64-2 1 JA1 45.5 JC1 9.5 Unit C/W The thermal resistance specifications are based on the device being mounted to a JEDEC 2P2S compliant, 4-layer PCB, as per JEDEC Standard JESD51-7. ESD CAUTION 2 kV 7 kV Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 9 of 27 AD7605-4 Data Sheet 64 63 62 61 60 59 58 V1GND V1 V2 AGND V2GND AGND AGND V3 AGND V4 V3GND V4GND AGND AGND AGND AGND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 AVCC 1 ANALOG INPUT 48 PIN 1 AVCC 47 AGND 46 REFGND DECOUPLING CAPACITOR PIN AGND 2 AGND 3 POWER SUPPLY AGND 4 45 REFCAPB GROUND PIN AGND 5 44 REFCAPA REFGND DIGITAL OUTPUT PAR/SER/BYTE SEL 6 AD7605-4 43 STBY 7 TOP VIEW (Not to Scale) 42 REFIN/REFOUT 41 AGND CONVST A 9 40 AGND CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 DB0 16 34 REF SELECT 33 DB15/BYTE SEL DIGITAL INPUT REFERENCE INPUT/OUTPUT RANGE 8 13503-010 DB14/HBEN DB13 DB12 DB10 DB11 DB9 AGND DB7/DOUTA DB8/DOUTB VDRIVE DB6 DB5 DB4 DB3 DB2 DB1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 8. Pin Configuration Table 6. Pin Function Descriptions1 Pin No. 1, 37, 38, 48 2, 3, 4, 5, 26, 35, 40, 41, 47 6 Type2 P Mnemonic AVCC GND AGND DI PAR/SER/ BYTE SEL 7 DI STBY 8 DI RANGE Description Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. Decouple these supply pins to AGND. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7605-4. Refer all analog input signals and external reference signals to these pins. Connect all AGND pins to the AGND plane of a system. Parallel Interface Selection Input (PAR). This pin is a logic input. If this pin is tied to a logic low, the parallel interface is selected. Parallel byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). Serial Interface Selection Input (SER). If this pin is tied to a logic high, the serial interface is selected. In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, tie the parallel output data bit pins (Pin 16 to Pin 22, and Pin 27 to Pin 33) to ground. Parallel Byte Interface Selection Input (BYTE SEL). In byte mode, DB15/BYTE SEL, in conjunction with PAR/SER/BYTE SEL, selects the parallel byte mode of operation (see Table 8). DB14/HBEN functions as the high byte enable (HBEN) pin. DB7 to DB0 transfer the 16-bit conversion results in two RD/SCLK operations, with DB0 as the LSB of the data transfers. Standby Mode Input. This pin places the AD7605-4 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. Analog Input Range Selection. RANGE is a logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section for more information. Rev. 0 | Page 10 of 27 Data Sheet AD7605-4 Pin No. 9 Type2 DI Mnemonic CONVST A 10 DI CONVST B 11 DI RESET 12 DI RD/SCLK 13 DI CS 14 DO BUSY 15 DO FRSTDATA 16 to 22 DO DB0 to DB6 23 P VDRIVE 24 DO DB7/DOUTA 25 DO DB8/DOUTB 27 to 31 DO DB9 to DB13 Description Conversion Start Input A. CONVST A is a logic input. Use this logic input to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling of V1 and V2. When the CONVST A pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog input is set to hold. Conversion Start Input B. CONVST B is a logic input. Use this logic input to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. CONVST B can be used to initiate simultaneous sampling on V3 and V4. When the CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog input is set to hold. Reset Input. When set to logic high, the rising edge of RESET resets the AD7605-4. The device receives a RESET pulse after power-up. The RESET high pulse is typically 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. Parallel Data Read Control Input When the Parallel Interface Is Selected (RD). When both CS and RD are logic low in parallel mode, the output bus is enabled. Serial Clock Input When the Serial Interface Is Selected (SCLK). In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For more information, see the Conversion Control section. Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS frames the serial read transfer and clocks out the MSB of the serial output data. Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of the BUSY pin signals that the conversion data is being latched into the output data registers and is available to read after a period of time, t4. Any data read while BUSY is high must be completed before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1, then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because this clocks out the MSB of V1 on DOUTA. FRSTDATA returns low on the 16th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details. Parallel Output Data Bits, DB0 to DB6. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, tie these pins to AGND. When operating in parallel byte interface mode, DB7 to DB0 outputs the 16-bit conversion result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB. Logic Power Supply Input. The voltage supplied at this pin, 2.3 V to 5.25 V, determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and field-programmable gate array (FPGA)). Parallel Output Data Bit 7 (DB7). When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin outputs DB7 of the conversion result. Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 1, this pin functions as DOUTA and outputs serial conversion data (see the Conversion Control section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. Parallel Output Data Bit 8 (DB8). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin outputs DB8 of the conversion result. Serial Interface Data Output Pin (DOUTB). When PAR/SER/BYTE SEL = 1, this pin functions as DOUTB and outputs serial conversion data (see the Conversion Control section for more details). Parallel Output Data Bits, DB9 to DB13. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, tie these pins to AGND. Rev. 0 | Page 11 of 27 AD7605-4 Data Sheet Pin No. 32 Type2 DO/DI Mnemonic DB14/ HBEN 33 DO/DI DB15/ BYTE SEL 34 DI REF SELECT 36, 39 CAP REGCAP 42 REF REFIN/ REFOUT 43, 46 44, 45 GND CAP REFGND REFCAPA, REFCAPB 49 AI V1 50, 52 AI GND 51 AI V1GND, V2GND V2 53, 54, 55, 56 GND AGND 57 AI V3 58 59 60 61, 62, 63, 64 AI GND AI AI GND AGND V3GND V4 V4GND AGND Description Parallel Output Data Bit 14 (DB14). When PAR/ SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin outputs DB14 of the conversion result. High Byte Enable (HBEN). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7605-4 operates in parallel byte interface mode. In parallel byte mode, the HBEN pin selects whether the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is output first, followed by the MSB. In serial mode, tie this pin to AGND. Parallel Output Data Bit 15 (DB15). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin outputs DB15 of the conversion result. Parallel Byte Mode Select (BYTE SEL). When PAR/SER/BYTE SEL = 1, the BYTE SEL pin selects between serial interface mode and parallel byte interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7605-4 operates in serial interface mode. When PAR/ SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7605-4 operates in parallel byte interface mode. Internal/External Reference Selection Input. REF SELECT is a logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple these output pins separately to AGND using a 1 F capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V. Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference of 2.5 V is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal and external reference options. Apply a 10 F capacitor from this pin to ground close to the REFGND pins. Reference Ground Pins. Connect these pins to AGND. Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low effective series resistance (ESR), 10 F ceramic capacitor. The voltage on these pins is typically 4.5 V. Analog Input 1. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. Analog Input Ground Pin 1 and Pin 2. These pins correspond to Analog Input Pin V1 and Analog Input Pin V2. Connect all analog input ground pins to the AGND plane of a system. Analog Input 2. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7605-4. Refer all analog input signals and external reference signals to these pins. Connect all the AGND pins to the AGND plane of a system. Analog Input 3. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. Analog Input Ground Pin 3. Connect all analog input ground pins to the AGND plane of a system. Analog Input 4. This pin is a single-ended analog input. Analog Input Ground Pin 4. Connect all analog input ground pins to the AGND plane of a system. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7605-4. Refer all analog input signals and external reference signals to these pins. Connect all the analog ground pins to the AGND plane of a system. Note that throughout this data sheet, multifunction pins, such as RD/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, RD, when only that function is relevant. 2 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, CAP is decoupling capacitor pin, AI is analog input, and GND is ground. 1 Rev. 0 | Page 12 of 27 Data Sheet AD7605-4 TYPICAL PERFORMANCE CHARACTERISTICS AVCC = 5 V, VDRIVE = 5 V, 10 V range, internal reference, TA = 25C, unless otherwise noted. 0 -20 -40 -60 AVCC, VDRIVE = 5V fSAMPLE = 300kSPS TA = 25C INTERNAL REFERENCE 10V RANGE 0.8 0.6 0.4 DNL (LSB) -80 -100 -120 0.2 0 -0.2 -0.4 -140 INPUT FREQUENCY (Hz) 13503 -011 -1.0 0 2349 4699 7048 9397 11746 14096 16445 18794 21143 23493 25842 28191 30541 32890 35239 37588 39938 42287 44636 46986 49335 51684 54033 56383 58732 61081 63430 65780 68129 70478 72828 75177 77526 79875 82225 84574 86923 89273 91622 93971 96320 98670 101019 103368 105717 108067 110416 112765 115115 117464 119813 122162 124512 126861 129210 131560 133909 136258 138607 140957 143306 145655 148004 150354 -0.8 -180 0 2.0 -60 1.0 50k 60k 0.5 -80 -100 0 -0.5 -120 -180 -2.0 INPUT FREQUENCY (Hz) 13503 -012 -1.5 0 2349 4699 7048 9397 11746 14096 16445 18794 21143 23493 25842 28191 30541 32890 35239 37588 39938 42287 44636 46986 49335 51684 54033 56383 58732 61081 63430 65780 68129 70478 72828 75177 77526 79875 82225 84574 86923 89273 91622 93971 96320 98670 101019 103368 105717 108067 110416 112765 115115 117464 119813 122162 124512 126861 129210 131560 133909 136258 138607 140957 143306 145655 148004 150354 -160 0 8192 CODE Figure 10. FFT Plot, 5 V Range 2.0 Figure 13. Typical INL, 5 V Range 1.00 AVCC, VDRIVE = 5V fSAMPLE = 300kSPS TA = 25C INTERNAL REFERENCE 10V RANGE 1.5 1.0 16,384 24,576 32,768 40,960 49,152 57,344 65,536 13503-015 -1.0 -140 AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE fSAMPLE = 300kSPS TA = 25C 0.75 0.50 DNL (LSB) 0.5 0 -0.5 0.25 0 -0.25 -1.0 -0.50 -1.5 -0.75 -2.0 0 10k 20k 30k 40k 50k CODE 60k 13503-013 INL (LSB) 40k AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE fSAMPLE = 300kSPS TA = 25C 1.5 INL (LSB) AMPLITUDE (dB) -40 30k Figure 12. Typical DNL, 10 V Range AVCC, VDRIVE = 5V INTERNAL REFERENCE 5V RANGE fSAMPLE = 300kSPS fIN = 1kHz SNR = 89.6dB THD = -113.5dB -20 20k CODE Figure 9. FFT Plot, 10 V Range 0 10k 13503-014 -0.6 -160 -1.00 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE Figure 14. Typical DNL, 5 V Range Figure 11. Typical INL, 10 V Range Rev. 0 | Page 13 of 27 13503-016 AMPLITUDE (dB) 1.0 AVCC, VDRIVE = 5V INTERNAL REFERENCE 10V RANGE fSAMPLE = 300kSPS fIN = 1kHz SNR = 90.3dB THD = -109.8dB AD7605-4 Data Sheet 20 10 15 5V RANGE 0 -5 -10 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 2 AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25C EXTERNAL REFERENCE SOURCE RESISTANCE IS MATCHED ON THE VxGND INPUT 10V AND 5V RANGE -2 13503-017 -20 -40 4 0 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -15 6 0 20k Figure 15. NFS Error vs. Temperature 80k 100k 120k 1.0 0.8 10 5 0 5V RANGE -5 10V RANGE -10 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -20 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) 0.4 0.2 0 5V RANGE -0.2 -0.4 10V RANGE -0.6 -1.0 -40 BIPOLAR ZERO CODE ERROR MATCHING (LSB) 8 PFS ERROR 6 4 NFS ERROR 2 0 -2 -4 -6 -10 5 20 35 50 TEMPERATURE (C) 65 80 13503-018 10V RANGE AVCC, VDRIVE = 5V EXTERNAL REFERENCE -25 -10 5 20 35 50 65 80 Figure 19. Bipolar Zero Code Error vs. Temperature 10 -10 -40 -25 TEMPERATURE (C) Figure 16. PFS Error vs. Temperature -9 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -0.8 13503-118 -15 0.6 13503-023 BIPOLAR ZERO CODE ERROR (LSB) 15 PFS ERROR (LSB) 60k Figure 18. PFS and NFS Error vs. Source Resistance 20 NFS AND PFS CHANNEL MATCHING (LSB) 40k SOURCE RESISTANCE () 4 3 5V RANGE 2 1 10V RANGE 0 -1 -2 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE -3 -4 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) Figure 20. Bipolar Zero Code Error Matching Between Channels Figure 17. NFS and PFS Error Matching Rev. 0 | Page 14 of 27 13503-024 NFS ERROR (LSB) 10V RANGE 5 13503-019 PFS AND NFS ERROR (%FS) 8 10 Data Sheet AD7605-4 -40 -50 -60 -80 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 -100 -110 -120 1k 10k 100k INPUT FREQUENCY (Hz) -90 10V RANGE -100 5V RANGE -110 -120 -130 -140 0 20 2.5005 REFOUT VOLTAGE (V) -80 105k 48.7k 23.7k 10k 5k 1.2k 100 51 0 140 160 100k INPUT FREQUENCY (Hz) 2.5000 2.4995 AVCC = 4.75V 2.4990 2.4985 13503-122 THD (dB) -70 10k 120 AVCC = 5.25V AVCC = 5V -60 -120 1k 100 2.5010 5V RANGE AVCC, VDRIVE = +5V -50 fSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS -110 80 Figure 23. Channel to Channel Isolation -40 -100 60 NOISE FREQUENCY (kHz) Figure 21. THD vs. Input Frequency for Various Source Impedances, 10 V Range -90 40 Figure 22. THD vs. Input Frequency for Various Source Impedances, 5 V Range 2.4980 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) Figure 24. REFOUT Voltage vs. Temperature for Different Supply Voltages Rev. 0 | Page 15 of 27 80 13503-029 -90 13503-021 THD (dB) -70 AVCC, VDRIVE = 5V INTERNAL REFERENCE RECOMMENDED DECOUPLING USED fSAMPLE = 150kSPS -70 TA = 25C INTERFERER ON ALL UNSELECTED CHANNELS -80 -60 13503-025 CHANNEL TO CHANNEL ISOLATION (dB) 10V RANGE AVCC, VDRIVE = +5V -50 fSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS AD7605-4 6 fSAMPLE = 200kSPS 900 AVCC = 5V VDRIVE = 2.5V NUMBER OF OCCURENCES 4 2 0 -2 -4 -6 -10 -10 -8 -6 -4 -2 0 2 4 6 8 10 INPUT VOLTAGE (V) 130 120 10V RANGE 110 5V RANGE 100 90 AVCC, VDRIVE = 5V INTERNAL REFERENCE RECOMMENDED DECOUPLING USED fSAMPLE = 200kSPS TA = 25C 60 0 100 200 300 400 500 600 700 800 900 1000 1100 AVCC NOISE FREQUENCY (kHz) 13503-030 POWER SUPPLY REJECTION RATIO (dB) 140 70 887 700 600 500 400 300 131 97 100 Figure 25. Analog Input Current vs. Input Voltage for Various Temperatures 80 928 800 200 +85C +25C -40C -8 13503-028 ANALOG INPUT CURRENT (A) 1000 AVCC, VDRIVE = 5V fSAMPLE = 300kSPS Figure 26. Power Supply Rejection Ratio (PSRR) Rev. 0 | Page 16 of 27 0 0 3 -3 -2 2 -1 0 1 2 CODE (LSB) Figure 27. Histogram of Codes (Six Codes) 3 13503-047 8 Data Sheet Data Sheet AD7605-4 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at 1/2 LSB below the first code transition; and full scale, at 1/2 LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V - 1/2 LSB. Bipolar Zero Code Error Matching Bipolar zero code error matching is the absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale Error Positive full-scale error is the deviation of the actual last code transition from the ideal last code transition (10 V - 11/2 LSB (9.99954) and 5 V - 11/2 LSB (4.99977)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Matching Positive full-scale error matching is the absolute difference in positive full-scale error between any two input channels. Negative Full-Scale Error Negative full-scale error is the deviation of the first code transition from the ideal first code transition (-10 V + 1/2 LSB (-9.99984) and -5 V + 1/2 LSB (-4.99992)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Match Negative full-scale error match is the absolute difference in negative full-scale error between any two input channels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 16-bit converter, the ideal signal-to-(noise + distortion) is 98 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the harmonics to the fundamental. For the AD7605-4, it is defined as THD (dB) = 20log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 + V7 2 + V8 2 + V9 2 V1 where: V2 to V9 are the rms amplitudes of the second through ninth harmonics. V1 is the rms amplitude of the fundamental. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa - fb), and the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC's VDD and VSS supplies of Frequency fS. PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the AVCC supply. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 23). Rev. 0 | Page 17 of 27 AD7605-4 Data Sheet THEORY OF OPERATION The AD7605-4 contains input clamp protection, input signal scaling amplifiers, a second-order anti-aliasing filter, track-andhold amplifiers, an on-chip reference, reference buffers, a high speed ADC, a digital filter, and high speed parallel and serial interfaces. Sampling on the AD7605-4 is controlled using the CONVST x signals. ANALOG INPUT Analog Input Ranges The AD7605-4 can handle true bipolar, single-ended input voltages. The logic level on the RANGE pin determines the analog input range of all analog input channels. If this pin is tied to a logic high, the analog input range is 10 V for all channels. If this pin is tied to a logic low, the analog input range is 5 V for all channels. A logic change on this pin has an immediate effect on the analog input range; however, there is typically a settling time of approximately 80 s, in addition to the normal acquisition time requirement. The recommended practice is to hardwire the RANGE pin according to the desired input range for the system signals. During normal operation, keep the applied analog input voltage within the analog input range selected via the RANGE pin. A RESET pulse must be applied after power up to ensure the analog input channels are configured for the range selected. When in one of the two power-down modes, it is recommended to tie the analog inputs to AGND. The overvoltage clamp protection is designed to protect against transient overvoltage conditions only; do not keep the clamp protection circuitry active for extended periods (see the Analog Input Clamp Protection section). Analog Input Impedance The analog input impedance of the AD7605-4 is 1 M. This fixed input impedance does not vary with sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7605-4, allowing direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. RFB CLAMP VxGND CLAMP 1M 1M SECONDORDER LPF RFB 13503-032 Vx Figure 28. Analog Input Circuitry Figure 29 shows the input clamp current vs. the source voltage characteristic of the clamp circuit. For input voltages of up to 16.5 V, no current flows in the clamp circuit. For input voltages greater than 16.5 V, the AD7605-4 clamp circuitry turns on. AV , VDRIVE = 5V 30 T CC A = 25C 20 10 0 -10 -20 -30 -40 -50 -20 -15 -10 -5 0 5 10 15 20 SOURCE VOLTAGE (V) 13503-033 The AD7605-4 is a data acquisition system that employs a high speed, low power, charge redistribution, successive approximation register (SAR) ADC and allows the simultaneous sampling of four analog input channels. The analog inputs on the AD7605-4 can accept true bipolar input signals. The RANGE pin selects either 10 V or 5 V as the input range. The AD7605-4 operates from a single 5 V supply. Figure 28 shows the analog input structure of the AD7605-4. Each analog input contains clamp protection circuitry. Despite single 5 V supply operation, this analog input clamp protection allows an input overvoltage of up to 16.5 V. Figure 29. Input Protection Clamp Profile Place a series resistor on the analog input channels to limit the current to 10 mA for input voltages greater than 16.5 V. In an application where there is a series resistance on an analog input channel, Vx, a corresponding resistance is required on the analog input ground channel, VxGND (see Figure 30). If there is no corresponding resistor on the VxGND channel, an offset error occurs on that channel. It is recommended that the input overvoltage clamp protection circuitry be used to protect the AD7605-4 against transient overvoltage events. It is not recommended to leave the AD7605-4 in a condition where the clamp protection circuitry is active in normal or power-down conditions for extended periods because doing so may degrade the bipolar zero code error performance of the AD7605-4. RFB AD7605-4 ANALOG INPUT SIGNAL R R C Vx VxGND CLAMP CLAMP 1M 1M RFB 13503-034 CONVERTER DETAILS Analog Input Clamp Protection INPUT CLAMP CURRENT (mA) Note that throughout this data sheet, multifunction pins, such as RD/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, RD, when only that function is relevant. Figure 30. Input Resistance Matching on the Analog Input of the AD7605-4 Rev. 0 | Page 18 of 27 Data Sheet AD7605-4 Analog Input Antialiasing Filter An analog antialiasing filter (a second-order Butterworth) is also provided on the AD7605-4. Figure 31 and Figure 32 show the frequency and phase response, respectively, of the analog antialiasing filter. In the 5 V range, the -3 dB frequency is typically about 15 kHz. In the 10 V range, the -3 dB frequency is typically about 23 kHz. 5 0 5V RANGE -15 -20 -25 -30 -35 10V RANGE -40 +25 +85 -0.1dB 10,303 9619 9326 -3dB 24,365Hz 23,389Hz 22,607Hz 5V RANGE -40 +25 +85 -0.1dB 5225 5225 4932 -3dB 16,162Hz 15,478Hz 14,990Hz -40 100 1k 10k 100k INPUT FREQUENCY (Hz) Figure 31. Analog Antialiasing Filter Frequency Response 18 16 14 PHASE DELAY (s) The conversion clock for the device is internally generated, and the conversion time for all channels is 2 s on the AD7605-4. The BUSY signal returns low after all four conversions are completed, to indicate the end of the conversion process. On the falling edge of BUSY, the track-and-hold amplifiers return to track mode. New data can be read from the output register via the parallel interface, parallel byte interface, or serial interface after BUSY goes low; or, alternatively, data from the previous conversion can be read while BUSY is high. Reading data from the AD7605-4 while a conversion is in progress has little effect on performance and allows a faster throughput to be achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. ADC TRANSFER FUNCTION 5V RANGE The output coding of the AD7605-4 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is FSR/65,536 for the AD7605-4. The ideal transfer characteristic for the AD7605-4 is shown in Figure 33. 12 10 The end of the conversion process across all channels is indicated by the falling edge of BUSY; it is at this point that the track-andholds return to track mode, and the acquisition time for the next set of conversions begins. 10V RANGE 8 6 4 2 VIN x 32,768 x 10V VIN 5V CODE = x 32,768 x 5V 10V CODE = 0 -2 10k INPUT FREQUENCY (Hz) 100k ADC CODE 011...111 011...110 13503-036 -4 AVCC, VDRIVE = 5V f = 200kSPS -6 SAMPLE TA = 25C -8 10 1k Figure 32. Analog Antialias Filter Phase Response 000...001 000...000 111...111 REF 2.5V REF 2.5V LSB = +FS - (-FS) 216 100...010 100...001 100...000 Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7605-4 allow the ADC to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. -FS + 1/2LSB 0V - 1/2LSB +FS - 3/2LSB ANALOG INPUT +FS 10V RANGE +10V 5V RANGE +5V MIDSCALE 0V 0V -FS -10V -5V LSB 305V 152V 13503-037 -10 10V RANGE AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25C 13503-035 ATTENUATION (dB) -5 The aperture time for the track-and-hold (that is, the delay time between the external CONVST x signal and the track-and-hold actually going into hold) is well matched, by design, across all track-and-holds on one device and from device to device. This matching allows more than one AD7605-4 device to be sampled simultaneously in a system. Figure 33. Transfer Characteristics The LSB size is dependent on the analog input range selected. Rev. 0 | Page 19 of 27 AD7605-4 Data Sheet When the AD7605-4 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple devices, the following configurations are recommended, depending on the application requirements. INTERNAL/EXTERNAL REFERENCE The AD7605-4 contains an on-chip 2.5 V band gap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7605-4. An externally applied reference of 2.5 V is also amplified to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7605-4 devices (see Figure 35). In this configuration, decouple each REFIN/REFOUT pin of the AD7605-4 with at least a 100 nF decoupling capacitor. The REF SELECT pin is a logic input pin that allows the user to select between the internal reference and an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7605-4 operates in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 F ceramic capacitor is required on the REFIN/REFOUT pin. Internal Reference Mode Use one AD7605-4 device, configured to operate in the internal reference mode, to drive the remaining AD7605-4 devices, which are configured to operate in external reference mode (see Figure 36). Decouple the REFIN/REFOUT pin of the AD7605-4 that is configured in internal reference mode, using a 10 F ceramic decoupling capacitor. For the other AD7605-4 devices, configured in external reference mode, use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. The AD7605-4 contains a reference buffer configured to amplify the REFIN/REFOUT voltage to 4.5 V, as shown in Figure 34. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 F applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. REFIN/REFOUT SAR REFCAPA BUF 10F REFCAPB 13503-038 2.5V REF Figure 34. Reference Circuitry AD7605-4 AD7605-4 AD7605-4 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT 100nF 100nF 100nF 13503-040 ADR421 0.1F Figure 35. Single External Reference Driving Multiple AD7605-4 REFIN/RFOUT Pins VDRIVE AD7605-4 AD7605-4 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT + 10F 100nF 100nF Figure 36. Internal Reference Driving Multiple AD7605-4 REFIN/REFOUT Pins Rev. 0 | Page 20 of 27 13503-039 AD7605-4 Data Sheet AD7605-4 The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7605-4 is placed in standby mode, the current consumption is 8 mA maximum and the power-up time is approximately 100 s because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. TYPICAL CONNECTION DIAGRAM Figure 37 shows the typical connection diagram for the AD7605-4. There are four AVCC supply pins on the device. Decouple each of the four pins using a 100 nF capacitor at each supply pin and a 10 F capacitor at the supply source. The AD7605-4 can operate with the internal reference or an externally applied reference. In this configuration, the AD7605-4 is configured to operate with the internal reference. When using a single AD7605-4 device on the board, decouple the REFIN/REFOUT pin with a 10 F capacitor. Refer to the Internal/External Reference section when using an application with multiple AD7605-4 devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 F ceramic capacitor. When the AD7605-4 is placed in shutdown mode, the current consumption is 6 A maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7605-4 is powered up from shutdown mode, a RESET signal must be applied to the AD7605-4 after the required power-up time has elapsed. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. Table 7. Power-Down Mode Selection After supplies are applied to the AD7605-4, apply a reset to ensure that the device is configured for the correct mode of operation. STBY Setting Power-Down Mode Standby Shutdown 0 0 POWER-DOWN MODES Two power-down modes are available on the AD7605-4: standby mode and shutdown mode. The STBY pin controls whether the AD7605-4 is in normal mode or in one of the two power-down modes. ANALOG SUPPLY VOLTAGE 5V1 + 1F REFIN/REFOUT 100nF 100nF REGCAP2 AVCC VDRIVE REFCAPA 10F + REFCAPB REFGND DB0 TO DB15/BYTESEL CONVST A, CONVST B CS RD/SCLK BUSY AD7605-4 PARALLEL INTERFACE MICROPROCESSOR/ MICROCONVERTER/ DSP 10F DIGITAL SUPPLY VOLTAGE +2.3V TO +5.25V RESET REF SELECT VDRIVE PAR/SER/BYTE SEL RANGE STBY VDRIVE AGND 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 37. Typical Connection Diagram Rev. 0 | Page 21 of 27 13503-041 FOUR ANALOG INPUTS V1 TO V4 V1 V1GND V2 V2GND V3 V3GND V4 V4GND RANGE Setting 1 0 AD7605-4 Data Sheet CONVERSION CONTROL for phase differences introduced by potential transformers (PTs) and current transformers (CTs). In a 50 Hz system, simultaneous sampling allows up to 9 of phase compensation; and in a 60 Hz system, it allows up to 10 of phase compensation. Simultaneous Sampling on All Analog Input Channels The AD7605-4 allows simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST x pins (CONVST A, CONVST B) are tied together. A single CONVSTx signal is used to control both CONVST x inputs. The rising edge of this common CONVST x signal initiates simultaneous sampling on all analog input channels. Simultaneous sampling is accomplished by pulsing the two CONVST x pins independently. CONVST A initiates simultaneous sampling of the first set of channels (V1 and V2); and CONVST B initiates simultaneous sampling on the second set of analog input channels (V3 and V4), as shown in Figure 38. On the rising edge of CONVST A, the track-and-hold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins after both rising edges of CONVST x occur; therefore, BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, t5 indicates the maximum allowable time between the CONVST x sampling points. The AD7605-4 contains an on-chip oscillator that performs the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST x is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB15 to DB0), the DOUTA and DOUTB serial data lines, or the parallel byte bus, DB7 to DB0. There is no change to the data read process when using two separate CONVST x signals. Simultaneously Sampling Two Sets of Channels Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. The AD7605-4 also allows the analog input channels to be sampled simultaneously in two sets. This feature can be used in power line protection and measurement systems to compensate V1 AND V2 TRACK-AND-HOLD ENTER HOLD V3 AND V4 TRACK-AND-HOLD ENTER HOLD CONVST A t5 CONVST B AD7605-4 CONVERTS ON ALL 4 CHANNELS BUSY tCONV CS, RD V1 V2 V3 V4 13503-042 DATA: DB15 TO DB0 FRSTDATA Figure 38. Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals--Parallel Mode Rev. 0 | Page 22 of 27 Data Sheet AD7605-4 APPLICATIONS INFORMATION The RD/SCLK pin is used to read data from the output conversion results register. Applying a sequence of RD pulses to the RD/SCLK pin of the AD7605-4 clocks the conversion results out from each channel onto the parallel bus, DB15 to DB0, in ascending order. The first RD signal falling edge after BUSY goes low clocks out the conversion result from Channel V1. The next RD signal falling edge updates the bus with the V2 conversion result, and so on. The AD7605-4 provides three interface options: a parallel interface, a high speed serial interface, and a parallel byte interface. The required interface mode is selected via the PAR/SER/BYTE SEL and DB15/BYTE SEL pins. Table 8. Interface Mode Selection PAR/SER/BYTE SEL Setting 0 1 1 DB15/BYTE SEL Setting 0 0 1 Interface Mode Parallel Serial Parallel byte Operation of the interface modes is discussed in the following sections. PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) Data can be read from the AD7605-4 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, tie the PAR/SER/BYTE SEL pin low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. AD7605-4 BUSY 14 INTERRUPT CS 13 [33:27] DB15 TO DB0 [25:24] [22:16] DIGITAL HOST 13503-043 RD/SCLK 12 Figure 39. AD7605-4 Interface Diagram--One AD7605-4 Device Using the Parallel Bus, with CS and RD/SCLK Shorted Together The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7605-4 devices to share the same parallel data bus. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (see Figure 2); or, alternatively, a read operation of data from the previous conversion process can take place while BUSY is high (see Figure 3). When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). When there is only one AD7605-4 device in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of the CS/RD signal. The combined CS and RD signal allows the data to be clocked out of the AD7605-4 and to be read by the digital host. In this case, CS frames the data transfer of each data channel. PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB15/BYTE SEL = 1) Parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8-bit transfers. Therefore, eight RD pulses are required to read all four conversion results from the AD7605-4. To configure the AD7605-4 to operate in parallel byte mode, tie the PAR/SER/BYTE SEL and DB15/BYTE SEL pins to logic high (see Table 8). In parallel byte mode, DB7 to DB0 are used to transfer the data to the digital host. DB0 is the LSB of the data transfer, and DB7 is the MSB of the data transfer. In parallel byte mode, the DB14/HBEN pin functions as HBEN. When DB14/HBEN is tied to logic high, the most significant byte (MSB) of the conversion result is output first, followed by the LSB of the conversion result. When DB14/HBEN is tied to logic low, the LSB of the conversion result is output first, followed by the MSB of the conversion result. The FRSTDATA pin remains high until the entire 16 bits of the conversion result from V1 are read from the AD7605-4. Rev. 0 | Page 23 of 27 AD7605-4 Data Sheet SERIAL INTERFACE (PAR/SER/BYTE SEL = 1) To read data back from the AD7605-4 over the serial interface, the PAR/SER/BYTE SEL pin must be tied high. The CS and SCLK signals are used to transfer data from the AD7605-4. The AD7605-4 has two serial data output pins, DOUTA and DOUTB. Data can be read back from the AD7605-4 using one or both of these DOUTx lines. For the AD7605-4, conversion results from Channel V1 and Channel V2 first appear on DOUTA, and conversion results from Channels V3 and Channel V4 first appear on DOUTB. The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 SCLK cycles. Figure 40 shows a read of four simultaneous conversion results using two DOUTx lines on the AD7605-4. In this case, a 32 SCLK transfer is used to access data from the AD7605-4, and CS is held low to frame all the 32 SCLK cycles. Data can also be clocked out using just one DOUTx line, in which case it is recommended that DOUTA be used to access all conversion data because the channel data is output in ascending order. For the AD7605-4 to access all four conversion results on the DOUTA line, a total of 64 SCLK cycles is required. These 64 SCLK cycles can be framed by one CS signal, or each group of 16 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just the one DOUTA line is that the throughput rate is reduced if reading occurs after conversion. Leave the unused DOUTB line unconnected in serial mode. If DOUTB is used as the single data output line, the channel results are output in the following order: V3, V4, V1, and V2; however, the FRSTDATA indicator returns low after V3 is read on DOUTB. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7605-4 in serial mode. The SCLK input signal provides the clock source for the serial read operation. The AD7605-4 can be accessed while the CS signal is held low. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 15 data bits are clocked out of the AD7605-4 on the SCLK rising edge. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock cycles must be provided to the AD7605-4. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 16th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is being output on this serial data output pin. The FRSTDATA output goes high only when V1 is available on DOUTA (when V3 is available on DOUTB for the AD7605-4). READING DURING CONVERSION Data can be read from the AD7605-4 while BUSY is high and the conversions are in progress. Reading during conversions has little effect on the performance of the converter. A parallel read, parallel byte read, or serial read can be performed during conversions. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with VDRIVE greater than 4.75 V. Data can be read from the AD7605-4 at any time other than on the falling edge of BUSY because the output data registers are updated with the new conversion data on the BUSY falling edge. Observe Time t6, as outlined in Table 3, in this condition. CS 32 DOUTA V1 V2 DOUTB V3 V4 Figure 40. Serial Interface with Two DOUTx Lines Rev. 0 | Page 24 of 27 13503-044 SCLK Data Sheet AD7605-4 LAYOUT GUIDELINES Design the PCB that houses the AD7605-4 so that the analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. It can be common or split between the digital and analog sections. In the case of the split plane, join the digital and analog ground planes in only one place, preferably as close as possible to the AD7605-4. Figure 41 shows the recommended decoupling on the top layer of the AD7605-4 board. Figure 42 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin decoupling. Where the ceramic 100 nF capacitors for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor can be shared between Pin 37 and Pin 38. If the AD7605-4 is in a system where multiple devices require analog to digital ground connections, make the connection at only one point: establish a star ground point as close as possible to the AD7605-4. Good connections must be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. 13503-054 Avoid running digital lines under the devices because doing so couples noise onto the die. Allow the analog ground plane to run under the AD7605-4 to avoid noise coupling. Shield fast switching signals like CONVST A, CONVST B, or clocks with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. Avoid crossover of digital and analog signals. Route traces on layers in close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. Figure 41. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Good decoupling is also important to lower the supply impedance presented to the AD7605-4 and to reduce the magnitude of the supply spikes. Place the decoupling capacitors close to (ideally, right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7605-4 pins; and, where possible, place them on the same side of the board as the AD7605-4 device. 13503-055 For the power supply lines to the AVCC and VDRIVE pins on the AD7605-4, use as large a trace as possible to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7605-4 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Figure 42. Bottom Layer Decoupling To ensure good device to device performance matching in a system that contains multiple AD7605-4 devices, a symmetrical layout between the AD7605-4 devices is important. Rev. 0 | Page 25 of 27 AD7605-4 Data Sheet Figure 43 shows a layout with two AD7605-4 devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. AVCC U2 These symmetrical layout principles can also be applied to a system that contains more than two AD7605-4 devices. The AD7605-4 devices can be placed in a north to south direction, with the reference voltage located midway between the devices and the reference track running in the north to south direction, similar to Figure 43. 13503-056 U1 Figure 43. Layout for Multiple AD7605-4 Devices--Top Layer and Supply Plane Layer Rev. 0 | Page 26 of 27 Data Sheet AD7605-4 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 49 64 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 44. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD7605-4BSTZ AD7605-4BSTZ-RL EVAL-AD7605-4SDZ EVAL-SDP-CB1Z 1 2 Temperature Range -40C to +85C -40C to +85C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Controller Board Package Option ST-64-2 ST-64-2 Z = RoHS Compliant Part. The EVAL-AD7605-4SDZ evaluation board requires the EVAL-SDP-CB1Z controller board to allow connection to a PC and full evaluation using the included evaluation software. (c)2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13503-0-9/16(0) Rev. 0 | Page 27 of 27