CY62148E MoBL®
4-Mbit (512 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05442 Rev. *J Revised July 14, 2011
Features
■Very high speed: 45 ns
■Voltage range: 4.5 V to 5.5 V
■Pin compatible with CY62148B
■Ultra low standby power
❐Typical standby current: 1 µA
❐Maximum standby current: 7 µA (Industrial)
■Ultra low active power
❐ Typical active current: 2.0 mA at f = 1 MHz
■Easy memory expansion with CE, and OE features
■Automatic power-down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)[1] packages
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH). The eight input and
output pins (I/O0 through I/O7) are placed in a high impedance
state when the device is deselected (CE HIGH), Outputs are
disabled (OE HIGH), or during an active Write operation (CE
LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
Logic Block Diagram
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A13
A14
A15
A16
A17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A11
A12
A18
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Note
1. SOIC package is available only in 55 ns speed bin.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 2 of 16
Contents
Pin Configuration ............................................................. 3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Capacitance ......................................................................4
Thermal Resistance ..........................................................5
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 3 of 16
Pin Configuration
Figure 1. 32-pin SOIC/TSOP II Pinout
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
VSS
VCC
A
18
WE
OE
CE
Product Portfolio
Product
Range
VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = 1 MHz f = fmax
Min Typ[2] Max Typ[2] Max Typ[2] Max Typ[2] Max
CY62148ELL TSOP II Industrial 4.5 5.0 5.5 45 2 2.5 15 20 1 7
CY62148ELL SOIC Industrial /
Automotive-A
4.5 5.0 5.5 55 2 2.5 15 20 1 7
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 4 of 16
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Supply voltage to
ground potential.................. –0.5 V to 6.0 V (VCCmax + 0.5 V)
DC voltage applied to outputs
in high Z state [3, 4].............. –0.5 V to 6.0 V (VCCmax + 0.5 V)
DC input voltage [3, 4]..........–0.5 V to 6.0 V (VCCmax + 0.5 V)
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current......................................................> 200 mA
Operating Range
Device Range Ambient
Temperature VCC[5]
CY62148E Industrial /
Automotive-A
–40 °C to +85 °C 4.5 V to 5.5 V
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions 45 ns 55 ns [6]
Unit
Min Typ[7] Max Min Typ[7] Max
VOH Output HIGH voltage IOH = –1 mA 2.4 – – 2.4 – – V
VOL Output LOW voltage IOL = 2.1 mA – – 0.4 – – 0.4 V
VIH Input HIGH voltage VCC = 4.5 V to 5.5 V 2.2 – VCC + 0.5 2.2 – VCC + 0.5 V
VIL Input LOW voltage VCC = 4.5 V to 5.5 V For TSOPII
package
–0.5 – 0.8 – – – V
For SOIC
package
–– ––0.5–0.6
[8]
IIX Input leakage current GND < VI < VCC –1 – +1 –1 – +1 µA
IOZ Output leakage
current
GND < VO < VCC, output disabled –1 – +1 –1 – +1 µA
ICC VCC operating supply
current
f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA
CMOS levels
– 15 20 – 15 20 mA
f = 1 MHz – 2 2.5 – 2 2.5
ISB2 [9] Automatic CE
power-down current
— CMOS inputs
CE > VCC – 0.2 V, VIN > VCC – 0.2 V
or VIN < 0.2 V, f = 0, VCC = VCC(max)
–1 7 –1 7 µA
Capacitance
Parameter[10] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) 10 pF
COUT Output capacitance 10 pF
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
6. SOIC package is available only in 55 ns speed bin.
7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V. This
is applicable to SOIC package only. Refer to AN13470 for details.
9. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 5 of 16
Thermal Resistance
Parameter [11] Description Test Conditions 32-pin SOIC
Package
32-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
75 77 C/W
JC Thermal resistance
(junction to case)
10 13 C/W
Figure 2. AC Test Loads and Waveforms
3.0 V
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameter [11] 5.0 V Unit
R1 1800
R2 990
RTH 639
VTH 1.77 V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 6 of 16
Data Retention Characteristics
Over the operating range
Parameter Description Conditions Min Typ[12] Max Unit
VDR VCC for data retention 2 – – V
ICCDR[13] Data retention current VCC = VDR, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Industrial /
Automotive-A
–17µA
tCDR Chip deselect to data retention time 0 – – ns
tR[14] Operation recovery time TSOP II 45 – – ns
SOIC 55 – – ns
Figure 3. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >2.0 V
DATA RETENTION MODE
tR
VCC
CE
Notes
12. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
13. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 7 of 16
Switching Characteristics
Over the operating range
Parameter [15] Description
45 ns 55 ns[16]
Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 – 55 – ns
tAA Address to data valid – 45 – 55 ns
tOHA Data hold from address change 10 – 10 – ns
tACE CE LOW to data valid –45–55ns
tDOE OE LOW to data valid –22–25ns
tLZOE OE LOW to low Z [17] 5–5–ns
tHZOE OE HIGH to high Z [17, 18] –18–20ns
tLZCE CE LOW to low Z [17] 10 – 10 – ns
tHZCE CE HIGH to high Z [17, 18] –18–20ns
tPU CE LOW to power-up 0–0–ns
tPD CE HIGH to power-down –45–55ns
Write Cycle[19]
tWC Write cycle time 45 – 55 – ns
tSCE CE LOW to write end 35 – 40 – ns
tAW Address setup to write end 35 – 40 – ns
tHA Address hold from write end 0 – 0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 35 – 40 – ns
tSD Data setup to write end 25 – 25 – ns
tHD Data hold from write end 0 – 0 – ns
tHZWE WE LOW to high Z [17, 18] –18–20ns
tLZWE WE HIGH to low Z [17] 10 – 10 – ns
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 8 of 16
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [23, 24]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
25
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 9 of 16
Figure 7. Write Cycle No. 2 (CE Controlled) [26, 27]
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27]
Truth Table
CE WE OE I/O Mode Power
H[29] X X High Z Deselect/power-down Standby (ISB)
L H L Data out Read Active (ICC)
L L X Data in Write Active (ICC)
L H H High Z Selected, outputs disabled Active (ICC)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
NOTE
28
Notes
26. Data I/O is high impedance if OE = VIH.
27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
28. During this period, the I/Os are in output state and input signals must not be applied.
29. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 10 of 16
Ordering Information
Tab l e 1 lists the CY62148E MoBL® key package features and ordering codes. The table contains only the parts that are currently
available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress
website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Ordering Code Definitions
Table 1. Key features and Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62148ELL-45ZSXI 51-85095 32-pin TSOP II (Pb-free) Industrial
CY62148ELL-45ZSXA 51-85095 32-pin TSOP II (Pb-free) Automotive-A
55 CY62148ELL-55SXI 51-85081 32-pin SOIC (Pb-free) Industrial
CY62148ELL-55SXA 51-85081 32-pin SOIC (Pb-free) Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = ZS or S
ZS= 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
E = Process Technology 90 nm
Bus width = × 8
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 48EX
LL X
-
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 11 of 16
Package Diagrams
Figure 9. 32-pin TSOP II, 51-85095
51-85095 *B
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 12 of 16
Figure 10. 32-pin (450-Mil) Molded SOIC, 51-85081
51-85081-*C
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 13 of 16
Acronyms Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
MoBL more battery life
SOIC small-outline integrated circuit
SRAM static random access memory
TSOP thin small outline package
WE write enable
Symbol Unit of Measure
ns nano seconds
VVolts
MHz Mega Hertz
µA micro Amperes
mA milli Amperes
pF pico Farads
ohms
°C degree Celsius
WWatts
%percent
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 14 of 16
Document History Page
Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05442
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 201580 AJU 01/08/04 New datasheet
*A 249276 SYT See ECN Changed from Advance Information to Preliminary
Moved Product Portfolio to Page 2
Added RTSOP II and Removed FBGA Package
Changed VCC stabilization time in footnote #7 from 100 s to 200 s
Changed ICCDR from 2.0 A to 2.5 A
Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45
ns Speed Bin
Changed tSCE from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed
Bin
Changed tHZCE from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Corrected typo in Package Name
Changed Ordering Information to include Pb-free Packages
*B 414820 ZSD See ECN Changed from Preliminary to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62148E
Changed ICC (Typ) value from 1.5 mA to 2 mA at f=1 MHz
Changed ICC (Max) value from 2 mA to 2.5 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f=fmax
Removed ISB1 spec from the Electrical characteristics table
Changed ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A
Modified footnote #4 to include current limit
Removed redundant footnote on DNU pins
Changed the AC testload capacitance from 100 pF to 30 pF on page #4
Changed test load parameters R1, R2, RTH and VTH from 1838 , 994 ,
645 and 1.75 V to 1800 , 990 , 639 and 1.77 V
Changed ICCDR from 2.5 A to 7 A
Added ICCDR typical value
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE and tLZWE from 6 ns to 10 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 22 ns to 25 ns
Updated the ordering information table and replaced Package Name column with
Package Diagram
*C 464503 NXR See ECN Included Automotive Range in product offering
Updated the Ordering Information
*D 485639 VKN See ECN Corrected the operating range to 4.5 V - 5.5 V on page# 3
*E 833080 VKN See ECN Added footnote #8
Added VILspec for SOIC package.
CY62148E MoBL®
Document #: 38-05442 Rev. *J Page 15 of 16
*F 890962 VKN See ECN Added Automotive-A part and its related information
Removed Automotive-E part and its related information
Added footnote #2 related to SOIC package
Added footnote #9 related to ISB2
Added AC values for 55 ns Industrial-SOIC range
Updated Ordering Information table
*G 2947039 VKN 06/10/2010 Added “CY62148ELL-45ZSXA” part in Ordering information.
Added footnote related to chip enable in Truth Table
Updated Package Diagrams
Added Contents, PSoC Solutions, and Sales, Solutions, and Legal Information.
*H 3006318 AJU 08/23/10 Template update.
Updated table of contents.
Added acronyms, units of measure and ordering code definitions.
Added reference to note 12 to parameter ICCDR on page 5.
*I 3235744 RAME 04/20/2011 Updated Functional Description (Removed the line “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM System
Guidelines”).
Updated Package Diagrams.
*J 3302815 RAME 07/14/2011 Updated as per latest template and updated table of contents.
Document History Page (continued)
Document Title: CY62148E MoBL®, 4-Mbit (512 K × 8) Static RAM
Document Number: 38-05442
Revision ECN Orig. of
Change
Submission
Date Description of Change
Document #: 38-05442 Rev. *J Revised July 14, 2011 Page 16 of 16
More Battery Life is a trademark and MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of
their respective holders.
CY62148E MoBL®
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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