July 200
Channel
TM
CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 9 of 54
3C080B
Pin # Pin Name Pin Symbol Input/Output Description
P9 Master Reset MRST Input
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go
high; EMPTY and PRAE will go low. In FWFT mode,
DRD
will go low and QRDY will go high. PRAF
and PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will not be maintained.
P10 Partial Reset PRST Input
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting PRST
low. In Standard mode, FULL and PRAF will go high;
EMPTY and PRAE will go low. In FWFT mode,
DRD
will go low and QRDY will go high. PRAF and
PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will be maintained.
T10 Write Clock WCLK Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
R10 Write Enable WEN Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
N12 Load Enable LOAD Input
During Master Reset, set LOAD low to select parallel
programming or one of eight default offset values. Set
LOAD high to select serial programming or one of eight
default offset values. After Master Reset, LOAD controls
write/read to/from offset registers during low to high
transition of WCLK/RCLK respectively. Use in
conjunction with WEN /REN .
M9 Default
Programming 1 PFS1 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS0.
M10 Default
Programming 0 PFS0 Input
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS1.
P11,R11,T11,P12,R12 Ch 0 D4-0
T12,P13,R13,T13,M12 Ch 1 D9-5
G14,G15,G16,F14,F15 Ch 2 D14-10
F16,E14,E15,E16,F13 Ch 3 D19-15
P14,R14,T14,R15,T15 Ch 4 D24-20
T16,R16,P15,P16,L12 Ch 5 D29-25
D14,D15,D16,C15,C16 Ch 6 D34-30
B16,A16,B15,A15,E13 Ch 7 D39-35
N14,N15,N16,M14,M15 Ch 8 D44-40
M16,L14,L15,L16,K13 Ch 9 D49-45
C14,B14,A14,C13,B13 Ch 10 D54-50
A13,C12,B12,A12,D13 Ch 11 D59-55
K14,K15,K16,J14,J15 Ch 12 D64-60
J16,H14,H15,H16,J13 Ch 13 D69-65
C11,B11,A11,C10,B10 Ch 14 D74-70
A10,C9,B9,A9,E12 Ch 15 D79-75
Input 80 - bit wide input data bus.
Table 1. Pin Descriptions