1
Features
•Low Voltage and Standard Voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•Internally Organized 128 x 8
•2-Wire Serial Interface
•Bidirectio nal Data Transfer Protocol
•100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Compatibility
•4-Byte P age Wr it e Mo de
•Self-Timed Write Cycle (10 ms m ax)
•High Reliabilit y
– Endurance: 1 Million Wr it e Cycles
– Data Retention: 100 Years
•A utomotive Grade, Extended Temperatur e and Lead-Free Devices Avai lable
•8-lead PDIP, 8- lead JEDEC SOIC and 8-lead TSSOP Packa ges
Description
The AT24C01 provides 1024 bits of ser ial electrically erasable and programmable
read only memor y (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low power
and low voltage operation are essential. The AT24C01 is available in space saving
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a
2-wire seri al interface. In addition , the entire family is available in 2.7V (2 .7V to 5.5V)
and 1.8V (1.8V to 5 .5V) versions.
2-Wire Serial
EEPROM
1K (128 x 8)
AT24C01
Rev. 0134G–SEEPR–7/03
Pin Configurations
Pin Name Functi on
NC No Connect
SDA Se r ia l D a ta
SCL Serial Clock Input
TEST Test Input (GND or VCC)
8-lead PDIP
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
8-l ead TSSO P
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
TEST
SCL
SDA
2AT24C01 0134G–SEEPR–7/03
Block Diagram
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maxim um Ratin gs” may cause permanent dam -
age to the de vice . This is a st ress rati ng only and
functional operati on of the device at these or any
other conditions beyond those i ndicated in the
operational secti ons of this specifi cation is not
implied. Exposure to absolute ma ximum rat ing
condit ions for ext ended per iods may affect
device reliability.
Storage Temperat ure.................. .. ............... .. -65°C to +150°C
Voltage on An y Pin
wit h R e spe ct to Gr o und ........... ......... .......... .......-1. 0V to +7.0 V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C01
0134G–SEEPR–7/03
Pin D escription SERIAL CLOCK (SCL) : The SCL input is used to positive edge clock data into eac h
EEPROM device a nd negative edge clock data out of each device.
S ERIA L DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-O Red with any number of other open-drain or op en
collector devices.
Memory Organization AT24C0 1, 1K S ERIAL EEP ROM: Internally organized with 128 pages of 1 byte each.
The 1K requires a 7-bit data word address for random word a ddressing.
Note: 1. VIL min and VIH max are reference only and are not tested.
Pin C apacitance
Applicable over recomme nded operat ing range from T A = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditi on
CI/O Input/Ou tput Capacit ance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0 V
DC Characteristics
Applicable over rec om m ended operating range fr om : TAI = - 40°C to +85°C, VCC = +1 .8V to + 5 .5 V , TAE = -4 0°C to +125°C,
VCC = +1 .8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 2.7 5.5 V
VCC4 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0 V READ at 100 kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V WRIT E at 100 kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 1.8V V IN = VCC or VSS 0.6 3.0 µA
ISB2 Standby Current VCC = 2.5V V IN = VCC or VSS 1.4 4.0 µA
ISB3 Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA
ISB4 Standby Current VCC = 5.0V V IN = VCC or VSS 8.0 18.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA
VIL Input Low Le vel(1) -0.6 VCC × 0.3 V
VIH Input High Level(1) VCC × 0.7 VCC + 0.5 V
VOL2 Output Low Le vel VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Le vel VCC = 1.8V IOL = 0.15 mA 0.2 V
4AT24C01 0134G–SEEPR–7/03
Note: 1. This paramete r is characteriz ed and is not 100% tested.
AC Characteristics
Applica ble over recommende d operatin g range f rom TAI = -4 0°C to +85°C, TAE = -40°C to +1 25°C, VCC = + 1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unle ss otherwise noted).
Symbol Parameter
2.7-, 2.5-, 1.8- vol t 5.0-volt
UnitsMin Max Min Max
fSCL Cloc k Frequency, SCL 100 400 kHz
tLOW Cloc k Pulse Width Low 4.7 1.2 µs
tHIGH Clock Pulse Width High 4.0 0.6 µs
tINoise Suppression Time(1) 100 50 ns
tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs
tBUF Time the bus must be free before a new
transmission can start(1) 4.7 1.2 µs
tHD.STA Start Hold Time 4.0 0.6 µs
tSU.STA Star t Set-up Time 4.7 0.6 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 200 100 ns
tRInputs Rise Time(1) 1.0 0.3 µs
tFInputs F all Time(1) 300 300 ns
tSU.STO Stop Set-up Time 4.7 0.6 µs
tDH Data Out Hold Time 100 50 ns
tWR Write Cycle Time 10 10 ms
Endurance(1) 5.0V, 25°C, Page Mode 1M 1M Write
Cycles
5
AT24C01
0134G–SEEPR–7/03
De vice Operation CLOCK and DAT A T RANSITIONS: The SDA pi n is norm ally p ulled hig h wi th an exter-
nal device. Data on t he S DA pin m ay ch ange onl y during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A hig h-to-low transition of SDA with SCL high is a start condi tion
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP COND ITION: A low- to-high trans ition of SDA with SCL high is a stop condition
which terminates all communications. After a read sequenc e, the stop command will
place the EEPROM in a standby power mode (refer to Start and Stop Definition timing
diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. Any device on the system bus receiving data (when com-
municating with the EEPROM) must pull the SDA bus low to acknowledge that it has
successfully received each word. This must happen during the ninth clock cycle after
each word received and after all other system devices have freed the SDA bus. The
EEPROM will likewise acknowledge by pull ing SDA l ow af ter rec eiving each address or
data word (refer to Acknowledge Response from Receiver timing diagram).
STANDBY MODE: The AT24C01 features a low power standby mode which is enabled:
(a) u pon powe r-up an d (b ) afte r the rec eipt of the STOP bit a nd t he com pleti on of a ny
internal operations.
MEMORY RESET: After an interrup tion in prot ocol, power loss or s ystem reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6AT24C01 0134G–SEEPR–7/03
Bus Timing
SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
twr(1)
STOP
CONDITION START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
7
AT24C01
0134G–SEEPR–7/03
Data Val idity
Start and Stop De finition
Output Acknowledge
8AT24C01 0134G–SEEPR–7/03
Write Operations BYTE WRITE: Followi ng a start condi tion, a wri te op eration re quire s a 7-bit da ta wo rd
address and a low write bit. Upon receipt of this address, the EEPROM w ill again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-
bit data word, the EEPROM will output a z ero and the addressing device, such as a
microcontroller, must terminate the write sequence with a stop condition. At this time the
EEPROM en ter s a n internally-timed write cycle to th e nonvolatile memory. All inputs are
disabled durin g this write cycle , tWR, and the EEPROM will not respond until the write is
comple te (refer to Figure 1).
PAGE WRITE: The AT24C01 is capable of a 4-byte page write.
A page write is initiated the same as a byte write but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowl edges rec ei pt of the fi rst data wo rd, the microcontroll er can t rans mit u p to t hree
more data words. The EEPRO M will respond with a zero after each data word received.
The m icrocontrol ler must terminate the p age write sequence wit h a st op condition (refer
to F i g ure 2).
The data word address lower 2 bits are internally incremented following the receipt of
each data word. The higher five data word address bits are not incremented, retaining
th e memor y pag e row lo cati on. W hen the w ord a ddress , intern ally ge ner ated , re aches
the page boundary, the following byte is placed at the beginning of the same page. If
more tha n four data word s ar e tra nsmitted to the EEP ROM , the d ata word addres s will
“roll over” and previous data will be overwritten.
ACKNOWLE DGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a ze ro allowing the read or write sequence to continue.
Rea d Oper ati on s Re ad operatio ns are initiated t he same way as write op erations with the ex ception t hat
the read/write select bit in the device address word is set to one. There are two read
operations: byte read and sequential read.
BYTE READ: A byte read is initiated with a start condition followed by a 7-bit data word
addres s and a high rea d bit. The AT24C01 wi ll respond with an ac kn owledge an d then
serially output 8 data bits. The m icrocontroller does not respond with a zero but does
generate a following stop condition (refer to Figure 3).
SEQUENTIAL READ: Sequen tial read s are initiated the s ame as a byt e read. Aft er the
microcontroller receives an 8-bi t data word, it r esponds with an acknowledge. As long as
the EEPROM receives an acknowledge, it will continue to increment the data word
addres s and serially clock out sequential data words. When the memory address limit is
reached, the data word address will “roll over” and the sequential read will continue. The
sequ ential re ad operation is terminated when the microcontroller does not respond with
an input zero but does generate a following stop condition (refer to Figure 4).
9
AT24C01
0134G–SEEPR–7/03
Figu re 1. Byte Write
Figu re 2. P age Wr it e
Figu re 3. Byte Read
Figu re 4. Sequent ial Read
10 AT24C01 0134G–SEEPR–7/03
Note: F or 2.7V devices used in the 4.5V to 5.5V range, please refer to per formance values in t he AC and DC Characteristics tables.
Ordering Information
Order ing Code Package Operation Range
AT24C01-10PI-2.7
AT24C01-10SI-2.7
AT24C01-10TI-2.7
8P3
8S1
8A2
Industrial
(-40°C to 85 °C)
AT24C01-10PI-1.8
AT24C01-10SI-1.8
AT24C01-10TI-1.8
8P3
8S1
8A2
Industrial
(-40°C to 85 °C)
AT24C01-10SJ-2.7
AT24C01-10SJ-1.8 8S1
8S1 Lead-Free/Industrial Temperature
(-40°C to 85 °C)
AT24C01-10SE-2.7 8S1 High Grade/Extended Temperat ure
(-40°C to 125°C)
Package Type
8P3 8-lea d, 0.300" Wide, Plast ic Dual Inline Package (PDIP)
8S1 8-lea d, 0. 150" Wide , Pl astic Gull Wing Small Ou tl ine (JEDEC SOIC)
8A2 8-lea d, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7 Low-Voltage (2.7V to 5.5V)
-1.8 Low-Voltage (1.8V to 5.5V)
11
AT24C01
0134G–SEEPR–7/03
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
12 AT24C01 0134G–SEEPR–7/03
8S1 – JEDEC SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
Note:
10/10/01
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 A
H
1
2
N
3
Top View
C
E
End View
A
B
L
A2
e
D
Side View COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
A – – 1.75
B – – 0.51
C – – 0.25
D – – 5.00
E – – 4.00
e 1.27 BSC
H – – 6.20
L – – 1.27
13
AT24C01
0134G–SEEPR–7/03
8A2 – TSSO P
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Pr inted o n rec ycled pa per.
0134G–SEEPR–7/03 xM
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