1
FEATURES
DPACKAGE
(TOP VIEW)
A0
A1
RESET
INT0
SD0
SC0
GND
VCC
SDA
SCL
INT
SC1
SD1
INT1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PWPACKAGE
(TOP VIEW)
A0
A1
RESET
INT0
SD0
SC0
GND
1
2
3
4
5
6
7
VCC
SDA
SCL
INT
SC1
SD1
INT1
14
13
12
11
10
9
8
DESCRIPTION/ORDERING INFORMATION
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007www.ti.com
•1-of-2 Bidirectional Translating Switches •Supports Hot Insertion•I
2
C Bus and SMBus Compatible •Low Standby Current•Two Active-Low Interrupt Inputs •Operating Power-Supply Voltage Range of2.3 V to 5.5 V•Active-Low Interrupt Output
•5-V Tolerant Inputs•Active-Low Reset Input
•0 to 400-kHz Clock Frequency•Two Address Pins Allowing up to FourDevices on the I
2
C Bus •Latch-Up Performance Exceeds 100 mA PerJESD78•Channel Selection Via I
2
C Bus, in AnyCombination •ESD Protection Exceeds JESD 22•Power Up With All Switch Channels – 2000-V Human-Body Model (A114-A)Deselected
– 200-V Machine Model (A115-A)•Low r
on
Switches
– 1000-V Charged-Device Model (C101)•Allows Voltage-Level Translation Between1.8-V, 2.5-V, 3.3-V, and 5-V Buses•No Glitch on Power Up
The PCA9543A is a bidirectional translating switch controlled by the I
2
C bus. The SCL/SDA upstream pair fansout to two downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can beselected, determined by the contents of the programmable control register. Two interrupt inputs ( INT0– INT1),one for each of the downstream pairs, are provided. One interrupt output ( INT) acts as an AND of the twointerrupt inputs.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube of 50 PCA9543ADSOIC – D PCA9543AReel of 2500 PCA9543ADR– 40 °C to 85 °C
Tube of 90 PCA9543APWTSSOP – PW PD543AReel of 2000 PCA9543APWR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
An active-low reset ( RESET) input allows the PCA9543A to recover from a situation where one of thedownstream I
2
C buses is stuck in a low state. Pulling RESET low resets the I
2
C state machine and causes all thechannels to be deselected, as does the internal power-on reset function.
The pass gates of the switches are constructed such that the V
CC
pin can be used to limit the maximum highvoltage, which will be passed by the PCA9543A. This allows the use of different bus voltages on each pair, sothat 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. Externalpullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
TERMINAL FUNCTIONS
D AND PW
NAME DESCRIPTIONPIN NUMBER
1 A0 Address input 0. Connect directly to V
CC
or ground.2 A1 Address input 1. Connect directly to V
CC
or ground.3 RESET Active-low reset input. Connect to V
CC
through a pullup resistor, if not used.4 INT0 Active-low interrupt input 0. Connect to V
CC
through a pullup resistor.5 SD0 Serial data 0. Connect to V
CC
through a pullup resistor.6 SC0 Serial clock 0. Connect to V
CC
through a pullup resistor.7 GND Ground8 INT1 Active-low interrupt input 1. Connect to V
CC
through a pullup resistor.9 SD1 Serial data 1. Connect to V
CC
through a pullup resistor.10 SC1 Serial clock 1. Connect to V
CC
through a pullup resistor.11 INT Active-low interrupt output. Connect to V
CC
through a pullup resistor.12 SCL Serial clock line. Connect to V
CC
through a pullup resistor.13 SDA Serial data line. Connect to V
CC
through a pullup resistor.14 V
CC
Supply power
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INT
A0
A1
PCA9543A
RESET
SC1
6
10
5
9
7
14
3
13
12 1
2
11
SC0
SD0
SD1
GND
VCC
SCL
SDA
INT1
INT0
InputFilter
OutputFilter
I CBus
Control
2
InterruptLogic
SwitchControlLogic
Power-On
Reset
4
8
Device Address
A1 A0
11 1
Fixed Hardware
selectable
0 0 R/W
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
BLOCK DIAGRAM
Figure 1. Block Diagram
Following a start condition, the bus master must output the address of the slave it is accessing. The address ofthe PCA9543A is shown in Figure 2 . To conserve power, no internal pullup resistors are incorporated on thehardware-selectable address pins and they must be pulled high or low.
Figure 2. Slave Address PCA9543A
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,while a logic 0 selects a write operation.
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Control Register
X B1
XXINT1
7 6 5 4 3 2 1 0
Interrupt
(ReadOnly)
Bits ChannelSelectionBits
(Read/Write)
Channel0
Channel1
INT0
INT1
INT0 X B0
Control Register Definition
Interrupt Handling
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9543A,which is stored in the control register (see Figure 3 ). If multiple bytes are received by the PCA9543A, it saves thelast byte received. This register can be written and read via the I
2
C bus.
Figure 3. Control Register
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (seeTable 1 ). After the PCA9543A has been addressed, the control register is written. The two LSBs of the controlbyte are used to determine which channel or channels are to be selected. When a channel is selected, thechannel becomes active after a stop condition has been placed on the I
2
C bus. This ensures that all SCn/SDnlines are in a high state when the channel is made active, so that no false conditions are generated at the time ofconnection. A stop condition must occur always right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)
(1)
D7 D6 INT1 INT0 D3 D2 B1 B0 COMMAND
0 Channel 0 disabledX X X X X X X
1 Channel 0 enabled0 Channel 1 disabledX X X X X X X1 Channel 1 enabled0 0 0 0 0 0 0 0 No channel selected; power-up/reset default state
(1) Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.
The PCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (seeTable 2 ). When an interrupt is generated by any device, it is detected by the PCA9543A and the interrupt outputis driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the controlregister.
Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the PCA9543A, respectively.Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs isloaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected tochannel 0 would cause bit 4 of the control register to be set on the read. The master then can address thePCA9543A and read the contents of the control register to determine which channel contains the devicegenerating the interrupt. The master then can reconfigure the PCA9543A to select this channel, and locate thedevice generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master toensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to V
CC
through a pullup resistor.
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RESET Input
Power-On Reset
Voltage Translation
5.0
4.0
V (V)
CC
V (V)
pass
3.0
2.0
1.0
5.0 5.52.0 2.5 3.0 3.5 4.0 4.5
Min
Typ
Max
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
Table 2. Control Register Read (Interrupt)
(1)
D7 D6 INT1 INT0 D3 D2 B1 B0 COMMAND
0 No interrupt on channel 0X X X X X X X1 Interrupt on channel 00 No interrupt on channel 1X X X X X X X1 Interrupt on channel 10 0 0 0 0 0 0 0 No channel selected; power-up/reset default state
(1) Two interrupts can be active at the same time.
The RESET input can be used to recover the PCA9543A from a bus-fault condition. The registers and the I
2
Cstate machine within this device initialize to their default states if this signal is asserted low for a minimum of t
WL
.All channels also are deselected in this case. RESET must be connected to V
CC
through a pullup resistor.
When power is applied to V
CC
, an internal power-on reset holds the PCA9543A in a reset condition until V
CC
hasreached V
POR
. At this point, the reset condition is released and the PCA9543A registers and I
2
C state machineare initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
CC
mustbe lowered below 0.2 V to reset the device.
The pass-gate transistors of the PCA9543A are constructed such that the V
CC
voltage can be used to limit themaximum voltage that is passed from one I
2
C bus to another.
Figure 4. V
pass
Voltage vs V
CC
Figure 4 shows the voltage characteristics of the pass gate transistors (note that the graph was generated usingthe data specified in Electrical Characteristics section of this data sheet). In order for the PCA9543A to act as avoltage translator, the V
pass
voltage should be equal to or lower than the lowest bus voltage. For example, if themain bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V
pass
must be equal to or below 2.7 Vto effectively clamp the downstream bus voltages. As shown in Figure 4, V
pass(max)
is at 2.7 V when thePCA9543A supply voltage is 3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pullupresistors then can be used to bring the bus voltages to their appropriate levels (see Figure 14 ).
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I
2
C Interface
SDA
SCL
DataLine
Stable;
DataValid
Change
ofdata
allowed
SDA SDA
SCL SCL
S P
STARTCondition STOP Condition
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Master
Transmitter/
Receiver
I C-Bus
Multiplexer
2
SDA
SCL
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
The I
2
C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serialdata line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullupresistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is notbusy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the highperiod of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 5 ).
Figure 5. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while theclock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high isdefined as the stop condition (P) (see Figure 6 ).
Figure 6. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device thatcontrols the message is the master and the devices that are controlled by the master are the slaves (seeFigure 7 ).
Figure 7. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is notlimited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDAline before the receiver can send an ACK bit.
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SDA
Slave Address ControlRegister
Stop
Condition
R/W
Start
Condition
Acknowledge
FromSlave
Acknowledge
FromSlave
A1S A0
11 1 0 0 0 A A PX X X X X X B1 B0
SDA
Slave Address ControlRegister
Stop
Condition
R/W
Start
Condition
No Acknowledge
FromMaster
Acknowledge
FromSlave
LastByte
A1S A0
11 1 0 0 1 A NA PX X INT1 INT0 X X B1 B0
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a mastermust generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. Thedevice that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stablelow during the high pulse of the ACK-related clock period (see Figure 8 ). Setup and hold times must be takeninto account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) afterthe last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 8. Acknowledgment on I
2
C Bus
Data is transmitted to the PCA9543A control register using the write mode shown in Figure 9 .
Figure 9. Write Control Register
Data is read from the PCA9543A control register using the read mode shown in Figure 10 .
Figure 10. Read Control Register
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range – 0.5 7 VV
I
Input voltage range
(2)
– 0.5 7 VI
I
Input current ± 20 mAI
O
Output current ± 25 mAContinuous current through V
CC
± 100 mAContinuous current through GND ± 100 mAD package 86θ
JA
Package thermal impedance
(3)
°C/WPW package 113P
tot
Total power dissipation 400 mWT
stg
Storage temperature range – 60 150 °CT
A
Operating free-air temperature range – 40 85 °C
(1) Stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operatingconditions ” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 5.5 VSCL, SDA 0.7 ×V
CC
6V
CC
= 2.3 V to 3.6 V 0.7 ×V
CC
V
CC
+ 0.5V
IH
High-level input voltage VA1, A0, INT1, INT0, RESET V
CC
= 3.6 V to 4.5 V 0.7 ×V
CC
V
CC
+ 0.5V
CC
= 4.5 V to 5.5 V 0.7 ×V
CC
V
CC
+ 0.5SCL, SDA – 0.5 0.3 ×V
CCV
IL
Low-level input voltage VA1, A0, INT1, INT0, RESET – 0.5 0.3 ×V
CC
T
A
Operating free-air temperature – 40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Electrical Characteristics
(1)
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
V
POR
Power-on reset voltage No load: V
I
= V
CC
or GND
(2)
V
POR
1.6 2.1 V5 V 3.64.5 V to 5.5 V 2.6 4.53.3 V 1.9V
SWin
= V
CC
,V
pass
Switch output voltage VI
SWout
= – 100 μA
3 V to 3.6 V 1.6 2.82.5 V 1.52.3 V to 2.7 V 1.1 2I
OH
INT V
O
= V
CC
2.3 V to 5.5 V 100 μAV
OL
= 0.4 V 3 7SDAI
OL
V
OL
= 0.6 V 2.3 V to 5.5 V 6 10 mAINT V
OL
= 0.4 V 3SCL, SDA V
I
= V
CC
or GND 2.3 V to 5.5 V – 1 12.3 V to 3.6 V – 1 1SC1 – SC0, SD1 – SD0 V
I
= V
CC
or GND
4.5 V to 5.5 V – 1 1002.3 V to 3.6 V – 1 1A1, A0 V
I
= V
CC
or GNDI
I
4.5 V to 5.5 V – 1 50 μA2.3 V to 3.6 V – 1 1INT1– INT0 V
I
= V
CC
or GND
4.5 V to 5.5 V – 1 502.3 V to 3.6 V – 1 1RESET V
I
= V
CC
or GND
4.5 V to 5.5 V – 1 505.5 V 17 50Operating f
SCL
= 100
V
I
= V
CC
or GND, I
O
= 0 3.6 V 6 20mode kHz
2.7 V 3 165.5 V 0.3 1I
CC
Low inputs V
I
= GND, I
O
= 0 3.6 V 0.1 1 μA2.7 V 0.1 1Standby
mode
5.5 V 0.3 1High inputs V
I
= V
CC
, I
O
= 0 3.6 V 0.1 12.7 V 0.1 1One INT1– INT0 input at 0.6 V,
8 20Other inputs at V
CC
or GNDINT1– INT0
One INT1– INT0 input at V
CC
– 0.6 V,
8 20Supply-
Other inputs at V
CC
or GNDΔI
CC
current 2.3 V to 5.5 V μASCL or SDA input at 0.6 V,change
8 20Other inputs at V
CC
or GNDSCL, SDA
SCL or SDA input at V
CC
– 0.6 V,
8 20Other inputs at V
CC
or GND
2.3 V to 3.6 V 4 5A1, A0 V
I
= V
CC
or GND
4.5 V to 5.5 V 4 52.3 V to 3.6 V 4 6INT1– INT0 V
I
= V
CC
or GNDC
i
4.5 V to 5.5 V 4 6 pF2.3 V to 3.6 V 4 5RESET V
I
= V
CC
or GND
4.5 V to 5.5 V 4 5SCL V
I
= V
CC
or GND 2.3 V to 5.5 V 9 12
(1) For operation between published voltage ranges, refer to the worst-case parameter in both ranges.(2) To reset the part, either RESET must be low or V
CC
must be lowered to 0.2 V.
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I
2
C Interface Timing Requirements
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
Electrical Characteristics (continued)over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
SDA 11 13C
io(OFF)
(3)
V
I
= V
CC
or GND, Switch OFF 2.3 V to 5.5 V pFSC1 – SC0, SD1 – SD0 6 84.5 V to 5.5 V 4 9 20V
O
= 0.4 V, I
O
= 15 mAr
on
Switch on-state resistance 3 V to 3.6 V 5 11 25 Ω
V
O
= 0.4 V, I
O
= 10 mA 2.3 V to 2.7 V 7 16 50
(3) C
io(ON)
depends on the device capacitance and load that is downstream from the device.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11 )
STANDARD MODE FAST MODEI
2
C BUS I
2
C BUS
UNITMIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 kHzt
sch
I
2
C clock high time 4 0.6 μst
scl
I
2
C clock low time 4.7 1.3 μst
sp
I
2
C spike time 50 50 nst
sds
I
2
C serial-data setup time 250 100 nst
sdh
I
2
C serial-data hold time 0
(1)
0
(1)
μst
icr
I
2
C input rise time 1000 20 + 0.1C
b
(2)
300 nst
icf
I
2
C input fall time 300 20 + 0.1C
b
(2)
300 nst
ocf
I
2
C output fall time 10-pF to 400-pF bus 300 20 + 0.1C
b
(2)
300 nst
buf
I
2
C bus free time between stop and start 4.7 1.3 μst
sts
I
2
C start or repeated start condition setup 4.7 0.6 μst
sth
I
2
C start or repeated start condition hold 4 0.6 μst
sps
I
2
C stop condition setup 4 0.6 μst
vdL(Data)
Valid-data time (high to low)
(3)
SCL low to SDA output low valid 1 1 μst
vdH(Data)
Valid-data time (low to high)
(3)
SCL low to SDA output high valid 0.6 0.6 μsACK signal from SCL lowt
vd(ack)
Valid-data time of ACK condition 1 1 μsto SDA output lowC
b
I
2
C bus capacitive load 400 400 pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V
IH
min of the SCL signal), in orderto bridge the undefined region of the falling edge of SCL.(2) C
b
= total bus capacitance of one bus line in pF(3) Data taken using a 1-k Ωpullup resistor and 50-pF load (see Figure 11 )
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Switching Characteristics
Interrupt and Reset Timing Requirements
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 13 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
R
ON
= 20 Ω, C
L
= 15 pF 0.3t
pd
(1)
Propagation delay time SDA or SCL SDn or SCn nsR
ON
= 20 Ω, C
L
= 50 pF 1t
iv
Interrupt valid time
(2)
INTn INT 4 μst
ir
Interrupt reset delay time
(2)
INTn INT 2 μs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).(2) Data taken using a 4.7-k Ωpullup resistor and 100-pF load (see Figure 13 )
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13 )
PARAMETER MIN MAX UNIT
t
PWRL
Required low-level pulse duration of INTn inputs
(1)
1μst
PWRH
Required high-level pulse duration of INTn inputs
(1)
0.5 μst
WL
Pulse duration, RESET low 4 nst
rst
(2)
RESET time (SDA clear) 500 nst
REC
Recovery time from RESET to start 0 ns
(1) The device has interrupt input rejection circuitry for pulses less than the listed minimum.(2) t
rst
is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,signaling a stop condition. It must be a minimum of t
WL
.
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PARAMETER MEASUREMENT INFORMATION
RL= 1 kΩ
VCC
CL= 50 pF
(See Note A)
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tvd(ACK)
or tvdL
tvdH
Stop
Condition
tsps
Repeat
Start
Condition
Start or Repeat
Start Condition
SCL
SDA
Start
Condition
(S)
Address
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
Two Bytes for Complete
Device Programming
I2C PORT LOAD CONFIGURATION
VOLTAGE WAVEFORMS
ticf
Stop
Condition
(P)
tsp
DUT SDn, SCn
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Address
Bit 1
Address
Bit 6
ACK
(A)
BYTE DESCRIPTION
I2C address + R/W
Control register data
1
2
A. CLincludes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω,
tr/tf= 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
0.7 × VCC
0.7 × VCC
0.3 × VCC
0.3 × VCC
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
Figure 11. I
2
C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): PCA9543A
www.ti.com
DUT INT
INTn
(input)
VOLTAGE WAVEFORMS (tiv)
tiv
VOLTAGE WAVEFORMS (tir)
INT
(output)
INTn
(input)
INT
(output)
tir
A. CLincludes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO= 50 Ω,
tr/tf= 30 ns.
C = 100 pF
(See Note A)
L
R = 4.7 k
LΩ
VCC
0.5 × VCC
0.5 × VCC
0.5 × VCC
0.5 × VCC
INTERRUPT LOAD CONFIGURATION
PCA9543ATWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 12. Reset Timing
Figure 13. Interrupt Load Circuit and Voltage Waveforms
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): PCA9543A
www.ti.com
APPLICATION INFORMATION
SD0
12
13
11
3
5
9
6
10
4
8
2
7
1
SC0
PCA9543A
VCC =2.7Vto5.5V
VCC =2.7Vto5.5V
Channel0
Channel1
SeeNote A
SeeNote A
SDA
SCL
VCC
SDA
SCL
I C/SMBus
Master
2
V =3.3V
CC
V =2.7Vto5.5V
CC
INT INT0
SD1
SC1
INT1
RESET
A1
GND
A0
NOTE: A.
B. PinnumbersshownarefortheDandPWpackages.
Ifthedevicegeneratingtheinterrupthasanopen-drainoutputstructureorcanbe3-stated,a
pullupresistorisrequired.
Ifthedevicegeneratingtheinterrupthasatotem-poleoutputstructureandcannotbe3-stated,
apullupresistorisnotrequired.
Theinterruptinputsshouldnotbeleftfloating.
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCHWITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
Figure 14 shows an application in which the PCA9543A can be used.
Figure 14. Typical Application
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): PCA9543A
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCA9543AD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543ADG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543ADR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543APW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543APWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCA9543APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Oct-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCA9543APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCA9543APWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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