TOSHIBA TC90A13N/F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9IOA13N, TCIOA13F 3 LINE DIGITAL Y/C SEPARATION IC The TC90A13N and TC90A13F separate luminance (Y) and TC90A13N chrominance (C) signals from an NTSC composite video signal. It employs the Toshiba original logical comb filter to realize high performance Y/C separation at low cost. FEATURES @ NTSC system @ PLL 4X multiplication circuit SDIP28-P-400-1.78 @ Sync. tip clampping circuit TC90A13F 8bit A/D converter 8bit D/A converters (2ch) 2H line memory @ Dynamic comb filter @ 1 line dot correction circuit SOP28-P-450-1.27 @ Vertical enhancer Weight SDIP28-P-400-1.78 : 1.7g (Typ.) @ Color killer mode (Y/C separation OFF) SOP28-P-450-1.27 : 0.8g (Typ.) @ Chrominance wide band output mode SDIP28 /SOP28 package 5V single power supply 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-11-18 1/14TOSHIBA TC90A13N/F BLOCK DIAGRAM VE VENH1 C ADIN (5 ADC 1H Line Memory Vertical Edge Coring Enhancement Circuit Circuit CLAMPC (7 Clamp 1H Line Memory Pedestal YOUT Clip Color Killer KILLER Circuit VREF1 Dynamic 1 Line Dot it Correction Comb Filter Circuit COUT CKIN (11 VFIL @ 1LINE CBPF TERMINAL CONNECTION DIAGRAM VREFL (1) 28) Vssa Vss1 Q) &) Vpp4 Vpp1 (26) VREF1 VREFH S 25) YouT ADIN G} 24) BIAS? BIAS; (6) 23) COUT crampc @)} 22) BIAS3 TEesT1 @} 27) Vss3 1/2Vpp @) 0) Vpp3 vFIL (9 '9) CORING cKIn (1) (8) 1LINE Vpp2 (17) VENH1 Vss2 G3) (1) VENHO KILLER (14) 15) CBPF (TOP VIEW) 1997-11-18 2/14TOSHIBA TC90A13N/F TERMINAL FUNCTION No. | NAME FUNCTION No. | NAME FUNCTION 1 | VREFL Bias for ADC 15 | CBPF L: C-BPF = WIDE, H : NARROW Vertical edge enhanced level 2 |Vss1 GND for ADC 16 | VENHO (VENHO, VENH1) =(L, L) = OFF 3 |Vpp1__|Vpp fer ADC 17 |VENH1 tH De H) = MID, . L : 1 line color ON 4 |VREFH Bias for ADC 18 | 1LINE H = 1 line color OFF . . L : Coring ON 1 RIN 5 | ADIN Video input 9 | CORING H : Coring OFF 6 | BIAS, Bias for ADC 20 |Vpp3 Vpp for digital 7 |CLAMPC [Clamp filter 21 |Vs553 GND for digital 8 |TEST1 Test terminal 22 | BIAS3 Bias for DAC 9 |1/2Vpp | Bias for line memory 23 | COUT C output 10 | VFIL VCO filter 24 | BIAS) Bias for DAC 11 | CKIN Clock input 25 | YOUT Y output 12 |Vpp2 Vpp for PLL 26 | VREF1 Bias for DAC 13 |Vss2 GND for PLL 27 |Vpp4__| Vpp for DAC 14 | KILLER |L: Color, H: B/W mode 28 | Vssa GND for DAC (Note) Pin9 and Pin 26 require external bias 1997-11-18 3/14TOSHIBA TC90A13N/F FUNCTION BLOCK DESCRIPTIONS 1. Input clamp (CLAMP) This block performs sync tip clamping of the composite video signal. It provides a feedback signal for clamping A/D-converted minimum data at Y/C separation to the internal DC bias level. A/D converter (ADC) This block comprises a high-speed series-parallel 8bit A/D converter that accepts an input video signal of 1.5Vp-p (from sync level to 100% white level). 1H memory This block consists of DRAM resident line memory for 1H delay. The 3-line comb filter is configured from two pairs of line memory. Vertical edge enhancement circuit (VENH) This block enhances the uncorrelated components among the three lines of the luminance signal following coring. There are three enhancement level selections of HIGH (1.9dB), MID (1.0dB) and LOW 0.5dB). The luminance signal, obtained by subtracting the chrominance signal from the composite video signal, is added to the vertical edge enhancement component and output through the D/A converter. However, this output signal is limited to the pedestal level (fixed internally) by the pedestal clipping circuit (except for the sync tip level). Horizontal band-pass filter (BPF) In this block, with fsc as the center frequency of the BPF, the chrominance signal is extracted from the 0H, 1H and 2H delayed composite video signal. Since the BPF for the chrominance signal output can be controlled (ON or OFF), the chrominance output can therefore be switched between a narrow band width and a wide band width. Vertical dynamic comb filter (DCF) This block comprises a band-pass filter that extracts the vertical component of the chrominance signal. Using Toshiba original logic, a correlation of the three lines is sought for. The absence of correlation is taken as an indication of a luminance signal, at which time chrominance signal output is suppressed. 1-line dot correction circuit Previously, a 1-line-only chrominance signal was processed as a luminance signal resulting in dot crawl. This circuit prevents this problem by extracting the 1-line dot component and adding it to the dynamic comb filter output. This circuit block can be set ON or OFF. Clock and memory timing generator (RTIM) This block supplies a 4 fsc (PLL 4X multiplied) buffered signal to the other circuit blocks, and also generates a timing signal for the memory. D/A converter (DAC) This block comprises a high-speed 8bit D/A converter. It provides Y output at approximately 1.5Vp-p and burst-level C output at approximately 572MVp-p- 1997-11-18 4/14TOSHIBA TC9O0A13N/F MODE TABLE KILLER| CBPF|VENHO|VENH1 | LINE KORING MODE ACTION L |Y/C separation ON Color mode H |Y/C separation OFF B/W mode (Killer) Chrominance signal L | horizontal band width Passes through BPF for WIDE chrominance signal output fn | | | | [RRR [oes not pas trough PF fx NARROW chrominance signal output L L |Vertical enhance OFF No vertical enhancement _ _ 4 L _ _ Vertical enhance level Vertical enhancement level MID 0.5dB _ _ L H _ _ Vertical enhance level | Vertical enhancement level LOW 1.0dB _ _ 4 4 _ _ Vertical enhance level | Vertical enhancement level HIGH 1.9dB L |1 line color ON 1 line dot correction circuit ON H |1 line color OFF 1 line dot correction circuit OFF L Coring ON Coring circuit ON H Coring OFF Coring circuit OFF RATINGS AND CHARACTERISTICS The following specifications were obtained in part from the test circuit shown on page 8. MAXIMUM RATINGS (Ta =25C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage Vpp Vos~Vss + 6.0 V Input Voltage VIN -0.3~Vpp + 0.3 Vv Power Dissipation TC90A13N Pp (Note) 900 mw TC90A13F 600 Storage Temperature Tstg -55~125 C (Note) Ta = 75C RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC SYMBOL TEST CONDITION MIN. | TYP. | MAX. | UNIT Power Supply Voltage Vpp 4.75 5.0| 5.25 Vv Input Voltage VIN Oo; Vpp V Operating Temperature Topr -10/; 75] % 1997-11-18 5/14TOSHIBA TC90A13N/F ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Ta = 25C, Vpp = 5V) CHARACTERISTIC SYMBOL ck. TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT Power Supply Voltage VDD 1 4.75 5.0} 5.25) V Supply Current IDD 1 40 60 80} mA Output Voltage Level YOUT 1 3.0} 3.15 3.3 Vv COUT 3.9 4.0 4.1 VREFL 1.4 1.5 1.6 VREFH 3.4 3.5 3.6 ADIN CLOCK = 3.579545MHz 1.5{ 16] 1.8 BIAS4 500MVp-p 0.8 1.4 2.4 Pin Voltage Level BIAS? 1 | VREF1 =3.0V 0.8 1.6 2.6) V BIAS3 1/2Vpp =2.5V 2.4 3.4 4.4 CLAMPC ViIN=No input (Note 2) 2.0 3.0 4.0 VFIL 0.9 1.9 2.9 CKIN 1.5 2.2 3.0 Input Voltage High Level VIH 1 4; V Low Level VIL 1 1 ADIN Pin Input Capacitance CIN 1 50; pF Pull Down Resistance Rpp 1 25 50 100] kO (Note 1) External bias must be applied at Pin9 and Pin 26. (Note 2) Ipp is Vin=modulated lamp wave. 1997-11-18 6/14TOSHIBA TC90A13N/F AC CHARACTERISTICS Y output (Ta=25C, Vpp=5V, Clock frequency 3.579545MHz, 0.5Vp-p, $1=2, VREF1 = 3.0V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT Input Level VIN 1 [0~140IRE 1.5[ 1.6| Vp-p $2=2, $3=2, $S4=1, $5=2 Low Frequency Gain GV 1 VIN = 15.734kHz, 1.5Vp-p -0.5 0.0 0.5 dB Vdc=2.5V MTF1 1 [922 S3=2, f2/f1| -2.0| -1.2] -0.5 $4=1, $5=2 Frequency Response Vin =1.5V dB = 1.9Vp-p _ _ _ MTF2 1 Vde=2.5V f4/f1 3.0 2.0 1.5 $2=2, $3=2, Comb Characteristics Comb 1 [S4=1, S5=2 2/43 | 40/ 45) | a Vdc=2.5V Ls 1 [2at S3=1, Y1/Y2 35 40 43 . . . 4=1, $5=2 Linearity (Fig.1) VIN=5 step signal % Ly 1 Vp (Fig.2) | /Y2| 57} 60] 63 2=1, $3=1, $5=2 VIN = 15.734kHz, 1.5Vp-p Output Impedance Zo 1 |Wde=2.5V 250| 400! 700] Zo 2 x 400 Oo V2 V1: S4=1, V2 : $4=2 Clock Leakage 2=2, $83 =2, $4=1, $5=1 L. 1 _ _ . 2 V (4fg Components) ck Vin =No input >-0 0 |MVrms Fundamental Clock Leakage $2=2, $3=2, $4=1, S5=1 (f Components) Lsc ' Vin =No input 7 1.0) 2.0 )mVrms 1997-11-18 7/14TOSHIBA TC90A13N/F C output (Ta=25C, Vpp = 5V, Clock frequency 3.579545MHz, 0.5Vp-p, $1=1, VREF1 =3.0V) (fg Components) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT $2=2, $3=2, S4=1, $5=2 Difference of amplitude WIDE BWCW 1 |between 1fs and 1fs -0.5] -0.2) 503496Hz BPF VIN = 1.5Vp-p, Vde =2.5V dB Characteristics $2=2, $3=2, S4=1, $5=2 Difference of amplitude NARROW | BWCN 1 |between 1fse and 1fg - -1.0| -0.5|/ 503496Hz VIN = 1.5Vp-p, Vde = 2.5V . $2=2, $3=2,$4=1, S5=1[ _ _ _ Gain CV 1 VIN= fees 430mVp-p 2.0 0.9 0.6] dB 2=2, $3 =2, oye S$4=1, $5=2 h 1 B Comb Characteristics Comb VIN = 430MVp.p, 3 /f2 30 35 d Vdc =2.5V $2=2, $3=3, S4=1, $5=1 Differential Gain DG 1 |Vin=5 step signal, 0 2 5| % Y = 1401RE = 1.5Vp-p C=40IRE (Fig.2) Differential Phase DP 1 |DG=(Comax - Comin) / 0 2 5 Comax (Fig.3) $2=2, $3=2, $5=2 Vin = 15.734kHz, 1.5Vp-p Output Impedance Zo 1 |Vde=2.5v 250] 400| 700] V1-V2 Zo =_ x 400 V2 V1: $4=1, V2: $4=2 Clock Leak $2=2, $3=2, S4=1, $5=1 L 1 A . 2 V (4fg Components) ck VIN =No input 9-0 0 )mVrms Fundamental Clock Leak $2=2, $3=2, $4=1, S5=1 (f Components) Lsc ' Vin =No input 7 0.3} 1.0 )mVims f1 = 15.734kHz, f2 =3.587412MHz, f3 =3.595279MHz, f4=4.783216MHz PLL CIRCUIT CHARACTERISTICS TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT Pull-in Frequency Range fck 1 3.57} 3.58) 3.59] MHz I Ampili nput Amplitude Vek 1 04} 05) | Vp-p 1997-11-18 8/14TOSHIBA TC90A13N/F TEST CIRCUIT 1 9 a - Qo 2 2 358 8 oO 4 uw Ww S Oo = > > S uw x 5 oO 23 22 19 18 17, 16 15 ) TC9IOAI3N/F v Y 7 8 9 10 14) 3 3 3 < < - uw uw uw | S & L g & X s s + Slo so 5 T BFL = t S we Oo g A 2 ae ] ao S w oc I 3 4 = Ms 5V VIDEO IN 2.5V CLOCK Oscilloscope Spectrum analyzer Vector scope 1997-11-18 9/14TOSHIBA TC90A13N/F Linearity test (Fig.1) 5 Step signal (Fig.2) Cin 3.58MHz (40 IRE) - g] | - 3] = x} te =| S| e > Sy oo cy) g a _ 2. Po 1 +s = z - e} |. 1H 63.5 ys | rm Tt Chroma differential gain (Fig.3) Co MAX Co MIN REFERENCE DATA (Fig.4-a) Definition of vertical edge enhancement INPUT a FULL SCALE =0~255 eH | OUTPUT as re Lt ir (Note) The output signal, to which the vertical edge enhancement component is added, is limited to pedestal level by the pedestal clip circuit. 1997-11-18 10/14TOSHIBA TC90A13N/F (Fig.4-b) Vertical edge enhancement characteristic 50 407 3075 207 107 nn) -104 -20 4 -304 -404 -50 - 300 (Fig.4-c) Vertical edge enhancement characteristic (detail) 100 300 10 84 64 a4 T -10 (Fig.5) Frequency characteristics of chroma output (dB) 0 -107 -207 - 307 -407 -50- Lode Ld - 60 0 nm 4------ Ber ch te ter - 5 f (MHz) The relation between a and b. (refer to Fig.4-a) a: The difference in luminance level is in the enhanced part of the edge. b: The component of vertical edge enhancement that is added to the luminance signal. Both are expressed as digital values. (A) Enhance Value HIGH 777-7" (B) MID ***"* (c) Low (D) Enhance value HIGH (E) MID -- (F) LOW A,B, C : Coring=OFF OD, E, F : Coring=ON Wide band width ---- Narrow band width 1997-11-18 11/14TOSHIBA TC90A13N/F APPLICATION CIRCUIT COUT O g a - 5 5 2 & & o - > > 3 al > Qa > uw E of N _ In 2 QO 23 22 19 18 17 16 15 ) TCOIOOAI3N/F 4 Y 7 11 14 uw uw 3 3 LL S w Felg < o = os S t ln o Oo Q mm uu = = CLOCK z a Oo < @ VIDEO IN xs aT w > 3 y y? 1997-11-18 12/14TOSHIBA TC90A13N/F OUTLINE DRAWING SDIP28-P-400-1.78 Unit : mm 28 15 Ca ra a a ar a ea a ) CYCICILICIPLICICICI CT OTOP OIC 1 14 o~1 5 8.8+0.2 10.16 26.1MAX 25.640.2 | 3.846.3 3.040.3 1.243TYP Weight : 1.7g (Typ.) 1997-11-18 13/14TOSHIBA OUTLINE DRAWING SOP28-P-450-1.27 TOODODg0ggngon 4 8.8+40.2 11.840.3 ) 0.995TYP -43+0.1 5] de OSD BED 1.27 19,0MAX 18.5+0.2 Nw Or 2 #2 STOR TO 8 710.1 gs Weight : 0.8g (Typ.) ECCT T TTR CTTiGe TC90A13N/F Unit : mm (450 mil) 0.15285 1997-11-18 14/14