EXE: L MICROELECTRONICS, ING. XL2817A 2K X 8 Bit Electrically Erasable PROM The XL2817A is a full-featured 2048 an internal Voc sensor which inhib- FEATURES x 8 bit NMOS electrically erasable its write commands when the = 2048 x 8 Bit 5V E2PROM programmable read only memory supply voltage is below 4.0V. (E2PROM) providing completely = Single Supply 5-Volt Operation ponvolatile storage as well as easy ire apple ati ons Tequiring a fast = Internal Address and Data in-circuit writeability. It is remark- ; Latches ably easy to use, operating from a sapabie oF inoyeters modification = Automatic Erase Before Write Single avon A writ supply ore util: The high data access speed makes @ Automatic Write Cycle zing read and write cycle timing the device compatible with high y very similar to that of a static RAM. : Time-Out: 10ms Max. The internally self-timed nonvolatile pertormance systems. ane the ine = On-Chip False Write write cycle latches both address grated reatures oftware ove thea d Protection and data to provide a free system required by other, less elegant, m JEDEC Approved 28-Pin Byte US during the write period. The E2PROMs. The simplicity of direct Wide Memory Pinout XL2817A incorporates an automatic : microprocessor interface ensures . . and transparent byte-erase cycle in - oe m= Compatible with Intel 2817A its byte write operation, completing both design ease and minimal @ 10 Year Data Retention the erase/write cycle in a maximum board space requirements. Typical : applications include robotics, user of 10ms. The READY/BUSY pin : . flags the completion of this erase/ programmable firmware, data log : : ing, security and encryption sys- write cycle so that the system is g freed for other tasks until the tems, remotely reprogrammable XL2817A announces Ready. Ad- machinery, and self-calibrating . ipment. vanced power up/down protection equip designed into the device includes PIN CONFIGURATION BLOCK DIAGRAM __ VW RDY/BUSY }1 28| Vcc ADDRESS BUFFER ROW NC ]2 27| WE Aa Aroe LATONES [| pecover [| 4 Ar ]|3 26] NC Ag |4 25| As As |5 24| Ag Vee Ag |6 23/ NC *y] GH VOLTAG 16,384 BIT vO Aa 17 221 OE veo] NAOVERTENT Genenaton [oO] EPROM BUFFERS _- _ INPUT nw 8 a Ato PROTECTION DATA. Lee 1/09 07 _ _ LATCH en Ao ]10 191 /O7 b>] fea VOo 11 18|- 1/06 | [e) YO, }12 17| I/Os = = VWO2 |13 16] WV/O4 Ea [| er Vss ]14 15| WVO3 CONTROL LOGIC = L ROY/BUSY PIN NAMES Ap-Aio ADDRESS INPUTS VOgl/O, DATA INPUTS/OUTPUTS Ag Ageenn] APORESS BUFFER] 1) COLUMN DECODER CE CHIP ENABLE LATCHES OE OUTPUT ENABLE WE WRITE ENABLE RDY/BUSY READY/BUSY INDICATOR NC NO CONNECT Voc +5V Vss Ground 3-29EXEL XL2817A DEVICE OPERATION Read Cycle Data is read from the XL2817A as simply as it is from a static RAM, with WE high, CE low and OE low. Since the stored charge which defines the bit state is not affected by read cycles, there is no restric- tion on the number of times that the XL2817A may be read. Data access times from the last to be asserted of CE, OE or valid address are specified in the Read Cycle Timing parameter section of this data sheet. The I/O pins remain in a high impedance state whenever OE or CE are high providing a dual line control structure to eliminate bus contention hazards. Write Cycle The XL2817A is designed for excep- tional ease of use, integrating data latches, address latches, a high vol- tage generator, and fully self-timed control logic on-chip so that it writes like a static RAM. Two dis- tinct write cycles are utilized by the XL2817A: one is the write operation performed by the host system and the second is an internal write operation that programs the E2PROM array. In this data sheet the term system write cycle refers to that cycle executed by the sys- tem wherein data is written to the XL2817As internal data latches, while the term nonvolatile write cycle refers to the internal opera- tion which transfers data from these latches into the E7PROM array. During a system write cycle, the address is secured into the internal address latches upon the last falling edge of WE or CE pro- viding that OE is high. The first ris- ing edge of WE or CE locks the data into the data latches (see fig- ures 2 and 3). The nonvolatile write cycle is com- pleted off-line in a fully self-timed operation in two transparent stages. During the first stage, the data then present in the location to be pro- grammed is automatically erased. Concurrent with this, the RDY/ BUSY pin is lowered to Voi, the control inputs are inhibited, and the data pins are brought to their high MODE SELECTION Xx Xx 5V 5V Read And Write Inhibit impedance state. The second stage copies the new data from the inter- nal latches into the appropriate locations in the E2PROM array for nonvolatile storage. Upon comple- tion of this stage RDY/BUSY is returned to Von. The E2PROM memory array is not accessible while the nonvolatile write cycle is in progress. Thus, neither a read nor a system write operation may be accomplished until the nonvolatile write cycle is completed. READY/BUSY Pin The RDY/BUSY pin (pin 1) is a dedicated device status indicator which remains at logic 1 during device operation unless the XL2817A is internally occupied with a non- volatile write cycle. When a write cycle is initiated, RDY/BUSY is brought to a logic 0, returning to a logic 1 when the nonvolatile write cycle is completed. This pin may be conveniently polled for nonvola- tile write cycle status or may be used to initiate an interrupt announc- ing to the controller that the cycle is complete and the device is, once again, available for normal access. The RDY/BUSY output is config- ured as an open-drain driver there- by allowing two or more RDY/ BUSY outputs to be OR-tied. This pin requires an appropriate pull-up resistor for proper operation. The pull-up resistor value for the RDY/ BUSY output may be calculated as follows: Rp = 4.8V/(2.1ma + Ii) where |), = the sum of the input currents of all devices tied to RDY/BUSY. False Write Protection Three mechanisms are designed into the XL2817A to protect the 3-30 Mode Read Power Active Active Active Active Write Write D High Z device from inadvertent write com- mands during power supply transi- tions and system noise periods. These mechanisms eliminate the need for external power up/down protection circuitry. Vec Level Detection A sensor on board the XL2817A monitors the supply voltage level and disables the internal write cir- cuitry whenever Vcc is less than 4.0V. This serves to protect the data integrity while allowing the device to tolerate an erratic control bus during power transitions, brownouts, and blackouts. Noise Protected WE A noise filter designed into the WE input ensures that a write pulse of less than 20ns duration will not activate a write cycle. Write Inhibit Logic. Logical inadvertent write protection is provided to the system by ensur- ing that the application of a logic __ 0 to OF or a logic 1 to CE or WE will inhibit the device's internal write circuitry. Standby Power consumption may be reduced by approximately 55% by deselect- ing the device with a logic 1 ap- plied to CE. In this mode the I/O pins are placed in a high impe- dance state independent of the sig- nals seen by OF and WE. Endurance and Data Retention The XL2817A is designed for appli- cations requiring up to 10,000 re- writes per E7PROM byte and ten years of secure data retention. This means that each byte may be reliably rewritten 104 times without degrading device operation, and that data will remain valid after the last rewrite for at least ten years with or without power applied.EXEL XL2817A eZ ABSOLUTE MAXIMUM RATINGS! Temperature Under Bias . 0.0.0.0... cee eee -65C to +125C Storage Temperature ........ 0... cece cece cette ee eens 65C to + 125C Voltage on any Pin with Respect to Ground? ................... 0.5V to +6V D.C. Output Current... 0... eect tener eee -5mA DC OPERATING CHARACTERISTICS Ta = -55C to +128C, Veo = 5V + 10%, for military (XLM) versions. Limits Test Symbol Parameter Min. Max. Units Conditions Vit (DC) Input Low Voltage (DC) -0.5 0.8 Vv Vit (AC) Input Low Voltage (AC) -0.4 Vv Time = 10ns Vin Input High Voltage 2.0 Voc + 0.5 Vv Vou Output Low Voltage 0.4 Vv lot = 2.1mA Vou Output High Voitage 2.4 v low = ~400uA Vwi Voc Trip Voltage for Write Inhibit 4.0 45 Vv loc Voc Current (Active) 110 mA CE = OF = VU All 1/O's = OPEN Other Inputs = 5.5V Isp Voc Current (Standby) 50 mA CE = Vin, OE = Vit All [/Os = OPEN Other Inputs = 5.5V locw Voc Current (Erase/Write Cycle) 150 mA CE = Vy OE = Vy, WE = LI ti Input Leakage Current 10 BA Vin = 0 to 5.5V lo Output Leakage Current +10 LA Vour = 0 to .5V CAPACITANCE Ta = 25C, f = 1.0 MHz, Voc = 5V Symbol Test Max. Unit Conditions Cvo Input/Output Capacitance 10 pF Vio = OV Cin Input Capacitance 10 pF Vin = OV Notes: 1. Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages higher than the rated maxima. 3. AC conditions of test: tnput Pulse Levels 0.45 to 2.4 Volts Input Rise and Fall Times 20 nsec Timing Reference Levels 0.8V and 2.0V Output Load 1 TTL Gate and C, = 100 pF 4. WE is noise protected. A write pulse of less than 20ns duration will not activate a write cycle. 3-31 ep) panes ao OD 2A wo aed aEXEL XL2817A AC CHARACTERISTICS? TA =-55C to +125C, Voc = 5V + 10%, for military (*XLM) versions. Read Cycle - See Figure 1. XLS2817A- XLS2817A- XLS2817A- 300 350 450 Units Limits Limits Limits Symbol Parameter Min. Max. Min. Max. | Min. Max. toe Chip Enable Access Time 300 350 450 ns taa Address Access Time 300 350 450 ns toe Output Enable Access Time 80 120 150 ns tu Chip Enable to Output in Low Z 10 10 10 ns tyz Chip Disable to Output in High Z 10 80 10 80 10 100 ns touz Output Enable to Output in Low Z 10 10 10 ns touz Output Disable to Output in High Zz 10 80 10 100 10 100 ns ton Output Hold from Address Change 20 20 20 ns ADDRESS x ok x j~ tog | z* + bwe toe OE * < WE Vin wt wy tiz tonz HIGH Z mourns | (on DATA OUT DATA VALID DATA VALID taa Figure 1. Read Cycle 3-32EXEL XL2817A Write Cycle - See Figures 2 and 3. Symbol Parameter Min. Limits Max. Units tnw Nonvolatile Write Time 10 ms tas Address Setup Time 10 ns taH Address Hold Time 125 ns tos Write Setup Time 0 ns tcH Write Hold Time 0 ns tow Chip Enable Pulse Width 150 ns toes Output Enable Setup Time 10 ns toeH Output Enable Hold Time 10 ns twp4 Write Pulse Width 150 ns to Data Latch Time 50 ns tos Data Setup Time 50 ns ton Data Hold Time 10 ns tos Time to Device Busy 120 yns\ tnw ADDRESS RDY/BUSY DATAIN DATA VALID tos b Figure 2. WE Controlled Write Cycle tnw > ag 12) = Ww = ADDRESS WE RDY/BUSY tos DATA IN DATA VALID Figure 3. CE Controlled Write Cycle 3-33EXEL ORDERING INFORMATION Part Number | Access Time (ns) |Temperature Range| Package XLM2817AC-300 300 XLM2817AC-350 350 -55 to +125C CERDIP XLM2817AC-450 450 3-34 XL2817A