SDR SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 Banks
MT48LC16M8A2 – 4 Meg x 8 x 4 Banks
MT48LC8M16A2 – 2 Meg x 16 x 4 Banks
Features
PC100- and PC133-compliant
Fully synchronous; all signals registered on positive
edge of system clock
Internal, pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths (BL): 1, 2, 4, 8, or full
page
Auto precharge, includes concurrent auto precharge
and auto refresh modes
Self refresh modes: Standard and low power
(not available on AT devices)
Auto Refresh
64ms, 4096-cycle refresh (commercial and
industrial)
16ms, 4096-cycle refresh (automotive)
LVTTL-compatible inputs and outputs
Single 3.3V ±0.3V power supply
Options Marking
Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)132M4
16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8
8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16
Write recovery (tWR)
tWR = 2 CLK A2
Options Marking
Plastic package – OCPL2
54-pin TSOP II (400 mil) TG
54-pin TSOP II (400 mil) Pb-free P
60-ball TFBGA (8mm x 16mm) FB1
60-ball TFBGA (8mm x 16mm) Pb-
free
BB1
54-ball VFBGA (x16 only) (8mm x
8mm)
F4
54-ball VFBGA (x16 only) (8mm x
8mm) Pb-free
B4
Timing – cycle time
7.5ns @ CL = 3 (PC133) -753
7.5ns @ CL = 2 (PC133) -7E
6.0ns @ CL = 3 (x16 only) -6A
Self refresh
Standard None
Low power L3
Revision :G/:L
Operating temperature range
Commercial (0˚C to +70˚C) None
Industrial (–40˚C to +85˚C) IT
Automotive (–40˚C to +105˚C) AT1
Notes: 1. Contact Micron for availability.
2. Off-center parting line.
3. Only available on Revision G.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
Clock
Frequency (MHz) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns)
-6A 167 3-3-3 18 18 18
-75 133 3-3-3 20 20 20
-7E 133 2-2-2 15 15 15
128Mb: x4, x8, x16 SDRAM
Features
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Products and specifications discussed herein are subject to change by Micron without notice.
Table 2: Address Table
Parameter 32 Meg x 4 16 Meg x 8 8 Meg x 16
Configuration 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh count 4K 4K 4K
Row addressing 4K A[11:0] 4K A[11:0] 4K A[11:0]
Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0]
Column addressing 2K A[9:0], A11 1K A[9:0] 512 A[8:0]
Table 3: 128Mb SDR Part Numbering
Part Numbers Architecture
MT48LC32M4A2TG 32 Meg x 4
MT48LC32M4A2P 32 Meg x 4
MT48LC16M8A2TG 16 Meg x 8
MT48LC16M8A2P 16 Meg x 8
MT48LC16M8A2FB 16 Meg x 8
MT48LC16M8A2BB 16 Meg x 8
MT48LC8M16A2TG 8 Meg x 16
MT48LC8M16A2P 8 Meg x 16
MT48LC8M16A2B4 8 Meg x 16
MT48LC8M16A2F4 16 Meg x 16
Note: 1. FBGA Device Decoder: www.micron.com/decoder
128Mb: x4, x8, x16 SDRAM
Features
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Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Automotive Temperature .............................................................................................................................. 8
Functional Block Diagrams ............................................................................................................................... 9
Pin and Ball Assignments and Descriptions ..................................................................................................... 12
Package Dimensions ....................................................................................................................................... 16
Temperature and Thermal Impedance ............................................................................................................ 19
Electrical Specifications .................................................................................................................................. 23
Electrical Specifications – IDD Parameters ........................................................................................................ 25
Electrical Specifications – AC Operating Conditions ......................................................................................... 27
Functional Description ................................................................................................................................... 30
Commands .................................................................................................................................................... 31
COMMAND INHIBIT .................................................................................................................................. 31
NO OPERATION (NOP) ............................................................................................................................... 32
LOAD MODE REGISTER (LMR) ................................................................................................................... 32
ACTIVE ...................................................................................................................................................... 32
READ ......................................................................................................................................................... 33
WRITE ....................................................................................................................................................... 34
PRECHARGE .............................................................................................................................................. 35
BURST TERMINATE ................................................................................................................................... 35
REFRESH ................................................................................................................................................... 36
AUTO REFRESH ..................................................................................................................................... 36
SELF REFRESH ....................................................................................................................................... 36
Truth Tables ................................................................................................................................................... 37
Initialization .................................................................................................................................................. 42
Mode Register ................................................................................................................................................ 44
Burst Length .............................................................................................................................................. 46
Burst Type .................................................................................................................................................. 46
CAS Latency ............................................................................................................................................... 48
Operating Mode ......................................................................................................................................... 48
Write Burst Mode ....................................................................................................................................... 48
Bank/Row Activation ...................................................................................................................................... 49
READ Operation ............................................................................................................................................. 50
WRITE Operation ........................................................................................................................................... 59
Burst Read/Single Write .............................................................................................................................. 66
PRECHARGE Operation .................................................................................................................................. 67
Auto Precharge ........................................................................................................................................... 67
AUTO REFRESH Operation ............................................................................................................................. 79
SELF REFRESH Operation ............................................................................................................................... 81
Power-Down .................................................................................................................................................. 83
Clock Suspend ............................................................................................................................................... 84
128Mb: x4, x8, x16 SDRAM
Features
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List of Figures
Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 9
Figure 2: 16 Meg x 8 Functional Block Diagram ............................................................................................... 10
Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 11
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 12
Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 13
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 14
Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 16
Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ...................................................... 17
Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 18
Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21
Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 22
Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22
Figure 13: ACTIVE Command ........................................................................................................................ 32
Figure 14: READ Command ........................................................................................................................... 33
Figure 15: WRITE Command ......................................................................................................................... 34
Figure 16: PRECHARGE Command ................................................................................................................ 35
Figure 17: Initialize and Load Mode Register .................................................................................................. 43
Figure 18: Mode Register Definition ............................................................................................................... 45
Figure 19: CAS Latency .................................................................................................................................. 48
Figure 20: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 49
Figure 21: Consecutive READ Bursts .............................................................................................................. 51
Figure 22: Random READ Accesses ................................................................................................................ 52
Figure 23: READ-to-WRITE ............................................................................................................................ 53
Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54
Figure 25: READ-to-PRECHARGE .................................................................................................................. 54
Figure 26: Terminating a READ Burst ............................................................................................................. 55
Figure 27: Alternating Bank Read Accesses ..................................................................................................... 56
Figure 28: READ Continuous Page Burst ......................................................................................................... 57
Figure 29: READ – DQM Operation ................................................................................................................ 58
Figure 30: WRITE Burst ................................................................................................................................. 59
Figure 31: WRITE-to-WRITE .......................................................................................................................... 60
Figure 32: Random WRITE Cycles .................................................................................................................. 61
Figure 33: WRITE-to-READ ............................................................................................................................ 61
Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 62
Figure 35: Terminating a WRITE Burst ............................................................................................................ 63
Figure 36: Alternating Bank Write Accesses ..................................................................................................... 64
Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 65
Figure 38: WRITE – DQM Operation ............................................................................................................... 66
Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 68
Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69
Figure 41: READ With Auto Precharge ............................................................................................................ 70
Figure 42: READ Without Auto Precharge ....................................................................................................... 71
Figure 43: Single READ With Auto Precharge .................................................................................................. 72
Figure 44: Single READ Without Auto Precharge ............................................................................................. 73
Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74
Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74
Figure 47: WRITE With Auto Precharge ........................................................................................................... 75
Figure 48: WRITE Without Auto Precharge ..................................................................................................... 76
Figure 49: Single WRITE With Auto Precharge ................................................................................................. 77
Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 78
128Mb: x4, x8, x16 SDRAM
Features
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Figure 51: Auto Refresh Mode ........................................................................................................................ 80
Figure 52: Self Refresh Mode .......................................................................................................................... 82
Figure 53: Power-Down Mode ........................................................................................................................ 83
Figure 54: Clock Suspend During WRITE Burst ............................................................................................... 84
Figure 55: Clock Suspend During READ Burst ................................................................................................. 85
Figure 56: Clock Suspend Mode ..................................................................................................................... 86
128Mb: x4, x8, x16 SDRAM
Features
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List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Address Table ..................................................................................................................................... 2
Table 3: 128Mb SDR Part Numbering ............................................................................................................... 2
Table 4: Pin and Ball Descriptions .................................................................................................................. 15
Table 5: Temperature Limits .......................................................................................................................... 19
Table 6: Thermal Impedance Simulated Values ............................................................................................... 20
Table 7: Absolute Maximum Ratings .............................................................................................................. 23
Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 23
Table 9: Capacitance ..................................................................................................................................... 24
Table 10: IDD Specifications and Conditions – Revision G ................................................................................ 25
Table 11: IDD Specifications and Conditions – Revision L ................................................................................. 25
Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 27
Table 13: AC Functional Characteristics ......................................................................................................... 28
Table 14: Truth Table – Commands and DQM Operation ................................................................................. 31
Table 15: Truth Table – Current State Bank n, Command to Bank n .................................................................. 37
Table 16: Truth Table – Current State Bank n, Command to Bank m ................................................................. 39
Table 17: Truth Table – CKE ........................................................................................................................... 41
Table 18: Burst Definition Table ..................................................................................................................... 47
128Mb: x4, x8, x16 SDRAM
Features
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Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Description
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory contain-
ing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchro-
nous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4
bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by
128Mb: x4, x8, x16 SDRAM
Important Notes and Warnings
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1999 Micron Technology, Inc. All rights reserved.
8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank; A[11:0] select the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations, or the full page, with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-
ation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the PRECHARGE cycles and provide seamless, high-speed, ran-
dom-access operation.
The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh
mode is provided, along with a power-saving, power-down mode. All inputs and out-
puts are LVTTL-compatible.
The devices offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks to hide precharge time, and
the capability to randomly change column addresses on each clock cycle during a burst
access.
Automotive Temperature
The automotive temperature (AT) option adheres to the following specifications:
16ms refresh rate
Self refresh not supported
Ambient and case temperature cannot be less than –40°C or greater than +105°C
128Mb: x4, x8, x16 SDRAM
General Description
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1999 Micron Technology, Inc. All rights reserved.
Functional Block Diagrams
Figure 1: 32 Meg x 4 Functional Block Diagram
Data
input
register
Data
output
register
12
RAS#
CAS#
Row-
address
MUX
CLK
CS#
WE#
CKE Control
logic
Column-
address
counter/
latch
Mode register
11
Command
decode
A[11:0],
BA0, BA1
DQM
12
Address
register
14
2048
(x4)
4096
I/O gating
DQM mask logic
read data latch
write drivers
Column
decoder
Bank 0
memory
array
(4096 x 2048 x 4)
Bank 0
row-
address
latch
and
decoder
4096
Sense amplifiers
Bank
control
logic
DQ[3:0]
4
4
4
12
Bank 1
Bank 2Bank 3
12
11
2
11
2
Refresh
counter
128Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
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1999 Micron Technology, Inc. All rights reserved.
Figure 2: 16 Meg x 8 Functional Block Diagram
Data
input
register
Data
output
register
12
RAS#
CAS#
Row-
address
MUX
CLK
CS#
WE#
CKE Control
logic
Column-
address
counter/
latch
Mode register
10
Command
decode
A[11:0,
BA0, BA1
DQM
12
Address
register
14
1024
(x8)
4096
I/O gating
DQM mask logic
read data latch
write drivers
Column
decoder
Bank 0
memory
array
(4096 x 1024 x 8)
Bank 0
row-
address
latch
and
decoder
4096
Sense amplifiers
Bank
control
logic
DQ[7:0]
8
8
8
12
Bank 1
Bank 2
Bank 3
12
10
2
11
2
Refresh
counter
128Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
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Figure 3: 8 Meg x 16 Functional Block Diagram
12
RAS#
CAS#
Row-
address
MUX
CLK
CS#
WE#
CKE Control
logic
Column-
address
counter/
latch
Mode register
9
Command
decode
A[11:0],
BA0, BA1
DQML,
DQMH
12
Address
register
14
512
(x16)
4096
I/O gating
DQM mask logic
read data latch
write drivers
Column
decoder
Bank 0
memory
array
(4096 x 512 x 16)
Bank 0
row-
address
latch
and
decoder
4096
Sense amplifiers
Bank
control
logic
DQ[15:0]
16
16
Data
input
register
Data
output
register
16
12
Bank 1Bank 2Bank 3
12
9
2
2 2
2
Refresh
counter
128Mb: x4, x8, x16 SDRAM
Functional Block Diagrams
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Pin and Ball Assignments and Descriptions
Figure 4: 54-Pin TSOP (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
DQMH
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
x8x16 x16x8 x4x4
DQ0
NC
DQ1
NC
DQ2
NC
DQ3
NC
NC
NC
NC
DQ0
NC
NC
NC
DQ1
NC
NC
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
NC
DQM
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
Notes: 1. A dash (–) indicates x8 and x4 pin function is same as x16 pin function.
2. Package may or may not be assembled with a location notch.
128Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions
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1999 Micron Technology, Inc. All rights reserved.
Figure 5: 60-Ball FBGA (TopView)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
12345678
Depopulated Balls
DQ7 VSS
NC VSSQ
VDDQ DQ6
DQ5 NC
NC VSSQ
VDDQ DQ4
NC NC
NC VSS
NC DQM
NC CK
NC CKE
A11 A9
A8 A7
A6 A5
A4 VSS
DQ0
VDDQ NC
DQ1 VSSQ
NC DQ2
NC
DQ3
NC NC
NC
WE# CAS#
RAS# NC
NC CS#
BA1 BA0
A0 A10
A2 A1
VDD A3
VDDQ
VSSQ
VDDQ
VDD
Note: 1. The balls at A4, A5, and A6 are not in the physical package. They are included in the
drawing to illustrate that rows 4, 5, and 6 exist but contain no balls.
128Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions
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1999 Micron Technology, Inc. All rights reserved.
Figure 6: 54-Ball VFBGA (Top View)
A
B
C
D
E
F
G
H
J
12345678
Top View
(Ball Down)
VSS
DQ14
DQ12
DQ10
DQ8
DQMH
NC/A12
A8
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VSSQ
VSSQ
VSSQ
VDDQ
VDDQ VDD
VDDQ
VDDQ
VSS
VSS VDD
VDD
CKE
A9
A6
A4
CAS#
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
DQML
RAS#
BA1
A1
A2
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
9
Note: 1. The balls at A4, A5, and A6 are not in the physical package. They are included in the
drawing to illustrate that rows 4, 5, and 6 exist but contain no balls.
128Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions
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1999 Micron Technology, Inc. All rights reserved.
Table 4: Pin and Ball Descriptions
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides precharge power-down and SELF REFRESH operation (all banks idle), active
power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro-
gress). CKE is synchronous except after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same mode. The input buffers, in-
cluding CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de-
coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already
in progress will continue, and DQM operation will retain its DQ mask capability while CS# is
HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid-
ered part of the command code.
CAS#, RAS#,
WE#
Input Command inputs: CAS#, RAS#, and WE# (along with CS#) define the command being en-
tered.
x4, x8:
DQM
x16:
DQML, DQMH
Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are High-Z (two-clock latency) during a READ cycle. On the x4 and x8, DQML
(pin 15) is NC; DQMH is DQM. On the x16, DQML corresponds to DQ[7:0] and DQMH corre-
sponds to DQ[15:8]. DQML and DQMH are considered same-state when referenced as DQM.
BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied.
A[11:0] Input Address inputs: A[11:0] are sampled during the ACTIVE command (row address A[11:0]) and
READ or WRITE command (column address A[9:0] and A11 for x4; A[9:0] for x8; A[8:0] for x16;
with A10 defining auto precharge) to select one location out of the memory array in the re-
spective bank. A10 is sampled during a PRECHARGE command to determine whether all
banks are to be precharged (A10 HIGH) or bank selected by BA[1:0] (A10 LOW). The address
inputs also provide the op-code during a LOAD MODE REGISTER command.
x16:
DQ[15:0]
I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51 are NC for x8; and
pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NC for x4).
x8:
DQ[7:0]
I/O Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4 TSOP; balls A8, D8, D1,
and A1 are NC for x4 FBGA).
x4:
DQ[3:0]
I/O Data input/output: Data bus for x4.
VDDQ Supply DQ power: Isolated DQ power to the die for improved noise immunity.
VSSQ Supply DQ ground: Isolated DQ ground to the die for improved noise immunity.
VDD Supply Power supply: 3.3V ±0.3V.
VSS Supply Ground.
NC No connect: These should be left unconnected. For x4 and x8 parts, G1 is a no connect; it is
A12 for 256Mb and 512Mb devices.
128Mb: x4, x8, x16 SDRAM
Pin and Ball Assignments and Descriptions
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Package Dimensions
Figure 7: 54-Pin Plastic TSOP (400 mil)
See Detail A
0.10 +0.10
-0.05
0.15 +0.03
-0.02
2X R 1.00
2X R 0.75
0.80 TYP
(for reference only)
2X 0.71
0.50 ±0.10
Pin #1 ID
Detail A
22.22 ±0.08
10.16 ±0.08
11.76 ±0.20
0.375 ±0.075 TYP
1.2 MAX
0.25
0.80
2X 0.10
2.80 Gage plane
Plated lead finish: 90% Sn, 10% Pb, or 100% Sn
Plastic package material: Epoxy novolac
Package width and length do not include
mold protrusion. Allowable protrusion is
0.25 per side.
0.10
Notes: 1. All dimensions are in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. 2X means the notch is present in two locations (both ends of the device).
4. Package may or may not be assembled with a location notch.
128Mb: x4, x8, x16 SDRAM
Package Dimensions
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1999 Micron Technology, Inc. All rights reserved.
Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB
Ball A1 ID
1.1 ±0.1
8 ±0.1
Ball A1 ID
60X Ø0.45
Dimensions apply
to solder balls
post-reflow on Ø0.33
NSMD ball pads.
0.8 TYP
11.2 CTR
16 ±0.1
0.12 A
A
Seating
plane
5.6 CTR
0.8 TYP
0.25 MIN
8 7 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes: 1. All dimensions are in millimeters.
2. Recommended pad size for PCB is 0.33mm ±0.025mm.
3. Topside part-marking decoder is available at www.micron.com/decoder.
128Mb: x4, x8, x16 SDRAM
Package Dimensions
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1999 Micron Technology, Inc. All rights reserved.
Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4
Ball A1 ID
0.65 ±0.05
Seating plane
0.12 C
C
1.00 MAX
Ball A9
0.80
TYP
0.80 TYP
3.20
6.40
8.00 ±0.10
4.00 ±0.05
Solder ball
diameter refers
to post reflow
condition. The pre-
reflow diameter
is 0.42.
54X Ø0.45 ±0.05
Solder ball material:
62% Sn, 36% Pb, 2% Ag or
96.5% Sn, 3% Ag, 0.5% Cu
Solder mask defined ball pads:
Ø0.40
Mold compound: Epoxy novolac
Substrate material: Plastic laminate
6.40
3.20
4.00 ±0.05
8.00 ±0.10
C
L
C
L
Ball A1 ID
Ball A1
Notes: 1. All dimensions are in millimeters.
2. Recommended pad size for PCB is 0.40mm SMD.
3. Topside part-marking decoder is available at www.micron.com/decoder.
128Mb: x4, x8, x16 SDRAM
Package Dimensions
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1999 Micron Technology, Inc. All rights reserved.
Temperature and Thermal Impedance
It is imperative that the SDRAM device’s temperature specifications, shown in Temper-
ature Limits below, be maintained to ensure the junction temperature is in the proper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly. The
thermal impedances are listed in Thermal Impedance Simulated Values for the applica-
ble die revision and packages being made available. These thermal impedance values
vary according to the density, package, and particular design used for each device.
Incorrectly using thermal impedances can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications” prior to using the thermal impedan-
ces listed in Thermal Impedance Simulated Values. To ensure the compatibility of cur-
rent and future designs, contact Micron Applications Engineering to confirm thermal
impedance values.
The SDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature
is too high, use of forced air and/or heat sinks may be required to satisfy the case tem-
perature specifications.
Table 5: Temperature Limits
Parameter Symbol Min Max Unit Notes
Operating case temperature Commercial TC0 80 °C 1, 2, 3, 4
Industrial –40 90
Automotive –40 105
Junction temperature Commercial TJ085°C3
Industrial –40 95
Automotive –40 110
Ambient temperature Commercial TA0 70 °C 3, 5
Industrial –40 85
Automotive –40 105
Peak reflow temperature TPEAK 260 °C
Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the
top side of the device, as shown in Figure 10 (page 21), Figure 11 (page 22), and Fig-
ure 12 (page 22).
2. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
3. All temperature specifications must be satisfied.
4. The case temperature should be measured by gluing a thermocouple to the top-center
of the component. This should be done with a 1mm bead of conductive epoxy, as de-
fined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple
bead is touching the case.
5. Operating ambient temperature surrounding the package.
128Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance
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Table 6: Thermal Impedance Simulated Values
Die
Revision Package Substrate
ˆ
ˆ
JA (°C/W)
Airflow =
0m/s
ˆ
JA (°C/W)
Airflow =
1m/s
ˆ
JA (°C/W)
Airflow =
2m/s
ˆ
JB (°C/W)
ˆ
JC (°C/W)
G 54-pin TSOP
(TG, P)
Low Con-
ductivity
86.2 67.8 62 46.9 11.3
High Con-
ductivity
58.9 50.7 47.6 41.5
54-ball VFBGA
(B4, F4)
Low Con-
ductivity
72.1 57.3 50.6 36 4.1
High Con-
ductivity
54.5 46.6 42.8 35.5
60-ball FBGA
(BB, FB)
Low Con-
ductivity
70.9 56.8 50.3 36.3 1.9
High Con-
ductivity
54.6 47.3 43.5 36.3
L 54-pin TSOP
(TG, P)
Low Con-
ductivity
122.3 105.6 98.1 89.5 20.7
High Con-
ductivity
101.9 93.5 88.8 87.6
54-ball VFBGA
(B4, F4)
Low Con-
ductivity
96.9 81.9 81.9 69.5 11.5
High Con-
ductivity
74.0 66.3 62.7 60.7
60-ball FBGA
(BB, FB)
Low Con-
ductivity
68.8 55.9 51.1 42.1 10.9
High Con-
ductivity
47.9 42.0 39.9 34.9
Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications
Engineering to confirm thermal impedance values.
2. Thermal resistance data is sampled from multiple lots, and the values should be viewed
as typical.
3. These are estimates; actual results may vary.
128Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance
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1999 Micron Technology, Inc. All rights reserved.
Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View)
22.22mm
11.11mm
Test point
10.16mm
5.08mm
Note: 1. Package may or may not be assembled with a location notch.
128Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance
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1999 Micron Technology, Inc. All rights reserved.
Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View)
Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View)
Test point
8.00mm
16.00mm
4.00mm
8.00mm
128Mb: x4, x8, x16 SDRAM
Temperature and Thermal Impedance
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128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1999 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Voltage/Temperature Symbol Min Max Unit
Voltage on VDD/VDDQ supply relative to VSS VDD/VDDQ –1 4.6 V
Voltage on inputs, NC, or I/O balls relative to VSS VIN –1 4.6
Operating temperature: Commercial TA070°C
Industrial TA–40 85
Storage temperature (plastic) TSTG –55 150 °C
Power dissipation 1 W
Table 8: DC Electrical Characteristics and Operating Conditions
Notes 1–3 apply to all parameters and conditions; VDD/VDDQ = +3.3V ±0.3V
Parameter/Condition Symbol Min Max Unit Notes
Supply voltage VDD, VDDQ 3 3.6 V
Input high voltage: Logic 1; All inputs VIH 2V
DD + 0.3 V 4
Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 4
Output high voltage: IOUT = –4mA VOH 2.4 V
Output low voltage: IOUT = 4mA VOL 0.4 V
Input leakage current:
Any input 0V VIN VDD (All other balls not under test = 0V)
IL–5 5 ˩A
Output leakage current: DQ are disabled; 0V VOUT VDDQ IOZ –5 5 ˩A
Notes: 1. All voltages referenced to VSS.
2. Minimum specifications are used only to indicate the cycle time at which proper opera-
tion over the full temperature range is ensured:
0°C TA +70°C (commercial)
–40°C TA +85°C (industrial)
–40°C TA +105°C (automotive)
3. An initial pause of 100˩s is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse
width 3ns.
128Mb: x4, x8, x16 SDRAM
Electrical Specifications
PDF: 09005aef8091e66d
128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice.
1999 Micron Technology, Inc. All rights reserved.