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FEATURES
APPLICATIONS
DESCRIPTION
APPLICATION CIRCUIT
_
+
IN−
IN+
PWM H−
Bridge
VO−
VO+
Internal
Oscillator
ToBattery
VDD
GND
Bias
Circuitry
Differential
Input
TPA2032D1
SHUTDOWN
A1 A2 A3
B1 B2 B3
C1 C2 C3
IN+ GND VO−
VDD PVDD PGND
IN− SHUTDWN VO+
1,4 mm
9-BALLWAFERCHIPSCALE,YZFPACKAGE,
(TOPVIEWOFPCB)
Note:PinA1ismarkedwitha “0” .
1,55mm
1,4mm
1,55mm
TPA
203xD1
0402
~
2,5
mm
~1,7mm
CS
CS
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
2.75-W FIXED GAIN MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER
•Wafer Chip Scale Packaging (WCSP)•Maximize Battery Life and Minimize Heat – NanoFree™ Lead-Free (Pb-Free: YZF)– 0.5- µA Shutdown Current– 3.0-mA Quiescent Current
•Ideal for Wireless Handsets, PDAs, and other– High Efficiency Class-D
mobile devices•88% at 400mW at 8 Ω•80% at 100mW at 8 Ω•Three Fixed Gain Versions
The TPA2032D1 (2V/V gain), TPA2033D1 (3V/Vgain), and TPA2034D1 (4V/V gain) are 2.75-W high– TPA2032D1 has a gain of 2 V/V (6dB)
efficiency filter-free class-D audio power amplifiers,– TPA2033D1 has a gain of 3 V/V (9.5dB)
each in an approximately 1.5-mm ×1.5-mm wafer– TPA2034D1 has a gain of 4 V/V (12dB)
chip scale package (WCSP) that requires only one•Only One External Component Required
external component. The pinout is the same as theTPA2010D1 except that the external gain setting– Internal Matched Input Gain and Feedback
input resistors required by the TPA2010D1 areResistors for Excellent PSRR and CMRR
integrated into the fixed gain TPA203xD1 family.– Optimized PWM Output Stage Eliminates
Features like –75dB PSRR and improvedLC Output Filter
RF-rectification immunity with a very small PCB– PSRR (–75 dB) and Wide Supply Voltage
footprint (WCSP amplifier plus single decoupling(2.5 V to 5.5 V) Eliminates Need for a
cap) make the TPA203xD1 family ideal for wirelessDedicated Voltage Regulator
handsets. A fast start-up time of 3.2 ms with minimalpop makes the TPA203xD1 family ideal for PDA– Fully Differential Design Reduces RF
applications.Rectification and Eliminates BypassCapacitor
In wireless handsets, the earpiece, speaker phone,– CMRR (–69 dB)Eliminates Two Input
and melody ringer can each be driven by aTPA203xD1. The TPA203xD1 family has a lowCoupling Capacitors
27- µV noise floor, A-weighted.•Thermal and Short-Circuit Protection•Pinout Very Similar to TPA2010D1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PACKAGE DISSIPATION RATINGS
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
T
A
PACKAGE PART NUMBER SYMBOL
–40 °C to 85 °C Wafer chip scale packaging – Lead free (YZF) TPA2032D1YZF
(1)
BPX–40 °C to 85 °C Wafer chip scale packaging – Lead free (YZF) TPA2033D1YZF
(1)
BPY–40 °C to 85 °C Wafer chip scale packaging – Lead free (YZF) TPA2034D1YZF
(1)
BPZ
(1) The YZF package is only available taped and reeled. To order add the suffix Rto the end of the part number for a reel of 3000, or addthe suffix Tto the end of the part number for a reel of 250 (e.g. TPA2032D1YZFR).
over operating free-air temperature range unless otherwise noted
(1)
TPA2032D1, TPA2033D1,
TPA2034D1
In active mode –0.3 V to 6 VV
DD
Supply voltage
In SHUTDOWN mode –0.3 V to 7 VV
I
Input voltage –0.3 V to V
DD
+ 0.3 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature –40 °C to 85 °CT
J
Operating junction temperature –40 °C to 125 °CT
stg
Storage temperature –65 °C to 150 °CESD Electro-Static Discharge Tolerance - Human Body Model (HBM) for all pins
(2)
2KV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The output pins Vo– and Vo+ are tolerant to 1.5KV HBM ESD
MIN NOM MAX UNIT
V
DD
Supply voltage 2.5 5.5 VV
IH
High-level input voltage SHUTDOWN 1.3 V
DD
VV
IL
Low-level input voltage SHUTDOWN 0 0.35 VV
IC
Common mode input voltage range V
DD
= 2.5 V, 5.5 V 0.5 V
DD
–0.8 VT
A
Operating free-air temperature –40 85 °C
DERATING FACTOR T
A
≤25 °C T
A
= 70 °C T
A
= 85 °CPACKAGE
(1 / θ
JA
) POWER RATING POWER RATING POWER RATING
YZF 4.8 mW/ °C
(1)
480 mW 264 mW 192 mWYZF 7.5 mW/ °C
(2)
750 mW 412 mW 300 mW
(1) Derating factor measured with JEDEC Low-K board; 1S0P - One signal layer and zero plane layers.(2) Derating factor measured with JEDEC High K board; 1S2P - One signal layer and two plane layers.Please see JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for usingpackage thermal information.Please see JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm.
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ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
T
A
= 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPA2032D1 5 25Output offset voltage|V
OS
| Inputs AC grounded, V
DD
= 2.5 V to 5.5 V TPA2033D1 5 25 mV(measured differentially)
TPA2034D1 5 25PSRR Power supply rejection ratio V
DD
= 2.5 V to 5.5 V –75 -61 dBV
DD
= 2.5 V –69 -52CMRR Common mode rejection ratio V
IC
= 0.5 V to (V
DD
–0.8 V) V
DD
= 3.6 V – 69 -52 dBV
DD
= 5.5 V –69 -52|I
IH
| High-level input current V
DD
= 5.5 V, V
I
= 5.8 V 50 µA|I
IL
| Low-level input current V
DD
= 5.5 V, V
I
= –0.3 V 5 µAV
DD
= 5.5 V, no load 4 5.7I
(Q)
Quiescent current V
DD
= 3.6 V, no load 3 mAV
DD
= 2.5 V, no load 2.2 3.7I
(SD)
Shutdown current V
( SHUTDOWN)
= 0.35 V, V
DD
= 2.5 V to 5.5 V 0.5 0.8 µAV
DD
= 2.5 V 550Static drain-source on-stater
DS(on)
V
DD
= 3.6 V 420 m Ωresistance
V
DD
= 5.0 V 350Output impedance in
V
( SHUTDOWN)
<= 0.35 V 2 k ΩSHUTDOWN
f
(sw)
Switching frequency V
DD
= 2.5 V to 5.5 V 240 300 400 kHzTPA2032D1 5.5 6 6.5Gain V
DD
= 2.5 V to 5.5 V TPA2033D1 9.0 9.5 10.0 dBTPA2034D1 11.5 12 12.5Resistance of internal pulldownR
PD
resistor from shutdown pin to 300 k ΩGND
T
A
= 25 °C, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V 2.75R
L
= 4 Ω, THD + N = 10%, f = 1 kHz V
DD
= 3.6 V 1.35 WV
DD
= 2.5 V 0.59V
DD
= 5 V 2.25R
L
= 4 Ω, THD + N = 1%, f = 1 kHz V
DD
= 3.6 V 1.12 WV
DD
= 2.5 V 0.48P
O
Output power
V
DD
= 5 V 1.68R
L
= 8 Ω, THD + N = 10%, f = 1 kHz V
DD
= 3.6 V 0.85 WV
DD
= 2.5 V 0.38V
DD
= 5 V 1.37R
L
= 8 Ω, THD + N = 1%, f = 1 kHz V
DD
= 3.6 V 0.68 WV
DD
= 2.5 V 0.31V
DD
= 5 V, P
O
= 1 W, R
L
= 8 Ω, f = 1 kHz 0.18%THD+ Total harmonic distortion plus
V
DD
= 3.6 V, P
O
= 0.5 W, R
L
= 8 Ω, f = 1 kHz 0.11%N noise
V
DD
= 2.5 V, P
O
= 200 mW, R
L
= 8 Ω, f = 1 kHz 0.10%V
DD
= 3.6 V, Inputs AC grounded f = 217 Hz,k
SVR
Supply ripple rejection ratio –73 dBwith C
I
= 1 µF V
(RIPPLE)
= 200 mV
pp
SNR Signal-to-noise ratio V
DD
= 5 V, P
O
= 1 W, R
L
= 8 Ω, A weighted noise 100 dB
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FUNCTIONAL BLOCK DIAGRAM
Input
Buffer SC
300KΩ
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
OPERATING CHARACTERISTICS (continued)T
A
= 25 °C, R
L
= 8 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
No weighting 35V
DD
= 3.6 V, f = 20 Hz to 20 kHz,V
n
Output voltage noise µV
RMSInputs AC grounded with C
i
= 1 µF
A weighting 27V
DD
= 3.6 V, V
IC
= 1.0 V
pp
, V
Cm
= 1.8CMRR Common mode rejection ratio f = 217 Hz –69 dBV
A
V
= 2 V/V 30.2R
I
Input impedance A
V
= 3 V/V 22.8 k ΩA
V
= 4 V/V 18.5Start-up time from shutdown V
DD
= 3.6 V 3.2 ms
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME YZF
IN– C1 I Negative differential audio inputIN+ A1 I Positive differential audio inputV
O-
A3 O Negative BTL audio outputV
O+
C3 O Positive BTL audio outputAnalog ground terminal. Must be connected to same potential as PGND using a direct connectionGND A2 I
to a single point ground.High-current Analog ground terminal. Must be connected to same potential as GND using a directPGND B3
connection to a single point ground.V
DD
B1 I Power supply terminal. Must be connected to same power supply as PV
DD
using a directconnection. Voltage must be within values listed in Recommended Operating Conditions table.High-current Power supply terminal. Must be connected to same power supply as V
DD
using aPV
DD
B2 I direct connection. Voltage must be within values listed in Recommended Operating Conditionstable.SHUTDOWN C2 I Shutdown terminal. When terminal is low the device is put into Shutdown mode.
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TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
TEST SET-UP FOR GRAPHS
TPA2032D1
IN+
IN −
OUT+
OUT −
VDD GND
CI
CI
Measurement
Output
+
−
1mF
+
−
VDD
Load
30kHz
Low Pass
Filter
Measurement
Input
+
−
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
FIGURE
Efficiency vs Output power 1, 2P
D
Power dissipation vs Output power 3, 4Supply current vs Output power 5, 6I
DD
Supply current vs Supply voltage 7I
(SD)
Shutdown current vs Shutdown voltage 8vs Load resistance 9, 10P
O
Output power
vs Supply voltage 11vs Output power 12, 13THD+N Total harmonic distortion plus noise vs Frequency 14, 15, 16, 17vs Common-mode input voltage 1819, 20, 21, 22, 23, 24, 25,K
SVR
Supply voltage rejection ratio vs Frequency
26, 27vs Time 28GSM power supply rejection
vs Frequency 29K
SVR
Supply voltage rejection ratio vs Common-mode input voltage 30, 31, 32vs Frequency 33CMRR Common-mode rejection ratio
vs Common-mode input voltage 34
(1) C
I
was shorted for any common-mode input voltage measurement. All other measurements were taken with a 1- µFC
I
(unless otherwise noted).(2) A 33- µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.(3) The 30-kHz low-pass filter is required, even if the analyzer has an internal low-pass filter. An RC low-pass filter(100 Ω, 47-nF) is used on each output for the data sheet graphs.
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0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.5 1 1.5 2 2.5 3
P -OutputPower-W
O
P -PowerDissipation-W
D
V =5V,R =4
DD L W
Class AB4 W
Class AB8 W
V =5V,R =8
DD L W
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
P -OutputPower-W
O
Efficiency-%
R =8
LW, 33 μH
V =5V
DD
V =2.5V
DD
V =3.6V
DD
Class AB
0
10
20
30
40
50
60
70
80
90
00.5 11.5 2 2.5
P -OutputPower-W
O
Efficiency-%
V =2.5V
DD
V =3.6V
DD
V =5V
DD
Class AB
R =4
LW, 33 μH
650
600
550
500
450
400
350
300
250
200
150
100
0
V =3.6V
DD
V =2.5V
DD
V =5V
DD
0 0.5 1 1.5 32.52
P -OutputPower-W
O
I -SupplyCurrent-mA
DD
R =4 ,33 μH
LW
50
360
320
280
240
200
160
120
80
40
0
V =3.6V
DD
V =2.5V
DD
V =5V
DD
P -OutputPower-W
O
I -SupplyCurrent-mA
DD
R =8 ,33 μH
LW
0 0.25 0.5 0.75 1 1.25 1.5 1.75
3.6
3.2
2.8
2.4
2
1.6
1.2
0.4
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
V =2.5V
DD
V =5V
DD
V =3.6V
DD
I -SupplyCurrent-mA
DD
ShutdownVoltage-V
R =NoLoad
L
0.8
P -OutputPower-W
O
0
0.5
1
1.5
2
2.5
3
3.5
4 9 14 19 24 29
R -LoadResistance-
LW
V =3.6V,10%
DD
V =2.5V,10%
DD
V =5V,10%
DD
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
EFFICIENCY EFFICIENCY POWER DISSIPATIONvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 1. Figure 2. Figure 3.
POWER DISSIPATION SUPPLY CURRENT SUPPLY CURRENTvs vs vsOUTPUT POWER OUTPUT POWER OUTPUT POWER
Figure 4. Figure 5. Figure 6.
SUPPLY CURRENT SHUTDOWN CURRENT OUTPUT POWERvs vs vsSUPPLY VOLTAGE SHUTDOWN VOLTAGE LOAD RESISTANCE
Figure 7. Figure 8. Figure 9.
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20
0.05
0.1
1
10
310m 100m 1
P -OutputPower-W
O
THD+N-TotalHarmonicDistortion+Noise-%
V =5V
DD
V =2.5V
DD
V =3V
DD
V =3.6V
DD
R =4
LW
0
0.5
1
1.5
2
2.5
3
2.5 3 3.5 4 4.5 5
V -SupplyVoltage-V
DD
4 THD+N=1%W
4 THD+N=10%W
8 THD+N=1%W
8 THD+N=10%W
P-OutputPower-W
O
0
0.5
1
1.5
2
2.5
4 9 14 19 24 29
R -LoadResistance-
LW
V =2.5V,1%
DD
V =3.6V,1%
DD
V =5V,1%
DD
P-OutputPower-W
O
20
0.05
0.1
1
210m 100m 1
P -OutputPower-W
O
THD+N-TotalHarmonicDistortion+Noise-%
V =5V
DD
V =2.5V
DD
V =3V
DD
V =3.6V
DD
R =8
LW
10
1
0.01
0.1
f-Frequency-Hz
20k20 100 1k 10k
P =500mW
O
P =25mW
O
P =125mW
O
THD+N-TotalHarmonicDistortion+Noise-%
RL=8
V =3.6V
W
DD
1
0.01
0.1
f-Frequency-Hz
20k20 100 1k 10k
THD+N-TotalHarmonicDistortion+Noise-%
P =1W
O
R =8
V =5V
L
DD
W
P =50mW
O
P =250mW
O
1
0.01
0.1
f-Frequency-Hz
20k20 100 1k 10k
V =2.5V
DD
V =5V
DD
V =4V
DD
V =3.6V
DD
V =3V
DD
THD+N-TotalHarmonicDistortion+Noise-%
R =4
LW
1
0.005
0.01
0.1
f-Frequency-Hz
20k20 100 1k 10k
P =200mW
O
P =15mW
O
P =75mW
O
THD+N-TotalHarmonicDistortion+Noise-%
R =8
V =2.5V
L
DD
W
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
TOTAL HARMONIC DISTORTION +OUTPUT POWER OUTPUT POWER NOISEvs vs vsLOAD RESISTANCE SUPPLY VOLTAGE OUTPUT POWER
Figure 10. Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +NOISE NOISE NOISEvs vs vsOUTPUT POWER FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION + TOTAL HARMONIC DISTORTION +NOISE NOISE NOISEvs vs vsFREQUENCY FREQUENCY COMMON MODE INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
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-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
10k
Inputsac-grounded,
C =1 F,
R =8 ,
Gain=2V/V
I
L
m
W
V =5V
DD
V =2.5V
DD
V =3.6V
DD
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
V =2.5V
DD
V =2.7V
DD
V =3.6V
DD
V =5V
DD
SupplyRippleRejectionRatio-dB
Inputsac-grounded,
C =1 F,
R =8 ,
Gain=3V/V
I
L
m
W
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =2.5V
DD
V =2.7V
DD
V =3.6V
DD
Inputsac-grounded,
C =1 F,
R =8 ,
Gain=4V/V
I
L
m
W
V =5V
DD
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =3.6V
DD
V =2.5V
DD
V =5V
DD
Inputsac-grounded,
C =1 F,
R =4 ,
Gain=2V/V
I
L
m
W
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =2.7V
DD
V =5V
DD
V =3.6V
DD
Inputsac-grounded,
C =1 F,
R =4 ,
Gain=4V/V
I
L
m
W
V =2.5V
DD
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =3.6V
DD
V =2.5V
DD
V =2.7V
DD
V =5V
DD
InputsFloating,
R =8 ,
Gain=2V/V
LW
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =2.5V
DD
V =2.7V
DD
V =3.6V
DD
V =5V
DD
InputsFloating,
R =8 ,
Gain=3V/V
LW
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1k 10k 100k
f-Frequency-Hz
SupplyRippleRejectionRatio-dB
V =2.5V
DD
V =2.7V
DD
V =3.6V
DD
V =5V
DD
InputsFloating,
R =8 ,
Gain=4V/V
LW
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIOvs vs vsFREQUENCY - TPA2032D1 FREQUENCY - TPA2033D1 FREQUENCY - TPA2034D1
Figure 19. Figure 20. Figure 21.
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIOvs vs vsFREQUENCY- TPA2032D1 FREQUENCY- TPA2033D1 FREQUENCY- TPA2034D1
Figure 22. Figure 23. Figure 24.
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIOvs vs vsFREQUENCY - TPA2032D1 FREQUENCY - TPA2033D1 FREQUENCY - TPA2034D1
Figure 25. Figure 26. Figure 27.
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V
200mV/div
DD
V
20mV/div
OUT
t-Time-2mS/div
0
-140
-120
-100
-80
-60
-40
-20
02k
200 400 600 800 1k 1.2k 1.4k 1.6k1.8k
f-Frequency-Hz
V -SupplyVoltage-dBV
DD
V -OutputVoltage-dBV
O
V ShowninFigure22
C =1 F,
Inputsac-Grounded
DD
Im
-150
-130
-110
-90
-70
-50
-30
10
-10
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DCCommon-ModeVoltage-V
SupplyRippleRejectionRatio-dB
V =2.5V
DD V =3.6V
DD
V =5V
DD
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DCCommon-ModeVoltage-V
SupplyRippleRejectionRatio-dB
V =3.6V
DD
V =5V
DD
V =2.5V
DD
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DCCommon-ModeVoltage-V
SupplyRippleRejectionRatio-dB
V =2.5V
DD
V =3.6V
DD
V =5V
DD
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V -Common-ModeInputVoltage-V
IC
V =2.5V
DD
V =5V
DD
CMRR-Common-ModeRejectionRatio-dB
V =3.6V
DD
-85
-80
-75
-70
-65
-60
10 100 1k 10k 100k
f-Frequency-Hz
CMRR-CommonModeRejectionRatio-dB
V =3.6V,
V =1Vpp,
R =8
DD
IC
LW
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
GSM POWER SUPPLY REJECTION GSM POWER SUPPLY REJECTIONvs vsTIME FREQUENCY
Figure 28. Figure 29.
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIOvs vs vsDC COMMON MODE VOLTAGE - DC COMMON MODE VOLTAGE - DC COMMON MODE VOLTAGE -TPA2032D1 TPA2033D1 TPA2034D1
Figure 30. Figure 31. Figure 32.
COMMON-MODE REJECTION COMMON-MODE REJECTIONRATIO RATIOvs vsFREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 33. Figure 34.
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
Advantages of Fully Differential Amplifiers
COMPONENT SELECTION
Decoupling Capacitor (C
S
)
Input Capacitors (C
I
)
fc+1
ǒ2pRICIǓ
(1)
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
The TPA2032D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifierconsists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that theamplifier outputs a differential voltage on the output that is equal to the differential input times the gain. Thecommon-mode feedback ensures that the common-mode voltage at the output is biased around V
DD
/2regardless of the common-mode voltage at the input. The fully differential TPA2032D1 can still be used with asingle-ended input; however, the TPA2032D1 should be used with differential inputs when in a noisyenvironment, like a wireless handset, to ensure maximum noise rejection.
•Input-coupling capacitors not required:– The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply. The inputs ofthe TPA2032D1 can be biased anywhere within the common mode input voltage range listed in theRecommended Operating Conditions table. If the inputs are biased outside of that range, input-couplingcapacitors are required.•Midsupply bypass capacitor, C
(BYPASS)
, not required:– The fully differential amplifier does not require a bypass capacitor. Any shift in the midsupply affects bothpositive and negative channels equally and cancels at the differential output.•Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. Thetransmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signalbetter than the typical audio amplifier.
Figure 35 shows the TPA2032D1 typical schematic with differential inputs, while Figure 36 shows theTPA2032D1 with differential inputs and input capacitors. Figure 37 shows the TPA2032D1 with a single-endedinput.
The TPA2032D1 is a high-performance class-D audio amplifier that requires adequate power supply decouplingto ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically1µF, placed as close as possible to the device V
DD
lead works best. Placing this decoupling capacitor close tothe TPA2032D1 is very important for the efficiency of the class-D amplifier, because any resistance orinductance in the trace between the device and the capacitor can cause a loss in efficiency. For filteringlower-frequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would alsohelp, but it is not required in most applications because of the high PSRR of this device. Typically, the smallerthe capacitor's case size, the lower the inductance and the closer it can be placed to the TPA2032D1.
The TPA2032D1 does not require input coupling capacitors if the design uses a differential source that is biasedwithin the common-mode input voltage range. That voltage range is listed in the Recommended OperatingConditions table. If the input signal is not biased within the recommended common-mode input range, such as inneeding to use the input as a high pass filter, shown in Figure 36 , or if using a single-ended source, shown inFigure 37 , input coupling capacitors are required. The same value capacitors should be used on both IN+ andIN– for best pop performance.
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)performance of the circuit. Speaker response may also be taken into consideration when setting the cornerfrequency using input capacitors.
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CI+1
ǒ2pRIfcǓ
(2)
_
+
IN−
IN+
PWM H−
Bridge
VO−
VO+
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
Differential
Input
TPA2032D1
Filter-Free Class D
SHUTDOWN
_
+
IN−
IN+
PWM H−
Bridge
VO−
VO+
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
Differential
Input
TPA2032D1
Filter-Free Class D
SHUTDOWN
CI
CI
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
APPLICATION INFORMATION (continued)Equation 2 is reconfigured to solve for the input coupling capacitance.
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF or larger).
Figure 35. Typical TPA2032D1 Application Schematic With Differential Input for a Wireless Phone
Figure 36. TPA2032D1 Application Schematic With Differential Input and Input Capacitors
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_
+
IN−
IN+
PWM H−
Bridge
VO−
VO+
Internal
Oscillator CS
To Battery
VDD
GND
Bias
Circuitry
Single-ended
Input
TPA2032D1
Filter-Free Class D
SHUTDOWN
CI
CI
BOARD LAYOUT
Copper
Trace Width
Solder Mask
Thickness
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
APPLICATION INFORMATION (continued)
Figure 37. TPA2032D1 Application Schematic With Single-Ended Input
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and theopening size is defined by the copper pad width. Figure 38 and Table 1 show the appropriate diameters for aWCSP layout. The TPA2032D1 evaluation module (EVM) layout is shown in the next section as a layoutexample.
Figure 38. Land Pattern Dimensions
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Component Location
Trace Width
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
APPLICATION INFORMATION (continued)Table 1. Land Pattern Dimensions
SOLDER PAD SOLDER MASK COPPER STENCIL STENCILCOPPER PADDEFINITIONS OPENING THICKNESS OPENING THICKNESS
Nonsolder mask 275 µm 375 µm 1 oz max (32 µm) 275 µm x 275 µm Sq. 125 µm thickdefined (NSMD) (+0.0, –25 µm) (+0.0, –25 µm) (rounded corners)
NOTES:
1. Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area insidethe solder mask opening. Wider trace widths reduce device stand off and impact reliability.2. Recommended solder paste is Type 3 or Type 4.3. Best reliability results are achieved when the PWB laminate glass transition temperature is above theoperating range of the intended application.4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction inthermal fatigue performance.5. Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.6. Best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemicallyetched stencils results in inferior solder paste volume control.7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentionalcomponent movement due to solder wetting forces.
Place all the external components very close to the TPA2032D1. Placing the decoupling capacitor, C
S
, close tothe TPA2032D1 is important for the efficiency of the class-D amplifier. Any resistance or inductance in the tracebetween the device and the capacitor can cause a loss in efficiency.
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCBtraces. Figure 39 shows the layout of the TPA2032D1 evaluation module (EVM).
For high current pins (V
DD
, GND V
O+
, and V
O-
) of the TPA2032D1, use 100- µm trace widths at the solder ballsand at least 500- µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN–, IN+, and SHUTDOWN) of the TPA2032D1, use 75- µm to 100- µm trace widths at the solderballs. IN– and IN+ traces need to run side-by-side to maximize common-mode noise cancellation.
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375 mm
(+0, -25 mm) 275 mm
(+0, -25 mm)
Circular Solder Mask Opening
Paste Mask (Stencil)
= Copper Pad Size
75 mm
100 mm
100 mm
100 mm
100 mm
100 mm
75 mm
75 mm
EFFICIENCY AND THERMAL INFORMATION
qJA +1
Derating Factor
(3)
TAMax +TJMax *qJAPDmax
(4)
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
Figure 39. Close Up of TPA2032D1 Land Pattern From TPA2032D1 EVM
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorfor the YZF package is shown in the dissipation rating table. Converting this to θ
JA
:
Given θ
JA
(from the Package Dissipation ratings table), the maximum allowable junction temperature (from theAbsolute Maximum ratings table), and the maximum internal dissipation (from Power Dissipation vs OutputPower figures) the maximum ambient temperature can be calculated with the following equation. Note that theunits on these figures are Watts RMS. Because of crest factor (ratio of peak power to RMS power) from 9–15dB, thermal limitations are not usually encountered.
The TPA2032D1 is designed with thermal protection that turns the device off when the junction temperaturesurpasses 150 °C to prevent damage to the IC. Note that using speakers more resistive than 4- Ωdramaticallyincreases the thermal performance by reducing the output current and increasing the efficiency of the amplifier.θ
JA
is a gross approximation of the complex thermal transfer mechanisms between the device and its ambientenvironment. If the θ
JA
calculation reveals a potential problem, a more accurate estimate should be made.Please contact TI for further information.
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WHEN TO USE AN OUTPUT FILTER
1 nF
Ferrite
Chip Bead
VO−
VO+
Ferrite
Chip Bead
1 nF
TPA2032D1
TPA2033D1
TPA2034D1
SLOS476 – JUNE 2006
Design the TPA2032D1 without an output filter if the traces from the amplifier to the speaker are short. Wirelesshandsets and PDAs are great applications for this class-D amplifier to be used without an output filter.
The TPA2032D1 passed FCC- and CE-radiated emissions testing with no shielding with speaker trace wires 100mm long or less. For longer speaker trace wires, a ferrite bead can often be used in the design if failing radiatedemissions testing without an LC filter; and, the frequency-sensitive circuit is greater than 1 MHz. If choosing aferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.The selection must also take into account the currents flowing through the ferrite bead. Ferrites can begin toloose effectiveness at much lower than rated current values. Please see the EVM User's Guide for componentsused successfully by TI.
Figure 40 shows a typical ferrite-bead output filter.
Figure 40. Typical Ferrite Chip Bead Filter
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA2033D1YZFR DSBGA YZF 9 3000 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1
TPA2033D1YZFT DSBGA YZF 9 250 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1
TPA2034D1YZFR DSBGA YZF 9 3000 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1
TPA2034D1YZFT DSBGA YZF 9 250 180.0 8.4 1.65 1.65 0.81 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA2033D1YZFR DSBGA YZF 9 3000 210.0 185.0 35.0
TPA2033D1YZFT DSBGA YZF 9 250 210.0 185.0 35.0
TPA2034D1YZFR DSBGA YZF 9 3000 210.0 185.0 35.0
TPA2034D1YZFT DSBGA YZF 9 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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