Semiconductor
MSC2343257D-xxBS8/DS8
4,194,304-word x 32-b it DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO
This version: Mar. 8. 1999
DESCRIPTION
The MSC2343257D-xxBS8/DS8 is a fully decoded, 4,194,304-word x 32-bit CMOS dynamic random access
memory module composed of eight 16Mb DRAMs (4Mx4) in SOJ packages mounted with eight decoupling
capacitor s on a 72-pin glass epoxy si ngle in-li ne pac k age. This m odule supports any appli c ation where high densi ty
and lar ge c apac it y of stor age memory ar e r equired.
FEATURES
· 4, 194,304-word x 32- bit or ganization
· 72-pin Singl e In-Line Memory M odule
MSC2343257D-xxBS 8 : Gold tab
MSC2343257D-xxDS8 : Solder tab
· Single +5V suppl y ± 10% tol er anc e
· I nput : T TL compatible
· Output : TTL compatible, 3-state
· Refresh : 2048cycles/32m s
· / CA S before /RA S r efresh, hi dden r efresh, /RA S only r efr esh capability
· F ast page mode with EDO c apability
· Mult i-bit test m ode c apability
PRODUCT FAMILY
Access Time (Max.) Power Dissipat i on
Family tRAC tAA tCAC
Cycle
Time
(Min.) Operating (Max.) Standby (Max.)
MSC2343257D-60BS8/DS8 60ns 30ns 15ns 104ns 4840mW
MSC2343257D-70BS8/DS8 70ns 35ns 20ns 124ns 4400mW 44mW
Semiconductor MSC2343257D
MODULE OUTLINE
1
72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
φ3.18
25.4±0.2
101.19Typ.
107.95±0.2
*1
3.38Typ.
5.28Max.
+0.1
-0.08
1.27
(Un i t : m m)
MSC2343257D-xxBS8/DS8
*1 The common size difference of the board width 12.5mm of its height is specified as ±0.2.
The value above 12.5mm is specified as ±0.5.
Semiconductor MSC2343257D
PIN CONFIG URATION
Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me
1V
SS 19 A10 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 VSS 57 DQ12
4 DQ1 22 DQ5 40 /CAS0 58 DQ28
5 DQ17 23 DQ21 41 /CAS2 59 VCC
6 DQ2 24 DQ6 42 /CAS3 60 DQ29
7 DQ18 25 DQ22 43 /CAS1 61 DQ13
8 DQ3 26 DQ7 44 /RAS0 62 DQ30
9 DQ19 27 DQ23 45 NC 63 DQ14
10 VCC 28 A7 46 NC 64 DQ31
11 NC 29 NC 47 /WE 65 DQ15
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14 A2 32 A9 50 DQ24 68 PD2
15 A3 33 NC 51 DQ9 69 PD3
16 A4 34 /RAS2 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 VSS
Presence Det ect P ins
Pin No. Pin Na me MSC2343257D
-60BS8/DS8 MSC2343257D
-70BS8/DS8
67 PD1 VSS VSS
68 PD2 NC NC
69 PD3 NC VSS
70 PD4 NC NC
Semiconductor MSC2343257D
BLOCK DIAGRAM
/WE
/CAS0
/RAS0
/CAS1
DQ0
A0-A10
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ1
DQ2
DQ3
V
CC
V
SS
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
/OE
V
CC
/RAS
/CAS
/WE
V
SS
DQ8
DQ9
DQ10
DQ11
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ12
DQ13
DQ14
DQ15
DQ16
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ17
DQ18
DQ19
V
CC
V
SS
V
CC
V
SS
DQ20
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ21
DQ22
DQ23
V
CC
V
SS
DQ24
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ25
DQ26
DQ27
V
CC
V
SS
DQ28
A0-A10
DQ
DQ
DQ
DQ
/OE
/RAS
/CAS
/WE
DQ29
DQ30
DQ31
V
CC
V
SS
/CAS2
/RAS2
/CAS3
Semiconductor MSC2343257D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Volt age on Any Pin Relati ve to VSS VIN, VOUT -0.5 to +7.0 V
Volt age on VCC Supply Relat ive to VSS VCC -0.5 to +7.0 V
Short Ci r cuit O ut put Cur r ent IOS 50 mA
Power Dissipation PD *8W
Operating Temperature TOPR 0 to +70 °C
Storage Temperature TSTG - 40 to +125 °C
* Ta = 25°C
Recommen ded Operating Conditions ( Ta = 0°C to +70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Suppl y Voltage VSS 000V
Input High Volt age VIH 2.4 - VCC + 0.5 V
Input Low Vol t age VIL -0.5 - 0.8 V
Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 - A10) CIN1 -57pF
Input Capaci t ance (/WE) CIN2 -65pF
Input Capaci t ance (/RAS0, /RAS2) CIN3 -35pF
Input Capaci t ance (/CAS0- /CAS3) CIN4 -20pF
I/O Capacitance (DQ0 - DQ31) CDQ -16pF
Semiconductor MSC2343257D
DC CHARACT ERIST ICS (VCC = 5V ± 10%, Ta = 0°C to +70°C )
MSC2343257D
-60BS8/DS8 MSC2343257D
-70BS8/DS8
Parameter Symbol Condition
Min. Max. Min. Max.
Unit Note
Input Leakage Current ILI
0V ≤ VIN ≤ 6.5V;
All ot her pins not
under test = 0V -80 80 -80 80 µA
Out put Leakage Current ILO DQ disable
0V ≤ VOUT ≤ 5.5V -10 10 -10 10 µA
Out put Hi gh Voltage VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V
Out put Low Vol t age VOL IOL = 4.2mA 0 0.4 0 0.4 V
Average Power
Supply Current
(Operating) ICC1 /RAS, /CAS c y cli n g,
tRC = Min. - 880 - 800 mA 1, 2
/RAS, /CAS = VIH -16-16mA1
Power suppl y cur r ent
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -8-8mA1
Average Power
Supply Current
(/RAS only r efresh) ICC3
/RAS cy c li ng ,
/CAS = VIH,
tRC = Min. - 880 - 800 mA 1, 2
Average Power
Supply Current
(/CAS before /RAS refresh) ICC6 /RAS cyc lin g,
/CAS before /RAS - 880 - 800 mA 1, 2
Average Power
Supply Current
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cy c li ng ,
tHPC = Min. - 720 - 640 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open c ondition.
2. Address can be changed once or less whil e /RAS = VIL.
3. Address can be changed once or less whil e /CAS = VIH.
Semiconductor MSC2343257D
AC CHARACTERISTICS (1/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Not e: 1, 2, 3, 10, 11
MSC2343257D
-60BS8/DS8 MSC2343257D
-70BS8/DS8
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Random Read or Wr ite Cycle Time tRC 104 - 124 - ns
Fast Page Mode Cycle Tim e t HPC 25 - 30 - ns
Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6
Access Time from /CAS tCAC - 15 - 20 ns 4, 5
Access Time from Column Address tAA - 30 - 35 ns 4, 6
Access Time from / CAS Precharge tCPA - 35 - 40 ns 4
Out put Low Impedance Tim e from / CAS t CLZ 0-0-ns4
Data Output Hold After /CAS Low tDOH 5-5-ns
/CAS to Data Output Buffer Turn-off Delay Ti me tCEZ 0 15 0 20 ns 7, 8
/RAS to Data Output Buffer Turn-off Delay Ti me tREZ 0 15 0 20 ns 7, 8
/WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 20 ns 7
Transi tion Time tT1 50 1 50 ns 3
Refr esh Per iod tREF -32-32ms
/RAS Pr echarge Time tRP 40 - 50 - ns
/RAS Pulse Widt h tRAS 60 10K 70 10K ns
/RAS Pulse Widt h ( Fast Page Mode wit h EDO) tRASP 60 100K 70 100K ns
/RAS Hold Time tRSH 10 - 13 - ns
/CAS Precharge Time (Fast Page Mode wit h EDO) tCP 10 - 10 - ns
/CAS Pulse Widt h tCAS 10 10K 13 10K ns
/CAS Hold Time tCSH 40 - 45 - ns
/CAS t o /RAS Prechar g e Time tCRP 5-5-ns
/RAS Hold Tim e from /CAS Precharge tRHCP 35 - 40 - ns
/RAS to /CAS Delay Time tRCD 14 45 14 50 ns 5
/RAS to Column Address Delay Time tRAD 12 30 12 35 ns 6
Row Address Set-up Tim e tASR 0-0-ns
Row Address Hold Time tRAH 10 - 13 - ns
Column Address Set-up Tim e tASC 0-0-ns
Col u mn Ad d r ess Hold Time tCAH 10 - 13 - ns
Column Address to /RAS Lead Time tRAL 30 - 35 - ns
Read Com mand Set-up Tim e tRCS 0-0-ns
Read Com mand Hol d Time tRCH 0-0-ns9
Read Com mand Hol d Time referenced to /RAS tRRH 0-0-ns9
Semiconductor MSC2343257D
AC Characteristics (2/ 2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Not e: 1, 2, 3, 10, 11
MSC2343257D
-60BS8/DS8 MSC2343257D
-70BS8/DS8
Parameter Symbol
Min. Max. Min. Max.
Unit Note
W r ite Command Set-up Tim e tWCS 0-0-ns
W r ite Command Hold Time tWCH 10 - 13 - ns
W r ite Command Pul se Wi dt h t WP 10 - 10 - ns
/WE Pulse Widt h ( DQ Di sable) tWPE 10 - 10 - ns
W r ite Command t o / RAS Lead Ti me tRWL 10 - 13 - ns
W r ite Command t o / CAS Lead Ti me tCWL 10 - 13 - ns
Data-i n Set-up Time tDS 0-0-ns
Dat a-i n Hold Time tDH 10 - 13 - ns
/CAS Active Delay Tim e from /RAS Precharge tRPC 5-5-ns
/RAS to /CAS Set-up Tim e
(/ CAS b efore /RAS) tCSR 5-5-ns
/RAS to /CAS Hold Time
(/ CAS b efore /RAS) tCHR 10 - 10 - ns
/WE to /RAS Precharge Time
(/ CAS b efore /RAS) tWRP 10 - 10 - ns
/WE Hold Time from /RAS
(/ CAS b efore /RAS) tWRH 10 - 10 - ns
/RAS to /W E Set-up Tim e
(Test Mode) tWTS 10 - 10 - ns
/RAS to /W E Hold Tim e
(Test Mode) tWTH 10 - 10 - ns
Semiconductor MSC2343257D
Notes: 1. A start- up delay of 200µs is required after power-up, followed by a minimum of eight ini tiali z ation cycles
(/RA S only r efr esh or / CA S before /RA S r efresh) before proper device operat ion is achieved.
2. The AC c har ac teristic s assumes tT = 2ns.
3. VIH(Min. ) and VIL(Max .) are ref erence lev els f or m easuring i nput ti mi ng si gnals. Transit ion ti me (tT) are
m easured bet ween VIH and VIL.
4. This param eter i s measured wi th a l oad c ircuit equivalent to 2TTL loads and 100pF.
5. Operati on within the tRCD(M ax.) l imi t ensures that tRAC(Max . ) can be met.
tRCD(Max.) is specified as a reference point only . If tRCD is greater than the specified tRCD(Max.) limit, then
the acc ess ti me is controlled by tCAC.
6. Operati on within the tRAD(Max. ) lim it ensures that t RAC(Max . ) can be met.
tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then
the acc ess ti me is controlled by tAA.
7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit
condi ti on and ar e not referenc ed to output voltage levels.
8. tCEZ and tREZ must be satisfied for open circuit c ondition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is an 8-bi t parall el test f unction. CA0, CA1 and CA10 are not used. In a read cycle, if all internal bi ts are
equal, the DQ pin will in dic at e a hig h level. If a ny inte rn a l bits a re n ot equal, the DQ pin w ill ind ica te a lo w
level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS
only refresh or /CAS bef ore /RAS ref resh cycle.
11. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the s pecified value.
These parameters should be specified in test mode cycle by adding the abov e value to the specified
value i n thi s data sheet.