2:2, Differential-to-LVPECL/LVDS Divider ICS879S216I-02 DATA SHEET General Description Features The ICS879S216I-02 is a Differential-to-LVPECL/ LVDS Clock Divider which can operate up to 2.5GHz. ICS879S216I-02 has 2 selectable differential clock inputs. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. ICS879S216I-02 can divide the input clock by /2, /4, /8 and /16. Table 4A lists all the available output dividers. * * * * * * * * * * High speed 2:2 differential divider Two differential LVPECL or LVDS output pairs Four selectable divide combinations PCLKx can accept the following input levels: LVPECL, LVDS, CML Maximum input frequency: 2.5GHz Propagation delay: 0.8ns (minimum), 1.6ns (maximum) Output Skew: 25ps (maximum) Full 3.3V or 2.5V supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 5) package Table 1A. VCC_TAP Function Table Outputs Q[1:0], nQ[1:0] Output Level Supply VCC_TAP LVPECL 2.5V VCC Input Outputs LVPECL 3.3V VCC SEL_OUT Q[1:0], nQ[1:0] LVDS 2.5V VCC 1 LVPECL (default) LVDS 3.3V Float 0 LVDS Table 1B. SEL_OUT Function Table N PCLK1 Pulldown nPCLK1 Pullup/Pulldown nQ0 /2, /4, /8, /16 (default) Q1 1 nQ1 Q1 nQ1 nQ0 17 3 16 nc PCLK1 4 15 nc nPCLK1 5 14 nc SEL_OUT 6 7 VCC 00 01 10 11 2 8 13 VEE 9 10 11 12 F_SEL0 Q0 nc PCLK0 nPCLK0 F_SEL1 0 24 23 22 21 20 19 18 VCC nc nPCLK0 Pullup/Pulldown 1 VEE PCLK0 Pulldown CLK_SEL VCC_TAP CLK_SEL Pulldown Q0 nc SEL_OUT Pullup VEE Pin Assignment Block Diagram ICS879S216I-02 24-Lead VFQFN F_SEL[1:0] Pullup 4mm x 4mm x 0.95mm package body 2 ICS879S216AKI-02 REVISION A APRIL 8, 2011 K Package Top View 1 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Table 2. Pin Descriptions Number Name 1 CLK_SEL Input Type Pulldown Description Clock select input. See Table 4B. LVCMOS/LVTTL interface levels. 2 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. 3 nPCLK0 Input Pullup/ Pulldown Inverting differential LVPECL clock input. 4 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. 5 nPCLK1 Input Pullup/ Pulldown 6 SEL_OUT Input Pullup 7, 18 VCC Power Power supply pins. 8 VCC_TAP Power Power supply pin. See Table 1A. 9, 13, 23 VEE Power Negative supply pins. 10, 14. 15, 16, 17, 24 nc Unused 11, 12 F_SEL1, F_SEL0 Input 19, 20 nQ1, Q1 Output Differential output pair. LVPECL or LVDS interface levels. 21, 22 nQ0, Q0 Output Differential output pair. LVPECL or LVDS interface levels. Select pin. See Table 1B. LVCMOS/LVTTL interface levels. No connect. Pullup Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 3. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Function Tables Table 4A. Clock Input Function Table Table 4B. CLK_SEL Function Table Input Inputs F_SEL1 F_SEL0 Divide CLK_SEL PCLK[0:1], nPCLK[0:1] 0 0 2 0 PCLK0, nPCLK0 (default) 0 1 4 1 PCLK1, nPCLK1 1 0 8 1 1 16 (default) ICS879S216AKI-02 REVISION A APRIL 8, 2011 NOTE: CLK_SEL is an asynchronous control. 2 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 49.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Power Supply Voltage 3.135 3.3 3.465 V VCC_TAP Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 65 mA Table 5B. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 60 mA Table 5C. LVDS Power Supply DC Characteristics, VCC = 3.3V 5%, VCC_TAP = Float, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 95 mA Table 5D. LVDS Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 90 mA ICS879S216AKI-02 REVISION A APRIL 8, 2011 Test Conditions 3 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Table 5E. LVCMOS/LVTTL DC Characteristics, VCC = VCC_TAP = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum VCC = 3.465V Typical Maximum Units 2.2 VCC + 0.3 V VCC = 2.625V 1.7 VCC + 0.3 V VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V CLK_SEL VCC = VIN = 3.465V or 2.625V 150 A F_SEL[1:0], SEL_OUT VCC = VIN = 3.465V or 2.625V 10 A CLK_SEL VCC = 3.465V or 2.625V, VIN = 0V -10 A F_SEL[1:0], SEL_OUT VCC = 3.465V or 2.625V, VIN = 0V -150 A Table 5F. LVPECL DC Characteristics, VCC = VCC_TAP = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter IIH Input High Current Test Conditions PCLK0, nPCLK0, PCLK1, nPCLK1 Minimum Typical VCC = VIN = 3.465V or 2.625V Maximum Units 150 A PCLK0, PCLK1 VCC = 3.465V or 2.625V -10 A nPCLK0, nPCLK1 VCC = 3.465V or 2.625V, VIN = 0V -150 A IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR 0.15 1.3 V Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 V VOH Output High Voltage; NOTE 3 VCC - 1.4 VCC - 0.8 V VOL Output Low Voltage; NOTE 3 VCC - 2.0 VCC - 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50 to VCC - 2V. Table 5G. LVDS DC Characteristics, VCC = 3.3V 5%, VCC_TAP = Float, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum VOD Differential Output Voltage SEL_OUT = 0 247 VOD VOD Magnitude Change SEL_OUT = 0 VOS Offset Voltage SEL_OUT = 0 VOS VOS Magnitude Change SEL_OUT = 0 Typical 1.125 Maximum Units 454 mV 50 mV 1.375 V 50 mV Maximum Units 454 mV 50 mV 1.375 V 50 mV Table 5H. LVDS DC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum VOD Differential Output Voltage SEL_OUT = 0 247 VOD VOD Magnitude Change SEL_OUT = 0 VOS Offset Voltage SEL_OUT = 0 VOS VOS Magnitude Change SEL_OUT = 0 ICS879S216AKI-02 REVISION A APRIL 8, 2011 4 1.1 Typical (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER AC Electrical Characteristics Table 6A. LVPECL AC Characteristics, VCC = VCC_TAP = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter fIN Input Frequency fOUT Output Frequency Test Conditions Minimum Typical Maximum Units 2.5 GHz F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz 1.6 ns tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(i) Input Skew 60 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOLATION MUX Isolation; NOTE 5 0.8 20% to 80% 650 ps 90 250 ps 47 53 % >100 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined according with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section. Table 6B. LVPECL AC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter fIN Input Frequency fOUT Output Frequency Test Conditions Minimum Typical Maximum Units 2.5 GHz F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz 1.6 ns tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(i) Input Skew 60 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOLATION MUX Isolation 0.8 20% to 80% 650 ps 90 250 ps 47 53 % >100 dB For NOTES, see Table 6A above. ICS879S216AKI-02 REVISION A APRIL 8, 2011 5 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Table 6C. LVDS AC Characteristics, VCC = 3.3V 5%, VCC_TAP = Float, VEE = 0V, TA = -40C to 85C Symbol Parameter fIN Input Frequency fOUT Output Frequency Test Conditions Minimum Typical Maximum Units 2.5 GHz F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz 1.6 ns tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(i) Input Skew 75 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOLATION MUX Isolation 0.8 20% to 80% 650 ps 70 250 ps 46 54 % >100 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined according with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section.. Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter fIN Input Frequency Test Conditions Minimum Typical Maximum Units 2.5 GHz F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz 1.6 ns fOUT Output Frequency tpLH Propagation Delay, Low-to-High; NOTE 1 tsk(i) Input Skew 75 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUXISOLATION MUX Isolation 0.8 20% to 80% 650 ps 70 250 ps 46 54 % >100 dB For NOTES, see Table 6C above. ICS879S216AKI-02 REVISION A APRIL 8, 2011 6 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Parameter Measurement Information 2V 2V VCC, VCC_TAP Qx SCOPE VCC, VCC_TAP LVPECL Qx SCOPE LVPECL nQx nQx VEE VEE -1.3V0.165V -0.5V0.125V 3.3V LVPECL Output Load AC Test Circuit 2.5V LVPECL Output Load AC Test Circuit SCOPE SCOPE Qx VCC 3.3V5% POWER SUPPLY + Float GND - 2.5V5% POWER SUPPLY + Float GND - LVDS VCC, VCC_TAP Qx LVDS nQx nQx VCC_TAP = Float 3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit VCC nPCLK0, nPCLK1 PCLK0, PCLK1 nPCLK[0:1] V PP Cross Points V CMR nQ[0:1] PCLK[0:1] Q[0:1] tpLH VEE Differential Input Level ICS879S216AKI-02 REVISION A APRIL 8, 2011 Propagation Delay 7 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Parameter Measurement Information, continued nPCLK0 Spectrum of Output Signal Q PCLK0 MUX selects active input clock signal Amplitude (dB) A0 nPCLK1 PCLK1 MUX_ISOL = A0 - A1 nQ MUX selects static input A1 Q tPD2 tPD1 (fundamental) tsk(i) Frequency tsk(i) = |tPD1 - tPD2| Input Skew MUX Isolation Par t 1 nQx nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Output Skew Part-to-Part Skew nQ[0:1] nQ[0:1] 80% 80% 80% 80% VSW I N G VOD Q[0:1] 20% 20% tR Q[0:1] tF tR tF LVPECL Output Rise/Fall Time LVDS Output Rise/Fall Time ICS879S216AKI-02 REVISION A APRIL 8, 2011 20% 20% 8 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Parameter Measurement Information, continued VDD VDD out DC Input LVDS 100 VOS/ VOS VOD/ VOD out LVDS DC Input out out Offset Voltage Setup Differential Output Voltage Setup nQ[0:1] Q[0:1] t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period ICS879S216AKI-02 REVISION A APRIL 8, 2011 9 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: PCLK/nPCLK Inputs LVPECL Outputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs LVCMOS Control Pins All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS879S216AKI-02 REVISION A APRIL 8, 2011 10 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER 3.3V LVPECL Clock Input Interface The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. The differential signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the PCLK/ nPCLK input driven by the most common driver types. 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50 R2 50 Zo = 50 PCLK PCLK R1 100 Zo = 50 nPCLK Zo = 50 nPCLK LVPECL Input CML LVPECL CML Built-In Pullup Input Figure 2B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 2A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 Zo = 50 R3 84 3.3V LVPECL Zo = 50 R4 84 C1 PCLK PCLK Zo = 50 Zo = 50 C2 nPCLK nPCLK LVPECL Input LVPECL R1 84 R2 84 R5 100 - 200 R6 100 - 200 R1 125 R2 125 LVPECL Input Figure 2D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V Zo = 50 PCLK R1 100 Zo = 50 nPCLK LVDS LVPECL Input Figure 2E. PCLK/nPCLK Input Driven by a 3.3V LVDS Driver ICS879S216AKI-02 REVISION A APRIL 8, 2011 11 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER 2.5V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS and other differential signals. The differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3C show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 3.3V 2.5V Zo = 50 Zo = 50 C1 R1 100 PCLK R3 100 PCLK R1 100 Zo = 50 nPCLK Zo = 50 LVPECL Input LVDS nPCLK C2 3.3V LVPECL Driv er R6 100-180 Figure 3A. PCLK/nPCLK Input Driven by a 2.5V LVDS Driver R7 100-180 R2 100 R4 100 Figure 3B. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 2.5V 2.5V R3 250 R4 250 Zo = 50 PCLK Zo = 50 nPCLK LVPECL R1 62.5 R2 62.5 LVPECL Input Figure 3C. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver ICS879S216AKI-02 REVISION A APRIL 8, 2011 12 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100 parallel resistor at the receiver and a 100 differential transmission line environment. In order to avoid any transmission line reflection issues, the 100 resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 4 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100 - 100 Differential Transmission Line Figure 4. Typical LVDS Driver Termination Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V 3.3V Zo = 50 3.3V R4 125 3.3V 3.3V + Zo = 50 + _ LVPECL Input Zo = 50 R1 50 _ LVPECL R2 50 R1 84 VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC - 2)) - 2 R2 84 RTT Figure 5A. 3.3V LVPECL Output Termination ICS879S216AKI-02 REVISION A APRIL 8, 2011 Input Zo = 50 Figure 5B. 3.3V LVPECL Output Termination 13 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C. Figure 6A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50 + 50 + 50 - 50 2.5V LVPECL Driver - R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 6A. 2.5V LVPECL Driver Termination Example Figure 6B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 6C. 2.5V LVPECL Driver Termination Example ICS879S216AKI-02 REVISION A APRIL 8, 2011 14 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 7. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale ICS879S216AKI-02 REVISION A APRIL 8, 2011 15 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER LVPECL Power Considerations This section provides information on power dissipation and junction temperature for the ICS879S2162I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS879S216I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 65mA = 225.225mW * Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 32mW = 64mW Total Power_MAX (3.465, with all outputs switching) = 225.225mW + 64mW = 289.225mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.5C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.289W * 49.5C/W = 99.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 24 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS879S216AKI-02 REVISION A APRIL 8, 2011 0 1 2.5 49.5C/W 43.3C/W 38.8C/W 16 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 8. VCCO Q1 VOUT RL 50 VCCO - 2V Figure 8. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.8V (VCC_MAX - VOH_MAX) = 0.8V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.6V (VCC_MAX - VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.8V)/50] * 0.8V = 19.2mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.6V)/50] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW ICS879S216AKI-02 REVISION A APRIL 8, 2011 17 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER LVDS Power Considerations This section provides information on power dissipation and junction temperature for the ICS879S2162I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS879S2162I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 95mA = 329.175mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.5C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.329W * 49.5C/W = 101.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 8. Thermal Resistance JA for 24 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS879S216AKI-02 REVISION A APRIL 8, 2011 0 1 2.5 49.5C/W 43.3C/W 38.8C/W 18 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Reliability Information Table 9. JA vs. Air Flow Table for a 24 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 49.5C/W 43.3C/W 38.8C/W Transistor Count The transistor count for ICS879S216I-02 is: 1039 ICS879S216AKI-02 REVISION A APRIL 8, 2011 19 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Package Outline and Package Dimensions Package Outline - K Suffix for 24 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e D2 2 N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C Bottom View w/Type A ID D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 10. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 10. JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 0.80 1.0 A1 0 0.05 A3 0.25 Reference b 0.18 0.30 e 0.50 Basic D, E 4 D2, E2 2.30 2.55 L 0.30 0.50 6 ND NE Reference Document: JEDEC Publication 95, MO-220 ICS879S216AKI-02 REVISION A APRIL 8, 2011 20 (c)2011 Integrated Device Technology, Inc. ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER Ordering Information Table 11. Ordering Information Part/Order Number 879S216AKI-02LF 879S216AKI-02LFT Marking 6AI02L 6AI02L Package "Lead-Free" 24 Lead VFQFN "Lead-Free" 24 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS879S216AKI-02 REVISION A APRIL 8, 2011 21 (c)2011 Integrated Device Technology, Inc. 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