MF6 National Semiconductor MF6 6th Order Switched Capacitor Butterworth Lowpass Filter General Description The MF6 is a versatile easy to use, precision 6th order But- terworth lowpass active filter. Switched capacitor tech- niques eliminate external component requirements and al- low a clock tunable cutoff frequency. The ratio of the clock frequency to the lowpass cutoff frequency is intemally set to 50 to 1 (MF6-50) or 100 to 1 (MF6-100). A Schmitt trigger clock input stage allows two clocking options, either self- clocking (via an external resistor and capacitor) for stand- alone applications, or an external TTL or CMOS logic com- patible clock can be used for tighter cutoff frequency con- trol. The maximally flat passband frequency response to- gether with a DC gain of 1 V/V allows cascading MF6 sec- tions for higher order filtering. In addition to the filter, two independent CMOS op amps are included on the die and are useful for any general signal conditioning applications. Features m No external components m@ 14-pin DIP or 14-pin wide-body S.O. package = Cutoff frequency accuracy of +0.3% typical a Cutoff frequency range of 0.1 Hz to 20 kHz @ Two uncommitted op amps available a 5V to 14V total supply voltage m Cutoff frequency set by external or internal clock Biock and Connection Diagrams a yet LEVEL TRI-STATE BUFFER SHIET ie 6 TL/H/5085-1 All Packages W. INVE ond 1 VU "4 af R "1 18 ' a pam NY? am WY oom b SH pee CLK A ~ ox FATER a Top View TL/H/5065-2 Order Number MFS6CWM-50 or MFECWN-100 See NS Package Number M14B Order Number MF6CN-50 or MF6CN-100 See NS Package Number N14A Order Number MF6CJ-50 or MF6CJ-100 See NS Package Number J14A 1-134Absolute Maximum Ratings (note 11) if Military/Aerospace specified devices are required, please contact the Natlonal Semiconductor Sales Otfice/Distributors for availability and specifications. See AN-450 Surface Mounting Methods and Their Effect on Product Reliability (Appendix D) for other methods of soldering surface mount devices. 94IN Supply Voltage 14V . . Voltage at Any Pin V- 0.2V,V+ + 0.2V Operating Ratings (note 11) Input Current at Any Pin (Note 13) 5 mA Temperature Range TIN <= Ta < Tmax Package Input Current (Note 13) 20 mA MF6CN-50, MF6CN-100 OCs Tas +70C Power Dissipation (Note 14) 500 mW MF6CWN-50, MF6CWM-100 oc <Ta < +70C Storage Temperature 65C to + 150C MF6CJ-50, MF6CJ-100 40C < Ta s + 88C ESD Susceptibility (Note 12) a00V Supply Voltage (Vg = Vt-V-) 5V to 14V Soldering Information N Package (10 sec.) 260C J Package (10 sec.) 300C SO Package Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C Filter Electrical Characteristics the totiowing specifications apply for fo. < 250 kHz (see Note 3) unless otherwise specified. Boldface Iimits apply for Thain to Tyax; all other limits Ta = Ty = 25C. MF6CWMN-50, MFECWM- 100, -50, MFECJ-100 MF6CN-50, MF6CN-100 MF6CJ-50, MF Parameter Conditions rypleal Tested Design rypleal Tested Design Units ote 3) | tit Limit (Note 3) Limit Limit (Note 9) (Note 10) (Note 9) |(Note 10) Vt = +5V,V- = -5V fc, Cutoff MF6-50 Min 0.1 0.1 Frequency Max 20k 20k Hz Range MF6-100 Min 0.1 0.4 (Note 1} Max 10k 10k Total Supply Current foik = 250 kHz 4.0 6.0 8.5 4.0 8.5 mA Maximum Clock Filter Output 30 30 mV Feedthrough Op Amp 1 Out 25 25 (peak-to- Op Amp 2 Out 20 20 peak) Ho, Resource 0.0 +0.30 +0. . +0, DC Gain < 2kn 0.30 0.0 0.30 dB fotk/fe, MF6-50 49.27+0.39%!/49.2741% | 49.27+1% [49.27403%| 49.271 1% Clock to Cutoft MF6-100 98.9740.3%|98.9741% | 9B.97+1% |98.97+03%| 96.9077 1% Frequency Ratio DC MF6-50, 200 -200 mV Offset Voltage MF6-100 400 400 Minimum Output RL =10kn +40 +3.5 +3.5 +4.0 +3.5 V Voltage Swing 41 3.8 -3.5 4.1 -3.5 ceo Source 50 60 80 50 80 mA ink! , I. . . a Current (Note 6) Sin 1.5 2.0 3.0 1.5 3.0 Dynamic Range MF6-50 83 83 op (Note 2) MF6-100 81 B1 Additional MF6-501 fo_k = 250 kHz Magnitude f=6000 Hz 9,47 9,47+0.5]-9,.47+0,.65 9.47 -9.47+0.65 dB Response Test f=4500 Hz 0.92 -0.9240.2] -0.92:0.3 0.92 -0.9210.3 Points (Note 4) MF6-100] fo. = 250 kHz f=3000 Hz ~9.48 9.48+0.5!-9.48+ 0.65 9.48 9.4810.65 dB f= 2250 Hz 0.97 0.97+0.2; -0.97+0.3 0.97 -0,97+0.3 1-135MF6 Filter Electrical Characteristics (Continued) The following specifications apply for fo_~ < 250 kHz (see Note 3) unless otherwise specified. Boldface limite apply for Tay to Trax; all other limits T, = T = 25C. MFECWNH-50, MF8CWM-100 MF6CN-50, MF6CN-100 MF6CJ-50, MF6CJ-100 Parameter Conditions typical Tested Design typical Tested Design Units Note a | Limit Limit (Nate 3) Limit Limit (Note 9) (Note 10) (Note 9} (Note 10) V+ = +5V,V = 85 (Continued) Attenuation Rate MF6-50ifo_K = 250 kHz: dB/ f; = 6000 Hz 36 -36 -36 octave fo= 8000 Hz MF6-100lfcL = 250 kHz aB/ f; = 3000 Hz 36 ~36 36 octave fp = 4000 Hz Vt = +2.5V,V- = 2.5V f,, Cutoff MF6-50 Min 0.1 0.1 Frequency Max 10k 10k He Range MF6-100 Min 0.1 0.1 (Note 1) Max} Sk Sk Total Supply Current foLk = 250 kHz| 2.5 4.0 4.0 2.5 4.0 mA Maximum Clock Filter Output 20 20 mV Feedthrough Op Amp 1 Out 16 15 (peak-to- Op Amp 2 Out 16 10 peak) Ho,DC Gain Rsourca <2 kf 0.0 +0.30 +0.30 0.0 +0.30 dB foux/fe. Clock to Cutoff Frequency MFB-50 49.1040.3%)/49.10+2%| 49.104+3% |49.10+0.3%} 49.10+3% Ratio MF6-160 98.65 + 0.3%) 98.65 + 2% |98.65 + 2.25% |/98.65+0.3%198.65 + 2.25% DC MF6-50 200 200 mV Offset Voltage MF6-100 400 400 Minimum Output R, = 10 kf +15 +190 + 1.0 +15 + 1.0 Vv Voltage Swing -22 -17 -1.5 2.2 14.5 Maximum Output Source 28 40 so 28 50 Short Circuit Sink 0.5 1.0 1.5 0.5 1.5 mA Current (Note 6} . . , . . Dynamic Range (Note 2) 77 77 dB Additional MF6-50]fc_K = 250 kHz Magnitude f=6000 Hz 9.54 9.5440.5) 9.34+0.65 9.54 9.54+0.65 dB Response Test f= 4500 Hz -0.96 0.96+0.2) 0,96+0.3 0.96 0.96+0.3 Points (Note 4) MF6-100lfc1 x = 250 kHz f= 3000 Hz 9.67 9.67+0.5) 9.67+0,.65 9.67 9.67+0.65 dB f= 2250 Hz 1.01 -1.01+0.2) 4.01+0.3 1.01 -1.01+0.3 Attenuation MF6-50!fo_k = 250 kHz! 4B/ Rate f4 = 6000 Hz 36 -36 36 octave fp =8000 Hz MF6-100) fc. = 250 kHz! 4B/ fy =3000 Hz 36 36 -36 octave fo = 4000 Hz 1-13691 Op Amp Electrical Characteristics Boldface limits apply for Tin to Tagax; all other limits Ta = Ty = 25C. MF6CN-50, MF6CN-100, MF6CWM-50, MF6CWM-100 MF6CJ-50, MF6CJ-100 Parameter Conditions Tested Design Tested Design Units Typical Typical (Note 8) Limit Limit (Note 8) Limit Limit (Note 9) | (Note 10) (Note 9) | (Note 10) V+ = +5V,V- = 5V Input Offset Voltage +80 +20 +20 +8.0 +20 mv Input Bias Current 10 10 pA CMRR (Op Amp #2 Only) Vom = 1.8V, 60 55 60 55 dB Vom2 = 2.2V Output Voltage Swing RL=10 kn +4.0 +3.8 +3.6 +40 +3.6 Vv 4.6 -4.0 -4.0 45 -4.0 Maximum Output Short Source 54 65 80 54 80 mA Circuit Current (Note 6) Sink 2.0 4.0 6.0 2.0 6.0 Slew Rate 7.0 7.0 V/ps DC Open Locp Gain 72 f2 dB Gain Bandwidth Product 1.2 1.2 MHz Vt = +2.5V,V- = -25V Input Offset Voltage 8.0 +20 +20 +6.0 +20 mV Input Bias Current 10 10 pA CMRR (Op-Amp #2 Only) Vemi = +0.5V, 60 55 60 55 dB Vom2 = 0.9V Output Voltage Swing RL = 10k +15 +1.3 +1.4 +15 +41.4 Vv 2.2 -1.7 -1.7 -2.2 41.7 Maximum Output Short Source 24 35 50 24 50 mA Circuit Current (Note 6) Sink 1.0 2.0 4.0 1.0 4.0 Slew Rate 6.0 6.0 V/ps DC Open Loop Gain 67 67 dB Gain Bandwidth Product 1.2 1.2 MHz 1-137MF6 Logic Input-Output Electrical Characteristics tha toilowing specifications apply for V- = OV (see Note 5) unless otherwise specified. Boldface limits apply for Twin to Twax; all other limits Ta = Ty = 25C. MF6CN-50, MFGCN-100 MFECWM-50, MFeCwM-100 | _ MF8CU-50, MF6CJ-100 Parameter Conditions Typical Tested Design Typical Tested Desion Units (Note 3) | Limit mit | (Notes)| malt (Note 9) | (Note 10) {Note 9) | (Note 10) TTL CLOCK INPUT, CLK R PIN (Note 7) Maximum Vj, Logical 0 08 0.8 0.8 Vv input Voltage Minimum Vy, Logical 1 input Voltage 2.0 2.0 2.0 Vv Maximum Leakage Current L Sh Pin at at CLK R Pin Mid- Supply 2.0 2.0 2.0 BA SCHMITT TRIGGER Vr+, Positive Going Min | V+ = 10V 7.0 6.1 6.1 7.0 6.1 Vv Threshold Voltage Max 8.9 3.9 8.9 Min | V+ = 5V 3.5 3.1 3.1 3.5 3.1 Vv Max 44 4.4 4.4 Vr, Negative Going Min | V+ = 10V 3.0 1.3 1.3 3.0 1.3 Vv Threshold Voltage Max 3.8 3.8 3.8 Min | V+ = 5V 1.5 0.6 0.6 1.5 0.6 Vv Max 1.9 1.9 1.9 Hysteresis (V74 Vr)| Min | V+ = 10V 4.0 2.3 2.3 4.0 2.3 Vv , Max 7.6 7.6 T.6 Min | V+ = 5 2.0 1.2 1.2 2.0 1.2 Vv Max 3.8 3.8 3.8 Minimum Logical 1 Output I. = 10uA Vt = 10V 9.0 9.0 9.0 Vv Voltage (Pin 11) BA) y+ = BV 45 4.5 4.5 Maximum Logical 0 Output I, = 10uA V+ = 10V 1.0 1.0 1.0 Vv Voltage (Pin 11) oT NBA |yt = 5V 0.5 0.5 0.5 Minimum Output Source GLKR Tied | V+ = 10V 6.0 3.0 3.0 6.0 3.6 mA Current (Pin 11) to Ground Vt = 5V 1.6 0.75 0.75 1.6 0.75 Maximum Output Sink CLKATied | Vt = 10V 5.0 2.5 2.5 5.0 2.5 mA Current (Pin 11) tovt Vt = 5V 1.3 0.65 0.68 13 0.65 Note 4: The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter. Note 2: For +5V supplies tha dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 urms for the MF6-50 and 250 Vrms for the MF8-100. For +2.5V suppiles the dynamic range is referenced to 1.06 Vrms (1.5V peak) where the wideband noise over a 20 kHz bandwidth is typically 140 1 Vrms for both the MF6-50 and the MF6-100. Note 3: The specifications for the MF6 have been given for a clock frequency (foLK) of 250 kHz and less. Above this clock frequency the cutoff frequency begins to deviate from the specified error band of + +4.0% but the filter still maintains its magnitude characteristics. See Appiication Hints, Section 1.5. Note 4: Besides checking the cutoff frequency (f,} and the stopband attenuation at 2 f,, two additional frequencies are used to check the magnitude response of the filter. The magnitudes ara referenced to a DC gain of 0.0 dB. Note &: For simplicity all the logic levels have been referenced to V~ = GV and will scale accordingly for + 5V and +2.5Y supplies (except for the TTL input logic levels). Note 6: The short circult source current is measured by forcing the output that is being tested to its maximum positive voitage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to Its maximum negative voltage swing and then shorting that output to the positive supply. Thesa are the worst-case conditions. Note 7: The MF6 is operating with symmetrical split supplies and L.Sh is tied to ground. Note 8: Typicals are at 25C and represent most likely parametric norm. Note 9: Tested limits are guaranteed to National's AOL (Average Outgoing Quality Level. Note 10: Design jimits are guaranteed, but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 11: Absalute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating tne device beyond its specified conditions. Note 12: Human body model, 100 pF discharged through a 1.5k 1 resistor. Note 13: When the input voltage (Vx) at any pin exceeds the power supply rails (Vij < V or Vin > V +) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four. Note 14: The maximum power dissipation must be derated at elevated temperatures and is dictated by Tymax, Oa, and the ambient temperature, Ta. The maximum allowable power dissipation at any temperature is Pp = (ymax Ta)/@ua or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, Tywax = 128C, and the typical junction-to-ambient thermal resistance of the MF6CN when board mounted is 67C/W. For the MF6CJ this number decreases to 62C/W. For MFBCWM, Oya = 78C/W. 1-138Typical Performance Characteristics Schmitt Trigger Threshold Voltage | Crosstalk from Filter vs Power Supply Voltage to Op-Amps (MF6-100) 3 = 5 a 12 _ Vo=10 Soy waz be x | f= 2se Bg 3 "0 z ~ ~o (SEE TEST CIRCUTT) an 3 8 = G 0 OPAMP tye TMH Eg : ? gS OPAMP 1 fg = S00KH: | TSN | g = : 5 S60 [omar tg= Bord: rr 5 . & 4 Ez Pt Ny = 128 i Nd z Z at =70 mn daad 3 ae a ak E 2 gf map [OPTAME2 fgg = 250ki2 Be 2! 7 Bg CIMT Tomine tantout 2 5 6 7 8 5 10 H 12 13 16 10 100 1K 1K = 100K Ve POWER SUPPLY YOLTAGE () FREQUENCY (Hz) ~ Crosstalk from Filter Crosstalk from Either Op-Amp to Op-Amps (MF6-50) to Filter Output (MF6-100) = 5 =2 0 & a g=10 5 Vg= 10 > Be 730 Tg= 25C 58 y= 25C =z za 0 TEST =o 0 (SEE TEST CIRCUT) 3 * gi F - ww HH 3 as ge i < = Sse 5% POLS ty=250KH2 rh z & E za cle 5 3a 7 25 m = a8 3 wan L_ fom = 125 kHz . ; * EF 3 s = - 9 : = 10 10 ik 1K = 10K 10 100 1K 101K 100K 2 FREQUENCY (Hz) FREQUENCY (Hz) Crosstalk from Elther Op-Amp to Filter Output (MF6-50) A g=i0V T= 25C TEST 250 fou 125 kHz 10 1 1K 1K 100K FREQUENCY (Hz) Equivalent Input Noise Voltage of Op-Amps 70 g=t0 600 T= 25C 500 0 300 2 100 Q 10 100 IK 11K 10K FREQUENCY (Hz) TL/H/5065-9 1-139 914MF6 Typical Performance Characteristics (continued) Positive Voltage Swing vs Power Supply Voltage (Op Amp Output) wi0ka POSITIVE VOLTAGE SWING (V) EERRESEREELE 50 60 70 86 80 100 110 120 130 Positive Voltage Swing vs Power Supply Voltage a (Fitter Output) POSITIVE VOLTAGE SWING () $9 60 70 8 80 100 110 POSITIVE VOLTAGE SWING () Positive Voltage Swing vs Temperature (Filter and a Op Amp Outputs) =i = 250 kH? 4a [Ft 40 3 WH3H-155 3 SS HIGGS POWER SUPPLY VOLTAGE (} POWER SUPPLY VOLTAGE (V) TEMPERATURE C: Negative Voltage Swing vs Negative Voltage Swing vs Power Supply Voltage Temperature (Filter and Power Supply Current vs ou (Fliter and Op Amp Outputs) was Op Amp Outputs) 10 Clock Frequency 28 fog = 2O0KHZ = 250 kHZ gq Bty = a2 R= Oko = maa [i= 10%0. = uo 3 3s z 415 40 390 Yn Ss a Bs 3 5 0 = 72 = nts 315 g = a E 2.90 to = 2.85 Vg = 5 ry 2.40 50 8D 72 80 90 100 110 120 130 S-H-15 5 BH 4S 6S BS 1051S 100200300 400 500800 700 800 900 1000 POWER SUPPLY VOLTAGE (V) TEMPERATURE (C) CLOCK FREQUENCY (KHZ) Power Supply Current Power Supply Current ve Temperature vs Power Supply Voltage POWER SUPPLY CURRENT (mA) BERBREREEEES POWER SUPPLY CURRENT (mA) B-B-15 5 BS SG SIGS TEMPERATURE (C) 55 a =250 SM & & uM 5 6 7 8 POWER SUPPLY VOLTAGE (V) 9 10 1 12 13 TL/H/5065-35 1-140Typical Performance Characteristics (continued) foik/fc Deviation vs Clock Frequency 0 - 20 i are a 10 20 30 bes PERCENT CHANGE OF fay /f, t 5 b 100 200 300 400 500 600 700 890 900 1000 CLOCK FREQUENCY (kHZ) - fei/fe Deviation vs Clock Frequency G MF6= R= twa =10 PERCENT CHANGE OF fou /t, seeder 100 206 300 400 560 600 700 800 9001000 CLOCK FREQUENCY (kHZ) DC Gain Deviation vs Temperature fey = 250 KHZ R= 10 ,=5 OC GAIN CHANGE (dB) 68.8883 he e 8 H-B-15 5 45 8S 85 105 125 TEMPERATURE (c) DC Gain Deviation va Temperature = 250kHZ 5955915 5 25 45 65 8S 105125 TEMPERATURE (C) fe_k/f_ Deviation oa? Temperature 06 |e Sou ae 5 Spee Ss 02 4 : 8 08 =10 12 5 14 =16 18 6-15 5 25 48 6S BS 105 125 TEMPERATURE (C) fo_k/te Deviation vs Temperature 10 ta? OB . SS os R= 10ka a 02 fo a2 - =05 08 S515 5 2 45 6S 8 105 125 TEMPERATURE (C) DC Gain Deviation ons vs Power Supply Voltage 0.08 | fey = 280 KHZ 0.04 |MF6-50 RE 10k DC GAIN CHANGE (dB) 444 eegeee.e 5 6 7 B& 8 10 11 12 13 POWER SUPPLY VOLTAGE () DC Gain Deviation vs Power Supply Voltage A 02 fox = 250 o | MF6-100 R= 10k 02 04 DC GAIN CHANGE (dB) O08 0.10 5.8 F 8 8 10 WAZ 15 POWER SUPPLY VOLTAGE (} foLk/f, Deviation wo Power Supply Voltage fey = 250 30 | MF6 ~50 PERCENT CHANGE OF fay /f, o 6 & 4 & Oo 6 7 8 8 0 7 12 13 POWER SUPPLY VOLTAGE (} feik/te Deviation vs Power Supply Voltage 4g foggy = 250 KHZ 30 |uFe=100 5 PERCENT CHANGE OF fry /f, 6 i b wn 6 7 B 9 10 1 12 13 POWER SUPPLY VOLTAGE () TL/H/5085-36 DC Gain Deviation vs Clock Frequency = 50 Vg= DC GAIN CHANGE (dB) BESROREREES 2. & 100-200 300 490-500 600 700 800 $00 1000 DC Gain Deviation vs Clock Frequency 12 1 10 MF6-100 Vg! Vs = 5V DG GAIN CHANGE (d) eeeeoreee 4 & 100 200-300 400 500 600 700 800 900 1000 CLOCK FREQUENCY {kHz) TL/H/5065-39 1-141 9AMF6 Crosstalk Test Circuits From Filter to Opamps FILTER wy Yor 20Hz=20kHz AY, CLK RNS Le asov Voz OP-AMP $2 From Elther Opamp to Filter Output 20Hz- 20kHz 1V RMS Pin Descriptions (in Numbers) Pin Description FILTER OUT (3) The output of the lowpass filter. It will typically sink 0.9 mA and source 3 mA and swing to within 1V of each supply rail. The input to the lowpass filter. To minimize gain errors the source impedance that drives this input should be less than 2k (see section 1.4}. For single supply operation the input signal must be biased to mid-supply or AC coupled. This pin is used to adjust the DC offset of the filter output; if not used it must be tied to the AGND potential. (See section 1.3) The analog ground pin. This pin sets the DC bias level for the filter section and the non- inverting input of Op-Amp #1 and must be tied to the system ground for split supply operation or to mid-supply for single supply operation (see section 1.2). When tied to mid-supply this pin should be well bypassed. Vo1 is the output and INV1 is the inverting input of Op-Amp #1. The non-inverting input of this Op-Amp is internally connected to the AGND pin. FILTER IN (8) VagADu (7) AGND (5) Vor (4), INV14 (13) aC VOLTWETER TLYH/5065 -10 FILTER ct L. 250 kHz Pin Voe (2), INV2 (14), NINV2 (1) V+(6), V(10) CLK IN (9) CLK R (11) L. Sh (12) ac VOLTMETER TL/H/5065-11 Description Voz is the output, INV2 is the inverting input, and NINV2 is the non-inverting input of Op-Amp #2. The positive and negative supply pins. The total power supply range is 5V to 14V. Decoupling these pins with 0.1. 2F capacitors is highly racommended. A CMOS Schmitt-trigger input to be used with an external CMOS logic level clock. Also used for self-clocking Schmitt-trigger oscillator (see section 1.1). A TTL logic level clock input when in split supply operation (+2.5V to +7V) and L. Sh tied to system ground. This pin becomes a low impedance output when L. Sh is tied to V. Also used in conjunction with the CLK IN pin for a self clocking Schmitt-trigger oscillator (sea section 1.1). Level shift pin, selects the logic threshold levals for the desired clock. When tied to V7 it enables an internal tri-state buffer stage between the Schmitt trigger and the internal clock level shift stage thus enabling the CLK IN Schmitt- trigger input and making the CLK R pin a low impedance output.Pin Descriptions (in Numbers) (Continued) Pin Description L. Sh (12) When the voitage level at this input exceeds [25% (Vt V-) + V-] the internal tri-state buffer is disabled allowing the CLK R pin to become the clock input for the internal ciock level shift stage. The CLK R threshold level is now 2V above the voltage applied to the L. Sh pin. Driving the CLK R pin with TTL logic lavels can be accomplished through the use of split supplies and by tying the L. Sh pin to system ground. 1.0 MF6 Application Hints The MF6 is comprised of a non-inverting unity gain lowpass sixth order Butterworth switched capacitor filter section and two undedicated CMOS Op-Amps. The switched capacitor topology makes the cutoff frequency (where the gain drops 3.01 dB below the DC gain) a direct ratio (100:1 or 50:1) of the clock frequency supplied to the lowpass filter. Internal integrator time constants set the filter's cutoff frequency. The resistive element of these integrators is actually a ca- pacitor which is switched at the clack frequency (for a detailed discussion see Input impedance Section). Varying the clock frequency changes the value of this resistive ele- ment and thus the time constant of the integrators. The clock to cutoff frequency ratio (fcLk/f,) is set by the ratio of the input and feedback capacitors in the integrators. The higher the clock to cutoff frequency ratio (or the sampling rate) the closer this approximation is to the theoretical But- terworth response. The MF6 is available in fo_K/f, ratios of 60:1 (MF6-50) or 100:1 (MF6-100). 1.1 CLOCK INPUTS The MF6 has a Schmitt-trigger inverting buffer which can be used to construct a simple R/C oscillator. The oscillators frequency is dependent on the buffer's threshold levels as well as on the resistor/capacitor tolerance (see Figure 7). {| a ANA to V= 1 ta. = ___________ it a RC inf (HoH | 2] = CLK IN CLK R L SH Vo V+ /r- 9 11 12 Typically for Veg = V+ - - = 10: . 1 {clk Te9RG LEVEL TRESTATE SHIFT = BUFFER STAGE MFE TL/H/5065-12 FIGURE 1. Schmitt Trigger R/C Oscillator iY ar NANV2 44 1 14, INV2 N.INV2 11 14} INV2 Vor42 13 INV! Yon 42 13 INV L.Sh L.Sh FILTER OUT 43 2 FILTER OUT 43 2 sy v CLKR y, R sono | Ty sono | " re UL ov + 5 19 -5.0V #5.0V 5 10 =O -5.0V OV vt cuKIN| pip #5 5.0V vt CLKIN Li oT VasA0T | FLTER| OY T Vos 40s | *L FULTER 7 8 r iy 7 8 F 0.1 pF 0.1 uF = O.1uF | 0.1 uF TL/H/5085-3 TL/AH/5065-4 FIGURE 2. Dual Supply Operation MF6 Driven with CMOS Logic Level Clock (Vin 2 0.8 Vee and Vi. < 0.2 Vee where Voc = V+ - V-) FIGURE 3. Dual Supply Operation MF6 Driven with TTL Logic Level Clock 94INMF6 Application Hints (continued) 4 Vog ADJ 0.1 pF 7 ov PS _-- MF6 + 6TH ORDER #10V rm >| BUTTERWORTH a 2 rer 2 FILTER 3 $ FILTER FILTER 1oka $ IN z OUT +{}; AGND < 0.1 uF 2 10ka oO LEVEL SHET . 7 2 : | 12h Voz r oO n TRESTATE = 14 BUFFER INV2 1 O] CLKR ninve | Eon # 7 a LK IN 4 13 6 10 Yor inv 4 Ve Ye +410 0.4 uF] a) Resistor Biasing of AGND Oo Vos ADI 7 MF6 + 6TH ORDER *5V Prey +++ p>] BUTTERWORTH 7) 8 FILTER 3 FILTER FILTER iN aS out +1}; AGND +H LEVEL SHET 2 | 12 Yoo 7 LSh are {] "1 CLKR aad " BL) SUL : : 9 4 13 6 10. (AKIN cuos You INV I ve V- LEVELS + 10V o.1uF] b) Using Op-Amp 2 to Buffer AGND FIGURE 4. Single Supply Operation TL/H/5065-14 10V ov TLYH/5065-15 1-144Application Hints (continue) 24k0 5ka 22ka Ve OA Anne V4 FILTER (CJ FILTER IN Vg ADJ OUT 8 ? 3 vy 6TH ORDER >] BUTTERWORTH FILTER M6 (a) TL/H/5065-16 330 ko 7] INVI Vor C > a0) Sle 7 FIGURE 5. Vos Adjust Schemes Schmitt-trigger threshold voltage levels can change signifi- cantly causing the R/C oscillators frequency to vary greatly from part to part. Where accuracy in f, is required an external clock can be usedto drive the CLK A input of the MF6. This input is TTL logic level compatible and also presents a very light load to the external clock source (~ 2 1A) with split supplies and L. Sh tied to system ground. The iogic level is programmed by the voltage applied to level shift (L. Sh) pin (See the Pin description for L. Sh pin). 1.2 POWER SUPPLY BIASING The MF6 can be biased from a single supply or dual split supplies. The split supply mode shown in Figures 2 and 2 is the most flexible and easiest to implement. As discussed earlier split supplies, +5V to +7V, will enable the use of TTL or CMOS clock logic levels. Figure 4 shows two schemes for single supply biasing. In this mode only CMOS clock logic levels can be used. 1.3 OFFSET ADJUST The VosADJ pin is used in adjusting the output offset level of the filter section. If this pin is not used it must be tied to the analog ground (AGND) level, either mid-supply for single ended supply operation or ground for split supply operation. This pin sets the zero reference for the output of the filter. The implementation of this pin can be seen in Figure . In 5(a), DC offset is adjusted using a potentiometer; in 5(b), the Op-Amp integrator circuit keeps the average DC output lev- el at AGND. The circuit in 5(b) is therefore appropriate only for AC-coupled signals and signals biased at AGND. 1.4 INPUT IMPEDANCE The MF6 lowpass filter input (FILTER IN pin) is not a high impedance buffer input. This input is a switched capacitor resister equivalent, and its effective impedance is inversely proportional to the clock frequency. The equivalent circuit of the input to the filter can be seen in Figure 6. The input capacitor charges to the input voltage (Vj,) during one half of the clock period, during the second half the charge is 8 3 13 6TH ORDER LJ BUTTERWORTH FILTER OP-AMP #1 AGND (b) TLYH/5065-17 FILTER 5 Aap INPUT R _.. IN AGND TL/H/S065-18 a) Equivalent Circuit for MF6 Filter Input NONOVERLAPPING CLOCKS By %, il iT FILTER INPUT Cu _ t Rw=et IN Gifouk | AGND ' TL/H/5065-19 b) Actual Circult for MF6 Filter Input FIGURE 6. MF6 Filter Input transferred to the feedback capacitor. The total transfer of charge in one clock cycle is therefore Q = Ci_Vin, and since current is defined as the flow of charge per unit time the average input current becomes lin = Q/T (where T equals one clock period) or lin = TT = CinVinfcik The equivalent input resistor (Rj,) then can be defined as 1 Cinfoix The input capacitor is 2 pF for the MF6-50 and 1 pF for the Rin = Vin lin = 1-145 9INMF6 Application Hints (continueg) MF6-100, so for the MF6-100 _ 1x 1012 1x 1012 1x 1010 Ri = = = n foux fo X 100 fe and rR, x1011 & x 1011 1% 1010 i" fouk fo x 50 fo for the MF6-50. As shown in the above equations for a given cutoff frequency (f,) the input impedance remains the same for the MF6-50 and the MF6-100. The higher tha clock to center frequency ratio, the greater equivalent input resist- ance for a given clock frequency. As the cutoff frequency increases the equivalent input impedance decreases. This input resistance will form a voltage divider with the source impedance (Asourea). Since Rin is inversely proportional to the cutoff frequency, operation at higher cutoff fraquencies will be more likely to load the input signal which would ap- par as an overall decrease in gain to the output of the filter. Since the filter's ideal gain is unity its overall gain is given by: Rin Pin + Asource If the MF6-50 or tha MF6-100 were set up for a cutoff fre- quency of 10 kHz the input impedance would be: Ay R,, = 1X 1010 N10 kHz in this example with a source impedance of 10k the overall gain, if the MF6 had an ideal gain of 1 or 0 dB, would be: _ 1Mo " 10k + 1M0 =1Mn = 0.99009 or 86.4 mdB AMPLITUDE (dB) & a a FREQUENCY (Hz) TL/H/5065-20 FIGURE 7a. MF6-100 +5V Supplies Ampiltude Response 10 0 AMPLITUDE (48) 2sabhbas 10 10 1K 1K FREQUENCY (Hz) TLH/5085-22 FIGURE 7c. MF6-100 + 2.5V Supplies Amplitude Response Since the maximum overall gain error for the MF6 is +0.3 cB with a Rg < 2k? the actual gain error for this case would be +0.21 dB to 0.39 dB. 1.6 CUTOFF FREQUENCY RANGE The filter's cutoff frequency (f,) has a lower limit caused by leakage currents through the internal switches discharging the stored charge on the capacitors. At lower clock frequen- cies these leakage currents can cause millivolts of error, for example: foLk = 100 Hz, leakage = 1pA,G = 1 pF _ 1pA 1 pF (100 Hz) The propagation delay in the logic and the settling time re- quired to acquire a new voltage lavel on the capaciters in- creases as the MF6 power supply voltage decreases. This causes a shift in the fo_K/f, ratio which will become notice- able when the clock frequency exceeds 250 kHz. The ampli- tude characteristic will stay within tolerance until foi 6x- ceeds 600 kHz and will peak at about 0.5 dB at the corner frequency with a 1 MHz clock. The response of the MF6 Is still a reasonable approximation of the ideal Butterworth lowpass characteristic as can be seen in Figure 7. 2.0 Designing with the MF6 Given any lowpass filter specification two equations will come in handy in trying to determine whether the MF6 will do the job. The first equation determines the order of the lowpass filter required: = 10mv y= (09,(10%1 Amin 1) tog (1091 Amax1) (1) 2 log (fs/fp) o o AMPLITUDE (48) #aeebad 10 100 1K 1K FREQUENCY (Hz) TL/H/5065-21 FIGURE 7b. MF6-50 + 5V Supplies Amplitude Response g FREQUENCY (Hz) TL/H/5085-23 FIGURE 7d. MF6-50 + 2.5V Supplies Amplitude Response 1-146Designing with the MF6 (continueg) where n is the order of the filter, Amin is the minimum stop- band attenuation (in dB) desired at frequency fs, and Ama, is the passband ripple or attenuation (in dB) at frequency fp. If the result of this equation is greater than 6, then more than a single MF6 is required. The attenuation at any frequency can be found by the fol- lowing equation: Attni(f) = where n = 10 log [1 + (101Amax 4) (/f,)2] dB 6 (the order of the filter). 2.1 A LOWPASS DESIGN EXAMPLE Suppose the amplitude response specification in Figure 4 is given. Can the MF6 be used? The order of the Butterworth approximation will have to be determined using ea. 1: Amin = 30 dB, Amax = 1.0 dB, fs = 2 kHz, and fy = 1 kHz (2) n= log (109 1} log(100-1 1) 2 log(2) Since n can only take on integer values, n = 6. Therefore the MF6 can be used. In general, ifn is 6 or less a single MF6 stage can be utilized. Likewise, the attenuation at f, can be found using equation 2 with the above values and n = 6 giving: Atten (2 kHz) = 10 log [1 + (100-1 1) (2 kHz/1 kHz)12] = 30.26 dB This result also meets the design specification given in Fig- ure 8 again verifying that a single MF6 section will be ade- quate. = 5.96 ANN NS -o AMPLITUDE (dB) z 3 Aun= e350 -- rrr rrr f= 1k FREQUENCY (Hz) TL/H/S065- 24 FIGURE 8. Design Example Magnitude Response Specification Where the Response of the Filter Design Must Fall Within the Shaded Area of the Specification Since the MF6s cutoff frequency f,, which corresponds to a gain attenuation of 3.01 dB, was not specified in this ex- ample it needs to be calculated. Solving equation 2 where f = f, as follows: ' [coer dB) 4)]1/(2n) ~ 'b (100-1 Amax 4) +k eee uy 714007 4 = 1.119 kHz where f, = foik/50 or fo_K/ 100. To implement this example for tha MF6-50 the clock fre- quency will have to be set to fo_K = 50(1.116 kHz) = 55.8 kHz or for the MF6-100 fo_x = 100(1.116 kHz) = 111.6 kHz. 2.2 CASCADING MFs In the case where a steeper stopband attenuation rate is required two MF6s can be cascaded (Figure 9) yielding a 12th order slope of 72 dB per octave. Because the MF6 is a Butterworth filter and therefore has no ripple in its pass- band, when MFs are cascaded the resulting filter also has no ripple in its passband. Likewise the DC and passband gains will remain at 1V/V. The resulting response is shown in Figure 10. In determining whether the cascaded MF6s will yield a filter that will meet a particular amplitude response specification, as above, equations 3 and 4 can be used, shown below. 1 = 129 (109-05 Amin 1) log (100-05 Amax 1) 2 tog (fs/ fy) Attn(f} = 10 log [1 + (109-05 Amax 1) (/4,)2n] dB where n = 6 (the order of each filter). Equation 3 will determine whether the order of the filter is adequate (n < 6) while equation 4 can determine if the required stopband attenuation is met and what actual cutoff frequency (f,) is required to obtain the particular frequency response desired. The design procedure would be identical to the one shown in section 2.1. 2.3 IMPLEMENTING A NOTCH FILTER WITH THE MF6 A notch filter with 60 dB of attenuation can be obtained by using one of the Op-Amps, available in the MF6, and three external resistors. The circuit and amplitude response are shown in Figure 77. The frequency where the notch will occur is equal to the frequency at which the output signal of the MF6 will have the same magnitude but be 180 degrees out of phase with its input signal. For a sixth order Butterworth filter 180 phase shift occurs where f = fp = 0.742 f.. The attenuation at this frequency is 0.12 dB which must be compensated for by making Ry = 1.014 X Ro. Since R; does not equal Ro there will be a gain inequality above and below the notch frequency. At frequencies below the notch frequency (f << fp), the signal through the filter has a gain of one and is non-inverting. Summing this with the input signal through the Op-Amp yields an overall gain of two or +6 dB. Forf >> f,, the signal at the output of the filter is greatly attenuated thus only the input signal will ap- pear at the output of the Op-Amp. With Rg = Ry = 1.014 Ro the overall gain is 0.986 or 0.12 dB at frequencies above the notch. (3) (4) 1-147 o4NMF6 Designing with the MF6 (continue) MFE MF6 8 3 8 5 O -O FILTER FILTER FILTER FILTER IN ouT IN OUT VosADJ acno ish vt CLKR VosADJ agno ish VP Vv" CLKR 7 5 |" 6 1 671 7 i 12 [6 10 711 = Of pF vi=45 0 T 0.1 pF =+5V0 t fork > TTL LOGIC LEVELS TL/H/5065-25 FIGURE 9. Cascading Two MF6s 10 0 ety 10 e -2 wo o fog, = 50 kHz = = 214390 Vog=*= 7= 10V 2 ; =< 97 < =360 - a a =5.40 6 0.5k 1.0k 15k 2.0k 0 al 1 5 Ww FREQUENCY (Hz) TL/H/5065-27 FREQUENCY (kHz) TL7H/5065-26 FIGURE 10a. One MF6-50 vs. Two MF6-50s Cascaded FIGURE 10b. Phase Response of Two Cascaded MF6-50s 1-148941 Designing with the MF6 (continue 0 Vos ADJ 7 MFG rm ertin Ohoeka rr. a 5 baw FILTER FILTER FILTER IN $ out acnp > = LEVEL SHFT \ Os 12 Yon LSh TRESTATE ~ O- 2 5Y 14 i BUFFER INV2 7 {} < ov faux CLKR nn | fi 9 CLK IN SIGHAL p 4 INPUT 4 NOTCH FILTER OUTPUT TLIH/5065-28 FIGURE 11a. Notch Filter +10 v=t i] toy_= 1OkHz ~10 AMPLITUDE. (dB) & 30 0 0 10 50 100 500 1K FREQUENCY (Hz) TL/H/506529 FIGURE 11b. MF6-50 Notch Filter Amplitude Response 1-149MF6 Designing with the MF6 (continued) 2.4 CHANGING CLOCK FREQUENCY INSTANTANEOUSLY The MF6 will respond favorably to a sudden change in clock frequency. Distortion in the output signal occurs at the tran- sition of the clock frequency and lasts approximately three cutoff frequency (f,) cycles. As shown in Figure 12, if the control signal is low the MF6-50 has a 100 kHz clock mak- ing fg = 2 kHz; when this signal goes high the clock fre- quency changes to 50 kHz yielding 1 kHz fg. The transient response of the MF6 seen in Figure 77 is also dependent on the f, and thus the fo. applied to the filter. The MF6 responds as a classical sixth order Butterworth lowpass filter. TL/H/5065-31 FIGURE 13. MF6-50 Step Input Response, Vertical = 2V/div., Horizontal = 1 ms/div., fo.x = 100 kHz the input signal contains a component at a frequency higher than half the clock frequency, as in Figure 74a, that compo- nent will be reflected about fc_K/2 into the frequency range below fo. K/2 as in Figure 746. lf this component is within the passband of the filter and of large enough ampli- tude it can cause problems. Therefore if frequency compo- nents in the input signal exceed fo_/2 they must be attenu- ated before being applied to the MF6 input. The necessary amount of attenuation will vary depending on system re- quirements. In critical applications the signal components TLAH/5065-30 above fc. /2 will have to be attenuated at least to the fil- fin = 1.5 kHz (scope time base = 2 ms/div) ters residual noise level. An example circuit is shown in FIGURE 12. MF6-50 Abrupt Clock Frequency Change Figure 15 using one of the uncommitted Op-Amps available 2.5 ALIASING CONSIDERATIONS in the MF6. Aliasing effects have to be taken into consideration when input signal frequencies exceed half the sampling rate. For the MF6 this equals half the clock frequency (fco_k). When AMPLITUDE AMPLITUDE fot, tL ttl qT ts fs 4 ts fy 8 fs 4 's 2 2 2 2 2 FREQUENCY FREQUENCY TL/H/5065-37 TL/H/5066-38 (a) Input Signal Spectrum (b) Output Signal Spectrum. Note that the input signal at f,/2 + f{ causes an output signal to appear at f,/2 f. Figure 14. The phenomenon of aliasing in sampled-data systems. An input signal whose frequency is greater than one- half the sampling frequency will cause an output to appear at a frequency lower than one-half the sampling frequency. In the MF6, fs = fcLik- 1-150Designing with the MF6 (Continued) (1) Vos AD) 7 MF6 $ 6TH ORDER + 7} >] BUTTERWORTH { } Vout rer FILTER 5 FILTER FILTER IN F OUT CI} 5 AGND c2 == oR UE ST Ly Uw 120 Sh Yoo >| " TRESTAIE {} 1s f2 BUFFER INV2 7 y Rt R2 CLER IN See AA Wie =v vv LI it 2 NINZ RB ct i g C 4 13 CLK IN = Vor INV t TL/H/5065~34 { om 2h Aaeica Ho = Ra/Rg (Ha = 1 when Rg and Rg are omitted and Vgp is directly tied to INV2). Design Procedure: pick C, _ 4 - 20C 109 for a 2nd Order Butterworth Q = 0.707 0.113 2 Cite make A, = Rp and Ra 1 C2 (2rrfpRy2C, Note: The paraliel combination of Ay (if used}, Ry and Rg should be = 10 kit In order not to load Op-Amp #2. FIGURE 15. Second Order Butterworth Anti-Aliasing Fitter Using Uncommitted Op-Amp #2 1-751 93IN