Preliminary
This is a product that has fixed target specifications but are
Ramtron International Corporation
subject to change pending characterization results.
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.1
http://www.ramtron.com
Apr. 2011 Page 1 of 15
FM21LD16
2Mbit F-RAM Memory
Features
2Mbit Ferroelectric Nonvolatile RAM
• Organized as 128Kx16
• Configurable as 256Kx8 Using /UB, /LB
• 10
14
Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
SRAM Compatible
• JEDEC 128Kx16 SRAM Pinout
• 60 ns Access Time, 110 ns Cycle Time
Advanced Features
• Software Programmable Block Write Protect
Superior to B a ttery-backed SRAM Modules
• No Battery Concerns
• Monolithic Reliability
• True Surface Mount Solution, No Rework Steps
• Superior for Moisture, Shock, and Vibration
Low Power Operation
• 2.7V – 3.6V Power Supply
• Low Standby Current (90µA typ.)
• Low Active Current (8 mA typ.)
Industry Sta ndard Configuration
• Industrial Temperature -40° C to +85° C
• 48-ball “Green”/RoHS FBGA package
• Pin compatible with FM22LD16 (4Mb) and
FM23MLD16 (8Mb)
Description
The FM21LD16 is a 128Kx16 nonvolatile memory
that reads and writes like a standard SRAM. A
ferroelectric random access memory or F-RAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make the
F-RAM superior to other types of memory.
In-system operation of the FM21LD16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The F-RAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM21LD16 ideal
for nonvolatile memory applications requiring
frequent or rapid writes in the form of an SRAM.
The FM21LD16 includes a low voltage monitor that
blocks access to the memory array when V
DD
drops
below V
DD
min. The memory is protected against an
inadvertent access and data corruption under this
condition. The device also features software-
controlled write protection. The memory array is
divided into 8 uniform blocks, each of which can be
individually write protected.
The device is available in a 48-ball FBGA package.
Device specifications are guaranteed over industrial
temperature range –40°C to +85°C.
Pin Configuration
/LB /OE A0 A1 A2 NC
DQ8 /UB A3 A4 /CE DQ0
DQ9 DQ10 A5 A6 DQ1 DQ2
VSS DQ11 NC A7 DQ3 VDD
VDD DQ12 NC A16 DQ4 VSS
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 NC A12 A13 /WE DQ7
NC A8 A9 A10 A11 NC
123456
A
B
C
D
E
F
G
H
Top View (Ball Down)
Ordering Information
FM21LD16-60-BG 60 ns access, 48-ball
“Green”/RoHS FBGA
FM21LD16-60-BGTR 60 ns access, 48-ball
“Green”/RoHS FBGA,
Tape & Reel
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 2 of 15
Address Latch & Write Protect
Block & Row Decoder
Figure 1. Block Diagram
Pin Description
Pin Name Type Pin Description
A(16:0) Input Address inputs: The 17 address lines select one of 131,072 words in the F-RAM array. The
lowest two address lines A(1:0) may be used for page mode read and write operations.
/CE Input Chip Enable input: The device is selected and a new memory access begins when /CE is
low. The entire address is latched internally on the falling edge of /CE. Subsequent changes
to the A(1:0) address inputs allow page mode operation when /CE is low.
/WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
/OE Input Output Enable: When /OE is low, the FM21LD16 drives the data bus when valid read data is
available. Deasserting /OE high tri-states the DQ pins.
DQ(15:0) I/O Data: 16-bit bi-directional data bus for accessing the F-RAM array.
/UB Input Upper Byte Select: Enables DQ(15:8) pins during reads and writes. Deasserting /UB high
tri-states the DQ pins. If the user does not perform byte writes and the device is not
configured as a 256Kx8, the /UB and /LB pins may be tied to ground.
/LB Input Lower Byte Select: Enables DQ(7:0) pins during reads and writes. Deasserting /LB high tri-
states the DQ pins. If the user does not perform byte writes and the device is not configured
as a 256Kx8, the /UB and /LB pins may be tied to ground.
VDD Supply Supply Voltage
VSS Supply Ground
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 3 of 15
Functional Trut h Table
1,2
/CE /WE A(16:2) A(1:0) Operation
H X X X Standby/Idle
↓ H V V Read
L H No Change Change Page Mode Read
L H Change V Random Read
↓ L V V /CE-Controlled Write
L ↓ V V /WE-Controlled Write
2
L ↓ No Change V Page Mode Write
3
↑ X X X Starts Precharge
Notes:
1) H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
2) /WE-controlled write cycle begins as a Read cycle and A(16:2) is latched then.
3) Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.
4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
Byte Select Trut h Table
/WE /OE /LB /UB Operation
H H X X
Read; Outputs Disabled
X H H
H L H L Read upper byte; Hi-Z lower byte
L H Read lower byte; Hi-Z upper byte
L L Read both bytes
L X H L Write upper byte; Mask lower byte
L H Write lower byte; Mask upper byte
L L Write both bytes
The /UB and /LB pins may be grounded if 1) the system does not perform byte writes and
2) the device is not configured as a 256Kx8.
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 4 of 15
Overview
The FM21LD16 is a wordwide F-RAM memory
logically organized as 131,072 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(16:2) changes.
Memory Operation
Users access 131,072 memory locations, each with 16
data bits through a parallel interface. The F-RAM
array is organized as 8 blocks each having 4096 rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to F-RAM called NoDelay
TM
writes.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM21LD16’s /CE-initiated access time is faster than
the address cycle time.
The FM21LD16 will drive the data bus when /OE
and at least one of the byte enables (/UB, /LB) is
asserted low. The upper data byte is driven when /UB
is low, and the lower data byte is driven when /LB is
low. If /OE is asserted after the memory access time
has been satisfied, the data bus will be driven with
valid data. If /OE is asserted prior to completion of
the memory access, the data bus will not be driven
until valid data is available. This feature minimizes
supply current in the system by eliminating transients
caused by invalid data being driven onto the bus.
When /OE is deasserted high, the data bus will
remain in a high-Z state.
Write Operation
Writes occur in the FM21LD16 in the same time
interval as reads. The FM21LD16 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address A(16:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM21LD16 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The F-RAM array is organized as 8 blocks each
having 4096 rows. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A(1:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins no later than t
AAP
, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 5 of 15
along with a new column address provides a page
mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time t
PC
.
Precharge is also activated by changing the upper
addess A(16:2). The current row is first closed prior
to accessing the new row. The device automatically
detects an upper order address change which starts a
precharge operation, the new address is latched, and
the new read data is valid within the t
AA
address
access time. Refer to the Read Cycle Timing 1
diagram on page 10. Likewise a similar sequence
occurs for write cycles. Refer to the Write Cycle
Timing 3 diagram on page 12. The rate at which
random addresses can be issued is t
RC
and t
WC
,
respectively.
Software Write Protection
The 128Kx16 address space is divided into 8 sectors
(blocks) of 16Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 16K x16 blocks
Sector 7 1FFFFh – 1C000h
Sector 6 1BFFFh – 18000h
Sector 5 17FFFh – 14000h
Sector 4 13FFFh – 10000h
Sector 3 0FFFFh – 0C000h
Sector 2 0BFFFh – 08000h
Sector 1 07FFFh – 04000h
Sector 0 03FFFh – 00000h
The write-protect read address sequence follows:
1. 12555h *
2. 1DAAAh
3. 01333h
4. 0ECCCh
5. 000FFh
6. 1FF00h
7. 1DAAAh
8. 0ECCCh
9. 0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 12555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 10
32
chance of randomly accessing
exactly the 1
st
six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 6 of 15
Figure 2. Write-Protect State Machine
For example, the following sequence write-protects addresses from 0C000h to 13FFFh (sectors 3 & 4):
Address Data
Read 12555h -
Read 1DAAAh -
Read 01333h -
Read 0ECCCh -
Read 000FFh -
Read 1FF00h -
Write 1DAAAh 18h ; bits 3 & 4 = 1
Write 0ECCCh E7h ; complement of 18h
Write 0FF00h - ; Data is don’t care
Read 00000h - ; return to Normal Operation
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 7 of 15
Figure 3. Sequence to Set Write-Protect Blocks
Note: This sequence requires t
AS
≥ 10ns and address must be stable while /CE is low.
Figure 4. Sequence to Read Write-Protect Settings
Note: This sequence requires t
AS
≥ 10ns and address must be stable while /CE is low.
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 8 of 15
SRAM Drop-In Replacement
The FM21LD16 has been designed to be a drop-in
replacement for standard asynchronous SRAMs. The
device does not require /CE to toggle for each new
address. /CE may remain low for as long as 10µs.
While /CE is low, the device automatically detects
address changes and a new access is begun. It also
allows page mode operation at speeds up to 33MHz.
The user must be sure /CE is not low at powerup
or powerdown events. If /CE and /WE are both
low during power cycles, data corruption will
occur. Figure 6 shows a pullup resistor on /CE
which will keep the pin high during power cycles
assuming the MCU/MPU pin is tri-stated during
the system reset. The pullup resistor value should
be chosen to ensure the /CE pin tracks V
DD
yet a
high enough value that the current drawn when
/CE is low is not an issue. A 10K ohm resistor
draws 330µA when /CE is low and V
DD
=3.3V.
Figure 5. Use of Pullup Resistor on /WE
For applications that require the lowest power
consumption, the /CE signal should be active only
during memory accesses. The FM21LD16 draws
supply current while /CE is low, even if addresses and
control signals are static. While /CE is high, the
device draws no more than the maximum standby
current I
SB
.
The FM21LD16 is backward compatible with the
1Mbit FM20L08 and 256Kbit FM18L08 devices.
That is, operating the FM21LD16 with /CE toggling
low on every address is perfectly acceptable. In terms
of package and pinout, the FM21LD16 is upward
compatible with the FM22LD16 (4Mb).
The /UB and /LB byte select pins are active for both
read and write cycles. They may be used to allow the
device to be wired as a 256Kx8 memory. The upper
and lower data bytes can be tied together and
controlled with the byte selects. Individual byte
enables or the next higher address line A(17) may be
available from the system processor.
Figure 6. FM21LD16 Wired as 256Kx8
CE
WE
OE
A(16:0)
DQ
FM21LD16
V
DD
MCU/
MPU
R
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 9 of 15
Electrical Specifications
A bsolute Maximum Ratings
Symbol Description Ratings
V
DD
Power Supply Voltage with respect to V
SS
-1.0V to +4.5V
V
IN
Voltage on any signal pin with respect to V
SS
-1.0V to +4.5V and
V
IN
< V
DD
+1V
T
STG
Storage Temperature -55°C to +125°C
T
LEAD
Lead Temperature (Soldering, 10 seconds) 260° C
V
ESD
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-F)
- Charged Device Model (JEDEC Std JESD22-C101-D)
- Machine Model (JEDEC Std JESD22-A115-A)
2.5kV
800V
200V
Package Moisture Sensitivity Level MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
V
DD
Power Supply 2.7 3.3 3.6 V
I
DD
Power Supply Current 8 12 mA 1
I
SB
Standby Current
@ T
A
= 25°C
@ T
A
= 85°C
90
-
150
270
µA
µA
2
I
LI
Input Leakage Current ±1 µA 3
I
LO
Output Leakage Current ±1 µA 3
V
IH
Input High Voltage 2.2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.6 V
V
OH1
Output High Voltage (
I
OH
= -1.0 mA)
2.4 V
V
OH2
Output High Voltage (
I
OH
= -100 µA)
V
DD
-0.2 V
V
OL1
Output Low Voltage (
I
OL
= 2.1 mA)
0.4 V
V
OL2
Output Low Voltage (
I
OL
= 100 µA)
0.2 V
Notes
1.
V
DD
= 3.6V, /CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or V
DD
-0.2V), all DQ pins unloaded.
2.
V
DD
= 3.6V, /CE at V
DD
, All other pins are static and at CMOS levels (0.2V or V
DD
-0.2V).
3.
V
IN
, V
OUT
between V
DD
and V
SS
.
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 10 of 15
Read Cycle AC Parameters (T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
RC
Read Cycle Time 110 - ns
t
CE
Chip Enable Access Time - 60 ns
t
A
A
Address Access Time - 110 ns
t
OH
Output Hold Time 20 - ns
t
AAP
Page Mode Address Access Time - 25 ns
t
OHP
Page Mode Output Hold Time 5 - ns
t
C
A
Chip Enable Active Time 60 10,000 ns
t
PC
Precharge Time 50 - ns
t
B
A
/UB, /LB Access Time - 20 ns
t
AS
Address Setup Time (to /CE low) 0 - ns
t
AH
Address Hold Time (/CE-controlled) 60 - ns
t
OE
Output Enable Access Time - 15 ns
t
HZ
Chip Enable to Output High-Z - 10 ns 1
t
OHZ
Output Enable High to Output High-Z - 10 ns 1
t
BHZ
/UB, /LB High to Output High-Z - 10 ns 1
Write Cycle AC Parameters (T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
WC
Write Cycle Time 110 - ns
t
C
A
Chip Enable Active Time 60 10,000 ns
t
CW
Chip Enable to Write Enable High 60 - ns
t
PC
Precharge Time 50 - ns
t
PWC
Page Mode Write Enable Cycle Time 25 - ns
t
WP
Write Enable Pulse Width 16 - ns
t
AS
Address Setup Time (to /CE low) 0 - ns
t
ASP
Page Mode Address Setup Time (to /WE low) 8 - ns
t
AHP
Page Mode Address Hold Time (to /WE low) 15 - ns
t
WLC
Write Enable Low to /CE High 25 - ns
t
BLC
/UB, /LB Low to /CE High 25 - ns
t
WL
A
Write Enable Low to A(16:2) Change 25 - ns
t
AWH
A(16:2) Change to Write Enable High 110 - ns
t
DS
Data Input Setup Time 14 - ns
t
DH
Data Input Hold Time 0 - ns
t
WZ
Write Enable Low to Output High Z - 10 ns 1
t
WX
Write Enable High to Output Driven 10 - ns 1
t
WS
Write Enable to /CE Low Setup Time 0 - ns 2
t
WH
Write Enable to /CE High Hold Time 0 - ns 2
Notes
1 This parameter is characterized but not 100% tested.
2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters t
WS
and t
WH
are not tested.
Capacitance (T
A
= 25° C , f=1 MHz, V
DD
= 3.3V)
Symbol Parameter Min Max Units Notes
C
I/O
Input/Output Capacitance (DQ) - 8 pF
C
IN
Input Capacitance - 6 pF
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 11 of 15
Power Cycle Timing (T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
PU
Power-Up (after V
DD
min. is reached) to First Access Time 450 - µs
t
PD
Last Write (/WE high) to Power Down Time 0 - µs
t
VR
V
DD
Rise Time 50 - µs/V 1,2
t
VF
V
DD
Fall Time 100 - µs/V 1,2
Notes
1 Slope measured at any point on V
DD
waveform.
2 Ramtron cannot test or characterize all V
DD
power ramp profiles. The behavior of the internal circuits is difficult to predict
when V
DD
is below the level of a transistor threshold voltage. Ramtron strongly recommends that V
DD
power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (V
DD
= 2.7V to 3.6V)
Parameter Min Units Notes
Data Retention 10 Years
AC Test Conditions
Input Pulse Levels 0 to 3V Input and Output Timing Levels 1.5V
Input Rise and Fall Times 3 ns Output Load Capacitance 30pF
Read Cycle Timing 1 (/CE low, /OE low)
Read Cycle Timing 2 (/CE-controlled)
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 12 of 15
Page Mode Read Cycle Timing
Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled)
Note: /OE (not shown) is low only to show effect of /WE on DQ pins
Write Cycle Timing 2 (/CE-Controlled)
CE
A(16:0)
WE
DQ(15:0)
tWS
tAS
tWH
tDH
tDS
D in
tCA tPC
UB/LB
tBLC
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 13 of 15
Write Cycle Timing 3 (/CE low)
Note: /OE (not shown) is low only to show effect of /WE on DQ pins
Page Mode Write Cycle Timing
Although sequential column addressing is shown, it is not required.
Power Cycle Timing
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 14 of 15
Mechanical Drawing
48-ba ll F BGA (0.7 5mm ball pitch)
Note: All dimensions in millimeters.
48 FBGA Package Marking Scheme
Legend:
XXXXXX= part number, S=speed, P=package
LLLLLL= lot code, YY=year, WW=work week
Examples: FM21LD16, 60ns access time, “Green”/RoHS FBGA package,
Lot C8556953BG1, Year 2009, Work Week 38
RAMTRON
FM21LD16-60-BG
C8556953BG1
0938
RAMTRON
XXXXXXX-S-P
LLLLLLL
YYWW
FM21LD16 - 128Kx16 FRAM
Rev. 1.1
Apr. 2011 Page 15 of 15
Revision History
Revision
Date
Summary
1.0 12/22/2009 Initial release.
1.1 4/11/2011 Added ESD ratings. Modified write-protect flow diagram and added read
sequence diagram. Made clarifications to Byte Select truth table. Added max.
CE active time.
