12-Bit, 125 MSPS Dual TxDAC+(R) Digital-to-Analog Converter AD9765 FEATURES FUNCTIONAL BLOCK DIAGRAM 12-bit dual transmit DAC 125 MSPS update rate SFDR to Nyquist @ 5 MHz output: 75 dBc Gain and offset matching: 0.1% Fully independent or single resistor gain control Dual-port or interleaved data On-chip 1.2 V reference 5 V or 3.3 V operation Power dissipation: 380 mW @ 5 V Power-down mode: 50 mW @ 5 V 48-lead LQFP DVDD WRT2 ACOM 1 LATCH PORT1 WRT1 AVDD DIGITAL INTERFACE 1 DAC IOUTA1 IOUTB1 REFERENCE REFIO FSADJ1 FSADJ2 GAINCTRL BIAS GENERATOR SLEEP AD9765 2 LATCH PORT2 CLK1 MODE 2 DAC IOUTA2 IOUTB2 CLK2 00619-001 DCOM Figure 1. APPLICATIONS Communications Base stations Digital synthesis Quadrature modulation GENERAL DESCRIPTION The AD9765 is a dual-port, high speed, 2-channel, 12-bit CMOS DAC. It integrates two high quality, 12-bit TxDAC+ cores, a voltage reference, and digital interface circuitry into a small, 48-lead LQFP. The AD9765 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9765 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9765 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The fullscale currents between each DAC are matched to within 0.1%. The AD9765 is manufactured on an advanced, low cost CMOS process. It operates from a single supply of 3.3 V to 5.0 V and consumes 380 mW of power. PRODUCT HIGHLIGHTS 1. The AD9765 is a member of a pin-compatible family of dual TxDACs providing 8-bit, 10-bit, 12-bit, and 14-bit resolution. 2. Dual 12-Bit, 125 MSPS DACs. A pair of high performance DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 3. Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. Low Power. Complete CMOS dual DAC function operates on 380 mW from a 3.3 V to 5.0 V single supply. The DAC fullscale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-Chip Voltage Reference. The AD9765 includes a 1.20 V temperature-compensated band gap voltage reference. 6. Dual 12-Bit Inputs. The AD9765 features a flexible dualport interface allowing dual or interleaved input data. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD9765 TABLE OF CONTENTS Features .............................................................................................. 1 Digital Inputs .............................................................................. 14 Applications....................................................................................... 1 DAC Timing................................................................................ 15 General Description ......................................................................... 1 Input Clock and Data Timing Relationship ........................... 16 Functional Block Diagram .............................................................. 1 Sleep Mode Operation............................................................... 17 Product Highlights ........................................................................... 1 Power Dissipation....................................................................... 17 Revision History ............................................................................... 2 Applying the AD9765 .................................................................... 18 Specifications..................................................................................... 3 Output Configurations .............................................................. 18 DC Specifications ......................................................................... 3 Differential Coupling Using a Transformer............................ 18 Dynamic Specifications ............................................................... 4 Differential Coupling Using an Op Amp................................ 18 Digital Specifications ................................................................... 5 Single-Ended, Unbuffered Voltage Output............................. 19 Absolute Maximum Ratings............................................................ 6 Single-Ended, Buffered Voltage Output Configuration........ 19 Thermal Resistance ...................................................................... 6 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 19 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Applications..................................................................................... 21 VDSL Applications Using the AD9765 ................................... 21 Terminology .................................................................................... 11 Using the AD9765 for Quadrature Amplitude Modulation (QAM) ......................................................................................... 21 Theory of Operation ...................................................................... 12 CDMA ......................................................................................... 23 Functional Description.............................................................. 12 Evaluation Board ............................................................................ 24 Reference Operation .................................................................. 13 General Description................................................................... 24 Gain Control Mode .................................................................... 13 Schematics................................................................................... 24 Reference Control Amplifier .................................................... 13 Evaluation Board Layout........................................................... 27 DAC Transfer Function ............................................................. 13 Outline Dimensions ....................................................................... 30 Analog Outputs........................................................................... 14 Ordering Guide............................................................................... 30 REVISION HISTORY 10/06--Rev. B to Rev. C Updated Format..................................................................Universal Changes to Figure 2.......................................................................... 5 Changes to Figure 3.......................................................................... 7 Changes to Functional Description Section ............................... 12 Changes to Figure 25 and Figure 26............................................. 15 Changes to Figure 28 and Figure 29............................................. 16 Changes to Power Dissipation Section ........................................ 17 Changes to Power and Grounding Considerations Section ..... 19 Changes to Figure 39...................................................................... 19 Changes to Figure 45...................................................................... 22 Changes to Evaluation Board Section.......................................... 24 Changes to Figure 47...................................................................... 24 Updated Outline Dimensions....................................................... 30 Changes to Ordering Guide .......................................................... 30 2/00--Rev. A to Rev. B 12/99--Rev. 0 to Rev. A 8/99--Revision 0: Initial Version Rev. C | Page 2 of 32 AD9765 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION DC ACCURACY 1 Integral Linearity Error (INL) TA = 25C TMIN to TMAX Differential Nonlinearity (DNL) TA = 25C TMIN to TMAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Gain Match Full-Scale Output Current 2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current 3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) 4 Digital Supply Current (IDVDD) 5 Supply Current Sleep Mode (IAVDD) Power Dissipation (5 V, IOUTFS = 20 mA) 4 Power Dissipation (5 V, IOUTFS = 20 mA) 5 Power Dissipation (5 V, IOUTFS = 20 mA) 6 Power Supply Rejection Ratio--AVDD 7 Power Supply Rejection Ratio--DVDD7 OPERATING RANGE Min 12 Typ Max Unit Bits -1.5 -2.0 0.4 +1.5 +2.0 LSB LSB -0.75 -1.0 0.3 +0.75 +1.0 LSB LSB +0.02 +2 +5 +1.6 +0.14 20.0 +1.25 % of FSR % of FSR % of FSR % of FSR dB mA V k pF 1.26 V nA 1.25 1 0.5 V M MHz 0 50 100 50 ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C -0.02 -2 -5 -1.6 -0.14 2.0 -1.0 0.25 1 0.1 100 5 1.14 1.20 100 0.1 3 2.7 5 5 71 5 8 380 5.5 5.5 75 7 15 12.0 410 420 450 mW -0.4 -0.025 +0.4 +0.025 mW % of FSR/V % of FSR/V -40 +85 C 450 1 Measured at IOUTA, driving a virtual ground. Nominal full-scale current, IOUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current use of <100 nA should drive any external load. 4 Measured at fCLK = 25 MSPS and fOUT = 1.0 MHz. 5 Measured at fCLK = 100 MSPS and fOUT = 1 MHz. 6 Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLK = 100 MSPS and fOUT = 40 MHz. 7 10% power supply variation. 2 Rev. C | Page 3 of 32 V V mA mA mA mA mW AD9765 DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLK) Output Settling Time (tST) (to 0.1%) 1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (90% to 10%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) Min Max 125 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLK = 100 MSPS; fOUT = 1.00 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output fCLK = 65 MSPS; fOUT = 1.00 MHz fCLK = 65 MSPS; fOUT = 2.51 MHz fCLK = 65 MSPS; fOUT = 5.02 MHz fCLK = 65 MSPS; fOUT = 14.02 MHz fCLK = 65 MSPS; fOUT = 25 MHz fCLK = 125 MSPS; fOUT = 25 MHz fCLK = 125 MSPS; fOUT = 40 MHz Spurious-Free Dynamic Range Within a Window fCLK = 100 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLK = 50 MSPS; fOUT = 5.02 MHz; 10 MHz Span fCLK = 65 MSPS; fOUT = 5.03 MHz; 10 MHz Span fCLK = 125 MSPS; fOUT = 5.04 MHz; 10 MHz Span Total Harmonic Distortion fCLK = 100 MSPS; fOUT = 1.00 MHz fCLK = 50 MSPS; fOUT = 2.00 MHz fCLK = 125 MSPS; fOUT = 4.00 MHz fCLK = 125 MSPS; fOUT = 10.00 MHz Multitone Power Ratio (Eight Tones at 110 kHz Spacing) fCLK = 65 MSPS; fOUT = 2.00 MHz to 2.99 MHz 0 dBFS Output -6 dBFS Output -12 dBFS Output -18 dBFS Output Channel Isolation fCLK = 125 MSPS; fOUT = 10 MHz fCLK = 125 MSPS; fOUT = 40 MHz 1 Typ 35 1 5 2.5 2.5 50 30 MSPS ns ns pV-s ns ns pA/Hz pA/Hz 70 81 77 72 70 81 79 78 68 55 67 60 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 80 90 88 88 88 dBc dBc dBc dBc -80 -78 -75 -75 Measured single-ended into 50 load. Rev. C | Page 4 of 32 Unit -70 dBc dBc dBc dBc 80 79 77 75 dBc dBc dBc dBc 85 77 dBc dBc AD9765 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage @ DVDD = 5 V Logic 1 @ DVDD = 3.3 V Logic 0 Voltage @ DVDD = 5 V Logic 0 @ DVDD = 3.3 V Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulse Width (tLPW, tCPW) Min Typ 3.5 2.1 5 3 0 Max 1.3 0.9 +10 +10 0 -10 -10 5 2.0 1.5 3.5 Timing Diagram tS tH DATA IN (WRT2) (WRT1/IQWRT) tLPW (CLK2) (CLK1/IQCLK) tPD Figure 2. Timing Diagram for Dual and Interleaved Modes Rev. C | Page 5 of 32 00619-002 tCPW IOUTA OR IOUTB Unit V V V V A A pF ns ns ns AD9765 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD DVDD ACOM AVDD MODE, CLK1, CLK2, WRT1, WRT2 Digital Inputs IOUTA1/IOUTA2, IOUTB1/IOUTB2 REFIO, FSADJ1, FSADJ2 GAINCTRL, SLEEP Junction Temperature Storage Temperature Range Lead Temperature (10 sec) With Respect to ACOM DCOM DCOM DVDD DCOM Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -0.3 V to +3 V -6.5 V to +6.5 V -0.3 V to DVDD + 0.3 V DCOM ACOM ACOM -0.3 V to DVDD + 0.3 V -1.0 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V THERMAL RESISTANCE ACOM -0.3 V to AVDD + 0.3 V 150C -65C to +150C Table 5. Thermal Resistance Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Package Type 48-lead LQFP 300C ESD CAUTION Rev. C | Page 6 of 32 JA 91 Unit C/W AD9765 48 47 46 45 44 43 42 SLEEP ACOM IOUTA2 IOUTB2 FSADJ2 GAINCTRL REFIO FSADJ1 IOUTB1 IOUTA1 AVDD MODE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 41 40 39 38 37 DB11P1 (MSB) 1 36 NC 35 NC DB9P1 3 34 DB0P2 (LSB) DB8P1 4 33 DB1P2 DB7P1 5 32 DB2P2 DB6P1 6 31 DB3P2 DB5P1 7 30 DB4P2 DB4P1 8 29 DB5P2 DB3P1 9 28 DB6P2 DB2P1 10 27 DB7P2 DB1P1 11 26 DB8P2 DB0P1 (LSB) 12 25 DB9P2 DB10P1 PIN 1 2 AD9765 TOP VIEW (Not to Scale) 00619-003 DB10P2 DB11P2 (MSB) DVDD2 DCOM2 WRT2/IQSEL CLK2/IQRESET CLK1/IQCLK WRT1/IQWRT DVDD1 DCOM1 NC NC = NO CONNECT NC 13 14 15 16 17 18 19 20 21 22 23 24 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 12 13, 14, 35, 36 15, 21 16, 22 17 18 19 20 23 to 34 37 38 39, 40 41 42 43 44 45, 46 47 48 Mnemonic PORT1 NC DCOM1, DCOM2 DVDD1, DVDD2 WRT1/IQWRT CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL PORT2 SLEEP ACOM IOUTA2, IOUTB2 FSADJ2 GAINCTRL REFIO FSADJ1 IOUTB1, IOUTA1 AVDD MODE Description Data Bit DB11P1 to Data Bit DB0P1. No Connect. Digital Common. Digital Supply Voltage. Input Write Signal for PORT 1 (IQWRT in Interleaving Mode). Clock Input for DAC1 (IQCLK in Interleaving Mode). Clock Input for DAC2 (IQRESET in Interleaving Mode). Input Write Signal for PORT 2 (IQSEL in Interleaving Mode). Data Bit DB11-P2 to Data Bit DB0-P2. Power-Down Control Input. Analog Common. PORT 2 Differential DAC Current Outputs. Full-Scale Current Output Adjust for DAC2. GAINCTRL Mode (0 = 2 Resistor, 1 = 1 Resistor). Reference Input/Output. Full-Scale Current Output Adjust for DAC1. PORT 1 Differential DAC Current Outputs. Analog Supply Voltage. Mode Select (1 = Dual Port, 0 = Interleaved). Rev. C | Page 7 of 32 AD9765 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, IOUTFS = 20 mA, 50 doubly terminated load, differential output, TA = 25C, SFDR up to Nyquist, unless otherwise noted. 90 85 5MSPS 80 25MSPS 0dBFS 75 SFDR (dBc) 70 125MSPS -6dBFS 70 -12dBFS 65 60 60 65MSPS 55 50 0 5 10 15 20 25 30 35 60 70 30 fOUT (MHz) Figure 4. SFDR vs. fOUT @ 0 dBFS 00619-008 fOUT (MHz) 00619-009 100 10 00619-005 50 1 00619-010 SFDR (dBc) 80 Figure 7. SFDR vs. fOUT @ 65 MSPS 95 85 80 0dBFS 90 75 SFDR (dBc) SFDR (dBc) 0dBFS 85 -6dBFS -12dBFS 70 -6dBFS 65 -12dBFS 60 80 55 50 1.25 1.50 1.75 2.00 2.25 fOUT (MHz) 00619-006 75 1.00 0 10 20 30 40 50 fOUT (MHz) Figure 5. SFDR vs. fOUT @ 5 MSPS Figure 8. SFDR vs. fOUT @ 125 MSPS 90 85 IOUTFS = 10mA 80 85 0dBFS IOUTFS = 20mA 75 SFDR (dBc) -6dBFS 75 -12dBFS IOUTFS = 5mA 70 65 70 60 65 55 50 60 0 2 4 6 8 fOUT (MHz) 10 12 00619-007 SFDR (dBc) 80 Figure 6. SFDR vs. fOUT @ 25 MSPS 0 5 10 15 20 25 fOUT (MHz) Figure 9. SFDR vs. fOUT and IOUTFS @ 65 MSPS and 0 dBFS Rev. C | Page 8 of 32 AD9765 90 75 0.91MHz/10MSPS 85 IOUTFS = 20mA 2.27MHz/25MSPS 70 IOUTFS = 10mA SINAD (dBc) SFDR (dBc) 80 75 65 70 60 11.37MHz/125MSPS IOUTFS = 5mA 65 -10 -5 0 AOUT (dBFS) 55 20 00619-011 -15 60 80 100 120 140 fCLK (MSPS) Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/11 Figure 13. SINAD vs. fCLK and IOUTFS @ fOUT = 5 MHz and 0 dBFS 90 0.6 1MHz/5MSPS 0.5 85 5MHz/25MSPS 2MHz/10MSPS 0.4 80 0.3 INL (LSB) SFDR (dBc) 40 00619-014 5.91MHz/65MSPS 60 -20 75 70 13MHz/65MSPS 0.2 0.1 0 -0.1 65 25MHz/125MSPS -0.2 60 -15 -10 -5 0 AOUT (dBFS) -0.4 00619-012 55 -20 0 1000 2000 3000 4000 CODE 00619-015 -0.3 Figure 14. Typical INL Figure 11. Single-Tone SFDR vs. AOUT @ fOUT = fCLK/5 0.05 80 3.38MHz/3.36MHz@25MSPS 0 0.965MHz/1.035MHz@7MSPS 75 DNL (LSB) 70 65 -0.10 -0.15 -0.20 6.75MHz/7.25MHz@65MSPS 60 -0.25 16.9MHz/18.1MHz@125MSPS 55 -20 -15 -10 -5 AOUT (dBFS) 0 -0.35 0 500 1000 1500 2000 2500 CODE Figure 15. Typical DNL Figure 12. Dual-Tone SFDR vs. AOUT @ fOUT = fCLK/7 Rev. C | Page 9 of 32 3000 3500 4000 00619-016 -0.30 00619-013 SFDR (dBc) -0.05 AD9765 85 0 fOUT = 1MHz -10 80 fOUT = 10MHz 75 -20 SFDR (dBm) fOUT = 25MHz 65 fOUT = 40MHz 60 55 -40 -50 -60 -70 fOUT = 60MHz 50 -80 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) -90 00619-017 45 -60 0 10 20 30 40 FREQUENCY (MHz) Figure 16. SFDR vs. Temperature @ 125 MSPS, 0 dBFS 00619-020 SFDR (dBc) -30 70 Figure 19. Dual-Tone SFDR @ fCLK = 125 MSPS 0.05 0 1.0 0.03 -20 0.5 GAIN ERROR 0 0 -0.03 -30 SFDR (dBm) OFFSET ERROR GAIN ERROR (%FS) OFFSET ERROR (%FS) -10 -40 -50 -60 -0.5 -70 -1.0 -20 0 20 40 60 80 TEMPERATURE (C) Figure 17. Reference Voltage Drift vs. Temperature 0 -10 -30 -40 -50 -60 -70 -80 -90 20 30 FREQUENCY (MHz) 40 00619-019 SFDR (dBm) -20 10 0 10 20 30 FREQUENCY (MHz) Figure 20. Four-Tone SFDR @ fCLK = 125 MSPS 10 0 -90 Figure 18. Single-Tone SFDR @ fCLK = 125 MSPS Rev. C | Page 10 of 32 40 00619-021 -0.05 -40 00619-018 -80 AD9765 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, and associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0. For IOUTB, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C (ppm/C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse, which is specified as the net area of the glitch in picovolts per second (pV-s). Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Rev. C | Page 11 of 32 AD9765 THEORY OF OPERATION 5V CLK1/IQCLK CLK2/IQRESET SLEEP MINI CIRCUITS T1-1T AVDD RSET1 2k REFIO PMOS CURRENT SOURCE ARRAY IOUTA1 0.1F FSADJ2 RSET 2 2k PMOS CURRENT SOURCE ARRAY 1.2V REF AD9765 GAINCTRL WRT1/ IQWRT DVDD DCOM RETIMED CLOCK OUTPUT* SEGMENTED LSB IOUTB1 SWITCHES FOR SWITCH DAC1 DAC 1 LATCH 50 IOUTA2 SEGMENTED LSB SWITCHES FOR SWITCH IOUTB2 DAC2 DAC 2 LATCH TO HP3589A SPECTRUM/ NETWORK ANALYZER 50 MODE MULTIPLEXING LOGIC 5V DVDD CHANNEL 1 LATCH CHANNEL 2 LATCH DB0 TO DB11 DB0 TO DB11 50 ACOM DCOM WRT2/ IQSEL DIGITAL DATA LECROY 9210 PULSE GENERATOR *AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. TEKTRONIX AWG-2021 w/OPTION 4 00619-004 FSADJ1 CLK DIVIDER Figure 21. Basic AC Characterization Test Setup for AD9765, Testing Port 1 in Dual-Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2 5V CLK1/IQCLK CLK2/IQRESET AVDD IREF 1 0.1F RSET 2 2k FSADJ1 REFIO FSADJ2 IREF 2 1.2V REF PMOS CURRENT SOURCE ARRAY PMOS CURRENT SOURCE ARRAY AD9765 VDIFF = VOUTA - VOUTB VOUT1A IOUTA1 SEGMENTED LSB SWITCHES FOR I SWITCH OUTB1 DAC1 DAC 1 LATCH DAC 2 LATCH IOUTA2 SEGMENTED LSB SWITCHES FOR I SWITCH OUTB2 DAC2 VOUT1B VOUT2A VOUT2B RL2B 50 MODE MULTIPLEXING LOGIC CHANNEL 1 LATCH GAINCTRL SLEEP ACOM CLK DIVIDER DVDD CHANNEL 2 LATCH RL1B 50 RL1A 50 RL2A 50 5V DCOM WRT1/ IQWRT DB0 TO DB11 DB0 TO DB11 DIGITAL DATA INPUTS WRT2/ IQSEL 00619-022 RSET 1 2k Figure 22. Simplified Block Diagram FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9765. The AD9765 consists of two DACs, each one with its own independent digital control logic and full-scale output current control. Each DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). All of these current sources are switched to one or the other of the two output nodes (IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSB is a binary weighted fraction of the middle bit current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the DAC high output impedance (that is, >100 k). The analog and digital sections of the AD9765 have separate power supply inputs (AVDD and DVDD) that can operate independently at 3.3 V or 5.0 V. The digital section is capable of operating up to a 125 MSPS clock rate and consists of edge triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V band gap voltage reference, and two reference control amplifiers. Rev. C | Page 12 of 32 AD9765 The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from 2 to 20 mA via an external resistor, RSET, connected to the full scale adjust (FSADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference (VREFIO) sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current (IOUTFS) is 32 x IREF. REFERENCE OPERATION The AD9765 contains an internal 1.20 V band gap reference. This can easily be overridden by an external reference with no effect on performance. REFIO serves as either an input or output, depending on whether an internal or external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 F capacitor. The internal reference voltage is present at REFIO. If the voltage at REFIO is used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 nA is used. An example of the use of the internal reference is shown in Figure 23. OPTIONAL EXTERNAL REFERENCE BUFFER GAINCTRL 1.2V REF AVDD AD9765 REFERENCE SECTION REFIO ADDITIONAL EXTERNAL LOAD 0.1F CURRENT SOURCE ARRAY FSADJ ACOM 2k 00619-023 IREF Figure 23. Internal Reference Configuration An external reference can be applied to REFIO as shown in Figure 24. The external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. The 0.1 F compensation capacitor is not required because the internal reference is overridden and the relatively high input impedance of REFIO minimizes any loading of the external reference. GAINCTRL 1.2V REF REFIO EXTERNAL REFERENCE FSADJ IREF Note that only parts with a date code of 9930 or later have the master/slave gain control function. For parts with a date code before 9930, Pin 42 must be connected to AGND, and the part operates in the two-resistor, independent gain control mode. REFERENCE CONTROL AMPLIFIER Both of the DACs in the AD9765 contain a control amplifier that is used to regulate the full-scale output current (IOUTFS). The control amplifier is configured as a V-I converter, as shown in Figure 23, so that its current output(IREF) is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS, as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS from 2 to 20 mA by setting IREF between 62.5 A and 625 A. The wide adjustment range of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9765, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency, small signal multiplying applications. DAC TRANSFER FUNCTION Both DACs in the AD9765 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current output (IOUTFS) when all bits are high (for example, DAC CODE = 4095), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as AD9765 REFERENCE SECTION CURRENT SOURCE ARRAY 2k ACOM IOUTA = (DAC CODE/4096) x IOUTFS (1) IOUTB = (1023 - DAC CODE/4096) x IOUTFS (2) where DAC CODE = 0 to 4095 (decimal representation). 00619-024 AVDD AVDD When GAINCTRL is low (connected to AGND), the independent channel gain control mode using two resistors is enabled. In this mode, individual RSET resistors are connected to FSADJ1 and FSADJ2. When GAINCTRL is high (connected to AVDD), the master/slave channel gain control mode, using one resistor, is enabled. In this mode, a single RSET resistor is connected to FSADJ1, and the resistor on FSADJ2 must be removed. This is nominally set by reference voltage (VREFIO) and external resistor RSET. It can be expressed as Figure 24. External Reference Configuration IOUTFS = 32 x IREF GAIN CONTROL MODE The AD9765 allows the gain of each channel to be set independently by connecting one RSET resistor to FSADJ1 and another RSET resistor to FSADJ2. To add flexibility and reduce system cost, a single RSET resistor can be used to set the gain of both channels simultaneously. (3) where Rev. C | Page 13 of 32 IREF = VREFIO/RSET (4) AD9765 The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB are directly connected to matching resistive loads (RLOAD) that are tied to analog common (ACOM). Note that RLOAD can represent the equivalent load resistance seen by IOUTA or IOUTB, as is the case in a doubly terminated 50 or 75 cable. The singleended voltage output appearing at the IOUTA and IOUTB nodes is simply VOUTA = IOUTA x RLOAD (5) VOUTB = IOUTB x RLOAD (6) Note that the full-scale value of VOUTA and VOUTB must not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA - IOUTB) x RLOAD (7) Equation 6 and Equation 7 highlight some of the advantages of operating the AD9765 differentially. First, the differential operation helps cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (VOUTA or VOUTB), thus providing twice the signal power to the load. The gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9765 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship, as shown in Equation 8. ANALOG OUTPUTS The complementary current outputs in each DAC, IOUTA and IOUTB, can be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor (RLOAD) as described in Equation 5 through Equation 8. The differential voltage (VDIFF) existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9765 is optimum and specified using a differential transformer coupled output in which the voltage swing at IOUTA and IOUTB is limited to 0.5 V. If a single-ended unipolar output is desired, select IOUTA. The distortion and noise performance of the AD9765 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load, assuming no source termination. Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9765 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 k in parallel with 5 pF. It is also slightly dependent on the output voltage (VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration results in the optimum dc linearity. Note that the INL/DNL specifications for the AD9765 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to so as to achieve optimum performance. The negative output compliance range of -1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit can result in a breakdown of the output stage and affect the reliability of the AD9765. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Applications requiring the AD9765 output (VOUTA and/or VOUTB) to extend its output compliance range must size RLOAD accordingly. Operation beyond this compliance range adversely affects the AD9765 linearity performance and subsequently degrades its distortion performance. DIGITAL INPUTS The AD9765 digital inputs consist of two independent channels. For the dual-port mode, each DAC has its own dedicated 12-bit data port, WRT line, and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described in the Interleaved Mode Timing section. The 12-bit parallel data inputs follow straight binary coding, where DB11 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. Rev. C | Page 14 of 32 AD9765 DAC TIMING The AD9765 can operate in two timing modes, dual and interleaved, which are described in the following sections. The block diagram in Figure 27 represents the latch architecture in the interleaved timing mode. Dual-Port Mode Timing When the MODE pin is at Logic 1, the AD9765 operates in dual-port mode (refer to Figure 21). The AD9765 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. The AD9765 features a double-buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. Once the data is loaded into the DAC latch, the analog output settles to its new value. For general consideration, the WRT lines control the channel input latches and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. The rising edge of CLK occurs before or simultaneously with the rising edge of WRT. If the rising edge of CLK occurs after the rising edge of WRT, a 2 ns minimum delay must be maintained from the rising edge of WRT to the rising edge of CLK. DATA IN D5 XX D1 D3 D2 D4 00619-026 IOUTA OR IOUTB Figure 26. Dual-Port Mode Timing Interleaved Mode Timing When the MODE pin is at Logic 0, the AD9765 operates in interleaved mode (refer to Figure 27). WRT1 functions as IQWRT and CLK1 functions as IQCLK. WRT2 functions as IQSEL and CLK2 functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL only changes state when IQWRT and IQCLK are low. When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the following rising edge on IQCLK updates both DAC latches with the data present at their inputs. In the interleaved mode, IQCLK is divided by 2 internally. Following this first rising edge, the DAC latches are only updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs. As with the dual-port mode, IQCLK occurs before or simultaneously with IQWRT. Timing specifications for interleaved mode are shown in Figure 28 and Figure 29. INTERLEAVED DATA IN, PORT 1 PORT 1 INPUT LATCH DAC1 LATCH DAC1 PORT 2 INPUT LATCH IQWRT IQSEL IQCLK IQRESET /2 DEINTERLEAVED DATA OUT DAC2 LATCH DAC2 The digital inputs are CMOS-compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDD), or tLPW VTHRESHOLD = DVDD/2(20%) CLK1/CLK2 D4 Figure 27. Latch Structure Interleaved Mode DATA IN tCPW tPD 00619-025 IOUTA OR IOUTB D3 CLK1/CLK2 tH WRT1/WRT2 D2 WRT1/WRT2 Timing specifications for dual-port mode are shown in Figure 25 and Figure 26. tS D1 Figure 25. Dual-Port Mode Timing Rev. C | Page 15 of 32 00619-027 The digital interface is implemented using an edge triggered master/slave latch. The DAC outputs are updated following either the rising edge or every other rising edge of the clock, depending on whether dual or interleaved mode is being used. The DAC outputs are designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulse width. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges can affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. AD9765 tS tH Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value (20 to 100 ) resistor network between the AD9765 digital inputs and driver outputs can be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain clean digital inputs. DATA IN IQSEL IQWRT tH* tLPW The external clock driver circuitry provides the AD9765 with a low jitter clock input meeting the minimum/maximum logic levels while providing fast edges. Fast clock edges help minimize any jitter that manifests itself as phase noise on a reconstructed wave-form. Thus, the clock input should be driven by the fastest logic family suitable for the application. IQCLK *APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY. 00619-028 tPD IOUTA OR IOUTB Note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (DVDD/2) and meets the minimum/maximum logic threshold. This typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. In addition, at higher sampling rates, the 20% tolerance of the digital logic threshold can be considered, because it affects the effective clock duty cycle and, subsequently, cuts into the required data setup and hold times. Figure 28. Interleaved Mode Timing INTERLEAVED DATA xx D1 D2 D3 D4 D5 IQSEL IQWRT IQCLK DVDD IQRESET D1 xx D4 D2 DIGITAL INPUT D3 00619-030 DAC OUTPUT PORT 2 xx 00619-029 DAC OUTPUT PORT 1 Figure 30. Equivalent Digital Input Figure 29. Interleaved Mode Timing The internal digital circuitry of the AD9765 is capable of operating at a digital supply of 3.3 V or 5.0 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers VOH (max). A DVDD of 3 V to 3.3 V typically ensures proper compatibility with most TTL logic families. Figure 30 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, with the exception that it contains an active pull-down circuit, thus ensuring that the AD9765 remains enabled if this input is left disconnected. Because the AD9765 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9765 with reduced logic swings and a corresponding digital supply (DVDD) results in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry are specified to meet the minimum setup and hold times of the AD9765 as well as its required min/max input logic level thresholds. INPUT CLOCK AND DATA TIMING RELATIONSHIP SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9765 is rising edge triggered and so exhibits SNR sensitivity when the data transition is close to this edge. The goal when applying the AD9765 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 31 shows the relationship of SNR to clock placement with different sample rates. Note that at the lower sample rates, much more tolerance is allowed in clock placement; much more care must be taken at higher rates. Rev. C | Page 16 of 32 60 70 50 90 40 50 30 40 20 30 10 20 10 -2 -1 0 1 2 TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE (ns) 3 4 0 5 POWER DISSIPATION The power dissipation (PD) of the AD9765 is dependent on several factors, including 20 25 Figure 32. IAVDD vs. IOUTFS Conversely, IDVDD is dependent on both the digital input waveform, fCLK, and the digital supply DVDD. Figure 33 and Figure 34 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLK) for various update rates with DVDD = 5 V and DVDD = 3.3 V, respectively. Note that IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3.3 V. 35 30 125MSPS 25 100MSPS IDVDD (mA) The AD9765 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the supply range of 3.3 V to 5.0 V and over the full operating temperature range. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 x AVDD. This digital input also contains an active pull-down circuit that ensures the AD9765 remains enabled if this input is left disconnected. The AD9765 takes less than 50 ns to power down and approximately 5 s to power back up. 15 IOUTFS Figure 31. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS SLEEP MODE OPERATION 10 20 65MSPS 15 10 * the power supply voltages (AVDD and DVDD) 5 * the full-scale current output (IOUTFS) 0 * the update rate (fCLK) * the reconstructed digital input waveform 25MSPS 5MSPS 0 0.1 0.2 0.3 0.4 0.5 00619-033 -3 0.5 00619-034 0 -4 00619-032 80 IAVDD 70 00619-031 SNR (dBc) AD9765 RATIO (fOUT/fCLK) Figure 33. IDVDD vs. Ratio @ DVDD = 5 V 18 The power dissipation is directly proportional to the analog supply current (IAVDD) and the digital supply current (IDVDD). IAVDD is directly proportional to IOUTFS, as shown in Figure 32, and is insensitive to fCLK. 125MSPS 16 14 100MSPS IDVDD (mA) 12 10 65MSPS 8 6 25MSPS 4 5MSPS 2 0 0 0.1 0.2 0.3 0.4 RATIO (fOUT/fCLK) Figure 34. IDVDD vs. Ratio @ DVDD = 3.3 V Rev. C | Page 17 of 32 AD9765 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configurations for the AD9765. Unless otherwise noted, IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage results if IOUTA and/or IOUTB is connected to an appropriately sized load resistor (RLOAD) referred to as ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier can be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity, because IOUTA or IOUTB is maintained at a virtual ground. Note that IOUTA provides slightly better performance than IOUTB. DIFFERENTIAL COUPLING USING A TRANSFORMER An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 35. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer pass band. An RF transformer such as the Mini-Circuits(R) T1-1T provides excellent rejection of common-mode distortion (that is, even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios can also be used for impedance matching purposes. Note that the transformer provides ac coupling only. AD9765 IOUTA MINI-CIRCUITS T1-1T IOUTB OPTIONAL RDIFF DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 36. The AD9765 is configured with two equal load resistors (RLOAD) of 25 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp distortion performance by preventing the DAC high slewing output from overloading the op amp input. The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide some additional signal gain. The op amp must operate from a dual supply, because its output is approximately 1.0 V. Select a high speed amplifier capable of preserving the differential performance of the AD9765 while meeting other system level objectives (cost or power). Consider the op amp differential gain, its gain setting resistor values, and full-scale output swing capabilities when optimizing this circuit. 500 AD9765 225 IOUTA 225 IOUTB AD8047 COPT 500 25 25 Figure 36. DC Differential Coupling Using an Op Amp The differential circuit shown in Figure 37 provides the necessary level-shifting required in a single supply system. In this case, AVDD, which is the positive analog supply for both the AD9765 and the op amp, is also used to level-shift the differential output of the AD9765 to midsupply (that is, AVDD/2). The AD8055 is a suitable op amp for this application. 00619-035 RLOAD around ACOM and are maintained with the specified output compliance range of the AD9765. A differential resistor (RDIFF) can be inserted in applications where the output of the transformer is connected to the load (RLOAD) via a passive reconstruction filter or cable. RDIFF is determined by the transformer impedance ratio and provides the proper source termination that results in a low VSWR. Approximately half the signal power is dissipated across RDIFF. 00619-036 APPLYING THE AD9765 Figure 35. Differential Output Using a Transformer The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (VOUTA and VOUTB) swing symmetrically Rev. C | Page 18 of 32 AD9765 COPT 500 AD9765 225 IOUTA 225 IOUTB RFB 200 AD8055 COPT AD9765 IOUTFS = 10mA IOUTA 1k AVDD U1 500 VOUT = IOUTFS x RFB IOUTB 00619-039 25 00619-037 25 200 Figure 37. Single-Supply DC Differential-Coupled Circuit Figure 39. Unipolar Buffered Voltage Output AD9765 IOUTFS = 20mA VOUTA = 0V TO 0.5V IOUTA 50 50 25 00619-038 IOUTB Figure 38. 0 V to 0.5 V Unbuffered Voltage Output SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION Figure 39 shows a buffered single-ended output configuration in which the Op Amp U1 performs an I-V conversion on the AD9765 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC INL performance, as described in the Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates can be limited by U1 slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. Set the full-scale output within U1 voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance can result with a reduced IOUTFS, because the signal current U1 required to sink is subsequently reduced. POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as power supply bypassing and grounding, to ensure optimum performance. Figure 47 to Figure 54 illustrate the recommended printed circuit board ground, power, and signal plane layouts, which are implemented on the AD9765 evaluation board. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the power supply rejection ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum of tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9765 AVDD supply over this frequency range is shown in Figure 40. 90 85 80 75 70 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (MHz) Figure 40. Power Supply Rejection Ratio vs. Frequency Rev. C | Page 19 of 32 1.1 00619-040 Figure 38 shows the AD9765 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 cable, because the nominal full-scale current (IOUTFS) of 20 mA flows through the equivalent RLOAD of 25 . In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL), as discussed in the Analog Outputs section. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. PSRR (dB) SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT AD9765 Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and, for simplicity's sake (to ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise appears as current noise superimposed on the DAC full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 40 at 250 kHz. To calculate the PSRR for a given RLOAD such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 40 by the scaling factor 20 x log (RLOAD). For example, if RLOAD is 50 , the PSRR is reduced by 34 dB (PSRR of the DAC at 250 kHz, which is 85 dB in Figure 40, becomes 51 dB VOUT/VIN). Proper grounding and decoupling are primary objectives in any high speed, high resolution system. The AD9765 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, decouple the analog supply (AVDD) to the analog common (ACOM) as close to the chip as physically possible. Similarly, decouple DVDD, the digital supply (DVDD) to digital common (DCOM) as close to the chip as possible. For those applications that require a single 5 V or 3.3 V supply for both the analog and digital supplies, a clean analog supply can be generated using the circuit shown in Figure 41. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low ESR type electrolytic and tantalum capacitors. FERRITE BEADS TTL/CMOS LOGIC CIRCUITS Rev. C | Page 20 of 32 ELECTROLYTIC CERAMIC AVDD 100F 10F TO 22F 0.1F ACOM TANTALUM 5V POWER SUPPLY Figure 41. Differential LC Filter for Single 5 V and 3.3 V Applications 00619-041 Note that the units in Figure 40 are given in units of amps out/volts in. Noise on the analog power supply has the effect of modulating the internal current sources, and therefore the output current. The voltage noise on AVDD, therefore, is added in a nonlinear manner to the desired IOUT. PSRR is very code dependent, thus producing mixing effects, which can modulate low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 40 represents a worstcase condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. AD9765 -30 APPLICATIONS -40 VDSL APPLICATIONS USING THE AD9765 -50 -70 -80 -90 -100 -110 -120 4.85 4.90 4.95 5.00 5.05 5.10 FREQUENCY (MHz) 5.15 00619-043 As with other multitone applications, each VDSL tone is capable of transmitting a given number of bits, depending on the signal-to-noise ratio (SNR) in a narrow band around that tone. For a typical VDSL application, the tones are evenly spaced over the range of several kHz to 10 MHz. At the high frequency end of this range, performance is generally limited by cable characteristics and environmental factors such as external interferers. Performance at the lower frequencies is much more dependent on the performance of the components in the signal chain. In addition to in-band noise, intermodulation from other tones can also potentially interfere with the data recovery for a given tone. The two graphs in Figure 42 and Figure 43 represent a 500-tone missing bin test vector, with frequencies evenly spaced from 400 Hz to 10 MHz. This test is very commonly done to determine if distortion limits the number of bits that can be transmitted in a tone. The test vector has a series of missing tones around 750 kHz, which is represented in Figure 42, and a series of missing tones around 5 MHz, which is represented in Figure 43. In both cases, the spurious-free dynamic range (SFDR) between the transmitted tones and the empty bins is greater than 60 dB. -60 (dBm) Very high frequency digital subscriber line (VDSL) technology is growing rapidly in applications requiring data transfer over relatively short distances. By using quadrature amplitude modulation (QAM) and transmitting the data in discrete multiple tones (DMT), high data rates can be achieved. Figure 43. Notch in Missing Bin at 5 MHz Is Down >60 dB (Peak Amplitude = 0 dBm) USING THE AD9765 FOR QUADRATURE AMPLITUDE MODULATION (QAM) QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (AM modulation) and phase (PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. -20 -30 -40 -50 -70 -80 -90 -100 -110 -120 0.665 0.685 0.705 0.725 0.745 0.765 0.785 0.805 0.825 FREQUENCY (MHz) Figure 42. Notch in Missing Bin at 750 kHz Is Down >60 dB (Peak Amplitude = 0 dBm) 00619-042 (dBm) -60 A common and traditional implementation of a QAM modulator is shown in Figure 44. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each component's spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the QAM signal. Rev. C | Page 21 of 32 AD9765 The AD9765 provides both I and Q DACs a common reference that improves the gain matching and stability. RCAL can be used to compensate for any mismatch in gain between the two channels. The mismatch can be attributed to the mismatch between RSET1 and RSET2, the effective load resistance of each channel, and/or the voltage offset of the control amplifier in each DAC. The differential voltage outputs of both DACs in the AD9765 are fed into the respective differential inputs of the AD8346 via matching networks. 12 DAC DSP OR ASIC 0 CARRIER FREQUENCY 90 TO MIXER 12 NYQUIST FILTERS 00619-044 DAC QUADRATURE MODULATOR Figure 44. Typical Analog QAM Architecture In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 45 helps improve the matching between the I and Q channels and also shows a path for upconversion using the AD8346 quadrature modulator. AVDD ROHDE & SCHWARZ FSEA30B 0.1F RL LA PORT I TEKTRONICS AWG2021 WITH OPTION 4 IQWRT PORT Q IQCLK DIGITAL INTERFACE IOUTA I DAC LATCH I DAC CB CA IOUTB RL LA RA RB RL RA BBIP VOUT RB + BBIN RL AD9765 QOUTA Q DAC LATCH Q DAC CB CA RL IQSEL RA RL LA RL QOUTB LA RB MODE FSADJ1 RSET 3.9k FSADJQ REFIO RSET 3.9k 0.1F NOTES 1. DAC's FULL-SCALE OUTPUT CURRENT = IOUTFS. 2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE FROM OHMTEK ORNXXXXD SERIES. LOIP RA BBQP RB PHASE SPLITTER LOIN CFILTER BBQN RL VDIFF = 1.82V p-p SLEEP SPECTRUM ANALYZER VPBF DIFFERENTIAL RLC FILTER RL = 200 RA = 2500 RB = 500 RP = 200 CA = 280pF CB = 45pF LA = 10H IOUTFS = 11mA AVDD = 5.0V VCM = 1.2V AD8346 ROHDE & SCHWARZ SIGNAL GENERATOR AVDD AD976x RL RB 0 TO IOUTFS Figure 45. Baseband QAM Implementation Using an AD9765 and an AD8346 Rev. C | Page 22 of 32 VDAC RA AD8346 VMOD 00619-045 ACOM AVDD DCOM DVDD AD9765 I and Q digital data can be fed into the AD9765 in two different ways. In dual-port mode, the Digital I information drives one input port, while the Digital Q information drives the other input port. If no interpolation filter precedes the DAC, the symbol rate is the rate at which the system clock drives the CLK and WRT pins on the AD9765. In interleaved mode, the digital input stream at Port 1 contains the I and the Q information in alternating digital words. Using IQSEL and IQRESET, the AD9765 can be synchronized to the I and Q data stream. The internal timing of the AD9765 routes the selected I and Q data to the correct DAC output. In interleaved mode, if no interpolation filter precedes the AD9765, the symbol rate is half that of the system clock driving the digital data stream and the IQWRT pin and IQCLK pin on the AD9765. CDMA Code division multiple access (CDMA) is an air transmit/receive scheme in which the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). The effect of this is to spread the transmitted signal across a wide spectrum. Similar to a discrete monotone (DMT) waveform, a CDMA waveform containing multiple subscribers can be characterized as having a high peak to average ratio (crest factor), thus demanding highly linear components in the transmit signal path. The bandwidth of the spectrum is defined by the CDMA standard being used, and in operation is implemented by using a spreading code with particular characteristics. Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (ACP). This is a regulatory issue due to the possibility of interference with other signals being transmitted by air. Regulatory bodies define a spectral mask outside of the transmit band, and the ACP must fall under this mask. If distortion in the transmit path causes the ACP to be above the spectral mask, then filtering, or different component selection, is needed to meet the mask requirements. Figure 46 shows the AD9765, when used with the AD8346, reconstructing a wideband CDMA signal at 2.4 GHz. The baseband signal is being sampled at 65 MSPS and has a chip rate of 8 M chips. -30 -40 -50 -60 == (dB) -70 -80 -90 -100 -110 c11 cu1 cu1 C0 C0 -130 CENTER 2.4GHz 3MHz FREQUENCY SPAN 30MHz 00619-046 c11 -120 Figure 46. CDMA Signal, 8 M Chips Sampled at 65 MSPS, Recreated at 2.4 GHz, Adjacent Channel Power > 6 dBm Rev. C | Page 23 of 32 AD9765 EVALUATION BOARD GENERAL DESCRIPTION This board allows the user the flexibility to operate the AD9765 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs can be used in dual-port or interleaved mode and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. When operating the AD9765, best performance is obtained by running the DVDD at 3.3 V and the AVDD at 5 V. The AD9765-EB is an evaluation board for the AD9765 12-bit dual DAC. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9765 in any application where a high resolution, high speed conversion is required. SCHEMATICS RED TP10 B3 L1 DVDDIN DVDD BEAD BAN-JACK BAN-JACK C9 10F 2 25V BLK TP37 BAN-JACK BLK TP38 BLK TP39 TP43 BLK DVDD L2 AVDDIN 1 B2 RED TP11 AVDD BEAD 1 B4 C10 10F 25V 2 BLK TP40 BAN-JACK DGND 2 1 3 A B JP16 2 1 2 JP5 A 2B 1 CLK1IN S2 IQCLK WHT TP31 JP4 A 2B 1 CLK2IN S3 RESET I DGND; 3, 4, 5 JP3 A2 B WHT TP32 1 WRT2IN S4 IQSEL DGND; 3, 4, 5 1 2 1 R1 50 2 1 R2 50 2 R3 50 1 2 I J 1 3 10 U1 Q 11 6 12 Q K CLR 15 3 5 13 CLK 2 DVDD C C8 0.01F 3 PRE 3 JP1 C I DGND; 3, 4, 5 2 AGND 4 DGND; 3, 4, 5 WHT TP30 1 C7 0.1F A B JP2 WRT1IN S1 IQWRT 1 JP6 DCLKIN2 DVDD WHT TP29 BLK TP42 TP44 BLK JP9 DCLKIN1 BLK TP41 PRE J 9 Q U2 CLK 7 Q K CLR 74112 14 DGND; 8 DVDD; 16 74112 DGND; 8 DVDD; 16 A B DVDD 1 3 2 JP7 /2 CLOCK DIVIDER 3 WRT1 C R4 50 CLK1 CLK2 WHT TP33 WRT2 SLEEP 1 2 SLEEP R13 50 RP16 R1 22 RCOM 1 2 INP1 R2 22 3 INP2 R3 22 4 INP3 R4 22 5 INP4 R5 22 6 R6 22 7 INP5 INP6 R7 22 8 INP7 R8 22 9 R9 22 RP9 R1 22 RCOM 10 1 INP8 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 INP9 INP10 INP11 INP12 INP13 INP14 R8 22 9 R1 22 1 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 10 INCK1 RP10 RCOM R9 22 RP15 R1 22 RCOM 1 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 INP31 INP32 INP33 INP34 INP35 INP36 Figure 47. Power Decoupling and Clocks on AD9765 Evaluation Board Rev. C | Page 24 of 32 R7 22 8 R8 22 9 INCK2 R9 22 10 00619-047 B1 AD9765 RP3 RP1 RCOM R1 R9 22 P1 P1 1 4 P1 P1 3 6 P1 P1 5 8 P1 P1 7 10 P1 P1 9 12 P1 P1 11 14 P1 P1 13 16 P1 P1 15 18 P1 P1 17 20 P1 P1 19 22 P1 P1 21 24 P1 P1 23 26 P1 P1 25 28 P1 P1 27 30 P1 P1 29 32 P1 P1 31 34 P1 P1 33 36 P1 P1 35 38 P1 P1 37 40 P1 P1 39 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9 INP10 INP11 INP12 INP13 INP14 1 16 RP5, 10 3 14 RP5, 10 5 12 RP5, 10 7 10 RP6, 10 1 16 RP6, 10 3 14 RP6, 10 5 12 2 DUTP2 15 DUTP3 RP5, 10 4 DUTP4 13 DUTP5 RP5, 10 6 DUTP6 11 DUTP7 RP5, 10 8 DUTP8 9 DUTP9 RP6, 10 2 DUTP10 15 DUTP11 RP6, 10 4 DUTP12 13 DUTP13 RP6, 10 DUTP14 11 RP6, 10 INCK1 8 DCLKIN1 9 RP2 R9 1 P2 1 P2 P2 3 6 P2 P2 5 8 P2 P2 7 10 P2 P2 9 12 P2 P2 11 14 P2 P2 13 16 P2 P2 15 18 P2 P2 17 20 P2 P2 19 22 P2 P2 21 24 P2 P2 23 26 P2 P2 25 28 P2 P2 27 30 P2 P2 29 32 P2 P2 31 34 P2 P2 33 36 P2 P2 35 38 P2 P2 37 40 P2 P2 39 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 1 16 RP7, 10 3 14 RP7, 10 5 12 RP7, 10 7 10 RP8, 10 1 16 RP8, 10 3 14 RP8, 10 5 12 2 3 4 5 6 7 8 9 10 1 RP12 RCOM R1 R9 33 2 3 4 5 6 7 8 9 10 1 RCOM R1 R9 33 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 DVDD DUTP23 RP7, 10 2 DUTP24 15 DUTP25 RP7, 10 4 DUTP26 13 DUTP27 RP7, 10 6 DUTP28 11 DUTP29 RP7, 10 8 DUTP30 9 DUTP31 RP8, 10 2 DUTP32 15 DUTP33 RP8, 10 4 DUTP34 13 DUTP35 RP8, 10 6 INCK2 R9 22 DVDD RP7, 10 RP14 RCOM R1 22 P2 2 3 4 5 6 7 8 9 10 1 DUTP1 RCOM R1 4 2 3 4 5 6 7 8 9 10 1 R9 33 DVDD RP4 2 RCOM R1 RP5, 10 6 INP23 R9 33 2 3 4 5 6 7 8 9 10 1 RP11 RCOM R1 DUTP36 11 RP8, 10 8 DCLKIN2 9 SPARES RP5, 10 7 10 RP8, 10 7 10 Figure 48. Digital Input Signal Conditioning Rev. C | Page 25 of 32 00619-048 2 DVDD RP5, 10 R9 22 2 3 4 5 6 7 8 9 10 1 INP1 RP13 RCOM R1 AD9765 BL1 TP34 WHT C1 2 VAL 1 C2 2 0.01F ACOM JP15 DVDD C3 0.1F 2 AVDD 1 2 1 NC = 5 3 2 R11 VAL 3 A B DB13P1MSB MODE 48 2 DB12P1 AVDD 47 3 DB11P1 IA1 46 DUTP1 1 DUTP2 DUTP3 DUTP4 1 4 DB10P1 1:1 6 T1 BL2 3 A B 1 2 C4 2 10pF 1 5 DB9P1 DUTP6 6 DB8P1 REFIO 43 DUTP7 7 DB7P1 GAINCTRL 42 2 R6 50 C5 2 10pF 1 TP45 WHT R9 1.92k 1 C16 22nF 1 FSADJ1 44 8 DB6P1 FSADJ2 41 DUTP9 9 DB5P1 IB2 40 DUTP10 10 DB4P1 IA2 39 C17 22nF 2 R10 1.92k 2 DB3P1 12 DB2P1 SLEEP 37 SLEEP DUTP13 13 DB1P1 DB0P2 36 DUTP36 DUTP14 14 DB0P1 DB1P2 35 DUTP35 15 DCOM1 DB2P2 34 DUTP34 16 DVDD1 DB3P2 33 DUTP33 17 WRT1 DB4P2 32 DUTP32 ACOM 38 C6 10pF 1 1 CLK1 18 CLK1 DB5P2 31 DUTP31 CLK2 19 CLK2 DB6P2 30 DUTP30 WRT2 20 WRT2 DB7P2 29 DUTP29 21 DCOM2 DB8P2 28 DUTP28 22 DVDD2 DB9P2 27 DUTP27 DUTP23 23 DB13P2MSB DB10P2 26 DUTP26 DUTP24 24 DB12P2 DB11P2 25 DUTP25 1 2 C15 10pF 1 11 DUTP12 U2 2 1 DUTP11 WRT1 1 R5 50 IB1 45 DUTP5 DUTP8 2 S6 OUT1 AGND; 3, 4, 5 1 MODE JP8 DVDD 4 2 1 R7 50 2 R8 50 2 R15 256 1 REFIO TP36 WHT 2 R14 256 1 1 2 2 C14 0.1F JP10 2 WHT TP46 BL3 TP35 WHT 3 R12 VAL 2 NC = 5 4 1:1 1 S11 OUT2 AGND; 3, 4, 5 6 T2 BL4 AVDD 1 C11 2 1F 1 C12 2 0.01F 1 C13 2 0.1F Figure 49. AD9765 and Output Signal Conditioning Rev. C | Page 26 of 32 00619-049 1 AD9765 00619-050 EVALUATION BOARD LAYOUT 00619-051 Figure 50. Assembly, Top Side Figure 51. Assembly, Bottom Side Rev. C | Page 27 of 32 00619-052 AD9765 00619-053 Figure 52. Layer 1, Top Side Figure 53. Layer 2, Ground Plane Rev. C | Page 28 of 32 00619-054 AD9765 00619-055 Figure 54. Layer 3, Power Plane Figure 55. Layer 4, Bottom Side Rev. C | Page 29 of 32 AD9765 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 7.20 7.00 SQ 6.80 TOP VIEW 0.15 0.05 0.20 0.09 7 3.5 0 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A 24 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 051706-A 1.45 1.40 1.35 Figure 56. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model AD9765AST AD9765ASTRL AD9765ASTZ 1 AD9765ASTZRL1 AD9765-EB 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP 48-Lead LQFP Evaluation Board Z = Pb-free part. Rev. C | Page 30 of 32 Package Option ST-48 ST-48 ST-48 ST-48 AD9765 NOTES Rev. C | Page 31 of 32 AD9765 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00619-0-10/06(C)