8-Bit AVR Microcontroller ATmega32A DATASHEET COMPLETE Introduction (R) The Atmel ATmega32A is a low-power CMOS 8-bit microcontroller based (R) on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32A achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. Features * * * * * High-performance, Low-power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture - 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16MIPS Throughput at 16MHz - On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments - 32Kbytes of In-System Self-programmable Flash program memory - 1024Bytes EEPROM - 2Kbytes Internal SRAM - Write/Erase cycles: 10,000 Flash/100,000 EEPROM - Data retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits * In-System Programming by On-chip Boot Program * True Read-While-Write Operation - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface Atmel QTouch(R) library support Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 * - Capacitive touch buttons, sliders and wheels - Atmel QTouch and QMatrix acquisition - Up to 64 sense channels Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - * * * * * 8-channel, 10-bit ADC * 8 Single-ended Channels * 7 Differential Channels in TQFP Package Only * 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x - Byte-oriented Two-wire Serial Interface - Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF Operating Voltages - 2.7 - 5.5V Speed Grades - 0 - 16MHz Power Consumption at 1MHz, 3V, 25C - Active: 0.6mA - Idle Mode: 0.2mA - Power-down Mode: < 1A Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 2 Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 1. Description.................................................................................................................9 2. Configuration Summary........................................................................................... 10 3. Ordering Information................................................................................................ 11 4. Block Diagram......................................................................................................... 12 5. Pin Configurations................................................................................................... 13 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10. 5.11. VCC............................................................................................................................................. 14 GND............................................................................................................................................14 PortA (PA7:PA0)......................................................................................................................... 14 Port B (PB7:PB0)........................................................................................................................15 Port C (PC7:PC0).......................................................................................................................15 Port D (PD7:PD0).......................................................................................................................15 RESET........................................................................................................................................15 XTAL1.........................................................................................................................................16 XTAL2.........................................................................................................................................16 AVCC........................................................................................................................................... 16 AREF..........................................................................................................................................16 6. Resources................................................................................................................17 7. Data Retention.........................................................................................................18 8. About Code Examples............................................................................................. 19 9. Capacitive Touch Sensing....................................................................................... 20 10. AVR CPU Core........................................................................................................ 21 10.1. Overview.....................................................................................................................................21 10.2. ALU - Arithmetic Logic Unit........................................................................................................22 10.3. Status Register...........................................................................................................................22 10.4. 10.5. 10.6. 10.7. General Purpose Register File................................................................................................... 24 Stack Pointer.............................................................................................................................. 25 Instruction Execution Timing...................................................................................................... 26 Reset and Interrupt Handling..................................................................................................... 27 11. AVR Memories.........................................................................................................29 11.1. 11.2. 11.3. 11.4. Overview.....................................................................................................................................29 In-System Reprogrammable Flash Program Memory................................................................ 29 SRAM Data Memory...................................................................................................................30 EEPROM Data Memory............................................................................................................. 31 11.5. I/O Memory.................................................................................................................................32 11.6. Register Description................................................................................................................... 32 12. System Clock and Clock Options............................................................................ 39 12.1. Clock Systems and their Distribution..........................................................................................39 12.2. Clock Sources............................................................................................................................ 40 12.3. Default Clock Source..................................................................................................................41 12.4. Crystal Oscillator........................................................................................................................ 41 12.5. Low-frequency Crystal Oscillator................................................................................................42 12.6. External RC Oscillator................................................................................................................ 43 12.7. Calibrated Internal RC Oscillator................................................................................................43 12.8. External Clock............................................................................................................................ 44 12.9. Timer/Counter Oscillator.............................................................................................................45 12.10. Register Description...................................................................................................................45 13. Power Management and Sleep Modes................................................................... 47 13.1. 13.2. 13.3. 13.4. 13.5. 13.6. 13.7. 13.8. 13.9. Sleep Modes...............................................................................................................................47 Idle Mode....................................................................................................................................48 ADC Noise Reduction Mode.......................................................................................................48 Power-down Mode......................................................................................................................48 Power-save Mode.......................................................................................................................48 Standby Mode............................................................................................................................ 49 Extended Standby Mode............................................................................................................ 49 Minimizing Power Consumption................................................................................................. 49 Register Description................................................................................................................... 51 14. System Control and Reset.......................................................................................53 14.1. 14.2. 14.3. 14.4. 14.5. Resetting the AVR...................................................................................................................... 53 Reset Sources............................................................................................................................53 Internal Voltage Reference.........................................................................................................57 Watchdog Timer......................................................................................................................... 57 Register Description................................................................................................................... 58 15. Interrupts................................................................................................................. 62 15.1. Interrupt Vectors in ATmega32A.................................................................................................62 15.2. Register Description................................................................................................................... 66 16. External Interrupts................................................................................................... 69 16.1. Register Description................................................................................................................... 69 17. I/O Ports.................................................................................................................. 74 17.1. 17.2. 17.3. 17.4. Overview.....................................................................................................................................74 Ports as General Digital I/O........................................................................................................75 Alternate Port Functions.............................................................................................................78 Register Description................................................................................................................... 88 18. Timer/Counter0 and Timer/Counter1 Prescalers................................................... 102 18.1. Overview...................................................................................................................................102 18.2. Internal Clock Source............................................................................................................... 102 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 4 18.3. Prescaler Reset........................................................................................................................102 18.4. External Clock Source..............................................................................................................102 18.5. Register Description................................................................................................................. 103 19. 16-bit Timer/Counter1............................................................................................105 19.1. Features................................................................................................................................... 105 19.2. Overview...................................................................................................................................105 19.3. Accessing 16-bit Registers.......................................................................................................107 19.4. Timer/Counter Clock Sources...................................................................................................110 19.5. Counter Unit..............................................................................................................................110 19.6. Input Capture Unit.....................................................................................................................111 19.7. Output Compare Units.............................................................................................................. 113 19.8. Compare Match Output Unit..................................................................................................... 115 19.9. Modes of Operation.................................................................................................................. 116 19.10. Timer/Counter Timing Diagrams.............................................................................................. 123 19.11. Register Description................................................................................................................. 124 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation............................. 140 20.1. Features................................................................................................................................... 140 20.2. Overview...................................................................................................................................140 20.3. Timer/Counter Clock Sources.................................................................................................. 141 20.4. Counter Unit............................................................................................................................. 141 20.5. Output Compare Unit................................................................................................................142 20.6. Compare Match Output Unit.....................................................................................................144 20.7. Modes of Operation..................................................................................................................145 20.8. Timer/Counter Timing Diagrams...............................................................................................149 20.9. Asynchronous Operation of the Timer/Counter........................................................................ 150 20.10. Timer/Counter Prescaler.......................................................................................................... 152 20.11. Register Description................................................................................................................. 152 21. 8-bit Timer/Counter0 with PWM.............................................................................162 21.1. 21.2. 21.3. 21.4. 21.5. 21.6. 21.7. 21.8. 21.9. Features................................................................................................................................... 162 Overview...................................................................................................................................162 Timer/Counter Clock Sources.................................................................................................. 163 Counter Unit............................................................................................................................. 163 Output Compare Unit................................................................................................................164 Compare Match Output Unit.....................................................................................................166 Modes of Operation..................................................................................................................167 Timer/Counter Timing Diagrams...............................................................................................171 Register Description................................................................................................................. 172 22. SPI - Serial Peripheral Interface........................................................................... 180 22.1. 22.2. 22.3. 22.4. 22.5. Features................................................................................................................................... 180 Overview...................................................................................................................................180 SS Pin Functionality................................................................................................................. 183 Data Modes.............................................................................................................................. 184 Register Description................................................................................................................. 185 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 5 23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter.............................................................................................................190 23.1. Features................................................................................................................................... 190 23.2. Overview...................................................................................................................................190 23.3. Clock Generation......................................................................................................................192 23.4. Frame Formats.........................................................................................................................195 23.5. USART Initialization..................................................................................................................196 23.6. Data Transmission - The USART Transmitter......................................................................... 197 23.7. Data Reception - The USART Receiver.................................................................................. 199 23.8. Asynchronous Data Reception.................................................................................................203 23.9. Multi-Processor Communication Mode.....................................................................................205 23.10. Accessing UBRRH/UCSRC Registers..................................................................................... 206 23.11. Register Description................................................................................................................. 208 23.12. Examples of Baud Rate Setting............................................................................................... 217 24. TWI - Two-wire Serial Interface............................................................................. 221 24.1. 24.2. 24.3. 24.4. 24.5. 24.6. 24.7. 24.8. Features................................................................................................................................... 221 Overview...................................................................................................................................221 Two-Wire Serial Interface Bus Definition..................................................................................223 Data Transfer and Frame Format.............................................................................................224 Multi-master Bus Systems, Arbitration and Synchronization....................................................227 Using the TWI...........................................................................................................................228 Multi-master Systems and Arbitration.......................................................................................245 Register Description................................................................................................................. 246 25. AC - Analog Comparator....................................................................................... 253 25.1. Overview...................................................................................................................................253 25.2. Analog Comparator Multiplexed Input...................................................................................... 253 25.3. Register Description................................................................................................................. 254 26. ADC - Analog to Digital Converter.........................................................................258 26.1. Features................................................................................................................................... 258 26.2. Overview...................................................................................................................................258 26.3. 26.4. 26.5. 26.6. 26.7. 26.8. Starting a Conversion...............................................................................................................260 Prescaling and Conversion Timing...........................................................................................261 Changing Channel or Reference Selection.............................................................................. 264 ADC Noise Canceler................................................................................................................ 265 ADC Conversion Result............................................................................................................269 Register Description................................................................................................................. 271 27. JTAG Interface and On-chip Debug System..........................................................282 27.1. 27.2. 27.3. 27.4. 27.5. 27.6. 27.7. Features................................................................................................................................... 282 Overview...................................................................................................................................282 TAP - Test Access Port............................................................................................................ 283 TAP Controller.......................................................................................................................... 284 Using the Boundary-scan Chain...............................................................................................285 Using the On-chip Debug System............................................................................................ 285 On-chip Debug Specific JTAG Instructions.............................................................................. 286 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 6 27.8. Using the JTAG Programming Capabilities.............................................................................. 286 27.9. Bibliography..............................................................................................................................287 27.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................287 27.11. Data Registers..........................................................................................................................288 27.12. Boundry-scan Specific JTAG Instructions................................................................................ 290 27.13. Boundary-scan Chain...............................................................................................................291 27.14. ATmega32A Boundary-scan Order.......................................................................................... 301 27.15. Boundary-scan Description Language Files............................................................................ 307 27.16. Register Description.................................................................................................................308 28. BTLDR - Boot Loader Support - Read-While-Write Self-Programming................ 311 28.1. 28.2. 28.3. 28.4. 28.5. 28.6. 28.7. 28.8. 28.9. Features....................................................................................................................................311 Overview...................................................................................................................................311 Application and Boot Loader Flash Sections............................................................................ 311 Read-While-Write and No Read-While-Write Flash Sections...................................................312 Boot Loader Lock Bits.............................................................................................................. 314 Entering the Boot Loader Program...........................................................................................315 Addressing the Flash During Self-Programming...................................................................... 316 Self-Programming the Flash.....................................................................................................317 Register Description................................................................................................................. 324 29. Memory Programming........................................................................................... 327 29.1. Program and Data Memory Lock Bits.......................................................................................327 29.2. Fuse Bits...................................................................................................................................328 29.3. Signature Bytes........................................................................................................................ 330 29.4. Signature Bytes........................................................................................................................ 330 29.5. Calibration Byte........................................................................................................................ 330 29.6. Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 330 29.7. Parallel Programming...............................................................................................................333 29.8. Serial Downloading...................................................................................................................341 29.9. Serial Programming Pin Mapping.............................................................................................341 29.10. Programming Via the JTAG Interface.......................................................................................345 30. Electrical Characteristics....................................................................................... 359 30.1. 30.2. 30.3. 30.4. 30.5. 30.6. 30.7. DC Characteristics....................................................................................................................359 Speed Grades.......................................................................................................................... 362 Clock Characteristics................................................................................................................362 System and Reset Characteristics........................................................................................... 363 Two-wire Serial Interface Characteristics................................................................................. 363 SPI Timing Characteristics....................................................................................................... 365 ADC Characteristics................................................................................................................. 367 31. Typical Characteristics...........................................................................................371 31.1. 31.2. 31.3. 31.4. 31.5. 31.6. Active Supply Current...............................................................................................................371 Idle Supply Current...................................................................................................................374 Power-down Supply Current.....................................................................................................377 Power-save Supply current...................................................................................................... 378 Standby Supply Current........................................................................................................... 379 Pin Pull-up................................................................................................................................ 379 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 7 31.7. Pin Driver Strength................................................................................................................... 381 31.8. Pin Thresholds and Hysteresis.................................................................................................383 31.9. BOD Thresholds and Analog Comparator Offset..................................................................... 386 31.10. Internal Oscillator Speed..........................................................................................................388 31.11. Current Consumption of Peripheral Units.................................................................................394 31.12. Current Consumption in Reset and Reset Pulsewidth............................................................. 397 32. Register Summary.................................................................................................399 33. Instruction Set Summary....................................................................................... 401 34. Packaging Information...........................................................................................406 34.1. 44-pin TQFP.............................................................................................................................406 34.2. 40-pin PDIP.............................................................................................................................. 407 34.3. 44-pin VQFN.............................................................................................................................408 35. Errata.....................................................................................................................409 35.1. ATmega32A, rev. J to rev. K..................................................................................................... 409 35.2. ATmega32A, rev. G to rev. I......................................................................................................410 36. Datasheet Revision History................................................................................... 412 36.1. 36.2. 36.3. 36.4. 36.5. 36.6. 36.7. 36.8. 36.9. 8155I - 08/2016........................................................................................................................ 412 8155H - 08/2016.......................................................................................................................412 8155G - 10/2015...................................................................................................................... 412 8155F - 08/2015....................................................................................................................... 412 8155E - 02/2014.......................................................................................................................412 8155D - 10/2013......................................................................................................................412 8155C - 02/2011....................................................................................................................... 412 8155B - 07/2009...................................................................................................................... 413 8155A - 06/2008...................................................................................................................... 413 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 8 1. Description The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega32A provides the following features: 32Kbytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024bytes EEPROM, 2048bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The Atmel AVR ATmega32A is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 9 2. Configuration Summary Features ATmega32A Pin count 44 Flash (KB) 32 SRAM (KB) 2 EEPROM (KB) 1 General Purpose I/O pins 32 SPI 1 TWI (I2C) 1 USART 1 ADC 10-bit, up to 76.9ksps (15ksps at max resolution) ADC channels 8 AC propagation delay Typ 400ns 8-bit Timer/Counters 2 16-bit Timer/Counters 1 PWM channels 4 RC Oscillator +/-3% VREF Bandgap Operating voltage 2.7 - 5.5V Max operating frequency 16MHz Temperature range -55C to +125C JTAG Yes Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 10 3. Ordering Information Speed (MHz) 16 Power Supply 2.7 - 5.5V Ordering Code(2) Package(1) ATmega32A-AU ATmega32A-AUR(3) 44A 44A ATmega32A-PU 40P6 ATmega32A-MU 44M1 ATmega32A-MUR(3) 44M1 ATmega32A-AN ATmega32A-ANR(3) 44A 44A ATmega32A-MN 44M1 ATmega32A-MNR(3) 44M1 Operational Range Industrial (-40oC to 85oC) Extended (-40oC to 105oC)(4) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Tape and Reel 4. See characterization specifications at 105C Package Type 44A 44-lead, 10 x 10 x 1.0mm, Thin Profile Plastic Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 11 4. Block Diagram Figure 4-1. Block Diagram SRAM TCK TMS TDI TDO JTAG OCD PARPROG MOSI MISO SCK CPU FLASH NVM programming EEPROMIF SPIPROG EEPROM Clock generation XTAL1 XTAL2 TOSC1 8MHz Crystal Osc 8MHz Calib RC 12MHz External RC Osc External clock 32.768kHz XOSC 1MHz int osc Power management and clock control D A T A B U S I/O PORTS PA[7:0] PB[7:0] PC[7:0] PD[7:0] TOSC2 ExtInt VCC RESET GND Power Supervision POR/BOD & RESET Watchdog Timer Internal Reference MISO MOSI SCK SS SPI SDA SCL TWI RxD0 TxD0 XCK0 USART 0 ADC AC INT[2:0] ADC[7:0] AREF AIN0 AIN1 ADCMUX TC 0 T0 OC0 TC 1 OC1A/B/C T1 ICP1 (8-bit sync) (16-bit) TC 2 (8-bit async) OC2 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 12 Pin Configurations Figure 5-1. Pinout TQFP ATmega32A PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/ INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) 44 43 42 41 40 39 38 37 36 35 34 Power Ground Programming/debug Digital Analog Crystal/Osc GND 6 28 GND XTAL2 7 27 AVCC XTAL1 8 26 PC7 (TOSC2) (RXD) PD0 9 25 PC6 (TOSC1) (TXD) PD1 10 24 PC5 (TDI) (INT0) PD2 11 23 PC4 (TDO) (SDA) PC1 22 AREF (TMS) PC3 29 21 5 (TCK) PC2 VCC 20 PA7 (ADC7) 19 30 (SCL) PC0 4 18 RESET GND PA6 (ADC6) 17 31 VCC 3 16 (SCK) PB7 (OC2) PD7 PA5 (ADC5) 15 32 (ICP1) PD6 2 14 (MISO) PB6 (OC1A) PD5 PA4 (ADC4) 13 33 (OC1B) PD4 1 12 (MOSI) PB5 (INT1) PD3 5. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 13 Figure 5-2. Pinout PDIP ATmega32A AIN0/ INT2 5.1. VCC Digital supply voltage. 5.2. GND Ground. 5.3. PortA (PA7:PA0) Port A serves as the analog inputs to the A/D Converter. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 14 Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running. 5.4. Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32A as listed in Alternate Functions of Port B. Related Links Alternate Functions of Port B on page 81 5.5. Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. The TD0 pin is tristated unless TAP states that shift out data are entered. Port C also serves the functions of the JTAG interface and other special features of the ATmega32A as listed in Alternate Functions of Port C. Related Links Alternate Functions of Port C on page 84 5.6. Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega32A as listed in Alternate Functions of Port D. Related Links Alternate Functions of Port D on page 86 5.7. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in System and Reset Characteristics. Shorter pulses are not guaranteed to generate a reset. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 15 Related Links System and Reset Characteristics on page 363 5.8. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 5.9. XTAL2 Output from the inverting Oscillator amplifier. 5.10. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 5.11. AREF AREF is the analog reference pin for the A/D Converter. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 16 6. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 17 7. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 18 8. About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 19 9. Capacitive Touch Sensing The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most (R) Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API's to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 20 10. AVR CPU Core 10.1. Overview This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 10-1. Block Diagram of the AVR MCU Architecture Register file R31 (ZH) R29 (YH) R27 (XH) R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 R30 (ZL) R28 (YL) R26 (XL) R24 R22 R20 R18 R16 R14 R12 R10 R8 R6 R4 R2 R0 Program counter Flash program memory Instruction register Instruction decode Data memory Stack pointer Status register ALU In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 21 as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 10.2. ALU - Arithmetic Logic Unit The high-performance Atmel AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description. 10.3. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 22 10.3.1. SREG - The AVR Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SREG Offset: 0x3F Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x5F Bit Access Reset 7 6 5 4 3 2 1 0 I T H S V N Z C R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference. Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 23 Bit 0 - C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. 10.4. General Purpose Register File The Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * * * * One 8-bit output operand and one 8-bit result input. Two 8-bit output operands and one 8-bit result input. Two 8-bit output operands and one 16-bit result input. One 16-bit output operand and one 16-bit result input. The following figure shows the structure of the 32 general purpose working registers in the CPU. Figure 10-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D Ge ne ra l R14 0x0E P urpos e R15 0x0F Working R16 0x10 Re gis te rs R17 0x11 ... R26 0x1A X-re gis te r Low Byte R27 0x1B X-re gis te r High Byte R28 0x1C Y-re gis te r Low Byte R29 0x1D Y-re gis te r High Byte R30 0x1E Z-re gis te r Low Byte R31 0x1F Z-re gis te r High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in the figure above, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. 10.4.1. The X-register, Y-register and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in the following figure. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 24 Figure 10-3. The X-, Y- and Z-Registers 15 X-re gis te r XH 7 XL 0 7 R27 (0x1B) 15 Y-re gis te r YL 0 Z-re gis te r ZH 7 0 0 7 R29 (0x1D) 15 0 R26 (0x1A) YH 7 0 0 R28 (0x1C) ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). 10.5. Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, refer to figure Data Memory Map in SRAM Data Memory. The following table contains Stack Pointer details. Table 10-1. Stack Pointer instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt RCALL The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 25 Figure 10-4. SPH and SPL - Stack Pointer High and Low Register Bit 15 14 13 12 11 10 9 8 0x3E S P15 S P14 S P13 S P12 S P11 S P10 S P9 S P8 S PH 0x3D S P7 S P6 S P5 S P4 S P3 S P2 S P1 S P0 S PL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Re a d/Write Initia l Va lue 0 0 Related Links SRAM Data Memory on page 30 10.6. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The following figure shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 10-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCP U 1s t Ins truction Fe tch 1s t Ins truction Exe cute 2nd Ins truction Fe tch 2nd Ins truction Exe cute 3rd Ins truction Fe tch 3rd Ins truction Exe cute 4th Ins truction Fe tch The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 10-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCP U Tota l Exe cution Time Re gis te r Ope ra nds Fe tch ALU Ope ra tion Exe cute Re s ult Write Ba ck Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 26 10.7. Reset and Interrupt Handling The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section Memory Programming for details. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to Interrupts for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support - Read-While-Write Self-Programming. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 27 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set global interrupt enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _enable_interrupt(); /* set global interrupt enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ Related Links Memory Programming on page 327 Interrupts on page 62 BTLDR - Boot Loader Support - Read-While-Write Self-Programming on page 311 10.7.1. Interrupt Response Time The interrupt execution response for all the enabled Atmel AVR interrupts is four clock cycles minimum. After four clock cycles, the Program Vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I-bit in SREG is set. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 28 11. AVR Memories 11.1. Overview This section describes the different memories in the Atmel AVR ATmega32A. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega32A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 11.2. In-System Reprogrammable Flash Program Memory The ATmega32A contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 16K x 16 bits. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32A Program Counter (PC) is 14 bits wide, thus addressing the 16K Program memory locations. The operation of Boot Program section and associated Boot Lock Bits for software protection are described in detail in Boot Loader Support - Read-While-Write Self-Programming. Memory Programming contains a detailed description on Flash Programming in SPI, JTAG, or Parallel Programming mode. Constant tables can be allocated within the entire Program memory address space (see the LPM - Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in Instruction Execution Timing. Figure 11-1. Program Memory Map $0000 Applica tion Fla s h S e ction Boot Fla s h S e ction $7FFF Related Links BTLDR - Boot Loader Support - Read-While-Write Self-Programming on page 311 Memory Programming on page 327 Instruction Execution Timing on page 26 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 29 11.3. SRAM Data Memory The figure below shows how the Atmel AVR ATmega32A SRAM Memory is organized. The lower 2144 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 2048 bytes of internal data SRAM in the ATmega32A are all accessible through all these addressing modes. The Register File is described in General Purpose Register File. Figure 11-2. Data Memory Map Re gis te r File Da ta Addre s s S pa ce R0 R1 R2 ... $0000 $0001 $0002 ... R29 R30 R31 I/O Re gis te rs $00 $01 $02 ... $001D $001E $001F $3D $3E $3F $005D $005E $005F Inte rna l S RAM $0060 $0061 ... $0020 $0021 $0022 ... $045E $045F Related Links General Purpose Register File on page 24 11.3.1. Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in the figure below. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 30 Figure 11-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCP U Addre s s Compute Addre s s Addre s s Va lid Write Da ta WR Re a d Da ta RD Me mory Vcce s s Ins truction 11.4. Next Ins truction EEPROM Data Memory The Atmel AVR ATmega32A contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described below, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. Memory Programming contains a detailed description on EEPROM Programming in SPI, JTAG, or Parallel Programming mode. Related Links Memory Programming on page 327 11.4.1. EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in the table "EEPROM Programming Time". A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Preventing EEPROM Corruption for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. Related Links EECR on page 36 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 31 11.4.2. EEPROM Write during Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation is completed, the Oscillator continues running, and as a consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 11.4.3. Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 11.5. I/O Memory The I/O space definition of the ATmega32A is shown in Register Summary. All ATmega32A I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections. Related Links Register Summary on page 399 11.6. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 32 11.6.1. EEARL - The EEPROM Address Register Low When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: EEARL Offset: 0x1E Reset: 0xXX Property: When addressing I/O Registers as data space the offset address is 0x3E Bit Access Reset 7 6 5 4 3 2 1 0 EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 - EEARn: EEPROM Address [n = 7:0] The EEPROM Address Registers - EEARH and EEARL - specify the EEPROM address in the 1Kbyte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1024. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. . Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 33 11.6.2. EEARH - The EEPROM Address Register High When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: EEARH Offset: 0x1F Reset: 0xXX Property: When addressing I/O Registers as data space the offset address is 0x3F Bit 7 6 5 Access Reset 4 3 2 1 0 EEAR9 EEAR8 R/W R/W x x Bit 1 - EEAR9: EEPROM Address Bit 0 - EEAR8: EEPROM Address Refer to EEARL. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 34 11.6.3. EEDR - The EEPROM Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: EEDR Offset: 0x1D Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x3D Bit Access Reset 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - EEDRn: EEPROM Data [n = 7:0] For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. * * EEDR[7] is MSB EEDR[0] is LSB Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 35 11.6.4. EECR - The EEPROM Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: EECR Offset: 0x1C Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x3C Bit 7 Access Reset 6 5 4 3 2 1 0 EERIE EEMWE EEWE EERE R/W R/W R/W R/W 0 0 x 0 Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. Bit 1 - EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. 2. 3. 4. 5. 6. Wait until EEWE becomes zero. Wait until SPMEN in SPMCR becomes zero. Write new EEPROM address to EEAR (optional). Write new EEPROM data to EEDR (optional). Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Boot Loader Support - Read-While-Write Self-Programming for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 36 When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. The following table lists the typical programming time for EEPROM access from the CPU. Table 11-1. EEPROM Programming Time Symbol Number of Calibrated RC Oscillator Cycles(1) Typ Programming Time EEPROM Write (from CPU) 8448 8.5ms Note: 1. Uses 1MHz clock, independent of CKSEL Fuse settings. The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)) ; /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 37 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)) ; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; } Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 38 12. 12.1. System Clock and Clock Options Clock Systems and their Distribution The figure below presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Power Management and Sleep Modes. The clock systems are detailed in the following figure. Figure 12-1. Clock Distribution As ynchronous Time r/Counte r Ge ne ra l I/O Module s ADC CP U Core RAM Fla s h a nd EEP ROM clkADC clkI/O AVR Clock Control Unit clkAS Y clkCP U clkFLAS H Re s e t Logic S ource Clock Wa tchdog Clock Clock Multiplexe r Time r/Counte r Os cilla tor Exte rna l RC Os cilla tor Exte rna l Clock Wa tchdog Time r Wa tchdog Os cilla tor Crys ta l Os cilla tor Low-Fre que ncy Crys ta l Os cilla tor Ca libra te d RC Os cilla tor 12.1.1. CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 12.1.2. I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchronously when clkI/O is halted, enabling TWI address reception in all sleep modes. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 39 12.1.3. Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 12.1.4. Asynchronous Timer Clock - clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 12.1.5. ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 12.2. Clock Sources The device has the following clock source options, selectable by Flash Fuse Bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 12-1. Device Clocking Options Select Device Clocking Option CKSEL3:0(1) External Crystal/Ceramic Resonator 1111 - 1010 External Low-frequency Crystal 1001 External RC Oscillator 1000 - 0101 Calibrated Internal RC Oscillator 0100 - 0001 External Clock 0000 Note: 1. For all fuses "1" means unprogrammed while "0" means programmed. The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in the table below. The frequency of the Watchdog Oscillator is voltage dependent as shown in Typical Characteristics. Table 12-2. Number of Watchdog Oscillator Cycles Typical Time-out (VCC = 5.0V) Typical Time-out (VCC = 3.0V) Number of Cycles 4.1ms 4.3ms 4K (4,096) 65ms 69ms 64K (65,536) Related Links Typical Characteristics on page 371 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 40 12.3. Default Clock Source The device is shipped with CKSEL = "0001" and SUT = "10". The default clock source setting is therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel Programmer. 12.4. Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in the figure below. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating in a very noisy environment or when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces power consumption considerably. This mode has a limited frequency range and it cannot be used to drive other clock buffers. For resonators, the maximum frequency is 8MHz with CKOPT unprogrammed and 16MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the next table. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 12-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as shown in the following table. Table 12-3. Crystal Oscillator Operating Modes CKOPT(1) CKSEL3:1 Frequency Range(MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 1 101(2) 0.4 - 0.9 - 1 110 0.9 - 3.0 12 - 22 1 111 3.0 - 8.0 12 - 22 0 101, 110, 111 1.0 -16.0 12 - 22 Note: 1. When CKOPT is programmed (0), the oscillator output will be a full rail-to-rail swing on the output. 2. This option should not be used with crystals, only with ceramic resonators. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 41 The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as shown in the next table. Table 12-4. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 00 258 CK(1) 4.1ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65ms Ceramic resonator, slowly rising power 0 10 1K CK(2) - Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.1ms Ceramic resonator, fast rising power 1 00 1K CK(2) 65ms Ceramic resonator, slowly rising power 1 01 16K CK - Crystal Oscillator, BOD enabled 1 10 16K CK 4.1ms Crystal Oscillator, fast rising power 1 11 16K CK 65ms Crystal Oscillator, slowly rising power Note: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 12.5. Low-frequency Crystal Oscillator To use a 32.768kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to "1001". The crystal should be connected as shown in Figure 12-2. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36pF. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in the table below. Table 12-5. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 1K CK(1) 4.1ms Fast rising power or BOD enabled 01 1K CK(1) 65ms Slowly rising power 10 32K CK 65ms Stable frequency at start-up 11 Reserved Note: 1. These options should only be used if frequency stability at start-up is not important for the application. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 42 12.6. External RC Oscillator For timing insensitive applications, the external RC configuration shown in the figure below can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22pF. By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor. Figure 12-3. External RC Configuration VCC R NC XTAL2 XTAL1 C GND The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:0 as shown in the following table. Table 12-6. External RC Oscillator Operating Modes CKSEL3:0 Frequency Range (MHz) 0101 0.1 - 0.9 0110 0.9 - 3.0 0111 3.0 - 8.0 1000 8.0 - 12.0 When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in the table below. Table 12-7. Start-up Times for the External RC Oscillator Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 18 CK - BOD enabled 01 18 CK 4.1ms Fast rising power 10 18 CK 65ms Slowly rising power 11 6 CK(1) 4.1ms Fast rising power or BOD enabled Note: 1. This option should not be used when operating close to the maximum frequency of the device. 12.7. Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0MHz clock. All frequencies are nominal values at 5V and 25C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in the following table. If selected, it will operate with no external components. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 43 The CKOPT Fuse should always be unprogrammed when using this clock option. During reset, hardware loads the 1MHz calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V, 25C and 1.0MHz Oscillator frequency selected, this calibration gives a frequency within 3% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve 1% accuracy at any given VCC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section Calibration Byte. Table 12-8. Internal Calibrated RC Oscillator Operating Modes CKSEL3:0 Nominal Frequency (MHz) 0001(1) 1.0 0010 2.0 0011 4.0 0100 8.0 Note: 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in the following table. XTAL1 and XTAL2 should be left unconnected (NC). Table 12-9. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset Recommended Usage (VCC = 5.0V) 00 6 CK - BOD enabled 01 6 CK 4.1ms Fast rising power 10(1) 6 CK 65ms Slowly rising power 11 Reserved Note: 1. The device is shipped with this option selected. Related Links Calibration Byte on page 330 12.8. External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in the figure below. To run the device on an external clock, the CKSEL Fuses must be programmed to "0000". By programming the CKOPT Fuse, the user can enable an internal 36pF capacitor between XTAL1 and GND. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 44 Figure 12-4. External Clock Drive Configuration EXTERNAL CLOCK S IGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in the following table. Table 12-10. Start-up Times for the External Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 6 CK - BOD enabled 01 6 CK 4.1ms Fast rising power 10 6 CK 65ms Slowly rising power 11 Reserved When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. 12.9. Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock source to TOSC1 is not recommended. Note: 1. The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36pF. 12.10. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 45 12.10.1. OSCCAL - The Oscillator Calibration Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: OSCCAL Offset: 0x31 Reset: 0x00 Property: Bit Access 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Reset Bits 7:0 - CALn: Oscillator Calibration Value [n = 7:0] Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1MHz calibration value which is located in the signature row High byte (address 0x00) is automatically loaded into the OSCCAL Register. If the internal RC is used at other frequencies, the calibration values must be loaded manually. This can be done by first reading the signature row by a programmer, and then store the calibration values in the Flash or EEPROM. Then the value can be read by software and loaded into the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing 0xFF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in the following table. Table 12-11. Internal RC Oscillator Frequency Range OSCCAL Value Min Frequency in Percentage of Nominal Frequency (%) Max Frequency in Percentage of Nominal Frequency (%) 0x00 50 100 0x7F 75 150 0xFF 100 200 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 46 13. 13.1. Power Management and Sleep Modes Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. Figure Clock Distribution in section Clock Systems and their Distribution presents the different clock systems in the ATmega32A, and their distribution. The figure is helpful in selecting an appropriate sleep mode. The table below shows the different clock options and their wake-up sources. Table 13-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains Sleep Mode Idle ADC Noise Reduction Oscillators clkCPU clkFLASH clkIO clkADC clkASY Main Clock Source Enabled X X X X X Timer Osc. Enabled INT2/ INT1/ INT0 TWIAddress Timer2 SPM/ Match EEPROM Ready ADC Other I/O X X(2) X X X X X X X(2) X(3) X X X X X(3) X X(3) X X(3) X X(3) X Powerdown Powersave X(2) Standby(1 ) Extended Standby(1 ) X(2) X X(2) Wake-up Sources X X(2) X X(2) X(2) Note: 1. External Crystal or resonator selected as clock source. 2. If AS2 bit in ASSR is set. 3. Only INT2 or level interrupt INT1 and INT0. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP instruction. See Table 13-2 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Related Links Clock Systems and their Distribution on page 39 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 47 13.2. Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register - ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 13.3. ADC Noise Reduction Mode When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an External level interrupt on INT0 or INT1, or an external interrupt on INT2 can wake up the MCU from ADC Noise Reduction mode. 13.4. Power-down Mode When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brownout Reset, a Two-wire Serial Interface address match interrupt, an External Level Interrupt on INT0 or INT1, or an External Interrupt on INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to External Interrupts for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in Clock Sources. Related Links External Interrupts on page 69 Clock Sources on page 40 13.5. Power-save Mode When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 48 * If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt enable bit in SREG is set. If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter2 if clocked asynchronously. 13.6. Standby Mode When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles. 13.7. Extended Standby Mode When the SM2:0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 13.8. Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 13.8.1. Analog-to-Digital Converter (ADC) If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to Analog-to-Digital Converter for details on ADC operation. Related Links ADC - Analog to Digital Converter on page 258 13.8.2. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to Analog Comparator for details on how to configure the Analog Comparator. Related Links AC - Analog Comparator on page 253 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 49 13.8.3. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brownout Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Brown-out Detection for details on how to configure the Brown-out Detector. Related Links Brown-out Detection on page 56 13.8.4. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to Internal Voltage Reference for details on the start-up time. Related Links Internal Voltage Reference on page 57 13.8.5. Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Watchdog Timer for details on how to configure the Watchdog Timer. Related Links Watchdog Timer on page 57 13.8.6. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep Modes for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. Related Links Digital Input Enable and Sleep Modes on page 78 13.8.7. JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: * * * Disable OCDEN Fuse. Disable JTAGEN Fuse. Write one to the JTD bit in MCUCSR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 50 that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. 13.9. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 51 13.9.1. MCUCR - MCU Control Register The MCU Control Register contains control bits for power management. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: MCUCR Offset: 0x35 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x55 Bit Access 7 6 5 4 3 SE SM2 SM1 SM0 R/W R/W R/W R/W 0 0 0 0 Reset 2 1 0 Bit 7 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to set the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. Bits 6:4 - SMn: Sleep Mode n Select Bits [n = 2:0] These bits select between the six available sleep modes as shown in the table. Table 13-2. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC Noise Reduction 0 1 0 Power-down 0 1 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) 1 1 1 Extended Standby (1) Note: 1. Standby mode is only available with external crystals or resonators. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 52 14. System Control and Reset 14.1. Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP - absolute jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa. The circuit diagram in the following section shows the Reset Logic. The Table in System and Reset Characteristics defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in Clock Sources. Related Links System and Reset Characteristics on page 363 Clock Sources on page 40 14.2. Reset Sources The ATmega32A has five sources of Reset: * * * * * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled. JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section IEEE 1149.1 (JTAG) Boundary-scan for details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 53 Figure 14-1. Reset Logic DATA BUS P ORF BORF EXTRF WDRF JTRF MCU Control a nd S ta tus Re gis te r (MCUCS R) Brown-Out Re s e t Circuit BODEN BODLEVEL P ull-up Re s is tor S P IKE FILTER JTAG Reset Register Wa tchdog Os cilla tor Clock Ge ne ra tor CK De lay Counte rs TIMEOUT CKS EL[3:0] S UT[1:0] Related Links IEEE 1149.1 (JTAG) Boundary-scan on page 287 14.2.1. Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in the table in System and Reset Characteristics. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 54 Figure 14-2. MCU Start-up, RESET Tied to VCC VCC RES ET VP OT VRS T tTOUT TIME-OUT INTERNAL RES ET Figure 14-3. Figure: MCU Start-up, RESET Extended Externally VCC VP OT RES ET TIME-OUT VRS T tTOUT INTERNAL RES ET Related Links System and Reset Characteristics on page 363 14.2.2. External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see table in System and Reset Characteristics) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST on its positive edge, the delay counter starts the MCU after the time-out period tTOUT has expired. Figure 14-4. External Reset During Operation CC Related Links System and Reset Characteristics on page 363 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 55 14.2.3. Brown-out Detection ATmega32A has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and VCC decreases to a value below the trigger level (VBOT- in the figure below), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in the figure below), the delay counter starts the MCU after the time-out period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in the table in System and Reset Characteristics. Figure 14-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RES ET tTOUT TIME-OUT INTERNAL RES ET Related Links System and Reset Characteristics on page 363 14.2.4. Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to Watchdog Timer for details on operation of the Watchdog Timer. Figure 14-6. Watchdog Reset During Operation CC CK Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 56 14.3. Internal Voltage Reference ATmega32A features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. 14.3.1. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in the table in System and Reset Characteristics. To save power, the reference is not always turned on. The reference is on during the following situations: 1. 2. 3. When the BOD is enabled (by programming the BODEN Fuse). When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Related Links System and Reset Characteristics on page 363 14.4. Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in the figure below. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATmega32A resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to the Watchdog Reset. To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer Control Register for details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 57 Figure 14-7. Watchdog Timer WATCHDOG OS CILLATOR Related Links Watchdog Reset on page 56 14.5. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 58 14.5.1. MCUCSR - MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The MCU Control and Status Register provides information on which reset source caused an MCU Reset. Name: MCUCSR Offset: 0x34 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x54 Bit Access Reset 7 6 5 4 3 2 1 0 JTRF WDRF BORF EXTRF PORF R/W R/W R/W R/W R/W - - - - - Bit 4 - JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 59 14.5.2. WDTCR - Watchdog Timer Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: WDTCR Offset: 0x21 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x41 Bit 7 6 5 Access Reset 4 3 2 1 0 WDTOE WDE WDP2 WDP1 WDP0 R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 4 - WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. Bit 3 - WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. Bits 2:0 - WDPn: Watchdog Timer Prescaler 2, 1, and 0 [n = 2:0] The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in the table below. Table 14-1. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 Number of WDT Oscillator Typical Cycles Time-out at VCC = 3.0V Typical Time-out at VCC = 5.0V 0 0 0 16K (16,384) 17.1ms 16.3ms 0 0 1 32K (32,768) 34.3ms 32.5ms 0 1 0 64K (65,536) 68.5ms 65ms 0 1 1 128K (131,072) 0.14s 0.13s 1 0 0 256K (262,144) 0.27s 0.26s 1 0 1 512K (524,288) 0.55s 0.52s 1 1 0 1,024K (1,048,576) 1.1s 1.0s 1 1 1 2,048K (2,097,152) 2.2s 2.1s Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 60 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example WDT_off: ; Reset WDT wdr ; Write logical one to WDTOE and WDE in r16, WDTCR ldi r16, (1<<WDTOE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret C Code Example void WDT_off(void) { /* Reset WDT*/ _WDRC(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 61 15. Interrupts This section describes the specifics of the interrupt handling performed by the ATmega32A. For a general explanation of the AVR interrupt handling, refer to Reset and Interrupt Handling. Related Links Reset and Interrupt Handling on page 27 15.1. Interrupt Vectors in ATmega32A Table 15-1. Reset and Interrupt Vectors Vector No. Program Source Address(2) Interrupt Definition 1 0x000(1) RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset 2 0x002 INT0 External Interrupt Request 0 3 0x004 INT1 External Interrupt Request 1 4 0x006 INT2 External Interrupt Request 2 5 0x008 TIMER2 COMP Timer/Counter2 Compare Match 6 0x00A TIMER2 OVF Timer/Counter2 Overflow 7 0x00C TIMER1 CAPT Timer/Counter1 Capture Event 8 0x00E TIMER1 COMPA Timer/Counter1 Compare Match A 9 0x010 TIMER1 COMPB Timer/Counter1 Compare Match B 10 0x012 TIMER1 OVF Timer/Counter1 Overflow 11 0x014 TIMER0 COMP Timer/Counter0 Compare Match 12 0x016 TIMER0 OVF Timer/Counter0 Overflow 13 0x018 SPI, STC SPI Serial Transfer Complete 14 0x01A USART, RXC USART, Rx Complete 15 0x01C USART, UDRE USART Data Register Empty 16 0x01E USART, TXC USART, Tx Complete 17 0x020 ADC ADC Conversion Complete 18 0x022 EE_RDY EEPROM Ready 19 0x024 ANA_COMP Analog Comparator 20 0x026 TWI Two-wire Serial Interface 21 0x028 SPM_RDY Store Program Memory Ready Note: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at reset, see Boot Loader Support - Read-While-Write Self-Programming. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 62 2. When the IVSEL bit in GICR is set, interrupt vectors will be moved to the start of the Boot Flash section. The address of each interrupt vector will then be address in this table added to the start address of the boot Flash section. The next table shows Reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the interrupt vectors are in the Boot section or vice versa. Table 15-2. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002 Note: 1. The Boot Reset Address is shown in table Boot Size Configuration in the Boot Loader Parameters section. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega32A is: address Labels Code Comments $000 jmp RESET ; Reset Handler $002 jmp EXT_INT0 ; IRQ0 Handler $004 jmp EXT_INT1 ; IRQ1 Handler $006 jmp EXT_INT2 ; IRQ2 Handler $008 jmp TIM2_COMP ; Timer2 Compare Handler $00A jmp TIM2_OVF ; Timer2 Overflow Handler $00C jmp TIM1_CAPT ; Timer1 Capture Handler $00E jmp TIM1_COMPA ; Timer1 CompareA Handler $010 jmp TIM1_COMPB ; Timer1 CompareB Handler $012 jmp TIM1_OVF ; Timer1 Overflow Handler $014 jmp TIM0_COMP ; Timer0 Compare Handler $016 jmp TIM0_OVF ; Timer0 Overflow Handler Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 63 address Labels Code Comments $018 jmp SPI_STC ; SPI Transfer Complete Handler $01A jmp USART_RXC ; USART RX Complete Handler $01C jmp USART0_UDRE ; UDR Empty Handler $01E jmp USART0_TXC ; USART TX Complete Handler $020 jmp ADC ; ADC Conversion Complete Handler $022 jmp EE_RDY ; EEPROM Ready Handler $024 jmp ANA_COMP ; Analog Comparator Handler $026 jmp TWI ; Two-wire Serial Interface Handler $028 jmp SPM_RDY ; Store Program Memory Ready Handler ldi r16,high(RAMEND) ; Main program start $02B out SPH,r16 ; Set Stack Pointer to top of RAM $02C ldi r16,low(RAMEND) $02D out SPL,r16 $02E sei $02F <instr> ; $02A :. RESET: :. ; Enable interrupts xxx :. When the BOOTRST fuse is unprogrammed, the Boot section size set to 4 Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 64 Adddress Labels Code Comments $000 RESET: ldi r16,high(RAMEND) ; Main program start $001 out SPH,r16 ; Set stack pointer to top of RAM $0002 ldi r16,low(RAMEND) $0003 out SPL,r16 $0004 sei $0005 <instr> xxx $3802 jmp EXT_INT0 ; IRQ0 Handler $3804 jmp EXT_INT1 ; IRQ1 Handler ; Enable interrupts ; .org $3802 :. :.. $3828 : jmp ; SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org $002 $002 jmp EXT_INT0 ; IRQ0 Handler $004 jmp EXT_INT1 ; IRQ1 Handler :. :.. $028 : ; jmp SPM_RDY ; Store Program Memory Handler ldi r16,high(RAMEND) ; Main program start $3801 out SPH,r16 ; Set stack pointer to top of RAM $3802 ldi r16,low(RAMEND) $3803 out SPL,r16 ; .org $3800 $3800 RESET: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 65 Address Labels Code Comments $3804 sei ; Enable interrupts $3805 <instr> xxx When the BOOTRST fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org $3800 $3800 jmp RESET ; Reset handler $3802 jmp EXT_INT0 ; IRQ0 Handler $3804 jmp EXT_INT1 ; IRQ1 Handler :. :.. $3828 : ; jmp SPM_RDY ; Store Program Memory Ready Handler ldi r16,high(RAMEND) ; Main program start $382B out SPH,r16 ; Set Stack Pointer to top of RAM $382C ldi r16,low(RAMEND) $382D out SPL,r16 $382E sei $382F <instr> ; $382A RESET: ; Enable interrupts xxx Related Links BTLDR - Boot Loader Support - Read-While-Write Self-Programming on page 311 ATmega32A Boot Loader Parameters on page 323 15.1.1. Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 15.2. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 66 15.2.1. GICR - General Interrupt Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: GICR Offset: 0x3B Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x5B Bit 7 6 5 4 Access Reset 3 2 1 0 IVSEL IVCE R/W R/W 0 0 Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses. Refer to the section Boot Loader Support - Read-While-Write Self-Programming for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. 2. Write the Interrupt Vector Change Enable (IVCE) bit to one. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: 1. If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Boot Loader Support - Read-While-Write Self-Programming for details on Boot Lock Bits. Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 67 C Code Example void Move_interrupts(void) { /* Enable change of Interrupt Vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); } Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 68 16. External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0:2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register - MCUCR - and MCU Control and Status Register - MCUCSR. When the external interrupt is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock, described in "Clock Systems and their Distribution" on page 25. Low level interrupts on INT0/INT1 and the edge interrupt on INT2 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s (nominal) at 5.0V and 25C. The frequency of the Watchdog Oscillator is voltage dependent as shown in "Electrical Characteristics" on page 296. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in "System Clock and Clock Options" on page 25. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the startup time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. Related Links Clock Systems and their Distribution on page 39 Electrical Characteristics on page 359 System Clock and Clock Options on page 39 16.1. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 69 16.1.1. MCUCR - MCU Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: MCUCR Offset: 0x35 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x55 Bit 7 6 5 Access Reset 4 3 2 1 0 ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R/W 0 0 0 0 Bits 3:2 - ISC1n: Interrupt Sense Control 1 Bit 1 and Bit 0 [n = 1:0] The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corresponding interrupt mask in the GICR are set. The level and edges on the external INT1 pin that activate the interrupt are defined in the next table. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 16-1. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Any logical change on INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. Bits 1:0 - ISC0n: Interrupt Sense Control 0 Bit 1 and Bit 0 [n = 1:0] The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in the next table. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 16-2. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 70 16.1.2. MCUCSR - MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: MCUCSR Offset: 0x34 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x54 Bit 7 6 5 4 3 2 1 0 ISC2 Access R/W Reset 0 Bit 6 - ISC2: ISC2: Interrupt Sense Control 2 The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum pulse width given in the table below will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled. Table 16-3. Asynchronous External Interrupt Characteristics Symbol Parameter tINT Minimum pulse width for asynchronou s external interrupt Condition Min Typ 50 Max Units ns Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 71 16.1.3. GICR - General Interrupt Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: GICR Offset: 0x3B Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x5B Bit Access Reset 7 6 5 INT1 INT0 INT2 R/W R/W R/W 0 0 0 4 3 2 1 0 Bit 7 - INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. Bit 5 - INT2: External Interrupt Request 2 Enable When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control2 bit (ISC2) in the MCU Control and Status Register (MCUCSR) defines whether the External Interrupt is activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interrupt request even if INT2 is configured as an output. The corresponding interrupt of External Interrupt Request 2 is executed from the INT2 Interrupt Vector. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 72 16.1.4. GIFR - General Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: GIFR Offset: 0x3A Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x5A Bit Access Reset 7 6 5 INTF1 INTF0 INTF2 R/W R/W R/W 0 0 0 4 3 2 1 0 Bit 7 - INTF1: External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. Bit 6 - INTF0: External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. Bit 5 - INTF2: External Interrupt Flag 2 When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one). If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Note that when entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See Digital Input Enable and Sleep Modes for more information. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 73 17. I/O Ports 17.1. Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in the following figure. Refer to Electrical Characteristics - TA = -40C to 85C for a complete list of parameters. Figure 17-1. I/O Pin Equivalent Schematic R pu Logic Pxn C pin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used (i.e., PORTB3 for bit 3 in Port B, here documented generally as PORTxn). The physical I/O Registers and bit locations are listed in Register Description. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. In addition, the Pullup Disable - PUD bit in SFIOR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in Ports as General Digital I/O. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Alternate Port Functions. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Related Links Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 74 Electrical Characteristics on page 359 17.2. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. The following figure shows a functional description of one I/O-port pin, here generically called Pxn. Figure 17-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET D PORTxn Q CLR WPx RESET SLEEP DATA BUS Q Pxn RDx RRx SYNCHRONIZER D Q D RPx Q PINxn L Q Q clk I/O PUD: SLEEP: clkI/O: PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: RRx: RPx: WPx: WRITE DDRx READ DDRx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports 17.2.1. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Register Description, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 75 PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. The table below summarizes the control signals for the pin value. Table 17-1. Port Pin Configurations 17.2.2. DDxn PORTxn PUD (in SFIOR) I/O Pull-up Comment 0 0 x Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if external pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 x Output No Output Low (Sink) 1 1 x Output No Output High (Source) Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register Bit. As shown in Figure 17-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. The next figure shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 17-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 76 tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 1-1/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in the figure below. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 17-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) :. ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB :. C Code Example(1) unsigned char i; :. /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; :. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 77 Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 17.2.3. Digital Input Enable and Sleep Modes As shown in figure Figure 17-2, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Powerdown mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in Alternate Port Functions. If a logic high level ("one") is present on an Asynchronous External Interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. 17.2.4. Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 17.3. Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. The following figure shows how the port pin control signals from the simplified Figure 17-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 78 Figure 17-5. Alternate Port Functions(1) PUOExn 1 PUOVxn PUD 0 DDOExn 1 DDOVxn Q D DDxn 0 Q CLR PVOExn RESET WDx RDx 1 Pxn Q 0 D PORTxn Q CLR DIEOExn 1 0 WPx DIEOVxn DATA BUS PVOVxn RESET RRx SLEEP SYNCHRONIZER D SET Q D RPx Q PINxn L CLR Q CLR Q clk I/O DIxn AIOxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PUD: Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL PULLUP DISABLE WDx: RDx: RRx: RPx: WPx: clkI/O: DIxn: AIOxn: WRITE DDRx READ DDRx READ PORTx REGISTER READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin. The following table summarizes the function of the overriding signals. The pin and port indexes from the figure above are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 17-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/ cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 79 Signal Name Full Name Description DDOE Data Direction Override Enable If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. DDOV Data Direction Override Value If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. PVOV Port Value Override Value If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. DIEOE Digital Input Enable Override Enable If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). DIEOV Digital Input Enable Override Value If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/ cleared, regardless of the MCU state (Normal mode, sleep mode). DI Digital Input This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the Schmitt Trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. AIO Analog Input/Output This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 17.3.1. Alternate Functions of Port A Port A has an alternate function as analog input for the ADC as shown in the table below. If some Port A pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. Table 17-3. Port A Pins Alternate Functions Port Pin Alternate Functions PA7 ADC7 (ADC input channel 7) PA6 ADC6 (ADC input channel 6) PA5 ADC5 (ADC input channel 5) PA4 ADC4 (ADC input channel 4) PA3 ADC3 (ADC input channel 3) PA2 ADC2 (ADC input channel 2) PA1 ADC1 (ADC input channel 1) PA0 ADC0 (ADC input channel 0) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 80 The two tables below relates the alternate functions of Port A to the overriding signals shown in the figure in section Alternate Port Functions. Table 17-4. Overriding Signals for Alternate Functions in PA7:PA4 Signal Name PA7/ADC7 PA6/ADC6 PA5/ADC5 PA4/ADC4 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI - - - - AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT Table 17-5. Overriding Signals for Alternate Functions in PA3:PA0 17.3.2. Signal Name PA3/ADC3 PA2/ADC2 PA1/ADC1 PA0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI - - - - AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port B The Port B pins with alternate functions are shown in the table below: Table 17-6. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 SCK (SPI Bus Serial Clock) PB6 MISO (SPI Bus Master Input/Slave Output) PB5 MOSI (SPI Bus Master Output/Slave Input) PB4 SS (SPI Slave Select Input) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 81 Port Pin Alternate Functions PB3 AIN1 (Analog Comparator Negative Input) OC0 (Timer/Counter0 Output Compare Match Output) PB2 AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PB1 T1 (Timer/Counter1 External Counter Input) PB0 T0 (Timer/Counter0 External Counter Input) XCK (USART External Clock Input/Output) The alternate pin configuration is as follows: * SCK - Port B, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB7 bit. * MISO - Port B, Bit 6 MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit. * MOSI - Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. * SS - Port B, Bit 4 SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit. * AIN1/OC0 - Port B, Bit 3 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. OC0, Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. * AIN0/INT2 - Port B, Bit 2 AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. INT2, External Interrupt Source 2: The PB2 pin can serve as an external interrupt source to the MCU. * T1 - Port B, Bit 1 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 82 T1, Timer/Counter1 Counter Source. * T0/XCK - Port B, Bit 0 T0, Timer/Counter0 Counter Source. XCK, USART External Clock. The Data Direction Register (DDB0) controls whether the clock is output (DDB0 set) or input (DDB0 cleared). The XCK pin is active only when the USART operates in Synchronous mode. The tables below relate the alternate functions of Port B to the overriding signals shown in the figure in section Alternate Port Functions. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 17-7. Overriding Signals for Alternate Functions in PB7:PB4 Signal Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS PUOE SPE * MSTR SPE * MSTR SPE * MSTR SPE * MSTR PUOV PORTB7 * PUD PORTB6 * PUD PORTB5 * PUD PORTB4 * PUD DDOE SPE * MSTR SPE * MSTR SPE * MSTR SPE * MSTR DDOV 0 0 0 0 PVOE SPE * MSTR SPE * MSTR SPE * MSTR 0 PVOV SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS AIO - - - - Table 17-8. Overriding Signals for Alternate Functions in PB3:PB0 Signal Name PB3/OC0/AIN1 PB2/INT2/AIN0 PB1/T1 PB0/T0/XCK PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC0 ENABLE 0 0 UMSEL PVOV OC0 0 0 XCK OUTPUT DIEOE 0 INT2 ENABLE 0 0 DIEOV 0 1 0 0 DI - INT2 INPUT T1 INPUT XCK INPUT/T0 INPUT AIO AIN1 INPUT AIN0 INPUT - - Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 83 17.3.3. Alternate Functions of Port C The Port C pins with alternate functions are shown in the table below. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Table 17-9. Port C Pins Alternate Functions Port Pin Alternate Function PC7 TOSC2 (Timer Oscillator Pin 2) PC6 TOSC1 (Timer Oscillator Pin 1) PC5 TDI (JTAG Test Data In) PC4 TDO (JTAG Test Data Out) PC3 TMS (JTAG Test Mode Select) PC2 TCK (JTAG Test Clock) PC1 SDA (Two-wire Serial Bus Data Input/Output Line) PC0 SCL (Two-wire Serial Bus Clock Line) The alternate pin configuration is as follows: * TOSC2 - Port C, Bit 7 TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. * TOSC1 - Port C, Bit 6 TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC6 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. * TDI - Port C, Bit 5 TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. * TDO - Port C, Bit 4 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TD0 pin is tri-stated unless TAP states that shifts out data are entered. * TMS - Port C, Bit 3 TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. * TCK - Port C, Bit 2 TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. * SDA - Port C, Bit 1 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 84 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Twowire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can still be controlled by the PORTC1 bit. * SCL - Port C, Bit 0 SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC0 is disconnected from the port and becomes the Serial Clock I/O pin for the Twowire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. When this pin is used by the Two-wire Serial Interface, the pull-up can still be controlled by the PORTC0 bit. The tables below relate the alternate functions of Port C to the overriding signals shown in Alternate Port Functions. Table 17-10. Overriding Signals for Alternate Functions in PC7:PC4 Signal Name PC7/TOSC2 PC6/TOSC1 PC5/TDI PC4/TDO PUOE AS2 AS2 JTAGEN JTAGEN PUOV 0 0 1 0 DDOE AS2 AS2 JTAGEN JTAGEN DDOV 0 0 0 SHIFT_IR + SHIFT_DR PVOE 0 0 0 JTAGEN PVOV 0 0 0 TDO DIEOE AS2 AS2 JTAGEN JTAGEN DIEOV 0 0 0 0 DI - - - - AIO T/C2 OSC OUTPUT T/C2 OSC INPUT TDI - Table 17-11. Overriding Signals for Alternate Functions in PC3:PC0(1) Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL PUOE JTAGEN JTAGEN TWEN TWEN PUOV 1 1 PORTC1 * PUD PORTC0 * PUD DDOE JTAGEN JTAGEN TWEN TWEN DDOV 0 0 SDA_OUT SCL_OUT PVOE 0 0 TWEN TWEN PVOV 0 0 0 0 DIEOE JTAGEN JTAGEN 0 0 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 85 Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL DIEOV 0 0 0 0 DI - - - - AIO TMS TCK SDA INPUT SCL INPUT Note: 1. When enabled, the Two-wire Serial Interface enables slew-rate controls on the output pins PC0 and PC1. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. 17.3.4. Alternate Functions of Port D The Port D pins with alternate functions are shown in the table below: Table 17-12. Port D Pins Alternate Functions Port Pin Alternate Function PD7 OC2 (Timer/Counter2 Output Compare Match Output) PD6 ICP1 (Timer/Counter1 Input Capture Pin) PD5 OC1A (Timer/Counter1 Output Compare A Match Output) PD4 OC1B (Timer/Counter1 Output Compare B Match Output) PD3 INT1 (External Interrupt 1 Input) PD2 INT0 (External Interrupt 0 Input) PD1 TXD (USART Output Pin) PD0 RXD (USART Input Pin) The alternate pin configuration is as follows: * OC2 - Port D, Bit 7 OC2, Timer/Counter2 Output Compare Match output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDD7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. * ICP1 - Port D, Bit 6 ICP1 - Input Capture Pin: The PD6 pin can act as an Input Capture pin for Timer/Counter1. * OC1A - Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/ Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. * OC1B - Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/ Counter1 Output Compare B. The pin has to be configured as an output (DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. * INT1 - Port D, Bit 3 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 86 INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt source. * INT0 - Port D, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source. *TXD - Port D, Bit 1 TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. * RXD - Port D, Bit 0 RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit. The tables below relate the alternate functions of Port D to the overriding signals shown in the figure in section Alternate Port Functions. Table 17-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PD7/OC2 PD6/ICP1 PD5/OC1A PD4/OC1B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC2 ENABLE 0 OC1A ENABLE OC1B ENABLE PVOV OC2 0 OC1A OC1B DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI - ICP1 INPUT - - AIO - - - - Table 17-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL PUOE 0 0 TXEN RXEN PUOV 0 0 0 PORTD0 * PUD DDOE 0 0 TXEN RXEN DDOV 0 0 1 0 PVOE 0 0 TXEN 0 PVOV 0 0 TXD 0 DIEOE INT1 ENABLE INT0 ENABLE 0 0 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 87 Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL DIEOV 1 1 0 0 DI INT1 INPUT INT0 INPUT - RXD AIO - - - - 17.4. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 88 17.4.1. SFIOR - Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SFIOR Offset: 0x30 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit 7 6 5 4 3 2 1 0 PUD Access Reset R/W 0 Bit 2 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See Configuring the Pin for more details about this feature. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 89 17.4.2. PORTA - Port A Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PORTA Offset: 0x1B Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x3B Bit Access Reset 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PORTAn: Port A Data Register [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 90 17.4.3. DDRA - Port A Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: DDRA Offset: 0x1A Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x3A Bit Access Reset 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - DDAn: Port A Data Direction Register [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 91 17.4.4. PINA - Port A Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PINA Offset: 0x19 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x39 Bit 7 6 5 4 3 2 1 0 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 - PINAn: Port A Input Pins Address [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 92 17.4.5. PORTB - The Port B Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PORTB Offset: 0x18 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x38 Bit Access Reset 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PORTBn: Port B Data [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 93 17.4.6. DDRB - The Port B Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: DDRB Offset: 0x17 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x37 Bit Access Reset 7 6 5 4 3 2 1 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - DDBn: Port B Data Direction [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 94 17.4.7. PINB - The Port B Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PINB Offset: 0x16 Reset: N/A Property: When addressing I/O Registers as data space the offset address is 0x36 Bit 7 6 5 4 3 2 1 0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Access R R R R R R R R Reset x x x x x x x x Bits 7:0 - PINBn: Port B Input Pins Address [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 95 17.4.8. PORTC - The Port C Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PORTC Offset: 0x15 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x35 Bit Access Reset 7 6 5 4 3 2 1 0 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PORTCn: Port C Data [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 96 17.4.9. DDRC - The Port C Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: DDRC Offset: 0x14 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x34 Bit Access Reset 7 6 5 4 3 2 1 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - DDCn: Port C Data Direction [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 97 17.4.10. PINC - The Port C Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-Pull Zero Output. The port pins assumes their initial value, even if the clock is not running. Note that the DDRC and PINC Registers are available in ATmega103 compatibility mode, and should not be used for 100% backward compatibility. Name: PINC Offset: 0x13 Reset: N/A Property: When addressing I/O Registers as data space the offset address is 0x33 Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Access R R R R R R R R Reset 0 x x x x x x x Bits 7:0 - PINCn: Port C Input Pins Address [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 98 17.4.11. PORTD - The Port D Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PORTD Offset: 0x12 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x32 Bit Access Reset 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - PORTDn: Port D Data [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 99 17.4.12. DDRD - The Port D Data Direction Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: DDRD Offset: 0x11 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x31 Bit Access Reset 7 6 5 4 3 2 1 0 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - DDDn: Port D Data Direction [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 100 17.4.13. PIND - The Port D Input Pins Address When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: PIND Offset: 0x10 Reset: N/A Property: When addressing I/O Registers as data space the offset address is 0x30 Bit 7 6 5 4 3 2 1 0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 Access R R R R R R R R Reset x x x x x x x x Bits 7:0 - PINDn: Port D Input Pins Address [n = 7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 101 18. Timer/Counter0 and Timer/Counter1 Prescalers 18.1. Overview Timer/Counte1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counte1 and Timer/Counter0. 18.2. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 18.3. Prescaler Reset The prescaler is free running (i.e., operates independently of the clock select logic of the Timer/Counter) and it is shared by Timer/Counte1 and Timer/Counter0. Since the prescaler is not affected by the Timer/ Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 18.4. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. The figure below shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 18-1. T1/T0 Pin Sampling Tn D Q D Q Tn_s ync (To Clock S e le ct Logic) D Q LE clk I/O S ynchroniza tion Edge De te ctor Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 102 The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 18-2. Prescaler for Timer/Counte1 and Timer/Counter0(1) clk I/O 10-BIT T/C PRESCALER CK/1024 CK/256 PSR10 CK/64 CK/8 Clear OFF Tn Synchronization CSn0 CSn1 CSn2 TIMER /COUNTERn CLOCK SOURCE clk Tn Note: 1. The synchronization logic on the input pins (T1/T0) is shown in figure T1/T0 Pin Sampling in this section. 18.5. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 103 18.5.1. SFIOR - Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SFIOR Offset: 0x30 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit 7 6 5 4 3 2 1 0 PSR10 Access Reset R/W 0 Bit 0 - PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 104 19. 16-bit Timer/Counter1 19.1. Features * * * * * * * * * * * 19.2. True 16-bit Design (i.e., allows 16-bit PWM) Two independent Output Compare Units Double Buffered Output Compare Registers One Input Capture Unit Input Capture Noise Canceler Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator External Event Counter Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. Most register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in the following figure. For the actual placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 105 Figure 19-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA TCCRnB Note: 1. Refer to Pin Configurations, table Port B Pins Alternate Functions in Alternate Functions of Port B, and table Port D Pins Alternate Functions in Alternate Functions of Port D for Timer/Counter1 pin placement and description. Related Links Pin Configurations on page 13 Alternate Functions of Port B on page 81 Alternate Functions of Port D on page 86 19.2.1. Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section Accessing 16-bit Registers. The Timer/Counter Control Registers (TCCRnA/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCRnA/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B). See Output Compare Units. The Compare Match event will also set the Compare Match Flag (OCFnA/B) which can be used to generate an Output Compare interrupt request. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 106 The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins (see Analog Comparator). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output. Related Links AC - Analog Comparator on page 253 19.2.2. Definitions The following definitions are used extensively throughout the document: Table 19-1. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. 19.2.3. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: * * * All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: * * * PWM10 is changed to WGM10. PWM11 is changed to WGM11. CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: * * FOC1A and FOC1B are added to TCCR1A. WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 19.3. Accessing 16-bit Registers The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. A 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 107 16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCRnA/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnA/B and ICRn Registers. Note that when using "C", the compiler handles the 16-bit access. Assembly Code Example(1) :. ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH :. C Code Example(1) unsigned int i; :. /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; :. Note: 1. See About Code Examples. The assembly code example returns the TCNTn value in the r17:r16 Register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the same principle. Asesmbly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 108 C Code Example(1) unsigned int TIM16_ReadTCNTn( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. See About Code Examples. The assembly code example returns the TCNTn value in the r17:r16 Register pair. The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 out TCNTnH,r17 out TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. See About Code Examples. The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNTn. Related Links About Code Examples on page 19 19.3.1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 109 19.4. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler, see Timer/ Counte1 and Timer/Counter0 Prescalers. Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 102 19.5. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. The figure below shows a block diagram of the counter and its surroundings. Figure 19-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic Edge Detector clkTn Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): count Increment or decrement TCNTn by 1. direction Select between increment and decrement. clear Clear TCNTn (set all bits to zero). clkTn Timer/Counter clock. TOP Signalize that TCNTn has reached maximum value. BOTTOM Signalize that TCNTn has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNTnH) containing the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the clock select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 110 the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OCnx. For more details about advanced counting sequences and waveform generation, see Modes of Operation. The Timer/Counter Overflow (TOVn) flag is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 19.6. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a timestamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the timestamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram below. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small "n" in register and bit names indicates the Timer/Counter number. Figure 19-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator TCNTnL (8-bit) TCNTn (16-bit Counter) ACIC* ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.) ICPn When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn = 1), the Input Capture Flag generates an Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 111 Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the Low byte (ICRnL) and then the High byte (ICRnH). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter's TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the High byte must be written to the ICRnH I/O location before the Low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to Accessing 16-bit Registers. 19.6.1. Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn). Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICPn) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the Tn pin (see figure Tn Pin Sampling in section External Clock Source). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. Related Links External Clock Source on page 102 19.6.2. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 19.6.3. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 112 Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal's duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 19.7. Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (See Modes of Operation.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator. The figure below shows a block diagram of the Output Compare unit. The small "n" in the register and bit names indicates the device number (n = n for Timer/Counter n), and the "x" indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 113 Figure 19-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, nonsymmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNTn and ICRn Register). Therefore OCRnx is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The High byte (OCRnxH) has to be written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte (OCRnxL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to Accessing 16-bit Registers. 19.7.1. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing Compare Match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare Match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 114 19.7.2. Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 19.7.3. Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next Compare Match. Secondly the COMnx1:0 bits control the OCnx pin output source. The figure below shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a System Reset occur, the OCnx Register is reset to "0". Figure 19-5. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx D DATA BUS 19.8. 0 OCnx Pin Q PORT D Q DDR clk I/O Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 115 The general I/O port function is overridden by the Output Compare (OCnx) from the waveform generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 19-2, Table 19-3 and Table 19-4 for details. The design of the Output Compare Pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See Register Description. The COMnx1:0 bits have no effect on the Input Capture unit. 19.8.1. Compare Output Mode and Waveform Generation The waveform generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the waveform generator that no action on the OCnx Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 19-2. For fast PWM mode refer to Table 19-3, and for phase correct and phase and frequency correct PWM refer to Table 19-4. A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are written. For nonPWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 19.9. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a Compare Match. See Compare Match Output Unit. For detailed timing information refer to Timer/Counter Timing Diagrams. 19.9.1. Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 116 19.9.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown below. The counter value (TCNTn) increases until a Compare Match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 19-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA[1:0] = 0x1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation: OCnA = clk_I/O 2 1 + OCRnA N represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the Timer Counter TOVn Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 19.9.3. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In noninverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the singleslope operation, the operating frequency of the fast Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 117 PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: FPWM = log TOP+1 log 2 In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in the figure below. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Figure 19-7. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCFnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCRnA Register, however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 118 is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to 3. Refer to table Table 19-3. The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: OCnxPWM = clk_I/O 1 + TOP N represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnA to toggle its logical level on each Compare Match (COMnA1:0 = 1). This applies only if OCRnA is used to define the TOP value (WGMn3:0 = 15). The waveform generated will have a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 19.9.4. Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: PCPWM = log TOP+1 log 2 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 119 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown in the figure below. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Figure 19-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0]] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in the timing diagram above illustrates, changing the TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to 3. Refer to Table 19-4. The actual OCnx value will only be visible Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 120 on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: OCnxPCPWM = clk_I/O 2 TOP N variable represents the prescale divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCRnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 19.9.5. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 19-8 and Figure 19-9). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: PFCPWM = log TOP+1 log 2 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on timing diagram below. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a Compare Match occurs. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 121 Figure 19-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNTn and the OCRnx. As the timing diagram above shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to 3. Refer to Table 19-4. The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: OCnxPFCPWM = clk_I/O 2 TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 122 If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA output will toggle with a 50% duty cycle. 19.10. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). The next figure shows a timing diagram for the setting of OCFnx. Figure 19-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx The next figure shows the same timing data, but with the prescaler enabled. Figure 19-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx The next figure shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 123 Figure 19-12. Timer/Counter Timing Diagram, no Prescaling. clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) New OCRnx Value Old OCRnx Value The next figure shows the same timing data, but with the prescaler enabled. Figure 19-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn(FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 19.11. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 124 19.11.1. TCCR1A - Timer/Counter1 Control Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TCCR1A Offset: 0x2F Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4F Bit Access Reset 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 R/W R/W R/W R/W W W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:6 - COM1An: Compare Output Mode for Channel A [n = 1:0] Bits 5:4 - COM1Bn: Compare Output Mode for Channel B [n = 1:0] The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1n1:0 bits is dependent of the WGM13:0 bits setting. The table below shows the COM1n1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 19-2. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). The next table shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 125 Table 19-3. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details. The table below shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 19-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when down-counting. 1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when down-counting. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. Refer to Phase Correct PWM Mode for details. Bit 3 - FOC1A: Force Output Compare for channel A Bit 2 - FOC1B: Force Output Compare for channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 126 Bits 1:0 - WGM1n: Waveform Generation Mode [n = 1:0] Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, refer to the table below. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation). Table 19-5. Waveform Generation Mode Bit Description Mode WGM13 WGM12 WGM11 WGM10 Timer/Counter Mode of Operation(1) (CTC1) (PWM11) (PWM10) TOP Update of TOV1 Flag OCR1x at Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 Reserved - - - 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 127 19.11.2. TCCR1B - Timer/Counter1 Control Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TCCR1B Offset: 0x2E Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4E Bit Access 7 6 4 3 2 1 0 ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 Reset 5 Bit 7 - ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. Bit 6 - ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. Bit 4 - WGM13: Waveform Generation Mode Refer to TCCR1A. Bit 3 - WGM12: Waveform Generation Mode Refer to TCCR1A. Bits 2:0 - CS1n: Clock Select [n = 0:2] The three Clock Select bits select the clock source to be used by the Timer/Counter. Refer to figures Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling and Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8). Table 19-6. Clock Select Bit Description CA12 CA11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 128 CA12 CA11 CS10 Description 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 129 19.11.3. TCNT1L - Timer/Counter1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TCNT1L Offset: 0x2C Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4C Bit 7 6 5 4 3 2 1 0 TCNT1L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TCNT1L[7:0]: Timer/Counter 1 Low byte The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers for details. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 130 19.11.4. TCNT1H - Timer/Counter1 High byte Name: TCNT1H Offset: 0x2D Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4D Bit 7 6 5 4 3 2 1 0 TCNT1H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TCNT1H[7:0]: Timer/Counter 1 High byte Refer to TCNT1L. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 131 19.11.5. OCR1AL - Output Compare Register 1 A Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: OCR1AL Offset: 0x2A Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4A Bit 7 6 5 4 3 2 1 0 OCR1AL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR1AL[7:0]: Output Compare 1 A Low byte The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Registers for details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 132 19.11.6. OCR1AH - Output Compare Register 1 A High byte Name: OCR1AH Offset: 0x2B Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x4B Bit 7 6 5 4 3 2 1 0 OCR1AH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR1AH[7:0]: Output Compare 1 A High byte Refer to OCR1AL. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 133 19.11.7. OCR1BL - Output Compare Register 1 B Low byte Name: OCR1BL Offset: 0x28 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x48 Bit 7 6 5 4 3 2 1 0 OCR1BL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR1BL[7:0]: Output Compare 1 B Low byte Refer to OCR1AL. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 134 19.11.8. OCR1BH - Output Compare Register 1 B High byte Name: OCR1BH Offset: 0x29 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x49 Bit 7 6 5 4 3 2 1 0 OCR1BH[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR1BH[7:0]: Output Compare 1 B High byte Refer to OCR1AL. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 135 19.11.9. ICR1L - Input Capture Register 1 Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ICR1L Offset: 0x26 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x46 Bit 7 6 5 4 3 2 1 0 ICR1L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ICR1L[7:0]: Input Capture 1 Low byte The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16.bit Registers for details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 136 19.11.10. ICR1H - Input Capture Register 1 High byte Name: ICR1H Offset: 0x27 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x47 Bit 7 6 5 4 3 2 1 0 ICR1H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - ICR1H[7:0]: Input Capture 1 High byte Refer to ICR1L. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 137 19.11.11. TIMSK - Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. Name: TIMSK Offset: 0x39 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x59 Bit Access Reset 7 6 5 4 3 2 TICIE1 OCIE1A OCIE1B TOIE1 R/W R/W R/W R/W 0 0 0 0 1 0 Bit 5 - TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see Interrupts) is executed when the ICF1 Flag, located in TIFR, is set. Bit 4 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see Interrupts) is executed when the OCF1A Flag, located in TIFR, is set. Bit 3 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see Interrupts) is executed when the OCF1B Flag, located in TIFR, is set. Bit 2 - TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see Interrupts) is executed when the TOV1 Flag, located in TIFR, is set. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 138 19.11.12. TIFR - Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. Name: TIFR Offset: 0x38 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x58 Bit Access Reset 7 6 5 4 3 2 ICF1 OCF1A OCF1B TOV1 R/W R/W R/W R/W 0 0 0 0 1 0 Bit 5 - ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. Bit 4 - OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. Bit 3 - OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. Bit 2 - TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to table Waveform Generation Mode Bit Description for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 139 20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 20.1. Features * Single Channel Counter * Clear Timer on Compare Match (Auto Reload) * Glitch-free, phase Correct Pulse Width Modulator (PWM) * Frequency Generator * 10-bit Clock Prescaler * Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) * Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in the figure below. For the actual placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description. Figure 20-1. 8-bit Timer/Counter Block Diagram TCCRn count TOVn (Int. Re q.) cle a r Control Logic dire ction clkTn TOS C1 BOTTOM TOP T/C Os cilla tor P re s ca le r TOS C2 Time r/Counte r TCNTn =0 = 0xFF clkI/O OCn (Int. Re q.) Wave form Ge ne ra tion = OCn OCRn DATA BUS 20.2. S ynchronize d S ta tus Fla gs clkI/O S ync hro nizatio n Unit clkAS Y S ta tus Fla gs AS S Rn a s ynchronous Mode S e le ct (AS n) Related Links Pin Configurations on page 13 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 140 20.2.1. Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). For details, see Output Compare Unit. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. 20.2.2. Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in the following table are also used extensively throughout the document. Table 20-1. Definitions 20.3. BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, refer to Asynchronous Operation of the Timer/Counter. For details on clock sources and prescaler, refer to Timer/Counter Prescaler. Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 102 20.4. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. The following figure shows a block diagram of the counter and its surrounding environment. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 141 Figure 20-2. Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS TOS C1 count TCNTn cle a r Control Logic clk Tn T/C Os cilla tor P re s ca le r dire ction BOTTOM TOS C2 TOP clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. TOP Signalizes that TCNT2 has reached maximum value. BOTTOM Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/ Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC2. For more details about advanced counting sequences and waveform generation, refer to Modes of Operation . The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 20.5. Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (refer to Modes of Operation). The following figure shows a block diagram of the Output Compare unit. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 142 Figure 20-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. 20.5.1. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). 20.5.2. Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 20.5.3. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 143 Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. The figure below shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 20-4. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Wave form Ge ne ra tor D Q 1 OCn D DATABUS 20.6. 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 144 The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See Register Description. 20.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to table Compare Output Mode, Non-PWM Mode. For fast PWM mode, refer to table Compare Output Mode, Fast PWM Mode, and for phase correct PWM refer to table Compare Output Mode, Phase Correct PWM Mode. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. 20.7. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (refer to Compare Match Output Unit). For detailed timing information refer to Timer/Counter Timing Diagrams. 20.7.1. Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 20.7.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 145 Figure 20-5. CTC Mode, Timing Diagram OCn Inte rrupt Fla g S e t TCNTn OCn (Toggle ) Pe riod (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: OCn = clk_I/O 2 1 + OCRn The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 20.7.3. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in the following figure. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 146 small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 20-6. Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3. The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: OCnPWM = clk_I/O 256 The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 20.7.4. Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 147 mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on the following figure. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 20-7. Phase Correct PWM Mode, Timing Diagram OCn Inte rrupt Fla g S e t OCRn Upda te TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (refer to table Compare Output Mode, Phase Correct PWM Mode). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: OCnPCPWM = clk_I/O 510 The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 148 continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in the timing diagram above OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: * OCR2A changes its value from MAX, like in the timing diagram above. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 20.8. Timer/Counter Timing Diagrams The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/ Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 20-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the same timing data, but with the prescaler enabled. Figure 20-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the setting of OCF2 in all modes except CTC mode. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 149 Figure 20-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The figure below shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 20-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 20.9. Asynchronous Operation of the Timer/Counter 20.9.1. Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. * Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. 2. 3. 4. 5. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. Select clock source by setting AS2 as appropriate. Write new values to TCNT2, OCR2, and TCCR2. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. Clear the Timer/Counter2 Interrupt Flags. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 150 6. Enable interrupts, if needed. * The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented. When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: * * * 1. 2. 3. Write a value to TCCR2, TCNT2, or OCR2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. Enter Power-save or Extended Standby mode. * When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: * * Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 151 1. 2. 3. Write any value to either of the registers OCR2 or TCCR2. Wait for the corresponding Update Busy Flag to be cleared. Read TCNT2. * During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. 20.10. Timer/Counter Prescaler Figure 20-12. Prescaler for Timer/Counter2 P S R2 clkT2S /1024 clkT2S /256 clkT2S /128 clkT2S /64 AS 2 10-BIT T/C P RES CALER Cle a r clkT2S /32 TOS C1 clkT2S clkT2S /8 clkI/O 0 CS 20 CS 21 CS 22 TIMER/COUNTER2 CLOCK S OURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. 20.11. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 152 20.11.1. TCCR2 - Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TCCR2 Offset: 0x25 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x45 Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Access W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 - FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. Bit 6 - WGM20: Waveform Generation Mode [n=0:1] These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/ Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See table below and Modes of Operation. Table 20-2. Waveform Generation Mode Bit Description Mode WGM21 WGM20 Timer/Counter Mode of Operation(1) (CTC2) (PWM2) TOP Update of OCR2 TOV2 Flag Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF MAX BOTTOM Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Bits 5:4 - COM2n: Compare Match Output Mode [n = 1:0] These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 153 the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. The following table shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 20-3. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match The next table shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 20-4. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode for more details. The table below shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 20-5. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See Phase Correct PWM Mode for more details. Bit 3 - WGM21: Waveform Generation Mode [n=0:1] Refer to WGM20. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 154 Bits 2:0 - CS2n: Clock Select [n = 2:0] The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 20-6. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/32 (From prescaler) 1 0 0 clkI/O/64 (From prescaler) 1 0 1 clkI/O/128 (From prescaler) 1 1 0 clkI/O/256 (From prescaler) 1 1 1 clkI/O/1024 (From prescaler) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 155 20.11.2. TCNT0 - Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0 Register. Name: TCNT0 Offset: 0x24 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x44 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TCNT0[7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 156 20.11.3. OCR0 - Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0 pin. Name: OCR0 Offset: 0x23 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x43 Bit 7 6 5 4 3 2 1 0 OCR0[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR0[7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 157 20.11.4. ASSR - Asynchronous Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ASSR Offset: 0x22 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x42 Bit Access Reset 7 6 5 4 3 2 1 0 AS2 TCN2UB OCR2UB TCR2UB R/W R R R 0 0 0 0 Bit 3 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. Bit 2 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. Bit 1 - OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 158 20.11.5. TIMSK - Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TIMSK Offset: 0x39 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x59 Bit Access Reset 7 6 OCIE2 TOIE2 R/W R/W 0 0 5 4 3 2 1 0 Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR). Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 159 20.11.6. TIFR - Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TIFR Offset: 0x38 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x58 Bit Access Reset 7 6 OCF2 TOV2 R/W R/W 0 0 5 4 3 2 1 0 Bit 7 - OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/ Counter2 Compare Match Interrupt is executed. Bit 6 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 160 20.11.7. SFIOR - Special Function IO Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SFIOR Offset: 0x30 Reset: 0 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit 7 6 5 4 3 2 1 0 PSR2 Access Reset R/W 0 Bit 1 - PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/ Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 161 21. 8-bit Timer/Counter0 with PWM 21.1. Features * * * * * * * Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in the figure below. For the actual placement of I/O pins, refer to Pin Configurations. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Register Description. Figure 21-1. 8-bit Timer/Counter Block Diagram TCCRn count TOVn (Int. Re q.) cle a r Control Logic dire ction BOTTOM DATA BUS 21.2. Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) clkTn Clock Select Edge Detector TOP Tn Time r/Counte r TCNTn =0 = 0xFF (From Prescaler) OCn (Int. Re q.) = Wave form Ge ne ra tion OCn OCRn Related Links Pin Configurations on page 13 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 162 21.2.1. Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). For details, refer to Output Compare Unit. The Compare Match event will also set the Compare Flag (OCF0) which can be used to generate an Output Compare interrupt request. 21.2.2. Definitions Many register and bit references in this document are written in general form. A lower case "n" replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT0 for accessing Timer/Counter0 counter value and so on). The definitions in the following table are also used extensively throughout the document. Table 21-1. Definitions 21.3. BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see Timer/Counte1 and Timer/Counter0 Prescalers. Related Links Timer/Counter0 and Timer/Counter1 Prescalers on page 102 21.4. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. The following figure shows a block diagram of the counter and its surrounding environment. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 163 Figure 21-2. Counter Unit Block Diagram TOVn (Int. Re q.) DATA BUS Clock Select Edge Detector count TCNTn cle a r Control Logic Tn dire ction (From Prescaler) BOTTOM TOP Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Selects between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkT0 Timer/Counter clock. TOP Signalizes that TCNT0 has reached maximum value. BOTTOM Signalizes that TCNT0 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/ Counter Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC0. For more details about advanced counting sequences and waveform generation, see Modes of Operation. The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. 21.5. Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and global interrupt flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see Modes of Operation). The following figure shows a block diagram of the Output Compare unit. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 164 Figure 21-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Compa ra tor ) OCFn (Int. Re q.) TOP BOTTOM Wave form Ge ne ra tor OCn FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0 directly. 21.5.1. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0) bit. Forcing Compare Match will not set the OCF0 Flag or reload/clear the timer, but the OC0 pin will be updated as if a real Compare Match had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled). 21.5.2. Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 21.5.3. Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bit in Normal mode. The OC0 Register keeps its value even when changing between waveform generation modes. Be aware that the COM01:0 bits are not double buffered together with the compare value. Changing the COM01:0 bits will take effect immediately. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 165 21.6. Compare Match Output Unit The Compare Output mode (COM01:0) bits have two functions. The waveform generator uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Compare Match. Also, the COM01:0 bits control the OC0 pin output source. The figure below shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0 Register is reset to "0". Figure 21-4. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Wave form Ge ne ra tor D Q 1 OCn DATABUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0) from the waveform generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare Pin logic allows initialization of the OC0 state before the output is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See Register Description. 21.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM01:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM01:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 21-3. For fast PWM mode, refer to Table 21-4, and for phase correct PWM refer to Table 21-5. A change of the COM01:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 166 21.7. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see Compare Match Output Unit). For detailed timing information refer to Timer/Counter Timing Diagrams. 21.7.1. Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 21.7.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in the figure below. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0, and then counter (TCNT0) is cleared. Figure 21-5. CTC Mode, Timing Diagram OCn Inte rrupt Fla g S e t TCNTn OCn (Toggle ) Pe riod (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 167 If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation: OCn = clk_I/O 2 1 + OCRn The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 21.7.3. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in the figure below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 168 Figure 21-6. Fast PWM Mode, Timing Diagram OCRn Inte rrupt Fla g S e t OCRn Upda te a nd TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM01:0 to 3 (see Table 21-4). The actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0 Register at the Compare Match between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: OCnPWM = clk_I/O 256 The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256 or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0 to toggle its logical level on each Compare Match (COM01:0 = 1). The waveform generated will have a maximum frequency of foc0 = fclk_I/O/2 when OCR0 is set to zero. This feature is similar to the OC0 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 21.7.4. Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 169 operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on the figure below. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 21-7. Phase Correct PWM Mode, Timing Diagram OCn Inte rrupt Fla g S e t OCRn Upda te TOVn Inte rrupt Fla g S e t TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Pe riod 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (refer to Table 21-5). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Compare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: OCnPCPWM = clk_I/O 510 The N variable represents the prescaler factor (1, 8, 32, 64, 128, 256 or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 170 At the very start of period 2 in the timing diagram OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without a Compare Match: * OCR0 changes its value from MAX, like in the timing diagram above. When the OCR0 value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR0, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 21.8. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set. The first figure below contains timing data for basic Timer/Counter operation. It shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 21-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the same timing data, but with the prescaler enabled. Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The next figure shows the setting of OCF0 in all modes except CTC mode. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 171 Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Va lue OCFn The next figure shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 21-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCFn 21.9. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 172 21.9.1. TCCR0 - Timer/Counter Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TCCR0 Offset: 0x25 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x45 Bit 7 6 5 4 3 2 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Access W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 - FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare Match is forced on the waveform generation unit. The OC0 output is changed according to its COM21:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. Bit 6 - WGM00: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/ Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See table below and Modes of Operation. Table 21-2. Waveform Generation Mode Bit Description Mode WGM01 WGM00 Timer/Counter Mode of Operation(1) (CTC0) (PWM0) TOP Update of OCR0 TOV0 Flag Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0 Immediate MAX 3 1 1 Fast PWM 0xFF MAX BOTTOM Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Bits 5:4 - COM0n: Compare Match Output Mode [n = 1:0] These bits control the Output Compare Pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 173 the Data Direction Register (DDR) bit corresponding to the OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. The following table shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 21-3. Compare Output Mode, Non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Toggle OC0 on Compare Match 1 0 Clear OC0 on Compare Match 1 1 Set OC0 on Compare Match The next table shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 21-4. Compare Output Mode, Fast PWM Mode(1) COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Reserved 1 0 Clear OC0 on Compare Match, set OC0 at BOTTOM, (non-inverting mode) 1 1 Set OC0 on Compare Match, clear OC0 at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See Fast PWM Mode for more details. The table below shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Table 21-5. Compare Output Mode, Phase Correct PWM Mode(1) COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Reserved 1 0 Clear OC0 on Compare Match when up-counting. Set OC0 on Compare Match when downcounting. 1 1 Set OC0 on Compare Match when up-counting. Clear OC0 on Compare Match when downcounting. Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See Phase Correct PWM Mode for more details. Bit 3 - WGM01: Waveform Generation Mode [n=0:1] Refer to WGM00 above. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 174 Bits 2:0 - CS0n: Clock Select [n = 2:0] The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 21-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on falling edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 175 21.9.2. TCNT0 - Timer/Counter Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0 Register. Name: TCNT0 Offset: 0x24 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x44 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TCNT0[7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 176 21.9.3. OCR0 - Output Compare Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0 pin. Name: OCR0 Offset: 0x23 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x43 Bit 7 6 5 4 3 2 1 0 OCR0[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR0[7:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 177 21.9.4. TIMSK - Timer/Counter Interrupt Mask Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TIMSK Offset: 0x37 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x57 Bit Access Reset 7 6 5 4 3 2 1 0 OCIE0 TOIE0 R/W R/W 0 0 Bit 1 - OCIE0: Timer/CounterTimer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs (i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR). Bit 0 - TOIE0: Timer/CounterTimer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 178 21.9.5. TIFR - Timer/Counter Interrupt Flag Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TIFR Offset: 0x36 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x56 Bit Access Reset 7 6 5 4 3 2 1 0 OCF0 TOV0 R/W R/W 0 0 Bit 1 - OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and OCF0 are set (one), the Timer/ Counter0 Compare Match Interrupt is executed. Bit 0 - TOV0: Timer/Counter0 Overflow Flag The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 179 22. SPI - Serial Peripheral Interface 22.1. Features Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer * Seven Programmable Bit Rates * * * * End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and peripheral devices or between several AVR devices. Figure 22-1. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X 22.2. * * * Note: 1. Refer to Pin Configurations, table Port B Pins Alternate Functions in Alternate Functions of Port B for SPI pin placement. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 180 The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 22-2. SPI Master-slave Interconnection SHIFT ENABLE Vcc The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to the table below. For more details on automatic port overrides, refer to Alternate Port Functions. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 181 Table 22-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. Refer to table Port B Pins Alternate Functions in Alternate Functions of Port B for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret C Code Example(1) void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData) { /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; } Note: 1. See About Code Examples. The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 182 Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in r16,SPDR ret C Code Example(1) void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void) { /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; } Note: 1. See About Code Examples. Related Links Pin Configurations on page 13 Alternate Functions of Port B on page 81 Alternate Port Functions on page 78 About Code Examples on page 19 22.3. SS Pin Functionality 22.3.1. Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. The SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 22.3.2. Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 183 If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. 2. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 22.4. Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in the figures in this section. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 22-3 and Table 22-4, as done below: Table 22-2. CPOL and CPHA Functionality SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Figure 22-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 184 Figure 22-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 22.5. MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 185 22.5.1. SPCR - SPI Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPCR Offset: 0x0D Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x2D Bit Access Reset 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set. Bit 6 - SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. Bit 5 - DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. Bit 4 - MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. Bit 3 - CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to the figures in Data Modes for an example. The CPOL functionality is summarized below: Table 22-3. CPOL Functionality CPOL Leading Edge Trailing Edge 0 Rising Falling 1 Falling Rising Bit 2 - CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to the figures in Data Modes for an example. The CPHA functionality is summarized below: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 186 Table 22-4. CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample Bits 1:0 - SPRn: SPI Clock Rate Select [n = 1:0] These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the table below. Table 22-5. Relationship between SCK and Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency 0 0 0 fosc/4 0 0 1 fosc/16 0 1 0 fosc/64 0 1 1 fosc/128 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 fosc/32 1 1 1 fosc/64 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 187 22.5.2. SPSR - SPI Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPSR Offset: 0x0E Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x2E Bit 7 6 SPIF WCOL 5 4 3 2 1 SPI2X 0 Access R R R/W Reset 0 0 0 Bit 7 - SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). Bit 6 - WCOL: Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. Bit 0 - SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (refer to Table 22-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower. The SPI interface on the ATmega32A is also used for program memory and EEPROM downloading or uploading. Refer to section Serial Downloading for serial programming and verification. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 188 22.5.3. SPDR - SPI Data Register is a read/write register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPDR Offset: 0x0F Reset: 0xXX Property: When addressing I/O Registers as data space the offset address is 0x2F Bit Access Reset 7 6 5 4 3 2 1 0 SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 - SPIDn: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. * * SPID7 is MSB SPID0 is LSB Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 189 23. USART - Universal Synchronous and Asynchronous serial Receiver and Transmitter 23.1. Features * * * * * * * * * * * * 23.2. Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highlyflexible serial communication device. A simplified block diagram of the USART Transmitter is shown in the figure below. CPU accessible I/O Registers and I/O pins are shown in bold. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 190 Figure 23-1. USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR PIN CONTROL TRANSMIT SHIFT REGISTER TxDn Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnA UCSRnB RxDn UCSRnC Note: 1. Refer to Pin Configurations, table Overriding Signals for Alternate Functions PD7:PD4 and table Overriding Signals for Alternate Functions in PD3:PD0 in Alternate Functions of Port D for USART pin placement. The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (transfer clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a parity checker, control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. Related Links Pin Configurations on page 13 Alternate Functions of Port D on page 86 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 191 23.2.1. AVR USART vs. AVR UART - Compatibility The USART is fully compatible with the AVR UART regarding: * * * * * Bit locations inside all USART Registers. Baud Rate Generation. Transmitter Operation. Transmit Buffer Functionality. Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: * * A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost. The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Block Diagram in previous section) if the Buffer Registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions. The following control bits have changed name, but have same functionality and register location: * * 23.3. CHR9 is changed to UCSZ2. OR is changed to DOR. Clock Generation The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode. Below is a block diagram of the clock generation logic. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 192 Figure 23-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector xcko DDR_XCKn 1 0 UMSELn 1 UCPOLn txclk 1 0 rxclk Signal description: 23.3.1. txclk Transmitter clock (internal signal). rxclk Receiver base clock (internal signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (internal signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation - The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to the block diagram above. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator output is used directly by the Receiver's clock and data recovery units. However, the recovery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. The table below contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 193 Table 23-1. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode Equation for Calculating Baud Rate(1) BAUD = BAUD = BAUD = Equation for Calculating UBRR Value OSC 16 + 1 = OSC 2 +1 = OSC 8 + 1 = OSC -1 16BAUD OSC -1 8BAUD OSC -1 2BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). BAUD Baud rate (in bits per second, bps). fOSC System oscillator clock frequency. UBRR Contents of the UBRRH and UBRRL Registers, (0-4095). Some examples of UBRR values for some system clock frequencies are found in Table 23-9. 23.3.2. Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. 23.3.3. External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 23-2. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: XCK < OSC 4 The value of fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 23.3.4. Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 194 Figure 23-3. Synchronous Mode XCK Timing UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As the figure above shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. 23.4. Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: * * * * 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. The figure below illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 23-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 195 The USART Character Size (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero 23.4.1. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: even = - 1 ... 3 2 1 0 1 odd = - 1 ... 3 2 1 0 1 Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 23.5. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC Flag can be used to check that the Transmitter has completed all transfers, and the RXC Flag can be used to check that there are no unread data in the receive buffer. Note that the TXC Flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. When the function writes to the UCSRC Register, the URSEL bit (MSB) must be set due to the sharing of I/O location by UBRRH and UCSRC. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN)|(1<<TXEN) out UCSRB,r16 ; Set frame format: 8data, 2stop bit ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0) out UCSRC,r16 ret C Code Example(1) #define FOSC 1843200 // Clock Speed #define BAUD 9600 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 196 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { ... USART_Init(MYUBRR) ... } void USART_Init( unsigned int ubrr) { /*Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set frame format: 8data, 2stop bit */ UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0); } Note: 1. See About Code Examples. More advanced initialization routines can be written to include frame format as parameters, disable interrupts, and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. Related Links About Code Examples on page 19 23.6. Data Transmission - The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter's serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. 23.6.1. Sending Frames with 5 to 8 Data Bits A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register, U2X bit or by XCK depending on mode of operation. The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDRE) Flag. When using frames with less than eight bits, the most significant bits written to the UDR are ignored. The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16. Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 197 C Code Example(1) void USART_Transmit( unsigned char data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE)) ) ; /* Put data into buffer, sends the data */ UDR = data; } Note: 1. See About Code Examples. The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before loading it with new data to be transmitted. If the Data Register Empty Interrupt is utilized, the interrupt routine writes the data into the buffer. Related Links About Code Examples on page 19 23.6.2. Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRB,TXB8 sbrc r17,0 sbi UCSRB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDR,r16 ret C Code Example(1) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE))) ) ; /* Copy 9th bit to TXB8 */ UCSRB &= ~(1<<TXB8); if ( data & 0x0100 ) UCSRB |= (1<<TXB8); /* Put data into buffer, sends the data */ UDR = data; } Note: 1. These transmit functions are written to be general functions. They can be optimized if the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB Register is used after initialization. The ninth bit can be used for indicating an address frame when using multi processor communication mode or for other protocol handling as for example synchronization. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 198 23.6.3. Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag is useful in half-duplex communication interfaces (like the RS485 standard), where a transmitting application must enter Receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC Flag, this is done automatically when the interrupt is executed. 23.6.4. Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM1 = 1), the Transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 23.6.5. Disabling the Transmitter The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD pin. 23.7. Data Reception - The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver's serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock. 23.7.1. Receiving Frames with 5 to 8 Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received (i.e., a complete serial frame is present in the Receive Shift Register), the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 199 The following code example shows a simple USART receive function based on polling of the Receive Complete (RXC) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDR will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) ) ; /* Get and return received data from buffer */ return UDR; } Note: 1. See About Code Examples. The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. Related Links About Code Examples on page 19 23.7.2. Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis r16, RXC rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRA in r17, UCSRB in r16, UDR ; If error, return -1 andi r18,(1<<FE)|(1<<DOR)|(1<<PE) breq USART_ReceiveNoError ldi r17, HIGH(-1) ldi r16, LOW(-1) USART_ReceiveNoError: ; Filter the 9th bit, then return lsr r17 andi r17, 0x01 ret Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 200 C Code Example(1) unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC)) ) ; /* Get status and 9th bit, then data */ /* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR; /* If error, return -1 */ if ( status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See About Code Examples. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Related Links About Code Examples on page 19 23.7.3. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 23.7.4. Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 201 The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see Parity Bit Calculation and Parity Checker. 23.7.5. Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) Flag can then be read by software to check if the frame had a parity error. The UPE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 23.7.6. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 23.7.7. Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis r16, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; } Note: 1. See About Code Examples. Related Links About Code Examples on page 19 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 202 23.8. Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 23.8.1. Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. The figure below illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 23-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. 23.8.2. Asynchronous Data Recovery When the Receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode. The following figure shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. Figure 23-6. Sampling of Data and Parity Bit RxD BIT n Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (U2X = 1) 1 2 3 4 5 6 7 8 1 The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 203 having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. The following figure shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 23-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in the figure above. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver. 23.8.3. Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (refer to next table) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. slow = +1 - 1 + + fast = +2 + 1 + D Sum of character size and parity size (D = 5- to 10-bit). S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode. SF First sample number used for majority voting. SF = 8 for Normal Speed and SF = 4 for Double Speed mode. SM Middle sample number used for majority voting. SM = 9 for Normal Speed and SM = 5 for Double Speed mode. Rslow is the ratio of the slowest incoming data rate that can be accepted in relation to the Receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be accepted in relation to the Receiver baud rate. The following tables list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 204 Table 23-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D Rslow [%] Rfast [%] Max. Total Error [%] Recommended Max Receiver Error # (Data+Parity Bit) [%] 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 Table 23-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) D # (Data+Parity Bit) Rslow [%] Rfast [%] Max Total Error [%] Recommended Max Receiver Error [%] 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104.35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 The recommendations of the maximum Receiver baud rate error was made under the assumption that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the Receivers Baud Rate error. The Receiver's system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. 23.9. Multi-Processor Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCM setting, but has to be used differently when it is a part of a system utilizing the Multi-processor Communication mode. If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the frame type bit (the Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 205 first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data frames as normal, while the other Slave MCUs will ignore the received frames until another address frame is received. 23.9.1. Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame (TXB = 0) is being transmitted. The Slave MCUs must in this case be set to use a 9-bit character frame format. The following procedure should be used to exchange data in Multi-Processor Communication Mode: 1. 2. 3. 4. 5. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set). The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps the MPCM setting. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCM bit set, will ignore the data frames. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCM bit and waits for a new address frame from Master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the Receiver must change between using n and n+1 character frame formats. This makes full-duplex operation difficult since the Transmitter and Receiver uses the same character size setting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBS = 1) since the first stop bit is used for indicating the frame type. Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. 23.10. Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. 23.10.1. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC setting will be updated. The following code examples show how to access the two registers. Assembly Code Example(1) :. ; Set UBRRH to 2 ldi r16,0x02 out UBRRH,r16 :. ; Set the USBS and the UCSZ1 bit to one, and ; the remaining bits to zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 206 ldi r16,(1<<URSEL) | (1<<USBS) | (1<<UCSZ1) out UCSRC,r16 :. C Code Example(1) :. /* Set UBRRH to 2 */ UBRRH = 0x02; :. /* Set the USBS and the UCSZ1 bit to one, and */ /* the remaining bits to zero. */ UCSRC = (1<<URSEL) | (1<<USBS) | (1<<UCSZ1); :. Note: 1. See About Code Examples. As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O location. Related Links About Code Examples on page 19 23.10.2. Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents. Note that the timed sequence for reading the UCSRC is an atomic operation. Interrupts must therefore be controlled (e.g., by disabling interrupts globally) during the read operation. The following code example shows how to read the UCSRC Register contents. Assembly Code Example(1) USART_ReadUCSRC: ; Read UCSRC in r16,UBRRH in r16,UCSRC ret C Code Example(1) unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; } Note: 1. See About Code Examples. The assembly code example returns the UCSRC value in r16. Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordinary register, as long as the previous instruction did not access the register location. Related Links Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 207 About Code Examples on page 19 23.11. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 208 23.11.1. UDR - USART I/O Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: UDR Offset: 0x0C Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x2C Bit 7 6 5 4 3 2 1 0 TXB / RXB[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TXB / RXB[7:0]: USART Transmit / Receive Data Buffer The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 209 23.11.2. UCSRA - USART Control and Status Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: UCSRA Offset: 0x0B Reset: 0x20 Property: When addressing I/O Registers as data space the offset address is 0x2B Bit 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR PE U2X MPCM Access R R/W R R R R R/W R/W Reset 0 0 1 0 0 0 0 0 Bit 7 - RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e. does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC bit will become zero. The RXC Flag can be used to generate a Receive Complete interrupt (see description of the RXCIE bit). Bit 6 - TXC: USART Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDR). The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see description of the TXCIE bit). Bit 5 - UDRE: USART Data Register Empty The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a reset to indicate that the Transmitter is ready. Bit 4 - FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received (i.e., when the first stop bit of the next character in the receive buffer is zero). This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. Bit 3 - DOR: Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. Bit 2 - PE: Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 210 Bit 1 - U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. Bit 0 - MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCM setting. For more detailed information see Multiprocessor Communication Mode. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 211 23.11.3. UCSRB - USART Control and Status Register B When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: UCSRB Offset: 0x0A Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x2A Bit Access Reset 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 R/W R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 0 0 0 Bit 7 - RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXC bit in UCSRA is set. Bit 6 - TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set. Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set. Bit 4 - RXEN: Receiver Enable Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FE, DOR and PE Flags. Bit 3 - TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted). When disabled, the Transmitter will no longer override the TxD port. Bit 2 - UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Bit 1 - RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 212 Bit 0 - TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 213 23.11.4. UCSRC - USART Control and Status Register C When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The UCSRC Register shares the same I/O location as the UBRRH Register. See the Accessing UBRRH/ UCSRC Registers section which describes how to access this register. Name: UCSRC Offset: 0x20 Reset: 0x06 Property: When addressing I/O Registers as data space the offset address is 0x40 Bit Access Reset 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL R/W R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 1 0 Bit 7 - URSEL: Register Select This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when reading UCSRC. The URSEL must be one when writing the UCSRC. Bit 6 - UMSEL: Mode Select This bit selects between Asynchronous and Synchronous mode of operation. Table 23-4. UMSEL Bit Settings UMSEL Bit Settings Mode 0 Asynchronous Operation 1 Synchronous Operation Bits 5:4 - UPMn: Parity Mode [n = 1:0] These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set. Table 23-5. UPM Bits Settings UPM1 UPM0 ParityMode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity Bit 3 - USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 214 Table 23-6. USBS Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit Bits 2:1 - UCSZn: Character Size [n = 1:0] The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 23-7. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit Bit 0 - UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 23-8. UCPOL Bit Settings UCPOL Transmitted Data Changed (Output of TxD Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 215 23.11.5. UBRRL - USART Baud Rate Register Low When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: UBRRL Offset: 0x09 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x29 Bit 7 6 5 4 3 2 1 0 UBBR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - UBBR[7:0]: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 216 23.11.6. UBBRH - USART Baud Rate Register High When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The UBRRH Register shares the same I/O location as the UCSRC Register. See the Accessing UBRRH/ UCSRC Registers section which describes how to access this register. Name: UBBRH Offset: 0x20 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x40 Bit 7 6 5 4 3 2 URSEL Access Reset 1 0 UBRR[3:0] R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 7 - URSEL: Register Select This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when reading UBRRH. The URSEL must be zero when writing the UBRRH. Bits 3:0 - UBRR[3:0]: USART Baud Rate Register [n = 11:8] Refer to UBRRL. 23.12. Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings as listed in the table below. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see Asynchronous Operational Range). The error values are calculated using the following equation: % = BaudRateClosest Match - 1 x 100 % BaudRate Table 23-9. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate [bps] fosc = 1.0000MHz U2X = 0 fosc = 1.8432MHz U2X = 1 U2X= 0 fosc = 2.0000MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 217 Baud Rate [bps] fosc = 1.0000MHz U2X = 0 fosc = 1.8432MHz U2X = 1 U2X= 0 fosc = 2.0000MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k - - 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k - - 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k - - - - - - 0 0.0% - - - - 250k - - - - - - - - - - 0 0.0% Max(1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps Note: 1. UBRR = 0, Error = 0.0% Table 23-10. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate [bps] fosc = 3.6864MHz U2X = 0 fosc = 4.0000MHz U2X = 1 U2X = 0 fosc = 7.3728MHz U2X = 1 U2X = 0 U2X = 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5M - - 0 -7.8% - - 0 0.0% 0 -7.8% 1 -7.8% 1M - - - - - - - - - -7.8% Max.(1) 230.4kbps 460.8kbps - 250kbps 0.5Mbps 460.8kbps 0 921.6kbps Note: 1. UBRR = 0, Error = 0.0% Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 218 Table 23-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate [bps] fosc = 8.0000MHz U2X = 0 U2X = 1 UBRR Error UBRR Error 2400 207 0.2% 416 4800 103 0.2% 9600 51 0.2% 14.4k 34 19.2k fosc = 11.0592MHz fosc = 14.7456MHz U2X = 0 U2X = 0 U2X = 1 Error UBRR Error UBRR Error UBRR Error -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5M 0 0.0% 1 0.0% - - 2 -7.8% 1 -7.8% 3 -7.8% 1M - - 0 0.0% - - - - -7.8% 1 -7.8% Max.(1) 0.5Mbps 1Mbps UBRR U2X = 1 691.2kbps 0 1.3824Mbps 921.6kbps 1.8432Mbps Note: 1. UBRR = 0, Error = 0.0% Table 23-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) Baud Rate [bps] fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 UBRR Error 2400 416 4800 UBRR U2X = 1 U2X = 1 Error UBRR Error UBRR Error UBRR Error UBRR Error -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 0.0% 29 0.0% 15 1.7% -1.4% 119 14 32 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 219 Baud Rate [bps] fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz U2X = 0 U2X = 0 U2X = 0 U2X = 1 UBRR Error 115.2k 8 230.4k UBRR U2X = 1 U2X = 1 Error UBRR Error UBRR Error UBRR Error -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5M 1 0.0% 3 0.0% - - 4 -7.8% - - 4 0.0% 1M 0 0.0% 1 0.0% - - - - - - - Max.(1) 1Mbps 2Mbps 1.152Mbps 2.304Mbps - 1.25Mbps UBRR Error 2.5Mbps Note: 1. UBRR = 0, Error = 0.0% Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 220 24. TWI - Two-wire Serial Interface 24.1. Features * * * * * * * * * * Overview The TWI module is comprised of several submodules, as shown in the following figure. All registers drawn in a thick line are accessible through the AVR data bus. Figure 24-1. Overview of the TWI Module SCL Sle w-rate Control SD A Spik e Filter Sle w-rate Control Spik e Filter Bit Rate Gener ator Bus Interf ace Unit START / ST OP Control Spik e Suppression Arbitration detection Address/Data Shift Register (TWDR) Prescaler Address Match Unit Address Register (TWAR) Address Compar ator Bit Rate Register (TWBR) Ack Control Unit Status Register (TWSR) Control Register (TWCR) State Machine and Status control TWI Unit 24.2. Simple, yet Powerful and Flexible Communication Interface, only two Bus Lines Needed Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7-bit Address Space Allows up to 128 Different Slave Addresses Multi-master Arbitration Support Up to 400kHz Data Transfer Speed Slew-rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus Lines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake-up When AVR is in Sleep Mode Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 221 24.2.1. SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slewrate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. 24.2.2. Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: SCL frequency = * * CPU Clock frequency 16 + 2(TWBR) PrescalerValue TWBR = Value of the TWI Bit Rate Register PrescalerValue = Value of the prescaler, see description of the TWI Prescaler bit in the TWSR Status Register description (TWSR.TWPS) Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See the Two-Wire Serial Interface Characteristics for a suitable value of the pull-up resistor. Related Links Two-wire Serial Interface Characteristics on page 363 24.2.3. Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a Master. If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. 24.2.4. Address Match Unit The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI Power-down address match Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 222 and wakes up the CPU, the TWI aborts operation and return to it's idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. 24.2.5. Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT Flag is set in the following situations: * * * * * * * * 24.3. After the TWI has transmitted a START/REPEATED START condition. After the TWI has transmitted SLA+R/W. After the TWI has transmitted an address byte. After the TWI has lost arbitration. After the TWI has been addressed by own slave address or general call. After the TWI has received a data byte. After a STOP or REPEATED START has been received while still addressed as a Slave. When a bus error has occurred due to an illegal START or STOP condition. Two-Wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pullup resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 24-2. TWI Bus Interconnection VCC Device 1 Device 2 Device 3 ........ Device n R1 R2 SD A SCL 24.3.1. TWI Terminology The following definitions are frequently encountered in this section. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 223 Table 24-1. TWI Terminology 24.3.2. Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. Electrical Interconnection As depicted in Figure 24-2, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices tristate their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in Two-wire Serial Interface Characteristics. Two different sets of specifications are presented there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz. Related Links Two-wire Serial Interface Characteristics on page 363 24.4. Data Transfer and Frame Format 24.4.1. Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 24-3. Data Validity SDA SCL Data Stab le Data Stab le Data Change 24.4.2. START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 224 and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 24-4. START, REPEATED START and STOP conditions SDA SCL START 24.4.3. STOP START REPEATED START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/ WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Master's request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 24-5. Address Packet Format Addr MSB Addr LSB R/W ACK 7 8 9 SD A SCL 1 2 START Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 225 24.4.4. Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 24-6. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SD A SDA from Transmitter SDA from Receiv er SCL from Master 1 2 7 SLA+R/W 24.4.5. ST OP, REPEA TED START or Ne xt Data Byte Data Byte Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. The following figure depicts a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software. Figure 24-7. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB 7 8 9 1 Data LSB ACK 8 9 SD A SCL 1 START 2 SLA+R/W 2 7 Data Byte Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 ST OP 226 24.5. Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: * * An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. Figure 24-8. SCL Synchronization Between Multiple Masters TAhigh TAlow SCL from Master A TBlow TBhigh SCL from Master B SCL Bus Line Masters Star t Counting Lo w P er iod Masters Star t Counting High P er iod Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 227 Figure 24-9. Arbitration Between Two Masters START SD A from Master A Master A Loses Arbitration, SD AA SDA SD A from Master B SD A Line Synchroniz ed SCL Line Note that arbitration is not allowed between: * * * A REPEATED START condition and a data bit. A STOP condition and a data bit. A REPEATED START and a STOP condition. It is the user software's responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 24.6. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in order to detect actions on the TWI bus. When the TWINT Flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. The following figure is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 228 Application Action Figure 24-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCRto initiate transmission of START TWI Hardware Action TWI bus 1. 2. 3. 4. 5. 6. 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one, and TWSTA is written to zero. START 2.TWINT set. Status code indicates START condition sent SLA+W 5. Check TWSRto see if SLA+W was sent and ACK received. Application loads data into TWDR, and loads appropriate control signals into TWCR, making sure that TWINT is written to one A 4.TWINT set. Status code indicates SLA+W sent, ACK received Data 7. Check TWSRto see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one A 6.TWINT set. Status code indicates data sent, ACK received STOP Indicates TWINT set The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 229 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent. Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: * * * When the TWI has finished an operation and expects application response, the TWINT Flag is set. The SCL line is pulled low until TWINT is cleared. When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. The following table lists assembly and C implementation examples. Note that the code below assumes that several definitions have been made, e.g. by using include-files. Table 24-2. Assembly and C Code Example Assembly Code Example C Example Comments 1 ldi r16, (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) out TWCR, r16 TWCR = (1<<TWINT)| (1<<TWSTA)|(1<<TWEN) Send START condition 2 wait1: in r16,TWCR sbrs r16,TWINT rjmp wait1 while (!(TWCR & (1<<TWINT))); in r16,TWSR andi r16, 0xF8 cpi r16, START brne ERROR if ((TWSR & 0xF8) != START) ERROR(); ldi r16, SLA_W out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 TWDR = SLA_W; TWCR = (1<<TWINT) | (1<<TWEN); wait2: in r16,TWCR sbrs r16,TWINT rjmp wait2 while (!(TWCR & (1<<TWINT))); in r16,TWSR andi r16, 0xF8 cpi r16, MT_SLA_ACK brne ERROR if ((TWSR & 0xF8) != MT_SLA_ACK) ERROR(); Mask prescaler bits. If status different ldi r16, DATA out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 TWDR = DATA; TWCR = (1<<TWINT) | (1<<TWEN); TWINT bit in TWCR to start transmission Wait for TWINT Flag set. This indicates that the START condition has been transmitted. Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR. 3 4 Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address. Wait for TWINT Flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has been received. Check value of TWI Status Register. from MT_SLA_ACK go to ERROR. 5 Load DATA into TWDR Register. Clear of data. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 230 Assembly Code Example 24.6.1. Comments Wait for TWINT Flag set. This indicates wait3: in r16,TWCR sbrs r16,TWINT rjmp wait3 while (!(TWCR & (1<<TWINT))); in r16,TWSR andi r16, 0xF8 cpi r16, MT_DATA_ACK brne ERROR if ((TWSR & 0xF8) != MT_DATA_ACK) ERROR(); Mask prescaler bits. If status different ldi r16, (1<<TWINT)|(1<<TWEN)| (1<<TWSTO) out TWCR, r16 TWCR = (1<<TWINT)| (1<<TWEN)|(1<<TWSTO); Transmit STOP condition. 6 7 C Example that the DATA has been transmitted, and ACK/NACK has been received. Check value of TWI Status Register. from MT_DATA_ACK go to ERROR. Transmission Modes The TWI can operate in one of four major modes: * Master Transmitter (MT) * Master Receiver (MR) * Slave Transmitter (ST) * Slave Receiver (SR) Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures use the following abbreviations: S START condition Rs REPEATED START condition R Read bit (high level at SDA) W Write bit (low level at SDA) A Acknowledge bit (low level at SDA) A Not acknowledge bit (high level at SDA) Data 8-bit data byte P STOP condition SLA Slave Address Circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software. When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial transfer are given below in the Status Code table for each mode. Note that the prescaler bits are masked to zero in these tables. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 231 24.6.2. Master Transmitter Mode In the Master Transmitter (MT) mode, a number of data bytes are transmitted to a Slave Receiver, see figure below. In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether MT or Master Receiver (MR) mode is to be entered: If SLA +W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 24-11. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ Device n R1 R2 SD A SCL A START condition is sent by writing a value to the TWI Control Register (TWCR) of the type TWCR=1x10x10x: * * * The TWI Enable bit (TWCR.TWEN) must be written to '1' to enable the 2-wire Serial Interface The TWI Start Condition bit (TWCR.TWSTA) must be written to '1' to transmit a START condition The TWI Interrupt Flag (TWCR.TWINT) must be written to '1' to clear the flag. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Status Code table below). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to the TWI Data Register (TWDR). Thereafter, the TWCR.TWINT Flag should be cleared (by writing a '1' to it) to continue the transfer. This is accomplished by writing a value to TWRC of the type TWCR=1x00x10x. When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in the Status Code table below. When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing '1' to it) to continue the transfer. This is accomplished by writing again a value to TWCR of the type TWCR=1x00x10x. This scheme is repeated until the last byte has been sent and the transfer is ended, either by generating a STOP condition or a by a repeated START condition. A repeated START condition is accomplished by writing a regular START value TWCR=1x10x10x. A STOP condition is generated by writing a value of the type TWCR=1x01x10x. After a repeated START condition (status code 0x10), the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 232 to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 24-3. Status Codes for Master Transmitter Mode Status Code (TWSR) Prescaler Bits are 0 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR Next Action Taken by TWI Hardware To TWCR STA STO TWIN T TWE A 0x08 A START condition has been transmitted Load SLA+W 0 0 1 X SLA+W will be transmitted; ACK or NOT ACK will be received 0x10 A repeated START condition has been transmitted Load SLA+W or Load SLA+R 0 0 0 0 1 1 X X SLA+W will be transmitted; ACK or NOT ACK will be received SLA+R will be transmitted; Logic will switch to Master Receiver mode 0x18 SLA+W has been transmitted; ACK has been received Load data byte or No TWDR action or 0 1 0 0 1 1 X X No TWDR action or 0 1 1 X No TWDR action 1 1 1 X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x20 SLA+W has been transmitted; NOT ACK has been received Load data byte or No TWDR action or 0 1 0 0 1 1 X X No TWDR action or 0 1 1 X No TWDR action 1 1 1 X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x28 Data byte has been transmitted; ACK has been received Load data byte or No TWDR action or 0 1 0 0 1 1 X X No TWDR action or 0 1 1 X No TWDR action 1 1 1 X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x30 Data byte has been transmitted; NOT ACK has been received Load data byte or No TWDR action or 0 1 0 0 1 1 X X No TWDR action or 0 1 1 X No TWDR action 1 1 1 X Data byte will be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x38 Arbitration lost in SLA+W or data bytes No TWDR action or No TWDR action 0 1 0 0 1 1 X X 2-wire Serial Bus will be released and not addressed Slave mode entered A START condition will be transmitted when the bus becomes free Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 233 Figure 24-12. Formats and States in the Master Transmitter Mode MT Successfull transmission to a sla ve receiv er S SLA $08 W A DATA $18 A P $28 Next transfer star ted with a repeated star t condition RS SLA W $10 Not acknowledge received after the slave address A R P $20 MR Not acknowledge receiv ed after a data byte A P $30 Arbitration lost in sla ve address or data b yte A or A Other master contin ues A or A $38 Arbitration lost and addressed as sla ve A $68 From master to sla ve From sla ve to master 24.6.3. Other master contin ues $38 Other master contin ues $78 DATA To corresponding states in sla ve mode $B0 A n Any number of data b ytes and their associated ac kno wledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Ser ial Bus . The prescaler bits are z ero or mask ed to z ero Master Receiver Mode In the Master Receiver (MR) mode, a number of data bytes are received from a Slave Transmitter (see next figure). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter (MT) or MR mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 234 Figure 24-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL A START condition is sent by writing to the TWI Control register (TWCR) a value of the type TWCR=1x10x10x: * TWCR.TWEN must be written to '1' to enable the 2-wire Serial Interface * TWCR.TWSTA must be written to '1' to transmit a START condition * TWCR.TWINT must be cleared by writing a '1' to it. The TWI will then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (see Status Code table below). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter, the TWINT flag should be cleared (by writing '1' to it) to continue the transfer. This is accomplished by writing the a value to TWCR of the type TWCE=1x00x10x. When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in the table below. Received data can be read from the TWDR Register when the TWINT Flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A repeated START condition is sent by writing to the TWI Control register (TWCR) a value of the type TWCR=1x10x10x again. A STOP condition is generated by writing TWCR=1xx01x10x: After a repeated START condition (status code 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 235 Table 24-4. Status codes for Master Receiver Mode Status Code (TWSR) Prescaler Bits are 0 Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWD Next Action Taken by TWI Hardware To TWCR STA STO TWIN T TWE A 0x08 A START condition has been transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted ACK or NOT ACK will be received 0x10 A repeated START condition has been transmitted Load SLA+R or Load SLA+W 0 0 0 0 1 1 X X SLA+R will be transmitted ACK or NOT ACK will be received SLA+W will be transmitted Logic will switch to Master Transmitter mode 0x38 Arbitration lost in SLA+R or NOT ACK bit No TWDR action or No TWDR action 0 1 0 0 1 1 X X 2-wire Serial Bus will be released and not addressed Slave mode will be entered A START condition will be transmitted when the bus becomes free 0x40 SLA+R has been transmitted; ACK has been received No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x48 SLA+R has been transmitted; NOT ACK has been received No TWDR action or No TWDR action or 1 0 0 1 1 1 X X No TWDR action 1 1 1 X Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x50 Data byte has been received; ACK has been returned Read data byte or Read data byte 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x58 Data byte has been received; NOT ACK has been returned Read data byte or Read data byte or 1 0 0 1 1 1 X X Read data byte 1 1 1 X Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 236 Figure 24-14. Formats and States in the Master Receiver Mode MR Successfull reception from a sla v e receiv er S SLA $08 R A DATA $40 A DATA $50 A P $58 Next transf er star ted with a repeated star t condition RS SLA R $10 Not ac kno wledge received after the slave address A W P $48 Arbitration lost in sla ve address or data b yte MT A or A Other master contin ues A $38 Arbitration lost and addressed as sla ve A $68 From master to sla ve From slave to master 24.6.4. Other master contin ues $38 Other master contin ues $78 DATA To corresponding states in sla ve mode $B0 A n Any number of data b ytes and their associated ac kno wledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Ser ial Bus . The prescaler bits are z ero or mask ed to z ero Slave Receiver Mode In the Slave Receiver (SR) mode, a number of data bytes are received from a Master Transmitter (see figure below). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 237 Figure 24-15. Data transfer in Slave Receiver mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.TWGCI=1, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR must hold a value of the type TWCR=0100010x - TWCR.TWEN must be written to '1' to enable the TWI. TWCR.TWEA bit must be written to '1' to enable the acknowledgement of the device's own slave address or the general call address. TWCR.TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address, if enabled) followed by the data direction bit. If the direction bit is '0' (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action, as detailed in the table below. The SR mode may also be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78). If the TWCR.TWEA bit is reset during a transfer, the TWI will return a "Not Acknowledge" ('1') to SDA after the next received data byte. This can be used to indicate that the Slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the 2wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by writing '1' to it). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note: The 2-wire Serial Interface Data Register (TWDR) does not reflect the last byte present on the bus when waking up from these Sleep modes. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 238 Table 24-5. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR Prescaler Bits are 0 Next Action Taken by TWI Hardware To TWCR STA STO TWI NT TWE A 0x60 Own SLA+W has been received; ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x68 Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x70 General call address has been received; ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x78 Arbitration lost in SLA+R/W as Master; General call address has been received; ACK has been returned No TWDR action or No TWDR action X X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLA+W; data has been received; ACK has been returned Read data byte or X Read data byte X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned 0x88 Previously addressed with own SLA+W; data has been received; NOT ACK has been returned Read data byte or 0 Read data byte or 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA Read data byte or 1 0 1 0 Switched to the not addressed Slave mode; Read data byte 0 1 1 own SLA will be recognized; 1 GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free 0x90 Previously addressed with general call; data has been received; ACK has been returned Read data byte or X Read data byte X 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 239 Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR 0x98 To TWCR STA Prescaler Bits are 0 Next Action Taken by TWI Hardware STO TWI NT TWE A Previously addressed with general call; data has been Read data byte or 0 Read data byte or 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA received; NOT ACK has been Read data byte or 1 0 1 0 Switched to the not addressed Slave mode; returned Read data byte 0 1 1 own SLA will be recognized; 1 GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeated No action START condition has been received while still addressed as Slave 0 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 1 0 1 0 Switched to the not addressed Slave mode; 1 0 1 1 own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 240 Figure 24-16. Formats and States in the Slave Receiver Mode Reception of the o wn sla ve address and one or more data b ytes. All are acknowledged S SLA W A DATA $60 A DATA $80 Last data b yte receiv ed is not ac kno wledged A P or S $80 $A0 A P or S $88 Arbitration lost as master and addressed as sla ve A $68 Reception of the gener al call address and one or more data bytes General Call A DATA $70 A DATA $90 Last data b yte receiv ed is not ac knowledged A P or S $90 $A0 A P or S $98 Arbitration lost as master and addressed as sla ve b y gener al call A $78 From master to sla ve From sla ve to master 24.6.5. DATA A n Any number of data b ytes and their associated ac kno wledge bits This n umber (contained in TWSR) corresponds to a defined state of the 2-Wire Ser ial Bus . The prescaler bits are z ero or mask ed to z ero Slave Transmitter Mode In the Slave Transmitter (ST) mode, a number of data bytes are transmitted to a Master Receiver, as in the figure below. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 241 Figure 24-17. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER Device 3 ........ Device n R1 R2 SD A SCL To initiate the SR mode, the TWI (Slave) Address Register (TWAR) and the TWI Control Register (TWCR) must be initialized as follows: The upper seven bits of TWAR are the address to which the 2-wire Serial Interface will respond when addressed by a Master (TWAR.TWA[6:0]). If the LSB of TWAR is written to TWAR.TWGCI=1, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR must hold a value of the type TWCR=0100010x - TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device's own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is "1" (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT Flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in the table below. The ST mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state 0xB0). If the TWCR.TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives all '1' as serial data. State 0xC8 is entered if the Master demands additional data bytes (by transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting NACK from the Master). While TWCR.TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing '1' to it). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note: The 2-wire Serial Interface Data Register (TWDR) does not reflect the last byte present on the bus when waking up from these Sleep modes. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 242 Table 24-6. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR Prescaler Bits are 0 Next Action Taken by TWI Hardware To TWCR STA STO TWI NT TWE A 0xA8 Own SLA+R has been received; ACK has been returned Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0xB0 Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received 0xB8 Data byte in TWDR has been transmitted; ACK has been Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received No TWDR action or No TWDR action or 0 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 1 0 1 0 Switched to the not addressed Slave mode; 1 0 1 1 own SLA will be recognized; received 0xC0 Data byte in TWDR has been transmitted; NOT ACK has been received No TWDR action or GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; No TWDR action no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free 0xC8 Last data byte in TWDR has been transmitted (TWEA = "0"); ACK has been received No TWDR action or No TWDR action or No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Switched to the not addressed Slave mode; no recognition of own SLA or GCA 1 0 1 0 Switched to the not addressed Slave mode; 1 0 1 1 own SLA will be recognized; GCA will be recognized if TWGCE = "1" Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = "1"; a START condition will be transmitted when the bus becomes free Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 243 Figure 24-18. Formats and States in the Slave Transmitter Mode Reception of the o wn sla ve address and one or more data b ytes S SLA R A DATA A $A8 Arbitration lost as master and addressed as sla ve DATA $B8 A P or S $C0 A $B0 Last data b yte tr ansmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to sla ve From slave to master 24.6.6. Any number of data b ytes and their associated ac kno wledge bits A This number (contained in TWSR) corresponds to a defined state of the 2-Wire Ser ial Bus . The prescaler bits are z ero or mask ed to z ero n Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see the table below. Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Table 24-7. Miscellaneous States Status Code (TWSR) Status of the 2-wire Serial Bus and 2-wire Serial Interface Hardware Application Software Response To/from TWDR To TWCR STA Prescaler Bits are 0 Next Action Taken by TWI Hardware STO TWI NT 0xF8 No relevant state information available; TWINT = "0" No TWDR action No TWCR action 0x00 Bus error due to an illegal START or STOP condition No TWDR action 0 24.6.7. 1 1 TWE A Wait or proceed current transfer X Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared. Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 244 1. 2. 3. 4. The transfer must be initiated. The EEPROM must be instructed what location should be read. The reading must be performed. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated in a multimaster system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the Master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the Master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 24-19. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter S SLA+W A ADDRESS A S = ST ART SLA+R A DATA Rs = REPEA TED ST ART Transmitted from master to sla 24.7. Rs Master Receiv er ve A P P = ST OP Transmitted from sla ve to master Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. Figure 24-20. An Arbitration Example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........ Device n R1 R2 SD A SCL Several different scenarios may arise during arbitration, as described below: * Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 245 * * Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a '1' on SDA while another Master outputs a zero will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a '1' on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. This is summarized in the next figure. Possible status values are given in circles. Figure 24-21. Possible Status Codes Caused by Arbitration START SLA Data Arbitration lost in SLA Own Address / General Call received No STOP Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free Yes Direction Write 68/78 Read B0 24.8. Data byte will be received and NOT ACK will be returned Data byte will be received and ACK will be returned Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be received Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 246 24.8.1. TWBR - TWI Bit Rate Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TWBR Offset: 0x00 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x20 Bit Access Reset 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TWBRn: TWI Bit Rate Register [n = 7:0] TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See Bit Rate Generator Unit for calculating bit rates. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 247 24.8.2. TWCR - TWI Control Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. Name: TWCR Offset: 0x36 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x56 Bit Access Reset 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE R/W R/W R/W R/W R R/W R/W 0 0 0 0 0 0 0 Bit 7 - TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. Bit 6 - TWEA: TWI Enable Acknowledge The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. 2. 3. The device's own slave address has been received. A general call has been received, while the TWGCE bit in the TWAR is set. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. Bit 5 - TWSTA: TWI START Condition The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 248 Bit 4 - TWSTO: TWI STOP Condition Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. Bit 3 - TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. Bit 2 - TWEN: TWI Enable The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. Bit 0 - TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 249 24.8.3. TWSR - TWI Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: TWSR Offset: 0x01 Reset: 0xF8 Property: When addressing I/O Registers as data space the offset address is 0x21 Bit 7 6 5 4 3 1 0 TWS4 TWS3 TWS2 TWS1 TWS0 2 TWPS1 TWPS0 Access R R R R R R/W R/W Reset 0 0 0 0 1 0 0 Bits 7:3 - TWSn: TWI Status Bit 7 [n = 7:3] The TWS[7:3] reflect the status of the TWI logic and the 2-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. Bits 1:0 - TWPSn: TWI Prescaler [n = 1:0] These bits can be read and written, and control the bit rate prescaler. Table 24-8. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, refer to Bit Rate Generator Unit. The value of TWPS1:0 is used in the equation. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 250 24.8.4. TWDR - TWI Data Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. Name: TWDR Offset: 0x03 Reset: 0xFF Property: When addressing I/O Registers as data space the offset address is 0x23 Bit Access Reset 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1 Bits 7:0 - TWDn: TWI Data [n = 7:0] These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2wire Serial Bus. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 251 24.8.5. TWAR - TWI (Slave) Address Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters. The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. Name: TWAR Offset: 0x02 Reset: 0x7F Property: When addressing I/O Registers as data space the offset address is 0x22 Bit Access Reset 7 6 5 4 3 2 1 0 TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 0 Bits 7:1 - TWAn: TWI (Slave) Address [n = 6:0] These seven bits constitute the slave address of the TWI unit. Bit 0 - TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 252 25. AC - Analog Comparator 25.1. Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator's output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in the figure below. Figure 25-1. Analog Comparator Block Diagram(2) BANDGAP REFERENCE ACBG ACME ADEN ADC MULTIPLEXER OUTPUT (1) Note: 1. See Table Analog Comparator Multiplexed Input in next section. 2. Refer to the Pin Configuration and the Port D Pins Alternate Functions Table. Related Links Pin Configurations on page 13 Alternate Functions of Port D on page 86 25.2. Analog Comparator Multiplexed Input It is possible to select any of the ADC7:0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2:0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in the table below. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 25-1. Analog Comparator Multiplexed Input ACME ADEN MUX[2:0] Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 253 25.3. ACME ADEN MUX[2:0] Analog Comparator Negative Input 1 0 000 ADC0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 254 25.3.1. SFIOR - Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SFIOR Offset: 0x30 Reset: N/A Property: When addressing I/O Registers as data space the offset address is 0x50 Bit 7 6 5 4 3 2 1 0 ACME Access Reset R/W 0 Bit 3 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see Analog Comparator Multiplexed Input table. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 255 25.3.2. ACSR - Analog Comparator Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ACSR Offset: 0x08 Reset: N/A Property: When addressing I/O Registers as data space the offset address is 0x28 Bit Access Reset 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 R/W R/W R R/W R/W R/W R/W R/W 0 0 a 0 0 0 0 0 Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. Bit 2 - ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/ Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. Bits 1:0 - ACISn: Analog Comparator Interrupt Mode Select [n = 1:0] These bits determine which comparator events that trigger the Analog Comparator interrupt. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 256 Table 25-2. ACIS[1:0] Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 257 26. ADC - Analog to Digital Converter 26.1. Features * * * * * * * * * * * * * * * * 26.2. 10-bit Resolution 0.5 LSB Integral Non-Linearity 2 LSB Absolute Accuracy 13 - 260s Conversion Time Up to 15ksps at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.56V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Canceler Overview The ATmega32A features a 10-bit successive approximation ADC. The ADC is connected to an 8channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND). The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0dB (1x), 20dB (10x), or 46dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be expected. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown below. The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than 0.3V from VCC. See section ADC Noise Canceler on how to connect this pin. Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for better noise performance. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 258 Figure 26-1. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADPS2 ADIF ADATE ADEN ADSC MUX1 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & ST ATUS REGISTER (ADCSRA) MUX0 MUX2 MUX4 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC START CONVERSION LOGIC INTERNAL REFERENCE SAMPLE & HOLD COMPARATOR AREF 10-BIT DAC + AGND BANDGAP REFERENCE SINGLE ENDED / DIFFERENTIAL SELECTION ADC7 ADC5 ADC MULTIPLEXER OUTPUT + ADC6 POS. INPUT MUX ADC4 - ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier. If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 259 The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 26.3. Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 26-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . SOURCE n CONVERSION LOGIC EDGE DETECTOR ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 260 If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 26-3. ADC Prescaler ADEN START Reset CK/64 CK/128 CK/32 CK/8 CK/16 CK/4 7-BIT ADC PRESCALER CK CK/2 26.4. ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See Differential Gain Channels for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of a first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. When using Differential mode, along with auto trigging from a source other that the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see table ADC Conversion Time at the end of this section. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 261 Figure 26-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 12 2 13 14 16 15 17 18 19 20 21 23 22 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample and Hold MUX and REFS Update Figure 26-5. ADC Timing Diagram, Single Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 Next Conversion 8 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample and Hold Conversion Complete MUX and REFS Update MUX and REFS Update Figure 26-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Conversion Complete Prescaler Reset MUX and REFS Update Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 262 Figure 26-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Conversion Complete Sample and Hold MUX and REFS Update Table 26-1. ADC Conversion Time 26.4.1. Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 Auto Triggered conversions 2 13.5 Normal conversions, differential 1.5/2.5 13/14 Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration. Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC clock. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific edge of CKADC2. A conversion initiated by the user (that is, all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism. In free running mode, a new conversion is initiated immediately after the previous conversion completes, and since CKADC2 is high at this time, all automatically started (that is, all but the first) free running conversions will take 14 ADC clock cycles. The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage bandwidth limitation. For example the ADC clock period may be 6s, allowing a channel to be sampled at 12kSPS, regardless of the bandwidth of this channel. If differential gain channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the gain stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 263 (writing ADEN in ADCSRA to "0" then to "1"), only extended conversions are performed. The result from the extended conversions will be valid. Refer to Prescaling and Conversion Timing for timing details. 26.5. Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. 2. 3. When ADATE or ADEN is cleared. During conversion, minimum one ADC clock cycle after the trigger event. After a conversion, before the interrupt flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125s to stabilize to the new value. Thus conversions should not be started within the first 125s after selecting a new differential channel. Alternatively, conversion results obtained within this period should be discarded. The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in ADMUX). 26.5.1. ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: * In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. * In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. When switching to a differential gain channel, the first conversion result may have a poor accuracy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 264 26.5.2. ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either AVCC, internal 2.56V reference, or external AREF pin. AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedance voltmeter. Note that VREF is a high impedance source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AVCC than indicated in table ADC Characteristics, Differential Channels in ADC Characteristics Related Links ADC Characteristics on page 367 26.6. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. 2. 3. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note: The ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADCRSA.ADEN before entering such sleep modes to avoid excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result. 26.6.1. Analog Input Circuitry The analog input circuitry for single ended channels is illustrated below. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 265 sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 26-8. Analog Input Circuitry IIH ADCn 1..100k IIL CS/H= 14pF VCC/2 26.6.2. Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. 2. 3. 4. Keep analog signal paths as short as possible. Make sure analog tracks run over the ground plane, and keep them well away from high-speed switching digital tracks. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in the figure below. Use the ADC noise canceler function to reduce induced noise from the CPU. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 266 Analog Ground Plane PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC GND Figure 26-9. ADC Power Connections PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) AREF 10H PA7 (ADC7) AVCC 100nF GND PC7 26.6.3. Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 26.6.4. ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: * Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 267 Figure 26-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error * VREF Input Voltage Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB. Figure 26-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF * Input Voltage Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 26-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 268 * Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 26-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 * * 26.7. VREF Input Voltage Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, nonlinearity, and quantization error. Ideal value: 0.5 LSB. ADC Conversion Result After the conversion is complete (ADCSRA.ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is ADC = IN 1024 REF where VIN is the voltage on the selected input pin, and VREF the selected voltage reference (see Table 26-3 and Table 26-4). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. If differential channels are used, the result is ADC = (VPOS- VNEG ) GAIN 512 REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, GAIN the selected gain factor, and VREF the selected voltage reference. The result is presented in two's complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the results, it is sufficient to read the MSB of the result (ADC9 in ADCH). If this bit is one, the result is negative, and if this bit is zero, the result is positive. The next figure shows the decoding of the differential input range. The table below shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a gain of GAIN and a reference voltage of VREF. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 269 Figure 26-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF /GAIN 0 0x3FF VREF /GAIN Diffe re ntia l Input Volta ge (Volts ) 0x200 Table 26-2. Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding decimal value VADCm + VREF /GAIN 0x1FF 511 VADCm + 511/512 VREF /GAIN 0x1FF 511 VADCm + 510/512 VREF /GAIN 0x1FE 510 :. :. :. VADCm + 1/512 VREF /GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF /GAIN 0x3FF -1 :. :. :. VADCm - 511/512 VREF /GAIN 0x201 -511 VADCm - VREF /GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 270 Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV. ADCR = 512 x 10 x (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 26.8. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 271 26.8.1. ADMUX - ADC Multiplexer Selection Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ADMUX Offset: 0x07 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x27 Bit Access Reset 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:6 - REFSn: Reference Selection [n = 1:0] These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 26-3. ADC Voltage Reference Selection REFS[1:0] Voltage Reference Selection 00 AREF, Internal Vref turned off 01 AVCC with external capacitor at AREF pin 10 Reserved 11 Internal 2.56V Voltage Reference with external capacitor at AREF pin Bit 5 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see ADCL and ADCH. Bits 4:0 - MUXn: Analog Channel Selection [n = 4:0] The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. Refer to table below for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 272 Table 26-4. Input Channel and Gain Selections MUX[4:0] Single Ended Input 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 Positive Differential Input Negative Differential Input Gain N/A 01000(1) Reserved ADC0 ADC0 10x 01001 Reserved ADC1 ADC0 10x 01010(1) ADC0 ADC0 200x 01011 ADC1 ADC0 200x 01100 ADC2 ADC2 10x 01101 ADC3 ADC2 10x 01110 ADC2 ADC2 200x 01111 ADC3 ADC2 200x 10000 ADC0 ADC1 1x 10001 ADC1 ADC1 1x 10010 ADC2 ADC1 1x ADC3 ADC1 1x 10100 ADC4 ADC1 1x 10101 ADC5 ADC1 1x 10110 ADC6 ADC1 1x 10111 ADC7 ADC1 1x 11000 ADC0 ADC2 1x 11001 ADC1 ADC2 1x 11010 ADC2 ADC2 1x 11011 ADC3 ADC2 1x 11100 ADC4 ADC2 1x ADC5 ADC2 1x 10011 11101 N/A Reserved Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 273 MUX[4:0] Single Ended Input 11110 1.22V (VBG) 11111 0V (GND) Positive Differential Input Negative Differential Input Gain N/A Note: 1. Can be used for offset calibration. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 274 26.8.2. ADCSRA - ADC Control and Status Register A When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ADCSRA Offset: 0x06 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x26 Bit Access Reset 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in SFIOR. Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. Bits 2:0 - ADPSn: ADC Prescaler Select [n = 2:0] These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 275 Table 26-5. ADC Prescaler Selections ADPS[2:0] Division Factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 276 26.8.3. ADCL - ADC Data Register Low (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two's complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. Name: ADCL Offset: 0x04 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x24 Bit 7 6 5 4 3 2 1 0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 - ADCn: ADC Conversion Result [n = 7:0] These bits represent the result from the conversion. Refer to ADC Conversion Result for details. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 277 26.8.4. ADCH - ADC Data Register High (ADLAR=0) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ADCH Offset: 0x05 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x25 Bit 7 6 5 4 3 2 1 0 ADC9 ADC8 Access R R Reset 0 0 Bit 1 - ADC9: ADC Conversion Result Refer to ADCL Bit 0 - ADC8: ADC Conversion Result Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 278 26.8.5. ADCL - ADC Data Register Low (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ADCL Offset: 0x04 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x24 Bit 7 6 ADC1 ADC0 Access R R Reset 0 0 5 4 3 2 1 0 Bit 7 - ADC1: ADC Conversion Result Refer to ADCL Bit 6 - ADC0: ADC Conversion Result Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 279 26.8.6. ADCH - ADC Data Register High (ADLAR=1) When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: ADCH Offset: 0x05 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x25 Bit 7 6 5 4 3 2 1 0 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 - ADC9: ADC Conversion Result Bit 6 - ADC8: ADC Conversion Result Bit 5 - ADC7: ADC Conversion Result Bit 4 - ADC6: ADC Conversion Result Bit 3 - ADC5: ADC Conversion Result Bit 2 - ADC4: ADC Conversion Result Bit 1 - ADC3: ADC Conversion Result Bit 0 - ADC2: ADC Conversion Result Refer to ADCL Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 280 26.8.7. SFIOR - Special Function IO Register Name: SFIOR Offset: 0x30 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x50 Bit Access Reset 7 6 5 ADTS2 ADTS1 ADTS0 R/W R/W R/W 0 0 0 4 3 2 1 0 Bits 7:5 - ADTSn: ADC Auto Trigger Source [n = 2:0] If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 26-6. ADC Auto Trigger Source Selections ADTS[2:0] Trigger Source 000 Free Running mode 001 Analog Comparator 010 External Interrupt Request 0 011 Timer/Counter0 Compare Match 100 Timer/Counter0 Overflow 101 Timer/Counter1 Compare Match B 110 Timer/Counter1 Overflow 111 Timer/Counter1 Capture Event Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 281 27. JTAG Interface and On-chip Debug System 27.1. Features * * * * * * 27.2. JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard Debugger Access to: - All Internal Peripheral Units - Internal and External RAM - The Internal Register File - Program Counter - EEPROM and Flash Memories Extensive On-chip Debug Support for Break Conditions, Including: - AVR Break Instruction - Break on Change of Program Memory Flow - Single Step Break - Program Memory Breakpoints on Single Address or Address Range - Data Memory Breakpoints on Single Address or Address Range Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface On-chip Debugging Supported by Atmel Studio Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for: * * * Testing PCBs by using the JTAG Boundary-scan capability Programming the non-volatile memories, Fuses and Lock bits On-chip debugging A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in the sections Programming Via the JTAG Interface and IEEE 1149.1 (JTAG) Boundary-scan, respectively. The On-chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 27-1 shows the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI - input and TDO - output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for boardlevel testing. The JTAG Programming Interface (actually consisting of several physical and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip debugging only. Related Links Programming Via the JTAG Interface on page 345 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 282 TAP - Test Access Port The JTAG interface is accessed through four of the AVR's pins. In JTAG terminology, these pins constitute the Test Access Port - TAP. These pins are: * * * * TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. TCK: Test clock. JTAG operation is synchronous to TCK. TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed. For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored by the debugger to be able to detect External Reset sources. The debugger can also pull the RESET pin low to reset the whole system, assuming only open collectors on the Reset line are used in the application. Figure 27-1. Block Diagram I/O P ORT 0 DEVICE BOUNDARY BOUNDARY S CAN CHAIN J TAG P ROGRAMMING INTERFACE INS TRUCTION REGIS TER ID REGIS TER M U X FLAS H MEMORY Addre s s Da ta BREAKP OINT UNIT BYP AS S REGIS TER INTERNAL S CAN CHAIN FLOW CONTROL UNIT AVR CP U PC Ins truction DIGITAL P ERIP HERAL UNITS BREAKP OINT S CAN CHAIN ADDRES S DECODER J TAG / AVR CORE COMMUNICATION INTERFACE OCD S TATUS AND CONTROL Ana log inputs TAP CONTROLLER Control & Clock line s TDI TDO TCK TMS ANALOG P ERIP HERIAL UNITS 27.3. I/O P ORT n Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 283 Figure 27-2. TAP Controller State Diagram 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 0 P a us e -DR 0 0 P a us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 27.4. 1 Exit1-IR 0 1 0 1 1 0 1 Upda te -IR 0 1 0 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 27-2 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all Shift Registers. Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is: * At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register - Shift-IR state. While in this state, shift the 4 bits of the JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK. The TMS input must be Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 284 * * * held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register - Shift-DR state. While in this state, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, PauseDR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using Data Registers, and some JTAG instructions may select certain functions to be performed in the Run- Test/Idle, making it unsuitable as an Idle state. Note: 1. Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for 5 TCK clock periods. For detailed information on the JTAG specification, refer to the literature listed in Bibliography. 27.5. Using the Boundary-scan Chain A complete description of the Boundary-scan capabilities are given in the section IEEE 1149.1 (JTAG) Boundary-scan. 27.6. Using the On-chip Debug System As shown in Figure 27-1, the hardware support for On-chip Debugging consists mainly of: * * * A scan chain on the interface between the internal AVR CPU and the internal peripheral units Break point unit Communication interface between the CPU and JTAG system All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system. The Break point Unit implements Break on Change of Program Flow, Single Step Break, two Program Memory Break points, and two combined break points. Together, the four break points can be configured as either: * * * 4 Single Program Memory break points 3 Single Program Memory break points + 1 single Data Memory break point 2 Single Program Memory break points + 2 single Data Memory break points Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 285 * * 2 Single Program Memory break points + 1 Program Memory break point with mask ("range break point") 2 Single Program Memory break points + 1 Data Memory break point with mask ("range break point") A debugger, like the Atmel Studio(R), may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in On-chip Debug Specific JTAG Instructions. The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the On-chip Debug system is disabled when any Lock bits are set. Otherwise, the Onchip Debug system would have provided a back-door into a secured device. The Atmel Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. Atmel Studio supports source level execution of Assembly programs assembled with Atmel Corporation's AVR Assembler and C programs compiled with third party vendors' compilers. For a full description of the Atmel Studio, please refer to the Atmel Studio User Guide found in the Online Help in Atmel Studio. Only highlights are presented in this document. All necessary execution commands are available in Atmel Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have an unlimited number of code break points (using the BREAK instruction) and up to two data memory break points, alternatively combined as a mask (range) break point. 27.7. On-chip Debug Specific JTAG Instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Instruction opcodes are listed for reference. PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip Debug system. PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip Debug system. PRIVATE2; 0xA Private JTAG instruction for accessing On-chip Debug system. PRIVATE3; 0xB Private JTAG instruction for accessing On-chip Debug system. 27.8. Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN fuse must be programmed and the JTD bit in the MCUCSR Register must be cleared to enable the JTAG Test Access Port. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 286 The JTAG programming capability supports: * * * * Flash programming and verifying EEPROM programming and verifying Fuse programming and verifying Lock bit programming and verifying The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device. The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section Programming Via the JTAG Interface. Related Links Programming Via the JTAG Interface on page 345 27.9. Bibliography For more information about general Boundary-scan, the following literature can be consulted: * * IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993 Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992 27.10. IEEE 1149.1 (JTAG) Boundary-scan 27.10.1. Features * * * * * JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections Supports the Optional IDCODE Instruction Additional Public AVR_RESET Instruction to Reset the AVR 27.10.2. System Overview The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan provides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. Entering Reset, the outputs of any Port Pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 287 the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/ PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. The JTAGEN fuse must be programmed and the JTD bit in the I/O register MCUCSR must be cleared to enable the JTAG Test Access Port. When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run. 27.11. Data Registers The data registers relevant for Boundary-scan operations are: * * * * Bypass Register Device Identification Register Reset Register Boundary-scan Chain 27.11.1. Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 27.11.2. Device Identification Register The figure below shows the structure of the Device Identification Register. Figure 27-3. The format of the Device Identification Register LSB MSB Bit Device ID 28 31 27 12 11 Version Part Number 4 bits 16 bits 1 Manufacturer ID 11 bits 0 1 1-bit 27.11.2.1. Version Version is a 4-bit number identifying the revision of the component. The JTAG version number follows the revision of the device, and wraps around at revision P (0xF). Revision A and Q is 0x0, revision B and R is 0x1 and so on. 27.11.2.2. Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for ATmega32A is listed in the table below. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 288 Table 27-1. AVR JTAG Part Number Part Number JTAG Part Number (Hex) ATmega32A 0x9502 27.11.2.3. Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in the table below. Table 27-2. Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F 27.11.3. Reset Register The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port Pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to Clock Sources) after releasing the Reset Register. The output from this Data Register is not latched, so the Reset will take place immediately, as shown in the figure below. Figure 27-4. Reset Register To TDO From Othe r Inte rna l a nd Exte rna l Re s e t S ource s From TDI D Q Inte rna l Re s e t ClockDR * AVR_RES ET Related Links Clock Sources on page 40 27.11.4. Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. Refer to Boundary-scan Chain for a complete description. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 289 27.12. Boundry-scan Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. 27.12.1. EXTEST; 0x0 Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction. The active states are: * * * Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. Shift-DR: The Internal Scan Chain is shifted by the TCK input. Update-DR: Data from the scan chain is applied to output pins. 27.12.2. IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID Register as Data Register. The ID Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: * * Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. Shift-DR: The IDCODE scan chain is shifted by the TCK input. 27.12.3. SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states are: * * * Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. Shift-DR: The Boundary-scan Chain is shifted by the TCK input. Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins. 27.12.4. AVR_RESET; 0xC The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the Reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 290 * Shift-DR: The Reset Register is shifted by the TCK input. 27.12.5. BYPASS; 0xF Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are: * * Capture-DR: Loads a logic "0" into the Bypass Register. Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 27.13. Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. 27.13.1. Scanning the Digital Port Pins The first figure below shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable - PUExn - function, and a bidirectional pin cell that combines the three signals, Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 27-6 shows a simple digital Port Pin as described in the section I/O Ports. The Boundary-scan details from the first figure below replaces the dashed box in Figure 27-6. When no alternate port function is present, the Input Data - ID corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - corresponds to logic expression PUD * DDxn * PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 27-6 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 291 Figure 27-5. Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function. S hiftDR To Ne xt Ce ll EXTES T P ullup Ena ble (P UE) Vcc 0 FF2 0 D 1 LD2 Q D 1 Q G Output Control (OC) FF1 0 D 1 LD1 Q D Q 0 1 G Output Da ta (OD) 0 1 FF0 0 D 1 LD0 Q D Q 0 1 P ort P in (P Xn) G Input Da ta (ID) From La s t Ce ll ClockDR Upda te DR Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 292 Figure 27-6. General Port Pin Schematic diagram S e e Bounda ry-S ca n de s cription for de ta ils ! P UExn P UD D Q DDxn Q CLR RES ET OCxn WDx D Q P xn ODxn PORTxn Q IDxn CLR RES ET WP x DATA BUS RDx RRx S LEEP S YNCHRONIZER D Q D RP x Q PINxn L Q Q CLK I/O P UD: P UExn: OCxn: ODxn: IDxn: S LEEP : P ULLUP DIS ABLE P ULLUP ENABLE for pin P xn OUTP UT CONTROL for pin P xn OUTP UT DATA to pin P xn INP UT DATA from pin P xn S LEEP CONTROL WDx: RDx: WP x: RRx: RP x: CLK I/O : WRITE DDRx READ DDRx WRITE P ORTx READ P ORTx REGIS TER READ P ORTx P IN I/O CLOCK Related Links I/O Ports on page 74 27.13.2. Boundary-scan and the Two-wire Interface The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-chain; Twowire Interface Enable - TWIEN. As shown in the figure below, the TWIEN signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 27-11 is attached to the TWIEN signal. Note: 1. A separate scan chain for the 50ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-scan. 2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 293 Figure 27-7. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn Pxn TWIEN SRC Slew-rate limited IDxn 27.13.3. Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in the figure below is inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV. Figure 27-8. Observe-only Cell To ne xt ce ll S hiftDR From s ys te m pin To s ys te m logic FF1 0 D 1 From pre vious ce ll Q ClockDR 27.13.4. Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External RC, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 294 The figure below shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock output is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this Oscillator does not have external connections. Figure 27-9. Boundary-scan Cells for Oscillators and Clock Options XTAL1/TOS C1 To Ne xt Ce ll S hiftDR 0 1 0 D 1 From P re vious Ce ll Q Os cilla tor EXTES T From Digita l Logic D XTAL2/TOS C2 ENABLE S hiftDR To S ys te m Logic OUTP UT FF1 Q 0 G ClockDR To ne xt ce ll D 1 Q Upda te DR From P re vious Ce ll ClockDR The following table summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/ XTAL2 connections as well as 32kHz Timer Oscillator. Table 27-3. Scan Signals for the Oscillators(1)(2)(3) Enable signal Scanned Clock Line Clock Option Scanned Clock Line when not Used EXTCLKEN EXTCLK (XTAL1) External Clock 0 OSCON OSCCK External Crystal 0 External Ceramic Resonator RCOSCEN RCCK External RC 1 OSC32EN OSC32CK Low Freq. External Crystal 0 TOSKON TOSCK 32kHz Timer Oscillator 0 Note: 1. Do not enable more than one clock source as main clock at a time. 2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred. 3. The clock configuration is programmed by fuses. As a fuse does not change run-time, the clock configuration is considered fixed for a given application. The user is advised to scan the same clock option as to be used in the final system. The enable signals are supported in the scan chain because the system logic can disable clock options in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported in the scan- Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 295 chain, so the boundary scan chain can not make a XTAL Oscillator requiring internal capacitors to run unless the fuse is correctly programmed. 27.13.5. Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in the first figure below. The Boundary-scan cell from the second figure below is attached to each of these signals. The signals are described in Table 27-4. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 27-10. Analog comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIP LEXER OUTP UT Figure 27-11. General Boundary-scan Cell used for Signals for Comparator and ADC To Ne xt Ce ll S hiftDR EXTES T From Digita l Logic/ From Ana log Ciruitry 0 1 0 D 1 From P re vious Ce ll Q D To Ana log Circuitry/ To Digita l Logic Q G ClockDR Upda te DR Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 296 Table 27-4. Boundary-scan Signals for the Analog Comparator Signal Name Direction as Seen from the Comparator Description Recommended Input Output values when when not in Use Recommended Inputs are Used AC_IDLE Input Turns off Analog comparator when true 1 Depends upon C code being executed ACO Output Analog Comparator Output Will become input to C code being executed 0 ACME Input Uses output signal from ADC mux when true 0 Depends upon C code being executed ACBG Input Bandgap Reference 0 enable Depends upon C code being executed 27.13.6. Scanning the ADC The figure below shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 27-8 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 27-12. Analog to Digital Converter VCCREN AREF IREFEN 2.56V re f To Compa ra tor PAS S EN MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4 ADCBGEN S CTES T 1.22V re f EXTCH MUXEN_3 ADC_3 MUXEN_2 ADC_2 MUXEN_1 ADC_1 MUXEN_0 ADC_0 P RECH P RECH AREF AREF DACOUT DAC_9..0 10-bit DAC + COMP G20 G10 ADCEN + 10x NEGS EL_2 - ADC_2 NEGS EL_1 ADC_0 ACTEN 20x HOLD - GNDEN ADC_1 NEGS EL_0 + COMP - ST ACLK AMP EN The signals are described briefly in the following table. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 297 Table 27-5. Boundary-scan Signals for the ADC Signal Name Direction as Description Seen from the ADC Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC COMP Output Comparator Output 0 0 ACLK Input Clock signal to gain stages implemented as Switch-cap filters 0 0 ACTEN Input Enable path from gain stages to the comparator 0 0 ADCBGEN Input Enable Band-gap reference as 0 negative input to comparator 0 ADCEN Input Power-on signal to the ADC 0 0 AMPEN Input Power-on signal to the gain stages 0 0 DAC_9 Input Bit 9 of digital value to DAC 1 1 DAC_8 Input Bit 8 of digital value to DAC 0 0 DAC_7 Input Bit 7 of digital value to DAC 0 0 DAC_6 Input Bit 6 of digital value to DAC 0 0 DAC_5 Input Bit 5 of digital value to DAC 0 0 DAC_4 Input Bit 4 of digital value to DAC 0 0 DAC_3 Input Bit 3 of digital value to DAC 0 0 DAC_2 Input Bit 2 of digital value to DAC 0 0 DAC_1 Input Bit 1 of digital value to DAC 0 0 DAC_0 Input Bit 0 of digital value to DAC 0 0 EXTCH Input Connect ADC channels 0 - 3 to 1 by-pass path around gain stages 1 G10 Input Enable 10x gain 0 0 G20 Input Enable 20x gain 0 0 GNDEN Input Ground the negative input to comparator when true 0 0 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 298 Signal Name Direction as Description Seen from the ADC Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC HOLD Input Sample & Hold signal. Sample 1 analog signal when low. Hold signal when high. If gain stages are used, this signal must go active when ACLK is high. 1 IREFEN Input Enables Band-gap reference as AREF signal to DAC 0 0 MUXEN_7 Input Input Mux bit 7 0 0 MUXEN_6 Input Input Mux bit 6 0 0 MUXEN_5 Input Input Mux bit 5 0 0 MUXEN_4 Input Input Mux bit 4 0 0 MUXEN_3 Input Input Mux bit 3 0 0 MUXEN_2 Input Input Mux bit 2 0 0 MUXEN_1 Input Input Mux bit 1 0 0 MUXEN_0 Input Input Mux bit 0 1 1 NEGSEL_2 Input Input Mux for negative input for 0 differential signal, bit 2 0 NEGSEL_1 Input Input Mux for negative input for 0 differential signal, bit 1 0 NEGSEL_0 Input Input Mux for negative input for 0 differential signal, bit 0 0 PASSEN Input Enable pass-gate of gain stages. 1 1 PRECH Input Precharge output latch of comparator. (Active low) 1 1 SCTEST Input Switch-cap TEST enable. Output from x10 gain stage send out to Port Pin having ADC_4 0 0 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 299 Signal Name Direction as Description Seen from the ADC Recommended Input when not in Use Output Values when Recommended Inputs are Used, and CPU is not Using the ADC ST Input Output of gain stages will settle faster if this signal is high first two ACLK periods after AMPEN goes high. 0 0 VCCREN Input Selects Vcc as the ACC reference voltage. 0 0 Note: 1. Incorrect setting of the switches in Figure 27-12 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the output comparator in Figure 27-12. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground. If the ADC is not to be used during scan, the recommended input values from the table above should be used. The user is recommended not to use the Differential Gain stages during scan. Switch-Cap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided. The AVR ADC is based on the analog circuitry shown in Figure 27-12 with a successive approximation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. When using the ADC, remember the following: * * * The Port Pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention. In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before controlling/ observing any ADC signal, or perform a dummy conversion before using the first result. The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: 1024 1,5V 0,95 5V = 291 = 0x123 The upper limit is: 1024 1,5V 1,05 5V = 323 = 0x143 The recommended values from Table 27-5 are used unless other values are given in the algorithm in the following table. Only the DAC and Port Pin values of the Scan Chain are shown. The column "Actions" describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 300 columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 27-6. Algorithm for Using the ADC Step Actions ADCEN DAC 1 SAMPLE_P RELOAD 1 0x200 0x08 1 1 0 0 0 2 EXTEST 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 1 0x200 0x08 1 1 0 0 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 1 0x200 0x08 1 1 0 0 0 6 11 Verify the COMP bit scanned out to be 0 Verify the COMP bit scanned out to be 1 MUXEN HOLD PRECH PA3. Data PA3. Control PA3. Pullup_ Enable Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, thold,max 27.14. ATmega32A Boundary-scan Order The table below shows the Scan order between TDI and TDO when the Boundary-scan Chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A are scanned in the opposite bit order of the other ports. Exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 27-5, PXn. Data corresponds to FF0, PXn. Control corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 301 Table 27-7. ATmega32A Boundary-scan Order Bit Number Signal Name Module 140 AC_IDLE Comparator 139 ACO 138 ACME 137 ACBG 136 COMP 135 PRIVATE_SIGNAL1(1) 134 ACLK 133 ACTEN 132 PRIVATE_SIGNAL2(2) 131 ADCBGEN 130 ADCEN 129 AMPEN 128 DAC_9 127 DAC_8 126 DAC_7 125 DAC_6 124 DAC_5 123 DAC_4 122 DAC_3 121 DAC_2 120 DAC_1 119 DAC_0 118 EXTCH 117 G10 116 G20 115 GNDEN 114 HOLD 113 IREFEN 112 MUXEN_7 ADC Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 302 Bit Number Signal Name Module 111 MUXEN_6 ADC 110 MUXEN_5 109 MUXEN_4 108 MUXEN_3 107 MUXEN_2 106 MUXEN_1 105 MUXEN_0 104 NEGSEL_2 103 NEGSEL_1 102 NEGSEL_0 101 PASSEN 100 PRECH 99 SCTEST 98 ST 97 VCCREN Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 303 Bit Number Signal Name Module 96 PB0.Data Port B 95 PB0.Control 94 PB0.Pullup_Enable 93 PB1.Data 92 PB1.Control 91 PB1.Pullup_Enable 90 PB2.Data 89 PB2.Control 88 PB2.Pullup_Enable 87 PB3.Data 86 PB3.Control 85 PB3.Pullup_Enable 84 PB4.Data 83 PB4.Control 82 PB4.Pullup_Enable 81 PB5.Data 80 PB5.Control 79 PB5.Pullup_Enable 78 PB6.Data 77 PB6.Control 76 PB6.Pullup_Enable 75 PB7.Data 74 PB7.Control 73 PB7.Pullup_Enable 72 RSTT 71 RSTHV 70 EXTCLKEN 69 OSCON 68 RCOSCEN 67 OSC32EN Reset Logic (Observe-only) Enable signals for main Clock/Oscillators Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 304 Bit Number Signal Name Module 66 EXTCLK (XTAL1) 65 OSCCK Clock input and Oscillators for the main clock (Observe-only) 64 RCCK 63 OSC32CK 62 TWIEN TWI 61 PD0.Data Port D 60 PD0.Control 59 PD0.Pullup_Enable 58 PD1.Data 57 PD1.Control 56 PD1.Pullup_Enable 55 PD2.Data 54 PD2.Control 53 PD2.Pullup_Enable 52 PD3.Data 51 PD3.Control 50 PD3.Pullup_Enable 49 PD4.Data 48 PD4.Control 47 PD4.Pullup_Enable 46 PD5.Data 45 PD5.Control 44 PD5.Pullup_Enable 43 PD6.Data 42 PD6.Control 41 PD6.Pullup_Enable 40 PD7.Data 39 PD7.Control 38 PD7.Pullup_Enable Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 305 Bit Number Signal Name Module 37 PC0.Data Port C 36 PC0.Control 35 PC0.Pullup_Enable 34 PC1.Data 33 PC1.Control 32 PC1.Pullup_Enable 31 PC6.Data 30 PC6.Control 29 PC6.Pullup_Enable 28 PC7.Data 27 PC7.Control 26 PC7.Pullup_Enable 25 TOSC 24 TOSCON 32kHz Timer Oscillator Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 306 Bit Number Signal Name Module 23 PA7.Data Port A 22 PA7.Control 21 PA7.Pullup_Enable 20 PA6.Data 19 PA6.Control 18 PA6.Pullup_Enable 17 PA5.Data 16 PA5.Control 15 PA5.Pullup_Enable 14 PA4.Data 13 PA4.Control 12 PA4.Pullup_Enable 11 PA3.Data 10 PA3.Control 9 PA3.Pullup_Enable 8 PA2.Data 7 PA2.Control 6 PA2.Pullup_Enable 5 PA1.Data 4 PA1.Control 3 PA1.Pullup_Enable 2 PA0.Data 1 PA0.Control 0 PA0.Pullup_Enable Note: 1. PRIVATE_SIGNAL1 should always scanned in as zero. 2. PRIVATE_SIGNAL2 should always scanned in as zero. 27.15. Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 307 27.16. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 308 27.16.1. OCDR - On-chip Debug Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: OCDR Offset: 0x31 Reset: 0x20 Property: When addressing I/O Registers as data space the offset address is 0x51 Bit 7 6 5 4 3 2 1 0 IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Access Reset Bit 7 - IDRD/OCDR7: USART Receive Complete The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Register Dirty - IDRD - is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed. * * Bit 7 is MSB Bit 1 is LSB Refer to the debugger documentation for further information on how to use this register. Bits 6:0 - OCDRn: On-chip Debug Register n [n = 6:0] Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 309 27.16.2. MCUCSR - MCU Control and Status Register When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The MCU Control and Status Register contains control bits for general MCU functions, and provides information on which reset source caused an MCU Reset. Name: MCUCSR Offset: 0x34 Reset: 0x20 Property: When addressing I/O Registers as data space the offset address is 0x54 Bit Access Reset 7 6 5 4 JTD JTRF R/W R/W 3 2 1 0 0 Bit 7 - JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface. Bit 4 - JTRF: JTAG Reset Flag This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 310 28. BTLDR - Boot Loader Support - Read-While-Write Self-Programming 28.1. Features * * * * * * * Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table. No. of Words in a Page and No. of Pages in the Flash in Signal Names) used during programming. The page organization does not affect normal operation. Related Links Signal Names on page 331 28.2. Overview In this device, the Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. 28.3. Application and Boot Loader Flash Sections The Flash memory is organized in two main sections, the Application section and the Boot Loader section. The size of the different sections is configured by the BOOTSZ Fuses. These two sections can have different level of protection since they have different sets of Lock bits. 28.3.1. Application Section The Application section is the section of the Flash that is used for storing the application code. The protection level for the Application section can be selected by the application Boot Lock bits (Boot Lock bits 0). The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section. 28.3.2. BLS - Boot Loader Section While the Application section is used for storing the application code, the Boot Loader software must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (Boot Lock bits 1). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 311 28.4. Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section. The limit between the RWW- and NRWW sections is given in the Boot Loader Parameters section and Figure 28-2. The main difference between the two sections is: * * When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation The user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax "Read-While-Write section" refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. Related Links ATmega32A Boot Loader Parameters on page 323 28.4.1. RWW - Read-While-Write Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an on-going programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e. by a call/rjmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader section. The Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory Control Register (SPMCR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. Please refer to SPMCR - Store Program Memory Control Register in this chapter for details on how to clear RWWSB. 28.4.2. NRWW - No Read-While-Write Section The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU is halted during the entire Page Erase or Page Write operation. Table 28-1. Read-While-Write Features Which Section does the Zpointer Address during the Programming? Which Section can be read during Programming? CPU Halted? Read-While-Write Supported? RWW Section NRWW Section No Yes NRWW Section None Yes No Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 312 Figure 28-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses RWW Section Code Located in NRWW Section Can be Read During the Operation Z-pointer Addresses NRWW Section No Read-While-Write (NRWW) Section CPU is Halted During the Operation Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 313 Figure 28-2. Memory Sections Program Memory BOOTSZ = '10' Program Memory BOOTSZ = '11' 0x0000 Read-While-Write Section End RWW Start NRWW Application Flash Section Read-While-Write Section Program Memory BOOTSZ = '01' 0x0000 Application Flash Section No Read-While-Write Section End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Application Flash Section End RWW Start NRWW Application Flash Section Boot Loader Flash Section End Application Start Boot Loader Flashend Program Memory BOOTSZ = '00' Read-While-Write Section Boot Loader Flash Section End Application Start Boot Loader Flashend No Read-While-Write Section No Read-While-Write Section Application Flash Section No Read-While-Write Section Read-While-Write Section 0x0000 0x0000 Application Flash Section End RWW, End Application Start NRWW, Start Boot Loader Boot Loader Flash Section Flashend Related Links ATmega32A Boot Loader Parameters on page 323 28.5. Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: * * To protect the entire Flash from a software update by the MCU To protect only the Boot Loader Flash section from a software update by the MCU Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 314 * * To protect only the Application Flash section from a software update by the MCU Allow software update in the entire Flash The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted. Table 28-2. Boot Lock Bit0 Protection Modes (Application Section) BLB0 Mode BLB02 BLB01 Protection 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. Note: "1" means unprogrammed, "0" means programmed. Table 28-3. Boot Lock Bit1 Protection Modes (Boot Loader Section) BLB1 Mode BLB12 BLB11 Protection 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. 4 0 1 LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. Note: "1" means unprogrammed, "0" means programmed. 28.6. Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code. The fuses cannot be changed by the MCU itself. This means that Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 315 once the Boot Reset Fuse is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 28-4. Boot Reset Fuse BOOTRST Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset, as described by the Boot Loader Parameters Note: '1' means unprogrammed, '0' means programmed. 28.7. Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Since the Flash is organized in pages, the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in the following figure. The Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the same page in both the Page Erase and Page Write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits. The content of the Z-pointer is ignored and will have no effect on the operation. The LPM instruction does also use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 316 Figure 28-3. Addressing the Flash During SPM(1) BIT 15 ZPAGEMSB ZPCMSB 1 0 0 Z - REGISTER PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: 1. Fo the different variables used in the figure, see the table of the different variables used and the Mapping to the Z-pointer in the boot loader parameters section. 2. PCPAGE and PCWORD are listed in table Number of Words in a Page and number of Pages in the Flash in the Signal Names section. Related Links Signal Names on page 331 ATmega32A Boot Loader Parameters on page 323 28.8. Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase * Fill temporary page buffer * Perform a Page Erase * Perform a Page Write Alternative 2, fill the buffer after Page Erase * Perform a Page Erase Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 317 * * Fill temporary page buffer Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. Please refer to Simple Assembly Code Example for a Boot Loader for an assembly code example. 28.8.1. Performing Page Erase by SPM To execute page erase, set up the address in the Z-pointer, write "X0000011" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * * Page Erase to the RWW section: The NRWW section can be read during the Page Erase. Page Erase to the NRWW section: The CPU is halted during the operation. Note: If an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. In order to ensure atomic operation disable interrupts before writing to SPMCSR. 28.8.2. Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The content of PCWORD in the Z-register is used to address the data in the temporary page buffer. The temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in SPMCR. It is also erased after a System Reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 28.8.3. Performing a Page Write To execute page write, set up the address in the Z-pointer, write "X0000101" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * * Page Write to the RWW section: The NRWW section can be read during the Page Write Page Write to the NRWW section: The CPU is halted during the operation Note: If an interrupt occurs in the timed sequence the four cycle access cannot be guaranteed. In order to ensure atomic operation disable interrupts before writing to SPMCSR. 28.8.4. Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in Interrupts chapter. Related Links Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 318 Interrupts on page 62 28.8.5. Consideration While Updating Boot Loader Section (BLS) Special care must be taken if the user allows the Boot Loader Section (BLS) to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. 28.8.6. Prevent Reading the RWW Section During Self-Programming During Self-Programming (either page erase or page write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCR will be set as long as the RWW section is busy. During SelfProgramming the Interrupt Vector table should be moved to the BLS as described in Interrupts, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. Please refer to Simple Assembly Code Example for a Boot Loader for an example. Related Links Interrupts on page 62 28.8.7. Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock Bits, write the desired data to R0, write "X0001001" to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are the Boot Lock Bits that may prevent the Application and Boot Loader section from any software update by the MCU. Bit 7 6 5 4 3 2 1 0 Rd - 1 - 1 - BLB12 - BLB11 - BLB02 - BLB01 LB2 1 LB1 1 The tables in Boot Loader Lock Bits show how the different settings of the Boot Loader bits affect the Flash access. If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR. The Z-pointer is don't care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock Bits). For future compatibility It is also recommended to set bits 7, 6, 1, and 0 in R0 to "1" when writing the Lock Bits. When programming the Lock Bits the entire Flash can be read during the operation. 28.8.8. EEPROM Write Prevents Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock Bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCR Register. 28.8.9. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock Bits from software. To read the Lock Bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the value of the Lock Bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock Bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 319 Bit 7 6 5 4 3 2 1 0 Rd - - - BLB12 - BLB11 - BLB02 - BLB01 LB2 LB1 The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock Bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to table Fuse Low Byte in section Fuse Bits for a detailed description and mapping of the fuse low bits. Bit 7 6 5 4 3 2 1 0 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below. Refer to table Fuse High Byte in section Fuse Bits for detailed description and mapping of the fuse high bits. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Fuse and Lock bits that are programmed read as '0'. Fuse and Lock bits that are unprogrammed, will read as '1'. 28.8.10. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. 2. 3. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the Flash from unintentional writes. 28.8.11. Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. The following table shows the typical programming time for Flash accesses from the CPU. Table 28-5. SPM Programming Time(1) Symbol Min. Programming Time Max. Programming Time Flash write (Page Erase, Page Write, and write Lock bits 3.7ms by SPM) 4.5ms Note: 1. Minimum and maximum programming time is per individual operation. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 320 28.8.12. Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-It is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcrval, (1<<PGERS) | (1<<SPMEN) rcall Do_spm ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcall Do_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcrval, (1<<SPMEN) rcall Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256 brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<<PGWRT) | (1<<SPMEN) rcall Do_spm ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 321 rcall Do_spm ; read back and check, optional ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 rjmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) rcall Do_spm rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: in temp1, SPMCR sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 322 sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCR, spmcrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 28.8.13. ATmega32A Boot Loader Parameters In the following tables, the parameters used in the description of the self programming are given. Table 28-6. Boot Size Configuration, ATmega32A BOOTSZ1 BOOTSZ0 Boot Size Pages Application Flash Section Boot Loader Flash Section End Application Section Boot Reset Address (Start Boot Loader Section) 1 1 256 words 4 0x0000 0x3EFF 0x3F00 0x3FFF 0xEFF 0x3F00 1 0 512 words 8 0x0000 0x3DFF 0x3E00 0x3FFF 0x3DFF 0x3E00 0 1 1024 words 16 0x0000 0x3BFF 0x3C00 0x3FFF 0x3BFF 0x3C00 0 0 2048 words 32 0x0000 0x37FF 0x3800 0x3FFF 0x37FF 0x3800 Note: The different BOOTSZ Fuse configurations are shown in Figure 28-2. Table 28-7. Read-While-Write Limit, ATmega32A Section Pages Address Read-While-Write section (RWW) 224 0x0000 - 0x37FF No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF Note: For details about these two section, see NRWW - No Read-While-Write Section and RWW - Read-While-Write Section. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 323 Table 28-8. Explanation of Different Variables used in figure "Addressing the Flash During SPM" from earlier in this chapter and the Mapping to the Z-pointer, ATmega32A Variable Corresponding Zvalue(1) Description PCMSB 13 Most significant bit in the Program Counter. (The Program Counter is 14 bits PC[13:0]) PAGEMSB 5 Most significant bit which is used to address the words within one page (64 words in a page requires 6 bits PC [5:0]). ZPCMSB Z14 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1. ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1. PCPAGE PC[13:6] Z14:Z7 Program counter page address: Page select, for page erase and page write PCWORD PC[5:0] Program counter word address: Word select, for filling temporary buffer (must be zero during page write operation) Z6:Z1 Note: 1. Z15: always ignored. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See Addressing the Flash During Self-Programming for details about the use of Z-pointer during SelfProgramming. 28.9. Register Description Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 324 28.9.1. SPMCR - Store Program Memory Control Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPMCR Offset: 0x37 Reset: 0x00 Property: When addressing I/O Registers as data space the offset address is 0x57 Bit Access Reset 7 6 4 3 2 1 0 SPMIE RWWSB RWWSRE BLBSET PGWRT PGERS SPMEN R/W R R/W R/W R/W R/W R/W 0 0 0 0 0 5 Bit 7 - SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR Register is cleared. Bit 6 - RWWSB: Read-While-Write Section Busy When a Self-Programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. Bit 4 - RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost. Bit 3 - BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR Register (SPMCR.BLBSET and SPMCR.SPMEN), will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 325 Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. Bit 0 - SPMEN: Store Program Memory This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 326 29. 29.1. Memory Programming Program and Data Memory Lock Bits The ATmega32A provides six Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in table Lock Bit Protection Modes below. The Lock Bits can only be erased to "1" with the Chip Erase command. Table 29-1. Lock Bit Byte Bit No. Description Default Value(1) 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) BLB12 5 Boot Lock bit 1 (unprogrammed) BLB11 4 Boot Lock bit 1 (unprogrammed) BLB02 3 Boot Lock bit 1 (unprogrammed) BLB01 2 Boot Lock bit 1 (unprogrammed) LB2 1 Lock bit 1 (unprogrammed) LB1 0 Lock bit 1 (unprogrammed) Lock Bit Byte Note: 1. "1" means unprogrammed, "0" means programmed. Table 29-2. Lock Bit Protection Modes(2) Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled. 2 1 0 Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) 3 0 0 Further programming and verification of the Flash and EEPROM is disabled in parallel and SPI/JTAG Serial Programming mode. The Fuse Bits are locked in both Serial and Parallel Programming modes.(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 327 Memory Lock Bits Protection Type LB Mode LB2 LB1 4 0 1 BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 3 0 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. 4 0 1 LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. Note: 1. Program the Fuse Bits before programming the Lock Bits. 2. "1" means unprogrammed, "0" means programmed. 29.2. Fuse Bits The ATmega32A has two fuse bytes. The tables of this section describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed. Table 29-3. Fuse High Byte Fuse High Byte Bit No. Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog. enabled) CKOPT(2) 4 Oscillator options 1 (unprogrammed) EESAVE 3 EEPROM memory is preserved through the 1 (unprogrammed, EEPROM Chip Erase not preserved) BOOTSZ1 2 Select Boot Size (see table Boot Size Configuration in section ATmega32A Boot Loader Parameters for details) 0 (programmed)(3) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 328 Fuse High Byte Bit No. Description Default Value BOOTSZ0 1 Select Boot Size (see table Boot Size Configuration in section ATmega32A Boot Loader Parameters for details) 0 (programmed)(3) BOOTRST 0 Select Reset Vector 1 (unprogrammed) Note: 1. The SPIEN Fuse is not accessible in SPI Serial Programming mode. 2. The CKOPT Fuse functionality depends on the setting of the CKSEL bits, see Clock Sources for details. 3. The default value of BOOTSZ1:0 results in maximum Boot Size. See table Boot Size Configuration in section ATmega32A Boot Loader Parameters. 4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of lock bits and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption. 5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This to avoid static current at the TDO pin in the JTAG interface. Table 29-4. Fuse Low Byte Fuse Low Byte Bit No. Description Default Value BODLEVEL 7 Brown out detector trigger level 1 (unprogrammed) BODEN 6 Brown out detector enable 1 (unprogrammed, BOD disabled) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 0 (programmed)(2) CKSEL1 1 Select Clock source 0 (programmed)(2) CKSEL0 0 Select Clock source 1 (unprogrammed)(2) Note: 1. The default value of SUT1:0 results in maximum start-up time. See table Start-up Times for the Internal Calibrated RC Oscillator Clock Selection in section Calibrated Internal RC Oscillator for details. 2. The default setting of CKSEL3:0 results in Internal RC Oscillator @ 1MHz. See table Device Clocking Options Select in section Clock Sources for details. The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. Related Links ATmega32A Boot Loader Parameters on page 323 Clock Sources on page 40 Calibrated Internal RC Oscillator on page 43 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 329 29.2.1. Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 29.3. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega32A the signature bytes are given in the following table. Table 29-5. Device and JTAG ID Part ATmega32A 29.4. Signature Bytes Address JTAG 0x000 0x001 0x002 Part Number Manufacture ID 0x1E 0x95 0x02 9502 0x1F Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega32A the signature bytes are given in the following table. Table 29-6. Device and JTAG ID Part ATmega32A 29.5. Signature Bytes Address JTAG 0x000 0x001 0x002 Part Number Manufacture ID 0x1E 0x96 0x02 9602 0x1F Calibration Byte The ATmega32A stores four different calibration values for the internal RC Oscillator. These bytes resides in the signature row High byte of the addresses 0x0000, 0x0001, 0x0002, and 0x0003 for 1, 2, 4, and 8MHz respectively. During Reset, the 1MHz value is automatically loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be loaded manually, see OSCCAL - Oscillator Calibration Register for details. Related Links OSCCAL on page 46 29.6. Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the device. Pulses are assumed to be at least 250ns unless otherwise noted. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 330 29.6.1. Signal Names In this section, some pins of this device are referenced by signal names describing their functionality during parallel programming, refer to the following figure and table Pin Name Mapping in this section. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 29-9. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 29-10. Figure 29-1. Parallel Programming +5V RDY/BS Y P D1 OE P D2 WR P D3 BS 1 P D4 XA0 P D5 XA1 P D6 PAGEL P D7 +12 V VCC +5V AVCC DATA PB7-PB0 RES ET BS 2 PA0 XTAL1 GND Table 29-7. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command OE PD2 I Output Enable (Active low) WR PD3 I Write Pulse (Active low) BS1 PD4 I Byte Select 1 ("0" selects Low byte, "1" selects High byte) XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program memory and EEPROM Data Page Load Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 331 Signal Name in Programming Mode Pin Name I/O Function BS2 PA0 I DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low) Byte Select 2 ("0" selects Low byte, "1" selects second High byte) Table 29-8. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 29-9. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1) 0 1 Load Data (High or Low data byte for Flash determined by BS1) 1 0 Load Command 1 1 No Action, Idle Table 29-10. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Table 29-11. Number of Words in a Page and number of Pages in the Flash Flash Size Page Size PCWORD Number of Pages PCPAGE PCMSB 16K words (32 Kbytes) 64 words PC[5:0] 256 PC[13:6] 13 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 332 Table 29-12. Number of Words in a Page and number of Pages in the EEPROM EEPROM Size Page Size PCWORD Number of Pages PCPAGE EEAMSB 1Kbyte 4 bytes EEA[1:0] 256 EEA[9:2] 9 29.7. Parallel Programming 29.7.1. Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. 2. 3. 4. Apply 4.5 - 5.5V between VCC and GND, and wait at least 100s. Set RESET to "0" and toggle XTAL1 at least 6 times Set the Prog_enable pins listed in Table 29-8 to "0000" and wait at least 100ns. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100ns after +12V has been applied to RESET, will cause the device to fail entering Programming mode. Note, if External Crystal or External RC configuration is selected, it may not be possible to apply qualified XTAL1 pulses. In such cases, the following algorithm should be followed: 1. 2. 3. 4. 5. 6. 29.7.2. Set Prog_enable pins listed in Table 29-8 to "0000". Apply 4.5 - 5.5V between VCC and GND simultaneously as 11.5 - 12.5V is applied to RESET. Wait 100s. Re-program the fuses to ensure that External Clock is selected as clock source (CKSEL3:0 = 0b0000). If Lock bits are programmed, a Chip Erase command must be executed before changing the fuses. Exit Programming mode by power the device down or by bringing RESET pin to 0b0. Entering Programming mode with the original algorithm, as described above. Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. * * * 29.7.3. The command needs only be loaded once when writing or reading multiple memory locations. Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256byte EEPROM. This consideration also applies to Signature bytes reading. Chip Erase The Chip Erase will erase the Flash, the SRAM and the EEPROM memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command "Chip Erase": 1. 2. 3. 4. Set XA1, XA0 to "10". This enables command loading. Set BS1 to "0". Set DATA to "1000 0000". This is the command for Chip Erase. Give XTAL1 a positive pulse. This loads the command. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 333 5. 6. 29.7.4. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. Wait until RDY/BSY goes high before loading a new command. Programming the Flash The Flash is organized in pages, see Table 29-10. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: Step A. Load Command "Write Flash". 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. Step B. Load Address Low Byte. 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. Step C. Load Data Low Byte. 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. Step D. Load Data High Byte. 1. Set BS1 to "1". This selects high data byte. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. Step E. Latch Data. 1. Set BS1 to "1". This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (Refer to the last figure in this section on programming the Flash waveforms.) Step F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in the following figure in this section. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. Step G. Load Address High byte. 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 334 4. Give XTAL1 a positive pulse. This loads the address high byte. Step H. Program Page. 1. Set BS1 = "0" 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3. Wait until RDY/BSY goes high (Refer to the last figure on programming the Flash waveforms in this section). Step I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. Step J. End Page Programming. 1. 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA to "0000 0000". This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 29-2. Addressing the Flash Which is Organized in Pages PROGRAM COUNTER PCMSB PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Note: PCPAGE and PCWORD are listed in Table 29-11. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 335 Figure 29-3. Programming the Flash Waveforms F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: "XX" is don't care. The letters refer to the programming description above. 29.7.5. Programming the EEPROM The EEPROM is organized in pages, see Table 29-12, in the Page Size section. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (For details on Command, Address and Data loading, refer to Programming the Flash): 1. 2. 3. 4. 5. 6. 7. Step A: Load Command "0001 0001". Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Step C: Load Data (0x00 - 0xFF). Step E: Latch data (give PAGEL a positive pulse). Step K:Repeat 3 through 5 until the entire buffer is filled. Step L: Program EEPROM page 7.1. Set BS1 to "0". 7.2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 7.3. Wait until to RDY/BSY goes high before programming the next page. Refer to the figure below for signal waveforms. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 336 Figure 29-4. Programming the EEPROM Waveforms K DATA A G B 0x11 ADDR. HIGH ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 29.7.6. Reading the Flash The algorithm for reading the Flash memory is as follows (Please refer to Programming the Flash in this chapter for details on Command and Address loading): 1. 2. 3. 4. 5. 6. 29.7.7. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. 5. 29.7.8. Step A: Load Command "0000 0011". Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. Set OE to "1". Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. 3. 4. 29.7.9. Step A: Load Command "0000 0010". Step G: Load Address High Byte (0x00 - 0xFF). Step B: Load Address Low Byte (0x00 - 0xFF). Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. Set BS1 to "1". The Flash word high byte can now be read at DATA. Set OE to "1". Step A: Load Command "0100 0000". Step C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Set BS1 and BS2 to "0". Give WR a negative pulse and wait for RDY/BSY to go high. Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 337 1. 2. 3. 4. 5. Step A: Load Command "0100 0000". Step C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. Set BS1 to "1" and BS2 to "0". This selects high data byte. Give WR a negative pulse and wait for RDY/BSY to go high. Set BS1 to "0". This selects low data byte. Figure 29-5. Programming the FUSES Waveforms Write Fuse Low byte A DATA 0x40 A C DATA Write Fuse high byte XX 0x40 C DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 29.7.10. Programming the Lock Bits The algorithm for programming the Lock bits is as follows (Please refer to Programming the Flash for details on Command and Data loading): 1. 2. Step A: Load Command "0010 0000". Step C: Load Data Low Byte. Bit n = "0" programs the Lock bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 29.7.11. Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (Please refer to Programming the Flash for details on Command loading): 1. 2. 3. Step A: Load Command "0000 0100". Set OE to "0", BS2 to "0", and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). Set OE to "0", BS2 to "1", and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 338 4. 5. Set OE to "0", BS2 to "0", and BS1 to "1". The status of the Lock Bits can now be read at DATA ("0" means programmed). Set OE to "1". Figure 29-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fus e low byte DATA 0 Lock bits 1 Fus e high byte 1 BS 1 BS 2 29.7.12. Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. Step A: Load Command "0000 1000". Step B: Load Address Low Byte (0x00 - 0x02). Set OE to "0", and BS1 to "0". The selected Signature byte can now be read at DATA. Set OE to "1". 29.7.13. Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (Please refer to Programming the Flash for details on Command and Address loading): 1. 2. 3. 4. Step A: Load Command "0000 1000". Step B: Load Address Low byte, (0x00 - 0x03). Set OE to "0", and BS1 to "1". The Calibration byte can now be read at DATA. Set OE to "1". 29.7.14. Parallel Programming Characteristics Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 Data & Contol (DATA, XA0/1, BS1, BS2) PAGEL tDVXH tXLDX tBVPH tPLBX t BVWL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 339 Figure 29-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in the first figure in this section (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 29-9. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in the first figure in this section (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 29-13. Parallel Programming Characteristics, VCC = 5V 10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 A tDVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 340 Symbol Parameter Min Typ Max Units tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low 0 1 s tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms tXLOL XTAL1 Low to OE Low 0 tBVDV BS1 Valid to DATA valid 0 tOLDV tOHDZ ns 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns Note: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands. 2. tWLRH_CE is valid for the Chip Erase command. 29.8. Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Note: The pin mapping for SPI programming is listed in the following section. Not all parts use the SPI pins dedicated for the internal SPI interface. 29.9. Serial Programming Pin Mapping Table 29-14. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB5 I Serial Data in MISO PB6 O Serial Data out SCK PB7 I Serial Clock Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 341 Figure 29-10. Serial Programming and Verify(1) +2.7 - 5.5V VCC MOS I PB5 MIS O PB6 S CK PB7 +2.7 - 5.5V (2) AVCC XTAL1 RES ET GND Note: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3 < AVCC < VCC + 0.3, however, AVCC should always be within 2.7 - 5.5V. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the Serial Clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz 29.9.1. Serial Programming Algorithm When writing serial data to the ATmega32A, data is clocked on the rising edge of SCK. When reading data from the ATmega32A, data is clocked on the falling edge of SCK. Please refer to the figure, Figure 29-11 in SPI Serial Programming Characteristics section for timing details. To program and verify the ATmega32A in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 29-16 Serial Programming Waveforms: 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 342 2. 3. 4. 5. 6. 7. 8. 9. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. Note: If other commands than polling (read) are applied before any write operation (FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. In a chip erased device, no 0xFFs in the data file(s) need to be programmed. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. At the end of the programming session, RESET can be set high to commence normal operation. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. 29.9.2. Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See table in next section for tWD_FLASH value. 29.9.3. Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See table below for tWD_EEPROM value. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 343 Table 29-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location, VCC = 5V 10% Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 4.5ms tWD_EEPROM 9ms tWD_ERASE 9ms Figure 29-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 29-16. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. Load Program Memory Page 0100 H000 00xx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program memory page at word address b. Data Low byte must be loaded before Data High byte is applied within the same address. Write Program Memory Page 0100 1100 00aa aaaa bbxx xxxx xxxx xxxx Write Program memory Page at address a:b. Read EEPROM Memory 1010 0000 00xx xxaa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. Write EEPROM Memory 1100 0000 00xx xxaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock Bits. "0" = programmed, "1" = unprogrammed. See Table 29-1 for details. Write Lock Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock Bits. Set bits = "0" to program Lock Bits. See Table Table 29-1 for details. Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 344 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 Operation Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 29-4 for details. Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = "0" to program, "1" to unprogram. See Table 29-3 for details. Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. "0" = programmed, "1" = unprogrammed. See table Table 29-4 for details. Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. "0" = programmed, "1" = unprogrammed. See table Table 29-3 for details. Read Calibration Byte 0011 1000 xxxx xxxx 0000 00bb oooo oooo Read Calibration Byte o at address b. Note: a = address high bits b = address low bits H = 0 - Low byte, 1 - High byte o = data out i = data in x = don't care 29.9.4. SPI Serial Programming Characteristics For characteristics of the SPI module, see SPI Timing Characteristics. Related Links SPI Timing Characteristics on page 365 29.10. Programming Via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers. 29.10.1. Programming Specific JTAG Instructions The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for Programming are listed below. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 345 The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in the figure below. Figure 29-12. State Machine Sequence for Changing the Instruction Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 29.10.2. AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 346 Register is selected as Data Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this chain is not latched. The active states are: * Shift-DR: The Reset Register is shifted by the TCK input. 29.10.3. PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-bit Programming Enable Register is selected as data register. The active states are the following: * * Shift-DR: the programming enable signature is shifted into the data register. Update-DR: the programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. 29.10.4. PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15bit Programming Command Register is selected as data register. The active states are the following: * * * * Capture-DR: the result of the previous command is loaded into the data register. Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. Update-DR: the programming command is applied to the Flash inputs. Run-Test/Idle: one clock cycle is generated, executing the applied command. 29.10.5. PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. The 1024-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically loaded into the Flash page one byte at a time. Note: 1. The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. 29.10.6. PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port. The 1032-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to the Shift Register. The data are automatically transferred from the Flash page buffer byte by byte in the Shift-DR state by an internal state machine. This is the only active state: * Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the TCK input. The TDI input is ignored. Note: 1. The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 347 29.10.7. Data Registers The data registers are selected by the JTAG instruction registers described in section Programming Specific JTAG Instructions. The data registers relevant for programming operations are: * * * * * Reset Register Programming Enable Register Programming Command Register Virtual Flash Page Load Register Virtual Flash Page Read Register 29.10.8. Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to Clock Sources) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in figure Reset Register. Related Links Clock Sources on page 40 Reset Register on page 289 29.10.9. Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The Register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 29-13. Programming Enable Register TDI D A T A $A370 = D Q P rogra mming e na ble ClockDR & P ROG_ENABLE TDO 29.10.10. Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 348 Programming Instruction Set is shown in the following table. The state machine sequence when shifting in the programming commands is illustrated in the last figure in this section. Figure 29-14. Programming Command Register TDI S T R O B E S Fla s h EEP ROM Fus e s Lock Bits A D D R E S S / D A T A TDO Table 29-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don't care Instruction TDI sequence TDO sequence 1a. Chip erase 0100011_10000000 0110001_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b. Poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2f. Latch Data 0110111_00000000 1110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx Notes (2) (9) (1) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 349 Instruction TDI sequence TDO sequence Notes 2g. Write Flash Page 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write complete 0110111_00000000 xxxxxox_xxxxxxxx 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110010_00000000 0110110_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0110111_00000000 xxxxxxx_oooooooo 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 1110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 0110001_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g. Poll for Page Write complete 0110011_00000000 xxxxxox_xxxxxxxx 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_oooooooo 6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4f. Write EEPROM Page (2) (9) low byte high byte (9) (1) (1) (2) (9) (3) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 350 Instruction TDI sequence TDO sequence Notes 6c. Write Fuse High byte 0110111_00000000 0110101_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse Low byte 0110011_00000000 0110001_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 6g. Poll for Fuse Write complete 0110011_00000000 xxxxxox_xxxxxxxx 7a. Enter Lock bit Write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock bits 0110011_00000000 0110001_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx 8a. Enter Fuse/Lock bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. Read Fuse High Byte(7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8d. Read Lock bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8e. Read Fuses and Lock bits 0111010_00000000 0111110_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo (5) fuse ext. byte 0110010_00000000 xxxxxxx_oooooooo fuse high byte 0110110_00000000 xxxxxxx_oooooooo fuse low byte 0110111_00000000 xxxxxxx_oooooooo lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo (2) (2) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 351 Instruction TDI sequence TDO sequence 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo Notes Note: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = "1". 3. Set bits to "0" to program the corresponding fuse, "1" to unprogram the Fuse. 4. Set bits to "0" to program the corresponding lock bit, "1" to leave the Lock bit unchanged. 5. "0" = programmed, "1" = unprogrammed. 6. The bit mapping for Fuses High byte is listed in Table 29-3 7. The bit mapping for Fuses Low byte is listed in Table 29-4 8. The bit mapping for Lock bits byte is listed in Table 29-1 9. Address bits exceeding PCMSB and EEAMSB (Table 29-10 and Table 29-11) are don't care Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 352 Figure 29-15. State Machine Sequence for Changing/Reading the Data Word 1 Te s t-Logic-Re s e t 0 0 Run-Te s t/Idle 1 S e le ct-DR S ca n 1 S e le ct-IR S ca n 0 0 1 1 Ca pture -DR Ca pture -IR 0 0 S hift-DR S hift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pa us e -DR 0 0 Pa us e -IR 1 1 0 Exit2-DR Exit2-IR 1 1 Upda te -DR 1 0 1 1 0 1 Upda te -IR 0 1 0 29.10.11. Virtual Flash Page Load Register The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to load the entire Flash page buffer before executing Page Write. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 353 Figure 29-16. Virtual Flash Page Load Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 29.10.12. Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte. The first eight cycles are used to transfer the first byte to the internal Shift Register, and the bits that are shifted out during these 8 cycles should be ignored. Following this initialization, data are shifted out starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 354 Figure 29-17. Virtual Flash Page Read Register S TROBES TDI S ta te ma chine ADDRES S Fla s h EEP ROM Fus e s Lock Bits D A T A TDO 29.10.13. Programming Algorithm All references below of type "1a", "1b", and so on, refer to Table 29-17. 29.10.14. Entering Programming Mode 1. 2. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 29.10.15. Leaving Programming Mode 1. 2. 3. 4. Enter JTAG instruction PROG_COMMANDS. Disable all programming instructions by using no operation instruction 11a. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming Enable Register. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 29.10.16. Performing Chip Erase 1. 2. 3. Enter JTAG instruction PROG_COMMANDS. Start chip erase using programming instruction 1a. Poll for chip erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to table Command Byte Bit Coding in section Parallel Programming Parameters, Pin Mapping, and Commands). Related Links Parallel Programming Characteristics on page 339 29.10.17. Programming the Flash Before programming the Flash a Chip Erase must be performed. See Performing Chip Erase. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 355 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable Flash write using programming instruction 2a. Load address high byte using programming instruction 2b. Load address low byte using programming instruction 2c. Load data using programming instructions 2d, 2e and 2f. Repeat steps 4 and 5 for all instruction words in the page. Write the page using programming instruction 2g. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable Flash write using programming instruction 2a. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 29-10) is used to address within one page and must be written as 0. Enter JTAG instruction PROG_PAGELOAD. Load the entire page by shifting in all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Enter JTAG instruction PROG_COMMANDS. Write the page using programming instruction 2g. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Repeat steps 3 to 8 until all data have been programmed. Related Links Parallel Programming Characteristics on page 339 29.10.18. Reading the Flash 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Flash read using programming instruction 3a. Load address using programming instructions 3b and 3c. Read data using programming instruction 3d. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Flash read using programming instruction 3a. Load the page address using programming instructions 3b and 3c. PCWORD (refer to table Command Byte Bit Coding in section Parallel Programming Parameters, Pin Mapping, and Commands) is used to address within one page and must be written as 0. Enter JTAG instruction PROG_PAGEREAD. Read the entire page by shifting out all instruction words in the page, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Remember that the first 8 bits shifted out should be ignored. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 356 6. 7. Enter JTAG instruction PROG_COMMANDS. Repeat steps 3 to 6 until all data have been read. Related Links Parallel Programming Characteristics on page 339 29.10.19. Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See Performing Chip Erase. 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter JTAG instruction PROG_COMMANDS. Enable EEPROM write using programming instruction 4a. Load address high byte using programming instruction 4b. Load address low byte using programming instruction 4c. Load data using programming instructions 4d and 4e. Repeat steps 4 and 5 for all data bytes in the page. Write the data using programming instruction 4f. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM Related Links Parallel Programming Characteristics on page 339 29.10.20. Reading the EEPROM 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable EEPROM read using programming instruction 5a. Load address using programming instructions 5b and 5c. Read data using programming instruction 5d. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM 29.10.21. Programming the Fuses 1. 2. 3. 4. 5. 6. 7. 8. Enter JTAG instruction PROG_COMMANDS. Enable Fuse write using programming instruction 6a. Load data high byte using programming instructions 6b. A bit value of "0" will program the corresponding fuse, a "1" will unprogram the fuse. Write high Fuse byte using programming instruction 6c. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Load data low byte using programming instructions 6e. A bit value of "0" will program the corresponding fuse, a "1" will unprogram the fuse. Write Fuse low byte using programming instruction 6f. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 357 Related Links Parallel Programming Characteristics on page 339 29.10.22. Programming the Lock Bits 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Lock bit write using programming instruction 7a. Load data using programming instructions 7b. A bit value of "0" will program the corresponding lock bit, a "1" will leave the lock bit unchanged. Write Lock bits using programming instruction 7c. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to table Parallel Programming Characteristics, VCC = 5V 10% in chapter Parallel Programming Characteristics). Related Links Parallel Programming Characteristics on page 339 29.10.23. Reading the Fuses and Lock Bits 1. 2. 3. Enter JTAG instruction PROG_COMMANDS. Enable Fuse/Lock bit read using programming instruction 8a. - To read all Fuses and Lock bits, use programming instruction 8e. - To only read Fuse high byte, use programming instruction 8b. - To only read Fuse low byte, use programming instruction 8c. - To only read Lock bits, use programming instruction 8d. 29.10.24. Reading the Signature Bytes 1. 2. 3. 4. 5. Enter JTAG instruction PROG_COMMANDS. Enable Signature byte read using programming instruction 9a. Load address 0x00 using programming instruction 9b. Read first signature byte using programming instruction 9c. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 29.10.25. Reading the Calibration Byte 1. 2. 3. 4. Enter JTAG instruction PROG_COMMANDS. Enable Calibration byte read using programming instruction 10a. Load address 0x00 using programming instruction 10b. Read the calibration byte using programming instruction 10c. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 358 30. Electrical Characteristics Table 30-1. Absolute Maximum Ratings* 30.1. Operating Temperature -55C to +125C Storage Temperature -65C to +150C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC +0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.0mA and 400.0mA TQFP/MLF *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Table 30-2. TA = -40C to 85C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min VIL Input Low Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V -0.5 0.2 VCC(1) V Input High Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6 VCC(2) VCC + 0.5 V VIL1 Input Low Voltage XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1 VCC(1) V VIH1 Input High Voltage XTAL 1 pin VCC = 2.7V - 5.5V 0.7 VCC(2) VCC + 0.5 V VIL2 Input Low Voltage RESET pin VCC = 2.7V - 5.5V -0.5 0.2 VCC VIH2 Input High Voltage RESET pin VCC = 2.7V - 5.5V 0.9 VCC(2) VCC + 0.5 V VIH Typ Max Units VCC = 4.5V - 5.5V VCC = 4.5V - 5.5V VCC = 4.5V - 5.5V Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 V 359 Symbol Parameter Condition Min Typ Max Units Output Low Voltage(3) (Ports A,B,C,D) IOL = 20mA, VCC = 5V 0.7 V IOL = 10mA, VCC = 3V 0.5 V Output High Voltage(4) (Ports A,B,C,D) IOH = -20mA, VCC = 5V 4.2 V IOH = -10mA, VCC = 3V 2.2 V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 A IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 A RRST Reset Pull-up Resistor 30 85 k Rpu I/O Pin Pull-up Resistor 20 50 k ICC Power Supply Current VOL VOH Power-down mode(5) VACIO IACLK Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current tACPD Analog Comparator Propagation Delay 60 Active 1MHz, VCC = 3V 0.6 mA Active 4MHz, VCC = 3V 2.1 5 mA Active 8MHz, VCC = 5V 7.5 15 mA Idle 1MHz, VCC = 3V 0.2 mA Idle 4MHz, VCC = 3V 0.6 2.5 mA Idle 8MHz, VCC = 5V 2.8 8 mA WDT enabled, VCC = 3V <10 20 A WDT disabled, VCC = 3V <1 10 A 40 mV 50 nA VCC = 5V Vin = VCC/2 VCC = 5V -50 Vin = VCC/2 VCC = 2.7V 750 VCC = 4.0V 500 ns Note: 1. "Max" means the highest value where the pin is guaranteed to be read as low 2. "Min" means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 3.1. 3.2. The sum of all IOL, for all ports, should not exceed 200mA. The sum of all IOL, for ports A0 - A7 should not exceed 100mA. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 360 3.3. The sum of all IOL, for ports B0 - B7, C0 - C7, D0 - D7 and XTAL2, should not exceed 100mA. TQFP and QFN/MLF Package: 4. 3.1. 3.2. 3.3. 3.4. 3.5. The sum of all IOL, for all ports, should not exceed 400 mA. The sum of all IOL, for ports A0 - A7, should not exceed 100 mA. The sum of all IOL, for ports B0 - B4, should not exceed 100 mA. The sum of all IOL, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 100 mA. The sum of all IOL, for ports D3 - D7, should not exceed 100 mA. 3.6. The sum of all IOL, for ports C0 - C7, should not exceed 100 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 4.1. 4.2. 4.3. The sum of all IOH, for all ports, should not exceed 200 mA. The sum of all IOH, for port A0 - A7, should not exceed 100 mA. The sum of all IOH, for ports B0 - B7,C0 - C7, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP and QFN/MLF Package: 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 5. The sum of all IOH, for all ports, should not exceed 400 mA. The sum of all IOH, for ports A0 - A7, should not exceed 100 mA. The sum of all IOH, for ports B0 - B4, should not exceed 100 mA. The sum of all IOH, for ports B3 - B7, XTAL2, D0 - D2, should not exceed 100 mA. The sum of all IOH, for ports D3 - D7, should not exceed 100 mA. The sum of all IOH, for ports C0 - C7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Minimum VCC for Power-down is 2.5V. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 361 30.2. Speed Grades Figure 30-1. Maximum Frequency vs. Vcc 16 MHz 8 MHz S a fe Ope ra ting Are a 2.7V 30.3. Clock Characteristics 30.3.1. External Clock Drive Waveforms 4.5V 5.5V Figure 30-2. External Clock Drive Waveforms VIH1 VIL1 30.3.2. External Clock Drive Table 30-3. External Clock Drive Symbol Parameter VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Units Min Max Min Max 8 0 16 1/tCLCL Oscillator Frequency 0 tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 s tCHCL Fall Time 1.6 0.5 s tCLCL Change in period from one clock cycle to the next 2 2 % Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 MHz 362 Table 30-4. External RC Oscillator, Typical Frequencies R [k](1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz Note: 1. R should be in the range 3k - 100k, and C should be at least 20pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 30.4. System and Reset Characteristics Table 30-5. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter VPOT Min Typ Max Units Power-on Reset Threshold Voltage (rising)(1) 1.4 2.3 V Power-on Reset Threshold Voltage (falling) 1.3 2.3 V 0.9 VCC 1.5 s V VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VBOT Brown-out Reset Threshold Voltage(2) tBOD Condition 0.2 BODLEVEL = 1 2.5 2.7 2.9 BODLEVEL = 0 3.6 4.0 4.2 Minimum low voltage period for Brown-out Detection BODLEVEL = 1 2 s BODLEVEL = 0 2 s 50 mV VHYST Brown-out Detector hysteresis VBG Bandgap reference voltage tBG Bandgap reference start-up time 40 IBG Bandgap reference current consumption 10 1.15 1.23 1.35 V 70 s s Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling). 2. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 and BODLEVEL = 0 for ATmega32A. 30.5. Two-wire Serial Interface Characteristics The table below describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega32A Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 30-3. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 363 Table 30-6. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units V VIL Input Low-voltage -0.5 0.3VCC VIH Input High-voltage 0.7VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05VCC(2) - V VOL(1) Output Low-voltage 0 0.4 V tr(1) Rise Time for both SDA and SCL tof(1) Output Fall Time from VIHmin to VILmax tSP(1) Spikes Suppressed by Input Filter Ii Input Current each I/O Pin Ci(1) Capacitance for each I/O Pin fSCL SCL Clock Frequency Rp Value of Pull-up resistor tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO Hold Time (repeated) START Condition Low Period of the SCL Clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data setup time Setup time for STOP condition 3mA sink current 10pF < Cb < 400pF(3) 20 + 0.1Cb(3)(2) 300 ns 20 + 0.1Cb(3)(2) 250 ns 0 50(2) ns -10 10 A - 10 pF fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz fSCL 100kHz 1000ns fSCL > 100kHz CC - 0.4V 3mA 0.1VCC < Vi < 0.9VCC fSCL 100kHz CC - 0.4V 3mA 4.0 300ns - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 0 3.45 s fSCL > 100kHz 0 0.9 s fSCL 100kHz 250 - ns fSCL > 100kHz 100 - ns fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 364 Symbol Parameter Condition Min Max Units tBUF fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s Bus free time between a STOP and START condition Note: 1. In ATmega32A, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega32A Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. Figure 30-3. Two-wire Serial Bus Timing tof tHIGH tLOW tr tLOW S CL tS U;S TA tHD;S TA tHD;DAT tS U;DAT tS U;S TO S DA tBUF 30.6. SPI Timing Characteristics See figures below for details. Table 30-7. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 22-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 * tSCK 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 * tck 11 SCK high/low(1) Slave 2 * tck 12 Rise/Fall time Slave ns 1.6 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 s 365 Description Mode Min 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Slave Typ Max 15 ns 20 10 2 * tck Figure 30-4. SPI interface timing requirements (Master Mode) SS 6 1 S CK (CP OL = 0) 2 2 S CK (CP OL = 1) 4 MIS O (Da ta Input) 5 3 MS B ... LS B 8 7 MOS I (Da ta Output) MS B ... LS B SPI interface timing requirements (Slave Mode) 18 SS 10 9 16 S CK (CP OL = 0) 11 11 S CK (CP OL = 1) 13 MOS I (Da ta Input) 14 12 MS B ... LS B 17 15 MIS O (Da ta Output) MS B ... LS B X Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 366 30.7. ADC Characteristics Table 30-8. ADC Characteristics Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Absolute accuracy (Including INL, DNL, Quantization Error, Gain, and Offset Error) Single Ended Conversion 1.5 LSB 3 LSB 1.5 LSB 3 LSB 0.75 LSB 0.25 LSB 0.75 LSB 0.75 LSB VREF = 4V, VCC = 4V ADC clock = 200kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Noise Reduction mode Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz Noise Reduction mode Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Gain Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Offset Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Conversion Time 13 260 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 s 367 Symbol Parameter Condition Min Typ Max Units Clock Frequency 50 1000 kHz AVCC Analog Analog Supply Voltage VCC 0.3(1) VCC + 0.3(2) V VREF Reference Voltage 2.0 AVCC V VIN Input voltage GND VREF V ADC conversion output 0 1023 LSB Input bandwidth 2.3 38.5 kHz 2.56 2.7 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M Typ Max Units Note: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Table 30-9. ADC Characteristics Symbol Parameter Resolution Absolute Accuracy Condition Min Gain = 1x 10 Bits Gain = 10x 10 Bits Gain = 200x 10 Bits Gain = 1x 17 LSB 16 LSB 7 LSB VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 368 Symbol Parameter Condition Typ Max Units 0.75 LSB 0.75 LSB 2 LSB Gain = 1x 1.6 % Gain = 10x 1.5 % Gain = 200x 0.2 % Gain = 1x 1 LSB 1.5 LSB 4.5 LSB Integral Non-linearity (INL) Gain = 1x (Accuracy after calibration for Offset and Gain Error) VREF = 4V, VCC = 5V Min ADC clock = 50 - 200kHz Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain Error Offset Error VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain = 10x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Gain = 200x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz Conversion Time 65 260 s Clock Frequency 50 200 kHz AVCC Analog Analog Supply Voltage VCC - 0.3(1) VCC + 0.3(2) V VREF Reference Voltage 2.0 AVCC - 0.5 V VIN Input voltage GND AVCC V VDIFF Input differential voltage -VREF/Gain VREF/Gain V ADC conversion output -511 511 LSB Input bandwidth VINT Internal Voltage Reference 2.3 4 kHz 2.56 2.7 V Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 369 Symbol Parameter Condition Min Typ Max Units RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M Note: 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 370 31. Typical Characteristics Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 31-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 1.6 ICC (mA) 31.1. 1.4 5.5 V 1.2 5.0 V 1 4.5 V 0.8 4.0 V 3.6 V 3.3 V 0.6 2.7 V 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 371 Figure 31-2. Active Supply Current vs. Frequency (1 - 16MHz) ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 -16 MHz ICC (mA) 18 16 5.5V 14 5.0V 12 4.5V 10 4.0V 8 3.6V 6 3.3V 4 2.7V 2 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 31-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 12 25 C 10 85 C -40 C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 372 Figure 31-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 6 25 C 85 C 5 -40 C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-5. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ACTIVE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 1.6 25 C 85 C 1.4 -40 C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 373 Figure 31-6. Active Supply Current vs. VCC (External Oscillator, 32kHz) ACTIVE S UP P LY CURRENT vs . VCC EXTERNAL OS CILLATOR, 32 kHz 160 25 C 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 31-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz 0.7 0.6 5.5 V 0.5 ICC (mA) 31.2. 5.0 V 0.4 4.5 V 4.0 V 3.6 V 3.3 V 0.3 0.2 2.7 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 374 Figure 31-8. Idle Supply Current vs. Frequency (1 MHz - 16 MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 16 MHz 8 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 2.7V 1 3.3V 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Figure 31-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 8 MHz 5 -40 C 25 C 85 C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 375 Figure 31-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 4 MHz 2.5 -40 C 25 C 85 C ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OS CILLATOR, 1 MHz 0.8 0.7 85 C 0.6 25 C -40 C ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 376 Figure 31-12. Idle Supply Current vs. VCC (External Oscillator, 32kHz) IDLE S UP P LY CURRENT vs . VCC EXTERNAL OS CILLATOR, 32 kHz 40 35 25 C 30 ICC (uA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 31-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 2 85 C 1.6 -40 C 1.2 ICC (uA) 31.3. 25 C 0.8 0.4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 377 Figure 31-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VCC WATCHDOG TIMER ENABLED 20 85 C -40 C 25 C 16 ICC (uA) 12 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply current Figure 31-15. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) P OWER-S AVE S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 20 25 C 16 12 ICC (uA) 31.4. 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 378 31.5. Standby Supply Current Figure 31-16. Standby Supply Current vs. VCC (WDT Disabled) S TANDBY S UP P LY CURRENT vs . VCC WATCHDOG TIMER DIS ABLED 0.16 6MHz_xta l 6MHz_re s 0.14 0.12 4MHz_re s 4MHz_xta l ICC (mA) 0.1 0.08 2MHz_re s 2MHz_xta l 450kHz_re s 1MHz_re s 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 31-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE VCC = 5V 140 120 25 C 100 IOP (uA) 31.6. 85 C -40 C 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 379 Figure 31-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE VCC = 2.7V 70 25 C -40 C 60 85 C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 31-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE VCC = 5V 100 IRES ET (uA) 80 60 40 20 -40 C 25 C 85 C 0 0 1 2 3 4 5 6 VRES ET(V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 380 Figure 31-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE VCC = 2.7V 60 50 IRES ET (uA) 40 30 20 10 -40 C 0 25 C 85 C 0 0.5 1 1.5 2 2.5 3 VRES ET(V) Pin Driver Strength Figure 31-21. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE VCC = 5V 80 70 25 C 60 -40 C 85 C 50 IOH (mA) 31.7. 40 30 20 10 0 3 3.4 3.8 4.2 4.6 5 VOH (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 381 Figure 31-22. I/O Pin Source Current vs. Output Voltage (VCC = 3V) I/O P IN S OURCE CURRENT vs . OUTP UT VOLTAGE VCC = 3V 35 -40 C 25 C 30 85 C IOH (mA) 25 20 15 10 5 0 1 1.5 2 2.5 3 VOH (V) Figure 31-23. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE VCC = 5V 90 -40 C 80 25 C 70 85 C IOL (mA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 VOL (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 382 Figure 31-24. I/O Pin Sink Current vs. Output Voltage (VCC = 3V) I/O P IN S INK CURRENT vs . OUTP UT VOLTAGE VCC = 3V IOL (mA) 45 40 -40 C 35 25 C 30 85 C 25 20 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Pin Thresholds and Hysteresis Figure 31-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as "1") I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 3 85 C 25 C 2.5 -40 C 2 Thre s hold (V) 31.8. 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 383 Figure 31-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as "0") I/O P IN INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.5 85 C 25 C -40 C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-27. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . VCC 0.6 -40 C 25 C Input Hys te re s is (mV) 85 C 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 384 Figure 31-28. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as "1") RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIH, IO P IN READ AS '1' 2.5 Thre s hold (V) 2 -40 C 1.5 25 C 85 C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-29. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as "0") RES ET INP UT THRES HOLD VOLTAGE vs . VCC VIL, IO P IN READ AS '0' 2.5 85 C 25 C -40 C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 385 Figure 31-30. Reset Input Pin Hysteresis vs. VCC RES ET P IN INP UT HYS TERES IS vs . VCC 0.5 Input Hys te re s is (mV) 0.4 0.3 -40 C 0.2 25 C 0.1 85 C 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 31-31. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 4.0 V 4.1 Ris ing VCC 4 Thre s hold (V) 31.9. 3.9 Fa lling VCC 3.8 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture (C) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 386 Figure 31-32. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRES HOLDS vs . TEMP ERATURE BOD LEVEL IS 2.7 V 2.9 Ris ing VCC Thre s hold (V) 2.8 2.7 Fa lling VCC 2.6 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture (C) Figure 31-33. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs . VCC 1.25 1.248 Ba ndga p Volta ge (V) 1.246 1.244 1.242 1.24 25 C 1.238 85 C 1.236 -40 C 1.234 1.232 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 387 31.10. Internal Oscillator Speed Figure 31-34. Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . VCC 1320 -40 C 25 C 1300 1280 85 C F RC (kHz) 1260 1240 1220 1200 1180 1160 1140 1120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-35. Calibrated 8MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.5 8.3 8.1 F RC (MHz) 7.9 5.5 5.0 4.5 4.0 7.7 7.5 7.3 V V V V 3.6 V 3.3 V 7.1 6.9 2.7 V 6.7 6.5 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 388 Figure 31-36. Calibrated 8MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . VCC 9 8.5 -40 C 25 C F RC (MHz) 8 85 C 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-37. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 16 -40 C 14 25 C 85 C 12 F RC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 389 Figure 31-38. Calibrated 4MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 4.2 4.1 F RC (MHz) 4 5.5 5.0 4.5 4.0 3.9 3.8 V V V V 3.6 V 3.3 V 3.7 2.7 V 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Figure 31-39. Calibrated 4MHz RC Oscillator Frequency vs. VCC CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . VCC 4.2 -40 C 4.1 25 C F RC (MHz) 4 85 C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 390 Figure 31-40. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 8 7 -40 C 25 C 6 85 C F RC (MHz) 5 4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Figure 31-41. Calibrated 2MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 2.1 2.05 F RC (MHz) 2 5.5 5.0 4.5 4.0 3.6 3.3 1.95 1.9 V V V V V V 1.85 2.7 V 1.8 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 391 Figure 31-42. Calibrated 2MHz RC Oscillator Frequency vs. VCC CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . VCC 2.1 -40 C 25 C 2 F RC (MHz) 85 C 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-43. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 4 -40 C 3.5 25 C 85 C 3 F RC (MHz) 2.5 2 1.5 1 0.5 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 392 Figure 31-44. Calibrated 1MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 1.04 1.02 F RC (MHz) 1 5.5 5.0 4.5 4.0 3.6 3.3 0.98 0.96 V V V V V V 0.94 2.7 V 0.92 -60 -40 -20 0 20 40 60 80 100 Te mpe ra ture Figure 31-45. Calibrated 1MHz RC Oscillator Frequency vs. VCC CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . VCC 1.04 1.02 -40 C 25 C F RC (MHz) 1 85 C 0.98 0.96 0.94 0.92 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 393 Figure 31-46. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1 MHz RC OS CILLATOR FREQUENCY vs . OS CCAL VALUE 2 -40 C 25 C 85 C 1,8 1,6 F RC (MHz) 1,4 1,2 1 0,8 0,6 0,4 0,2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) 31.11. Current Consumption of Peripheral Units Figure 31-47. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs . VCC 20 -40 C 25 C 18 16 85 C 14 ICC (uA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 394 Figure 31-48. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs . V CC AREF = AVCC 350 85 C 25 C 300 -40 C ICC (uA) 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-49. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs . VCC 200 85 C 25 C -40 C ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 395 Figure 31-50. Analog Comparator Current vs. VCC ANALOG COMP ARATOR CURRENT vs . VCC 100 90 80 85 C ICC (uA) 70 25 C -40 C 60 50 40 30 20 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 31-51. Programming Current vs. VCC P ROGRAMMING CURRENT vs . VCC 9 8 -40 C 7 25 C ICC (mA) 6 85 C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 396 31.12. Current Consumption in Reset and Reset Pulsewidth Figure 31-52. Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) RES ET S UP P LY CURRENT vs . VCC EXCLUDING CURRENT THROUGH THE RES ET P ULLUP 3 2.5 5.5 V 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 3.6 V 3.3 V 1 2.7 V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 31-53. Reset Supply Current vs. Frequency (1 - 16MHz, Excluding Current Through The Reset Pull-up) RES ET S UP P LY CURRENT vs . V CC EXCLUDING CURRENT THROUGH THE RES ET P ULLUP 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 4.0V 8 3.6V 6 3.3V 4 2.7V 2 0 0 2 4 6 8 10 12 14 16 Fre que ncy (MHz) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 397 Figure 31-54. Minimum Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs . VCC 800 700 P uls e width (ns ) 600 500 400 85 C 25 C -40 C 300 200 100 0 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 398 32. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F (0x5F) SREG I T H S V N Z C 0x3E (0x5E) SPH - - - - SP11 SP10 SP9 SP8 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0x3C (0x5C) OCR0 0x3B (0x5B) GICR INT1 INT0 INT2 - - - IVSEL IVCE 0x3A (0x5A) GIFR INTF1 INTF0 INTF2 - - - - - TOIE0 Timer/Counter0 Output Compare Register 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 0x37 (0x57) SPMCR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 0x34 (0x54) MCUCSR JTD ISC2 - JTRF WDRF BORF EXTRF PORF 0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) OSCCAL Oscillator Calibration Register ACME PUD PSR2 PSR10 0x31 (0x51) OCDR On-Chip Debug Register 0x30 (0x50) SFIOR ADTS2 ADTS1 ADTS0 - 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 0x2E (0x4E) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 CS21 CS20 0x2D (0x4D) TCNT1H 0x2C (0x4C) TCNT1L Timer/Counter1 - Counter Register High byte Timer/Counter1 - Counter Register Low byte 0x2B (0x4B) OCR1AH Timer/Counter1 - Output Compare Register A High byte 0x2A (0x4A) OCR1AL Timer/Counter1 - Output Compare Register A Low byte 0x29 (0x49) OCR1BH Timer/Counter1 - Output Compare Register B High byte 0x28 (0x48) OCR1BL Timer/Counter1 - Output Compare Register B Low byte 0x27 (0x47) ICR1H Timer/Counter1 - Input Capture Register High byte 0x26 (0x46) ICR1L Timer/Counter1 - Input Capture Register Low byte 0x25 (0x45) TCCR2 0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register FOC2 WGM20 COM21 COM20 WGM21 CS22 0x22 (0x42) ASSR - - - - AS2 TCN2UB OCR2UB TCR2UB 0x21 (0x41) WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 0x20(1) UBRRH URSEL - - - (0x40)(1) UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 0x1F (0x3F) EEARH - - - - - - EEAR9 EEAR8 UBRR[11:8] 0x1E (0x3E) EEARL 0x1D (0x3D) EEDR EEPROM Address Register Low Byte 0x1C (0x3C) EECR - - - - EERIE EEMWE EEWE EERE 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 EEPROM Data Register Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 399 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x10 (0x30) PIND 0x0F (0x2F) SPDR 0x0E (0x2E) SPSR SPIF WCOL - - - - - SPI2X 0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 0x0C (0x2C) UDR 0x0B (0x2B) UCSRA RXC TXC UDRE 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE 0x09 (0x29) UBRRL SPI Data Register USART I/O Data Register FE DOR PE U2X MPCM RXEN TXEN UCSZ2 RXB8 TXB8 ACIS0 USART Baud Rate Register Low byte 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 0x05 (0x25) ADCH 0x04 (0x24) ADCL ADC Data Register High byte ADC Data Register Low byte 0x03 (0x23) TWDR Two-wire Serial Interface Data Register 0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register Note: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 400 33. Instruction Set Summary ARITHMETIC AND LOGIC INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks RJMP k Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 IJMP JMP(1) k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC + k + 1 None 3 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 401 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks Indirect Call to (Z) PC Z None 3 Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N A V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N A V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 402 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0:6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3:0)Rd(7:4),Rd(7:4)Rd(3:0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 CLH Clear Half Carry Flag in SREG H0 H 1 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks MOV Rd, Rr Move Between Registers Rd Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 403 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST - Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (Z) R1:R0 None - SPM IN Rd, P In Port Rd P None 1 OUT P, Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 404 MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Note: 1. Instruction not available in all devices. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 405 34. Packaging Information 34.1. 44-pin TQFP P IN 1 IDENTIFIER P IN 1 B e E1 E A1 A2 D1 D C 0~7 L A COMMON DIMENS IONS (Unit of Me a s ure = mm) MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 S YMBOL Note s : 1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. 2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum pla s tic body s ize dime ns ions including mold mis ma tch. 3. Le a d copla na rity is 0.10mm ma ximum. A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 0.37 0.45 C 0.09 (0.17) 0.20 L 0.45 0.60 0.75 e NOTE Note 2 Note 2 0.80 TYP 06/02/2014 44A, 44-le a d, 10 x 10mm body s ize , 1.0mm body thickne s s , 0.8 mm le a d pitch, thin profile pla s tic qua d fla t pa cka ge (TQFP ) 44A Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 C 406 34.2. 40-pin PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0 ~ 15 C COMMON DIMENSIONS (Unit of Measure = mm) REF eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). SYMBOL MIN NOM MAX A - - 4.826 A1 0.381 - - D 52.070 - 52.578 E 15.240 - 15.875 E1 13.462 - 13.970 B 0.356 - 0.559 B1 1.041 - 1.651 L 3.048 - 3.556 C 0.203 - 0.381 eB 15.494 - 17.526 e NOTE Note 2 Note 2 2.540 TYP 13/02/2014 40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual Inline Package (PDIP) C 40P6 Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 407 34.3. 44-pin VQFN D Marked Pin# 1 I D E SE ATING PLANE A1 TOP VIEW A3 A K L Pin #1 Co rne r D2 1 2 3 Option A SIDE VIEW Pin #1 Triangl e COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A 0.80 0.90 1.00 A1 - 0.02 0.05 SYMBOL E2 Option B K Option C b e Pin #1 Cham fe r (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW A3 0.20 REF b 0.18 0.23 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note : JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 . NOTE 0.30 0.50 BSC L 0.59 0.64 0.69 K 0.20 0.26 0.41 9/26/08 Package Drawing Contact: avr@atmel.com TITLE 44M1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (VQFN) GPC ZWS DRAWING NO. REV. 44M1 H Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 408 35. Errata 35.1. ATmega32A, rev. J to rev. K * * * * First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround 2. When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround 3. Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround * * 4. If ATmega32A is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega32A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega32A while reading the Device ID Registers of preceding devices of the boundary scan chain. * If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega32A must be the fist device in the chain. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 409 Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. 35.2. ATmega32A, rev. G to rev. I * * * * First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround 2. When the device has been powered or reset, disable then enable the Analog Comparator before the first conversion. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Workaround 3. Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega32A is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega32A by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega32A while reading the Device ID Registers of preceding devices of the boundary scan chain. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 410 - 4. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega32A must be the fist device in the chain. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 411 36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section refers to the document revision. 36.1. 8155I - 08/2016 1. 36.2. 8155H - 08/2016 1. 2. 3. 36.3. Updated the Features with Capacitive touch sensing capability. Added Errata: ATmega32A, rev. J to rev. K. 8155D - 10/2013 1. 36.7. New workflow used for the publication. 8155E - 02/2014 1. 2. 36.6. Updated the pinout. New AVR MCU Core drawing added. 8155F - 08/2015 1. 36.5. Updated TQFP (44-pins) pinout drawing: - Pin 42 changed to PB2 (AIN0/INT2) instead of PB2 (AIN0/T2) - Swapped the pin position of XTAL2 and XTAL1: XTAL2 on the pin 7 and XTAL1 on the pin 8 Updated PDIP (40-pins) pinout drawing: - Pin 32 changed to PB2 (AIN0/INT2) instead of PB2 (AIN0/T2) - Swapped the pin position of XTAL2 and XTAL1: XTAL2 on the pin 12 and XTAL1 on the pin 13 Removed the table note from the Table 25-1 Analog Comparator Multiplexed Input 8155G - 10/2015 1. 2. 36.4. Configuration Summary: Pin count and GPIO numbers updated. Added nominal values for symbol B, C and L in the TQFP-44 package drawing, 44-pin TQFP. 8155C - 02/2011 1. 2. 3. 4. 5. Updated the datasheet according to the Atmel new brand style guide (new logo, last page, etc). Inserted note in Performing Page Erase by SPM. Note 6 and Note 7 below Table 30-6 have been removed. Updated Ordering Information to include Tape & Reel and 105C devices. Updated all Typical Characteristics. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 412 36.8. 8155B - 07/2009 1. 2. 36.9. Updated Errata. Updated the last page with Atmel's new addresses. 8155A - 06/2008 1. Initial revision (Based on the ATmega32/L datasheet 2503N-AVR-06/08) Changes done compared ATmega32/L datasheet 2503N-AVR-06/08: - - - - - - Updated description in Stack Pointer. All Electrical characteristics is moved to Electrical Characteristics. Register descriptions are moved to sub sections at the end of each chapter. Test limits of Reset Pull-up Resistor (RRST) in DC Characteristics. New graphs in Typical Characteristics. New Ordering Information. Atmel ATmega32A [DATASHEET] Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 413 Atmel Corporation (c) 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2016 Atmel Corporation. / Rev.: Atmel-8155I-ATmega32A_Datasheet_Complete-08/2016 (R) (R) (R) Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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