MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow Power Consumption
− Active Mode: 200 μA at 1 MHz, 2.2 V
− Standby Mode: 0.7 μA
− Off Mode (RAM Retention): 0.1 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in
Less Than 6 μs
DFrequency-Locked Loop (FLL+)
D16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
D16-Bit Timer_A With Three or Five†
Capture/Compare Registers
DIntegrated LCD Driver for 96 Segments
DOn-Chip Comparator
DBrownout Detector
DSupply Voltage Supervisor/Monitor −
Programmable Level Detection on
MSP430F415/417 Devices Only
† Timer_A5 in ’F415 and ’F417 devices only
DSerial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by Security
Fuse
DBootstrap Loader in Flash Devices
DFamily Members Include:
− MSP430C412: 4KB ROM, 256B RAM
− MSP430C413: 8KB ROM, 256B RAM
− MSP430F412: 4KB + 256B Flash
256B RAM
− MSP430F413: 8KB + 256B Flash
256B RAM
− MSP430F415: 16KB + 256B Flash
512B RAM
− MSP430F417: 32KB + 256B Flash
1KB RAM
DAvailable in 64-Pin QFP (PM) and
64-Pin QFN (RTD/RGC) Packages
DFor Complete Module Descriptions,See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
The MSP430x41x series are microcontroller configurations with one or two built-in 16-bit timers, a comparator,
96 LCD segment drive capability, and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process the data and transmit them to a host system. The comparator and timer make the configurations ideal
for industrial meters, counter applications, handheld meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
T
PACKAGED DEVICES
TAPLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD/RGC)
−40°C to 85°C
MSP430C412IPM
MSP430C413IPM
MSP430F412IPM
MSP430F413IPM
MSP430F415IPM
MSP430F417IPM
MSP430C412IRGC
MSP430C413IRGC
MSP430F412IRTD
MSP430F413IRTD
MSP430F415IRTD
MSP430F417IRTD
pin designation − MSP430x412, MSP430x413
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.5/TACLK/ACLK
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/SVSOUT
P1.4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
P3.7/S10
P3.6/S11
P3.5/S12
P3.4/S13
P3.3/S14
P3.2/S15
P3.1/S16
P3.0/S17
P2.7/S18
P2.6/CAOUT/S19
P2.5/S20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/S23
P2.4/S21
P2.3/S22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
NC
NC
P5.1/S0
P5.0/S1
P4.7/S2
P4.5/S4
P4.6/S3
MSP430x412
NC − No internal connection. External connection to VSS recommended.
MSP430x413
DVCC
AVSS
AVCC
DVSS
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation − MSP430x415, MSP430x417
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.5/TA0CLK/ACLK
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0.0
P1.1/TA0.0/MCLK
P1.2/TA0.1
P1.3/TA1.0/SVSOUT
P1.4/TA1.0
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
P3.7/S10
P3.6/S11
P3.5/S12
P3.4/S13
P3.3/S14
P3.2/S15
P3.1/S16
P3.0/S17
P2.7/S18
P2.6/CAOUT/S19
P2.5/TA1CLK/S20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.6/CA0
P1.7/CA1
P2.0/TA0.2
P2.1/TA1.1
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/TA1.2/S23
P2.4/TA1.4/S21
P2.3/TA1.3/S22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
NC
P5.1/S0
P5.0/S1
P4.7/S2
P4.5/S4
P4.6/S3
MSP430x415
NC − No internal connection. External connection to VSS recommended.
MSP430x417
AVSS2
DVCC
AVSS1
AVCC
DVSS
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram − MSP430x412, MSP430x413
Comparator_
A
DVCC DVSS AVCC AVSS
RST/NMI
P2
Flash−F41x
ROM−C41x
8KB
4KB
RAM
256B
Watchdog
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
96
Segments
1,2,3,4 MUX
fLCD
8
Oscillators
FLL+
MCLK
8 MHz
CPU
incl. 16
Registers
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
P3
Port 3
8 I/O
8
Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Emulation
Module
(F versions
only)
functional block diagram − MSP430x415, MSP430x417
Comparator
_A
DVCC DVSS AVCC AVSS
RST/NMI
P2
Flash
32KB
16KB
RAM
1KB
512B
Watchdog
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
96
Segments
1,2,3,4 MUX
fLCD
8
Oscillators
FLL+
MCLK
8 MHz
CPU
incl. 16
Registers
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
P3
Port 3
8 I/O
8
Timer0_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P5
Port 5
8 I/O
8
P6
Port 6
6 I/O
8
P4
Port 4
8 I/O
8
Timer1_A5
5 CC Reg
Emulation
Module
(F versions
only)
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions − MSP430x412, MSP430x413
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
AVCC 64 Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive
divider circuitry; must not power up prior to DVCC.
AVSS 62 Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally
connected to DVSS.
DVCC 1 Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
NC 7, 10, 11 Not internally connected. Connection to VSS recommended.
P1.0/TA0 53 I/O General-purpose digital I/O / Timer_A, Capture: CCI0A input, compare: Out0 output/BSL transmit
P1.1/TA0/MCLK 52 I/O General-purpose digital I/O / Timer_A, Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive.
P1.2/TA1 51 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.3/SVSOUT 50 I/O General-purpose digital I/O / SVS: output of SVS comparator
P1.4 49 I/O General-purpose digital I/O
P1.5/TACLK/ ACLK 48 I/O General-purpose digital I/O / Input of Timer_A clock/output of ACLK
P1.6/CA0 47 I/O General-purpose digital I/O / Comparator_A input
P1.7/CA1 46 I/O General-purpose digital I/O / Comparator_A input
P2.0/TA2 45 I/O General-purpose digital I/O / Timer_A capture: CCI2A input, compare: Out2 output
P2.1 44 I/O General-purpose digital I/O
P2.2/S23 35 I/O General-purpose digital I/O / LCD segment output 23 (see Note 1)
P2.3/S22 34 I/O General-purpose digital I/O / LCD segment output 22 (see Note 1)
P2.4/S21 33 I/O General-purpose digital I/O / LCD segment output 21 (see Note 1)
P2.5/S20 32 I/O General-purpose digital I/O / LCD segment output 20 (see Note 1)
P2.6/CAOUT/S19 31 I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1)
P2.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 (see Note 1)
P3.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 (see Note 1)
P3.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 (see Note 1)
P3.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 (see Note 1)
P3.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 (see Note 1)
P3.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 (see Note 1)
P3.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 (see Note 1)
P3.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 (see Note 1)
P3.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 (see Note 1)
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions − MSP430x412, MSP430x413 (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
P4.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 (see Note 1)
P4.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 (see Note 1)
P4.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 (see Note 1)
P4.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 (see Note 1)
P4.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 (see Note 1)
P4.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 (see Note 1)
P4.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 (see Note 1)
P4.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 (see Note 1)
P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1 (see Note 1)
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0 (see Note 1)
COM0 36 O Common output. COM0−3 are used for LCD backplanes
P5.2/COM1 37 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.
P5.3/COM2 38 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.
P5.4/COM3 39 I/O General-purpose digital I/O / Common output. COM0−3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 41 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 42 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33 43 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)
P6.0 59 I/O General-purpose digital I/O
P6.1 60 I/O General-purpose digital I/O
P6.2 61 I/O General-purpose digital I/O
P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O General-purpose digital I/O
P6.7 6 I/O General-purpose digital I/O
RST/NMI 58 I Reset input / Nonmaskable interrupt input
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
TDI/TCLK 55 I Test data input / Test clock input. The device protection fuse is connected to TDI.
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1.
QFN Pad NA NA QFN package pad connection to VSS recommended.
NOTE 2: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions − MSP430x415, MSP430x417
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
AVCC 64 Positive terminal that supplies SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive
divider circuitry; must not power up prior to DVCC.
AVSS1 62 Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally
connected to DVSS.
DVCC 1 Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC.
DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
AVSS2 10 Negative terminal that supplies SVS, brownout, oscillator, comparator_A. Needs to be externally
connected to DVSS.
NC 7, 11 Not internally connected. Connection to VSS recommended.
P1.0/TA0.0 53 I/O General-purpose digital I/O / Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit
P1.1/TA0.0/MCLK 52 I/O General-purpose digital I/O / Timer0_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive
P1.2/TA0.1 51 I/O General-purpose digital I/O / Timer0_A, capture: CCI1A input, compare: Out1 output
P1.3/TA1.0/
SVSOUT 50 I/O General-purpose digital I/O / Timer1_A, capture: CCI0B input/SVS: output of SVS comparator
P1.4/TA1.0 49 I/O General-purpose digital I/O / Timer1_A, capture: CCI0A input, compare: Out0 output
P1.5/TA0CLK/
ACLK 48 I/O General-purpose digital I/O / input of Timer0_A clock/output of ACLK
P1.6/CA0 47 I/O General-purpose digital I/O / Comparator_A input
P1.7/CA1 46 I/O General-purpose digital I/O / Comparator_A input
P2.0/TA0.2 45 I/O General-purpose digital I/O / Timer0_A capture: CCI2A input, compare: Out2 output
P2.1/TA1.1 44 I/O General-purpose digital I/O / Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/TA1.2/S23 35 I/O General-purpose digital I/O / Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment
output 23 (see Note 1)
P2.3/TA1.3/S22 34 I/O General-purpose digital I/O / Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment
output 22 (see Note 1)
P2.4/TA1.4/S21 33 I/O General-purpose digital I/O / Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment
output 21 (see Note 1)
P2.5/TA1CLK/S20 32 I/O General-purpose digital I/O / input of Timer1_A clock/LCD segment output 20 (see Note 1)
P2.6/CAOUT/S19 31 I/O General-purpose digital I/O / Comparator_A output/LCD segment output 19 (see Note 1)
P2.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 (see Note 1)
P3.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 (see Note 1)
P3.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 (see Note 1)
P3.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 (see Note 1)
P3.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 (see Note 1)
P3.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 (see Note 1)
P3.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 (see Note 1)
P3.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 (see Note 1)
P3.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 (see Note 1)
NOTE 3: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions − MSP430x415, MSP430x417 (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
P4.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 (see Note 1)
P4.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 (see Note 1)
P4.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 (see Note 1)
P4.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 (see Note 1)
P4.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 (see Note 1)
P4.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 (see Note 1)
P4.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 (see Note 1)
P4.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 (see Note 1)
P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1 (see Note 1)
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0 (see Note 1)
COM0 36 O Common output. COM0−3 are used for LCD backplanes.
P5.2/COM1 37 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.
P5.3/COM2 38 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.
P5.4/COM3 39 I/O General-purpose digital I/O / common output. COM0−3 are used for LCD backplanes.
R03 40 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 41 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 42 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2)
P5.7/R33 43 I/O General-purpose digital I/O / output port of most positive analog LCD level (V1)
P6.0 59 I/O General-purpose digital I/O
P6.1 60 I/O General-purpose digital I/O
P6.2 61 I/O General-purpose digital I/O
P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O General-purpose digital I/O / SVS, analog input
RST/NMI 58 I Reset input / Nonmaskable interrupt input port
TCK 57 I Test clock. TCK is the clock input port for device programming and test.
TDI/TCLK 55 I Test data input / Test clock input. The device protection fuse is connected to TDI.
TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal.
TMS 56 I Test mode select. TMS is used as an input port for device programming and test.
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1.
QFN Pad NA NA QFN package pad connection to VSS recommended
NOTE 4: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs,Rd MOV R10,R11 R10 −−> R11
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11
R10 + 2−−> R10
Immediate DMOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active.
DLow-power mode 0 (LPM0)
− CPU is disabled.
− ACLK and SMCLK remain active, MCLK is available to modules.
− FLL+ loop control remains active.
DLow-power mode 1 (LPM1)
− CPU is disabled.
− ACLK and SMCLK remain active. MCLK is available to modules.
− FLL+ loop control is disabled.
DLow-power mode 2 (LPM2)
− CPU is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator remains enabled.
− ACLK remains active.
DLow-power mode 3 (LPM3)
− CPU is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator is disabled.
− ACLK remains active.
DLow-power mode 4 (LPM4)
− CPU is disabled.
− ACLK is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator is disabled.
− Crystal oscillator is stopped.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up
External reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer1_A5 (see Note 4) TA1CCR0 CCIFG (see Note 2) Maskable 0FFFAh 13
Timer1_A5 (see Note 4)
TA1CCR1 to TA1CCR4
CCIFGs and TA1CTL TAIFG
(see Notes 1 and 2)
Maskable 0FFF8h 12
Comparator_A CMPAIFG Maskable 0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
0FFF2h 9
0FFF0h 8
0FFEEh 7
Timer_A3/Timer0_A3 TACCR0/TA0CCR0 CCIFG
(see Note 2)
Maskable 0FFECh 6
Timer_A3/Timer0_A3
TACCR1/TA0CCR1,
TACCR2/TA0CCR2 CCIFGs
and TACLT/TA0CTL TAIFG
(see Notes 1 and 2)
Maskable 0FFEAh 5
I/O port P1 (eight flags) P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 (eight flags) P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
4. Implemented in MSP430x415 and MSP430x417 devices only
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h ACCVIE NMIIE
rw-0
7654 0321
Address
1h BTIE
rw-0
WDTIE: Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is
configured in interval timer mode.
OFIE: Oscillator fault interrupt enable
NMIIE: Nonmaskable interrupt enable
ACCVIE: Flash access violation interrupt enable
BTIE: Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw-0 rw-1 rw-(0)
Address
02h NMIIFG
7654 0321
Address
3h BTIFG
rw-0
WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,
or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
BTIFG: Basic Timer1 interrupt flag
module enable registers 1 and 2
7654 0321
Address
04h/05h
Legend: rw−0,1: Bit Can Be Read and Written. It Is Reset or Set by PUC.
rw−(0,1): Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
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memory organization
MSP430F412 MSP430F413 MSP430F415 MSP430F417
Memory
Interrupt vector
Code memory
Size
Flash
Flash
4KB
0FFFFh to 0FFE0h
0FFFFh to 0F000h
8KB
0FFFFh to 0FFE0h
0FFFFh to 0E000h
16KB
0FFFFh to 0FFE0h
0FFFFh to 0C000h
32KB
0FFFFh to 0FFE0h
0FFFFh to 08000h
Information memory Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
RAM Size 256 Byte
02FFh to 0200h
256 Byte
02FFh to 0200h
512 Byte
03FFh to 0200h
1 KB
05FFh to 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
MSP430C412 MSP430C413
Memory
Interrupt vector
Code memory
Size
ROM
ROM
4KB
0FFFFh to 0FFE0h
0FFFFh to 0F000h
8KB
0FFFFh to 0FFE0h
0FFFFh to 0E000h
Information memory Size NA NA
Boot memory Size NA NA
RAM Size 256 Byte
02FFh to 0200h
256 Byte
02FFh to 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION PM, RTD, RGC PACKAGE PINS
Data Transmit 53 - P1.0
Data Receive 52 - P1.1
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
With Interrupt Vectors
Segment 1
Segment 2
Segment n−1
Segment n
32KB
Segment A
Segment B
Main Memory
Information Memory
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
08400h
083FFh
08200h
081FFh
01000h
010FFh
08000h
01080h
0107Fh
16KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0C400h
0C3FFh
0C200h
0C1FFh
01000h
010FFh
0C000h
01080h
0107Fh
8KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0E400h
0E3FFh
0E200h
0E1FFh
01000h
010FFh
0E000h
01080h
0107Fh
4KB
0FFFFh
0FA00h
0FE00h
0FDFFh
0FC00h
0FBFFh
0F9FFh
0F400h
0F3FFh
0F200h
0F1FFh
01000h
010FFh
0F000h
01080h
0107Fh
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
oscillator and system clock
The clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low
power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module
provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed
level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision
(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6.
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
Basic Timer1
Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers
can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and clock for the
LCD module.
LCD driver
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
watchdog timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
Timer_A3/Timer0_A3
Timer_A3/Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3/Timer0_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3/Timer0_A3 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of
the capture/compare registers.
TIMER_A3/TIMER0_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
48 - P1.5 TACLK/TA0CLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
48 - P1.5 TACLK/TA0CLK INCLK
53 - P1.0 TA0/TA0.0 CCI0A 53 - P1.0
52 - P1.1 TA0/TA0.0 CCI0B
CCR0
TA0/TA0 0
DVSS GND CCR0 TA0/TA0.0
DVCC VCC
51 - P1.2 TA1/TA0.1 CCI1A 51 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1/TA0 1
DVSS GND CCR1 TA1/TA0.1
DVCC VCC
45 - P2.0 TA2/TA0.2 CCI2A 45 - P2.0
ACLK (internal) CCI2B
CCR2
TA2/TA0 2
DVSS GND CCR2 TA2/TA0.2
DVCC VCC
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
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Timer1_A5 (MSP430x415 and MSP430x417 only)
Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER1_A5 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
32 - P2.5 TA1CLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
32 - P2.5 TA1CLK INCLK
49 - P1.4 TA1.0 CCI0A 49 - P1.4
50 - P1.3 TA1.0 CCI0B
CCR0
TA1 0
DVSS GND CCR0 TA1.0
DVCC VCC
44 - P2.1 TA1.1 CCI1A 44 - P2.1
CAOUT (internal) CCI1B
CCR1
TA1 1
DVSS GND CCR1 TA1.1
DVCC VCC
35 - P2.2 TA1.2 CCI2A 35 - P2.2
Not Connected CCI2B
CCR2
TA1 2
DVSS GND CCR2 TA1.2
DVCC VCC
34 - P2.3 TA1.3 CCI3A 34 - P2.3
Not Connected CCI3B
CCR3
TA1 3
DVSS GND CCR3 TA1.3
DVCC VCC
33 - P2.4 TA1.4 CCI4A 33 - P2.4
Not Connected CCI4B
CCR4
TA1 4
DVSS GND CCR4 TA1.4
DVCC VCC
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog Timer control WDTCTL 0120h
Timer1_A5 Timer1_A interrupt vector TA1IV 011Eh
_
(MSP430x415 and
MSP430x417 only)
Timer1_A control TA1CTL 0180h
MSP430x417 only) Capture/compare control 0 TA1CCTL0 0182h
Capture/compare control 1 TA1CCTL1 0184h
Capture/compare control 2 TA1CCTL2 0186h
Capture/compare control 3 TA1CCTL3 0188h
Capture/compare control 4 TA1CCTL4 018Ah
Reserved 018Ch
Reserved 018Eh
Timer1_A register TA1R 0190h
Capture/compare register 0 TA1CCR0 0192h
Capture/compare register 1 TA1CCR1 0194h
Capture/compare register 2 TA1CCR2 0196h
Capture/compare register 3 TA1CCR3 0198h
Capture/compare register 4 TA1CCR4 019Ah
Reserved 019Ch
Reserved 019Eh
Timer_A3/Timer0_A3 Timer_A/Timer0_A interrupt vector TAIV/TA0IV 012Eh
__
Timer_A/Timer0_A control TACTL/TA0CTL 0160h
Capture/compare control 0 TACCTL0/TA0CCTL0 0162h
Capture/compare control 1 TACCTL1/TA0CCTL1 0164h
Capture/compare control 2 TACCTL2/TA0CCTL2 0166h
Reserved 0168h
Reserved 016Ah
Reserved 016Ch
Reserved 016Eh
Timer_A/Timer0_A register TAR/TA0R 0170h
Capture/compare register 0 TACCR0/TA0CCR0 0172h
Capture/compare register 1 TACCR1/TA0CCR1 0174h
Capture/compare register 2 TACCR2/TA0CCR2 0176h
Reserved 0178h
Reserved 017Ah
Reserved 017Ch
Reserved 017Eh
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD LCD memory 20 LCDM20 0A4h
: : :
LCD memory 16 LCDM16 0A0h
LCD memory 15 LCDM15 09Fh
: : :
LCD memory 1 LCDM1 091h
LCD control and mode LCDCTL 090h
Comparator_A Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
Brownout, SVS SVS control register SVSCTL 056h
FLL+ Clock FLL+ Control1 FLL_CTL1 054h
FLL+ Control0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter2 BTCNT2 047h
BT counter1 BTCNT1 046h
BT control BTCTL 040h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
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20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special Functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag2 IFG2 003h
SFR interrupt flag1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
absolute maximum ratings†
Voltage applied at VCC to VSS −0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note 1) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature: Unprogrammed device −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmed device −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
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recommended operating conditions
PARAMETER MIN NOM MAX UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC) (see Note 1) MSP430x41x 1.8 3.6 V
Suppl
y
volta
g
e durin
g
pro
g
ram execution, SVS enabled and PORON = 1, MSP430x412/413 2.2 3.6
V
Supply
voltage
during
program
execution
,
SVS
enabled
and
PORON
=
1
,
VCC (AVCC = DVCC = VCC) (see Note 1 and Note 2) MSP430x415/417 2.0 3.6 V
Supply voltage during programming of flash memory,
VCC (AVCC = DVCC = VCC)MSP430F41x 2.7 3.6 V
Supply voltage, VSS (AVSS/1/2 = DVSS = VSS) 0 0 V
Operating free-air temperature range, TAMSP430x41x −40 85 °C
LFXT1 t l f f
LF selected, XTS_FLL=0 Watch crystal 32768 Hz
LFXT1 crystal frequency, f(LFXT1)
(see Note 3)
XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000
kHz
(
see
N
o
t
e
3)
XT1 selected, XTS_FLL=1 Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f
VCC = 1.8 V DC 4.15
MHz
Processor frequency (signal MCLK), f(System) VCC = 3.6 V DC 8 MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
1.8 V 3.6 V
2.7 V 3 V
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ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
4.15 MHz
8 MHz
VCC − Supply Voltage − V
f(System) − Maximum Processor Frequency − MHz
Supply Voltage Range, x41x
During Program Execution
Supply Voltage Range
During Programming of
the Flash Memory
Figure 1. Frequency vs Supply Voltage
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Active mode,
C41x
2.2 V 160 200
I
Active
mode
,
f
(
MCLK
)
= f
(
SMCLK
)
= f
(
DCO
)
= 1 MHz, C41x
T40°Cto85°C
3 V 240 300
A
I(AM)
f(MCLK)
=
f(SMCLK)
=
f(DCO)
=
1
MHz
,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
F41x
TA = −40°C to 85°C2.2 V 200 250 μA
(ACLK)
(F41x: Program executes in flash) F41x 3 V 300 350
Low-power mode (LPM0)
f
(
MCLK
)
= f
(
SMCLK
)
= f
(
DCO
)
= 0.5 MHz, 2.2 V 32 45
I
f(MCLK)
=
f(SMCLK)
=
f(DCO)
=
0
.
5
MHz
,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0 (see Note 3) C41x
T40°Cto85°C
3 V 55 70
A
I(LPM0) Low-power mode (LPM0)
f
(
MCLK
)
= f
(
SMCLK
)
= f
(
DCO
)
= 1 MHz,
C41x
F41x TA = −40°C to 85°C
2.2 V 57 70
μA
f(MCLK)
=
f(SMCLK)
=
f(DCO)
=
1
MHz
,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0 (see Note 3) 3 V 92 100
I
Low power mode (LPM2) (see Note 3)
T40°Cto85°C
2.2 V 11 14
A
I(LPM2) Low-power mode (LPM2) (see Note 3) TA = −40°C to 85°C3 V 17 22 μA
TA = −40°C 0.95 1.4
TA = −10°C0.8 1.3
TA = 25°C2.2 V 0.7 1.2
TA = 60°C
2.2
V
0.95 1.4
I
Low power mode (LPM3) (see Note 2 and Note 3)
TA = 85°C 1.6 2.3
A
I(LPM3) Low-power mode (LPM3) (see Note 2 and Note 3) TA = −40°C 1.1 1.7 μA
TA = −10°C 1.0 1.6
TA = 25°C3 V 0.9 1.5
TA = 60°C
3
V
1.1 1.7
TA = 85°C 2.0 2.6
TA = −40°C 0.1 0.5
I
(
LPM4
)
Low-power mode (LPM4) (see Note 3) TA = 25°C2.2 V/3 V 0.1 0.5 μA
I(LPM4)
Low power
mode
(LPM4)
(see
Note
3)
TA = 85°C
2.2
V/3
V
0.8 2.5
μA
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption is measured with active Basic
Timer1 and LCD (ACLK selected).
The current consumption of the Comparator_A and the SVS module are specified in the respective sections.
2. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
3. Current for brownout included.
current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 140 μA/V × (VCC – 3 V)
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − ports P1, P2, P3, P4, P5, and P6
PARAMETER VCC MIN MAX UNIT
V
Positive going input threshold voltage
2.2 V 1.1 1.5
V
VIT+ Positive-going input threshold voltage 3 V 1.5 1.9 V
V
Negative going input threshold voltage
2.2 V 0.4 0.9
V
VIT− Negative-going input threshold voltage 3 V 0.9 1.3 V
V
Input voltage hysteresis (V V )
2.2 V 0.3 1.1
V
Vhys Input voltage hysteresis (VIT+ − VIT−)3 V 0.45 1 V
standard inputs − RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER VCC MIN MAX UNIT
VIL Low-level input voltage
2 2 V/3 V
VSS VSS+0.6 V
VIH High-level input voltage 2.2 V/3 V 0.8×VCC VCC V
inputs Px.x, TAx/TAx.x
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Port P1, P2: P1.x to P2.x, External
2.2 V/3 V 1.5 cycle
t(int) External interrupt timing
Port
P1
,
P2:
P1
.
x
to
P2
.
x
,
External
trigger signal for the interrupt flag
(N )
2.2 V 62
ns
(int)
pg
gg g p g
(see Note 1) 3 V 50 ns
t()
Timer A capture timing
TAx/TAx y
2.2 V 62
ns
t(cap) Timer_A, capture timing TAx/TAx.y 3 V 50 ns
f
Timer_A clock frequenc
y
externall
y
applied
TACLK/TAxCLK INCLK t=t
2.2 V 8
MHz
f(TAext)
Timer
_
A
clock
frequency
externally
applied
to pin TACLK/TAxCLK, INCLK t(H) = t(L) 3 V 10 MHz
f
Timer A clock frequency
SMCLK or ACLK signal selected
2.2 V 8
MHz
f(TAint) Timer_A clock frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(P1.x) Port P1 V(P1.x) (see Note 2) ±50
Ilkg(P2.x) Port P2 V(P2.x) (see Note 2) ±50
Ilkg(P3.x)
Leakage current
Port P3 V(P3.x) (see Note 2)
2 2 V/3 V
±50
nA
Ilkg(P4.x)
Leakage current Port P4 V(P4.x) (see Note 2) 2.2 V/3 V ±50 nA
Ilkg(P5.x) Port P5 V(P5.x) (see Note 2) ±50
Ilkg(P6.x) Port P6 V(P6.x) (see Note 2) ±50
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − ports P1, P2, P3, P4, P5, and P6
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
IOH(max) = −1.5 mA, See Note 1 2.2 V VCC−0.25 VCC
V
High level output voltage
IOH(max) = −6 mA, See Note 2 2.2 V VCC−0.6 VCC
V
VOH High-level output voltage IOH(max) = −1.5 mA, See Note 1 3 V VCC−0.25 VCC
V
IOH(max) = −6 mA, See Note 2 3 V VCC−0.6 VCC
IOL(max) = 1.5 mA, See Note 1 2.2 V VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA, See Note 2 2.2 V VSS VSS+0.6
V
VOL Low-level output voltage IOL(max) = 1.5 mA, See Note 1 3 V VSS VSS+0.25 V
IOL(max) = 6 mA, See Note 2 3 V VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(1 ≤x≤60≤y≤7)
CL = 20 pF, VCC = 2.2 V DC 10
MHz
fPx.y (1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
CL
=
20
pF
,
IL = ± 1.5mA VCC = 3 V DC 12 MHz
fACLK,
f
P1 1/TA0/MCLK P1 5/TACLK/ACLK
C20 pF
VCC = 2.2 V 8
MHz
fMCLK,
fSMCLK
P1.1/TA0/MCLK, P1.5/TACLK/ACLK CL = 20 pF
VCC = 3 V 12
MHz
P1.5/TACLK/ACLK,
fACLK = fLFXT1 = fXT1 40% 60%
P1
.
5/TACLK/ACLK
,
CL = 20 pF fACLK = fLFXT1 = fLF 30% 70%
CL
20
pF
VCC = 2.2 V / 3 V fACLK = fLFXT1/n 50%
tXdc Duty cycle of output frequency
P1.1/TA0/MCLK,
C20 pF
fMCLK = fLFXT1/n
50%−
15 ns 50% 50%+
15 ns
CL = 20 pF,
VCC = 2.2 V / 3 V fMCLK = fDCOCLK
50%−
15 ns 50% 50%+
15 ns
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x412, MSP430x413 outputs − ports P1, P2, P3, P4, P5, and P6 (see Note A)
VOL − Low-Level Output Voltage − V
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P1.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOL − Typical Low-Level Output Current − mA
Figure 2
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P1.0
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOL − Typical Low-Level Output Current − mA
Figure 3
VOH − High-Level Output Voltage − V
−14
−12
−10
−8
−6
−4
−2
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P1.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOH − Typical High-Level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P1.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOH − Typical High-Level Output Current − mA
Figure 5
NOTE A: One output loaded at a time
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x415, MSP430x417 outputs − ports P1, P2, P3, P4, P5, and P6 (see Note A)
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.4
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOL − Typical Low-Level Output Current − mA
Figure 6
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
30
35
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.4
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOL − Typical Low-Level Output Current − mA
Figure 7
VOH − High-Level Output Voltage − V
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOH − Typical High-Level Output Current − mA
Figure 8
VOH − High-Level Output Voltage − V
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
IOH − Typical High-Level Output Current − mA
Figure 9
NOTE B: One output loaded at a time
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz VCC = 2.2 V/3 V 6μs
td(LPM3)
Delay
time
f = 3 MHz
VCC
2.2
V/3
V
6
μs
RAM (see Note 1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(33) Voltage at P5.7/R33 2.5 VCC +0.2
V(23)
Analog voltage
Voltage at P5.6/R23
V3V
(V33−V03) × 2/3 + V03
V
V(13)
Analog voltage Voltage at P5.5/R13 VCC = 3 V (V(33)−V(03)) × 1/3 + V(03)
V
V(33) − V(03) Voltage at R33/R03 2.5 VCC + 0.2
I(R03) R03 = VSS No load at all ±20
I(R13) Input leakage P5.5/R13 = VCC/3 segment and
common lines
±20 nA
I(R23)
pg
P5.6/R23 = 2 × VCC/3
common
li
nes,
VCC = 3 V ±20
V(Sxx0) V(03) V(03) − 0.1
V(Sxx1) Se
g
ment line
I 3 A
V3V
V(13) V(13) − 0.1
V
V(Sxx2)
Segment
line
voltage I(Sxx) = −3 μA, VCC = 3 V V(23) V(23) − 0.1 V
V(Sxx3) V(33) V(33) + 0.1
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
2.2 V 25 40
A
I(CC) CAON = 1, CARSEL = 0, CAREF = 0 3 V 45 60 μA
I
CAON = 1, CARSEL = 0,
CAREF 1/2/3
2.2 V 30 50
A
I(Refladder/RefDiode) CAREF = 1/2/3,
No load at P1.6/CA0 and P1.7/CA1 3 V 45 71
μA
V(Ref025) Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1 2.2 V / 3 V 0.23 0.24 0.25
V(Ref050) Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1 2.2V / 3 V 0.47 0.48 0.50
V
See Fi
g
ure 10 and PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1 6/CA0 and P1 7/CA1;
2.2 V 390 480 540
mV
V(RefVT)
See
Figure
10
and
Figure 11 No load at P1.6/CA0 and P1.7/CA1;
TA = 85°C3 V 400 490 550
mV
V(IC)
Common-mode input
voltage range CAON = 1 2. 2 V/3 V 0 VCC−1.0 V
V(offset) Offset voltage See Note 2 2.2 V/3 V −30 30 mV
Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV
TA = 25°C, 2.2 V 160 210 300
ns
t
TA
=
25 C
,
Overdrive 10 mV, Without filter: CAF = 0 3 V 80 150 240 ns
t(response LH) TA = 25°C2.2 V 1.4 1.9 3.4
s
TA
=
25 C
Overdrive 10 mV, With filter: CAF = 1 3 V 0.9 1.5 2.6 μs
TA = 25°C2.2 V 130 210 300
ns
t
TA
=
25 C
Overdrive 10 mV, Without filter: CAF = 0 3 V 80 150 240 ns
t(response HL) TA = 25°C, 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
,
Overdrive 10 mV, With filter: CAF = 1 3 V 0.9 1.5 2.6 μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Typical
V(RefVT) − Reference Voltage − mV
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 10
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
Typical
V(RefVT) − Reference Voltage − mV
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 11
_
+
CAON
0
1
V+ 0
1
CAF
Low Pass Filter
τ ≈ 2 μs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 12. Comparator_A Module Block Diagram
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 13. Overdrive Definition
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR brownout, reset (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 μs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 14) 0.7 × V(B_IT−) V
V(B_IT−)
Brownout
dVCC/dt ≤ 3 V/s (see Figure 14, Figure 15, Figure 16) 1.71 V
Vhys(B_IT−)
B
rownout
dVCC/dt ≤ 3 V/s (see Figure 14) 70 130 180 mV
t(reset)
Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V 2μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT−) + Vhys(B_IT−) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+
settings must not be changed until VCC ≥ VCC(min). See the MSP430x4xx Family User’s Guide (SLAU056) for more information on
the brownout/SVS circuit.
0
1
V
VCC(start)
Vhys(B_IT−)
VCC
td(BOR)
(B_IT−)
Figure 14. POR/Brownout Reset (BOR) vs Supply Voltage
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC (drop) − V
0
0.5
1
1.5
2
0.001 1 1000
V = 3 V
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − μst
pw − Pulse Width − μs
cc
VCC
3 V
VCC(drop)
tpw
Figure 15. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
3 V
VCC(drop)
tpw
0
0.5
1
1.5
2
tpw − Pulse Width − μs
0.001 1 1000 tftr
tpw − Pulse Width − μs
tf = tr
V = 3 V
Typical Conditions
cc
VCC (drop) − V
Figure 16. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
SVS (supply voltage supervisor/monitor) (MSP430x412, MSP430x413 only) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dVCC/dt > 30 V/ms (see Note 2) 5 150 μs
td(SVSR) dVCC/dt ≤ 30 V/ms (see Note 2) 2000 μs
td(SVSon) SVSon, switch from 0 to 1, VCC = 3 V (see Note 2) 20 150 μs
V(SVSstart)
SVS
dVCC/dt ≤ 3 V/s (see Figure 17) 1.55 1.7 V
V(SVS_IT−)
SVS dVCC/dt ≤ 3 V/s (see Figure 17) 1.8 1.95 2.2 V
Vhys(SVS_IT−) dVCC/dt ≤ 3 V/s (see Figure 17) 70 100 155 mV
ICC(SVS)
(see Note 1) VLD ≠ 0 (VLD bits are in SVSCTL register), VCC = 2.2 V/3 V 10 15 μA
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. The SVS is not active at power up.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor) (MSP430x415, MSP430x417 only) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 17) 5 150
μs
td(SVSR) dVCC/dt ≤ 30 V/ms 2000 μs
td(SVSon) SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 μs
tsettle VLD ≠ 0‡12 μs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 17) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 17) VLD = 2 to 14 V(SVS_IT−)
× 0.004
V(SVS_IT−)
× 0.008
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 17),
External voltage applied on SVSIN VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
VCC/dt ≤3 V/s (see Figure 17)
VLD = 7 2.46 2.65 2.86
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 17) VLD = 8 2.58 2.8 3
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt ≤ 3 V/s (see Figure 17),
External voltage applied on SVSIN VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. The SVS is not active at power up.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V
Software Sets VLD>0:SVS is Active
Undefined
0
1
Brownout
0
1
0
1
Set POR
Brownout
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVS out
Vhys(SVS_IT−)
Vhys(B_IT−)
td(BOR)
td(SVSon)
td(SVSR)
td(BOR)
(SVS_IT−)
Figure 17. SVS Reset (SVSR) vs Supply Voltage
VCC(drop)
0
0.5
1
1.5
2
1 ns 1 ns
tpw − Pulse Width − μs
1 10 1000
tftr
t − Pulse Width − μs
100
tf = tr
Rectangular Drop
VCC(drop) − V
Triangular Drop
3 V
VCC tpw
3 V
VCC tpw
VCC(drop)
Figure 18. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK)
N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0, fCrystal = 32.768 kHz 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0 DCOPLUS 1
2.2 V 0.3 0.65 1.25
MHz
f(DCO=2) FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 3 V 0.3 0.7 1.3 MHz
f
FN 8 FN 4 FN 3 FN 2 0 DCOPLUS 1
2.2 V 2.5 5.6 10.5
MHz
f(DCO=27) FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 3 V 2.7 6.1 11.3 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1 DCOPLUS 1
2.2 V 0.7 1.3 2.3
MHz
f(DCO=2) FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 3 V 0.8 1.5 2.5 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1 DCOPLUS 1
2.2 V 5.7 10.8 18
MHz
f(DCO=27) FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 3 V 6.5 12.1 20 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x DCOPLUS 1
2.2 V 1.2 2 3
MHz
f(DCO=2) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 3 V 1.3 2.2 3.5 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 9 15.5 25
MHz
f(DCO=27) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x; DCOPLUS = 1 3 V 10.3 17.9 28.5 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x DCOPLUS 1
2.2 V 1.8 2.8 4.2
MHz
f(DCO=2) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 3 V 2.1 3.4 5.2 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x DCOPLUS 1
2.2 V 13.5 21.5 33
MHz
f(DCO=27) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 =x, DCOPLUS = 1 3 V 16 26.6 41 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x DCOPLUS 1
2.2 V 2.8 4.2 6.2
MHz
f(DCO=2) FN_8 = 1, FN_4 = FN_3 = FN_2=x, DCOPLUS = 1 3 V 4.2 6.3 9.2 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x DCOPLUS 1
2.2 V 21 32 46
MHz
f(DCO=27) FN_8 = 1,FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps:
S f /f
1 < TAP ≤ 20 1.06 1.11
SnSn = fDCO(Tap n+1) / fDCO(Tap n)
(see Figure 20 for taps 21 to 27) TAP = 27 1.07 1.17
D
Temperature drift, N
(
D
CO)
= 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, 2.2 V –0.2 –0.3 –0.4
%/_C
Dt
Temperature
drift
,
N(DCO)
=
01Eh
,
FN
_
8
=
FN
_
4
=
FN
_
3
=
FN
_
2
=
0
,
D = 2, DCOPLUS = 0 3 V –0.2 –0.3 –0.4 %/_C
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 19. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 20. DCO Tap Step Size
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
f(DCO)
Figure 21. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
OSCCAPx = 0h 0
C
Integrated load capacitance
OSCCAPx = 1h
2 2 V/3 V
10
pF
CXIN Integrated load capacitance OSCCAPx = 2h 2.2 V/3 V 14 pF
OSCCAPx = 3h 18
OSCCAPx = 0h 0
C
Integrated load capacitance
OSCCAPx = 1h
2 2 V/3 V
10
pF
CXOUT Integrated load capacitance OSCCAPx = 2h 2.2 V/3 V 14 pF
OSCCAPx = 3h 18
VIL
Input levels at XIN
see Note 3
2.2 V/3 V VSS 0.2×VCC
V
VIH
Input levels at XIN see Note 3 2.2 V/3 V 0.8×VCC VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(CXIN × CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
•Keep the trace between the MSP430x41x and the crystal as short as possible.
•Design a good ground plane around oscillator pins.
•Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
•Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
•Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
•If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
•Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
flash memory
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and erase supply voltage 2.7 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA
tCPT Cumulative program time See Note 1 2.7 V/ 3.6 V 10 ms
tCMErase Cumulative mass erase time See Note 2 2.7 V/ 3.6 V 200 ms
Program/erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 35
tBlock, 0Block program time for 1st byte or word 30
tBlock, 1-63 Block program time for each additional byte or word
See Note 3
21
t
tBlock, End Block program end-sequence wait time See Note 3 6tFTG
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the flash controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the flash controller’s state machine (tFTG = 1/fFTG).
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN TYP MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
V
Voltage level on TDI/TCLK for fuse blow
MSP430C41x 3.5 3.9 V
VFB Voltage level on TDI/TCLK for fuse-blow MSP430F41x 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 via JTAG/Test is possible. The JTAG block is switched to bypass mode.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematics
Port P1, P1.0 to P1.5, input/output with Schmitt trigger
TACLK†
P1OUT.x
Module X OUT
P1DIR.x
Direction Control
From Module
P1SEL.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x
P1.x
EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
CAPD.x
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
P1SEL.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1SEL.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2
P1SEL.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3
P1SEL.4 P1DIR.4 P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4
P1SEL.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5
P1SEL.0 P1DIR.0 P1OUT.0 P1IN.0 P1IE.0 P1IFG.0 P1IES.0
SVSOUT Unused
Unused
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.4
P1DIR.5
P1DIR.0
ACLK
MCLK
Module X IN
P1IN.x
P1.5/TACLK/ACLK
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.4
P1.3/SVSOUT
Control
NOTE: 0 ≤ x ≤ 5.
Port Function is Active if CAPD.x = 0
†Timer_A3/Timer0_A3
‡Timer1_A5 (MSP430x415, MSP430x417 only)
§MSP430x412, MSP430x413 only
Out0 Sig.†
Out1 Sig.†
CCI0A†
CCI1A†
CCI0B†
MSP430x412,
MSP430x413 only
MSP430x415,
MSP430x417 only
P1.5/TA0CLK/ACLK
P1.0/TA0.0
P1.1/TA0.0/MCLK
P1.2/TA0.1
P1.4/TA1.0
P1.3/TA1.0/SVSOUT
Out0 Sig.‡
DVSS
CCI0A‡
§§
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P1, P1.6, P1.7 input/output with Schmitt trigger
Comparator_A
P1OUT.7
DVSS
P1DIR.7
P1SEL.7
D
EN
Interrupt
Edge
Select
P1IES.7 P1SEL.7
P1IE.7
P1IFG.7
P1IRQ.07 EN
Set
Q
0
1
1
0
CAPD.7
P1OUT.6
DVSS
P1DIR.6
P1SEL.6
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IFG.7
P1IRQ.07
P1.6/
CA0
EN
Set
Q
0
1
1
0
CAPD.6
Note: Port Function Is Active if CAPD.6 = 0
P1IN.6
unused
P1.7/
CA1
Reference Block
CCI1B
CAF
CAREF
P2CA
CAEX
CAREF
to Timer_Ax −
+
2
AVcc
CA0
CA1
Pad Logic
0: Input
1: Output
Bus
Keeper
Pad Logic
0: Input
1: Output
Bus
Keeper
P1DIR.6
P1DIR.7
P1IN.7
unused
P1IE.7
Note: Port Function Is Active if CAPD.7 = 0
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P2, P2.0 to P2.7, input/output with Schmitt trigger
P2SEL.1 P2DIR.1 P2OUT.1 P2IN.1 P2IE.1 P2IFG.1 P2IES.1
P2SEL.2 P2DIR.2 P2OUT.2 P2IN.2 P2IE.2 P2IFG.2 P2IES.2
P2SEL.3 P2DIR.3 P2OUT.3 P2IN.3 P2IE.3 P2IFG.3 P2IES.3
P2SEL.4 P2DIR.4 P2OUT.4 P2IN.4 P2IE.4 P2IFG.4 P2IES.4
P2SEL.5 P2DIR.5 P2OUT.5 P2IN.5 P2IE.5 P2IFG.5 P2IES.5
P2SEL.0 P2DIR.0 P2OUT.0 P2IN.0 P2IE.0 P2IFG.0 P2IES.0
P2DIR.1
P2DIR.2
P2DIR.0
0: Port Active
1: Segment xx
P2SEL.6 P2DIR.6
P2SEL.7 P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
P2IN.6
P2IN.7
CAOUT P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
P2DIR.3
P2DIR.4
P2DIR.5
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x
P2.x
EN
Set
Q
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.x
Module X IN
Module X IN
P2IN.x
Control
NOTE: 0 ≤ x ≤ 7
Out2 Sig.†CCI2A†
DVSS
DVSS
Unused
Unused
P2.7/S18
P2.6/CAOUT/S19
P2.5/S20
P2.0/TA2
P2.1
P2.2/S23
P2.4/S21
P2.3/S22
Segment xx
Function Active
LCDM.5
LCDM.6
LCDM.7
P2.2 to P2.5
P2.0, P2.1
P2.6, P2.7
MSP430x412,
MSP430x413 only
MSP430x415,
MSP430x417 only
P2.7/S18
P2.6/CAOUT/S19
P2.5/TA1CLK/S20
P2.0/TA0.2
P2.1/TA1.1
P2.2/TA1.2/S23
P2.4/TA1.4/S21
P2.3/TA1.3/S22
†Timer_A3/Timer0_A3
‡Timer1_A5 (MSP430x415, MSP430x417 only)
§MSP430x412, MSP430x413 only
Out1 Sig.‡
Out2 Sig.‡
Out3 Sig.‡
Out4 Sig.‡
CCI1A‡
CCI2A‡
CCI3A‡
CCI4A‡
TA1CLK‡
DVSS§
DVSS§
DVSS§
DVSS§
Unused§
Unused§
Unused§
Unused§
Unused§
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P3, P3.0 to P3.7, input/output with Schmitt trigger
P3SEL.0 P3DIR.0 P3OUT.0 P3IN.0
0: Port Active
1: Segment xx
DVSS Unused
P3OUT.x
Module X OUT
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
P3.x
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Module X IN
Module X IN
P3IN.x
Control
NOTE: 0 ≤ x ≤ 7
DVSS
DVSS
DVSS
DVSS
DVSS
Unused
Unused
Unused
Unused
Unused
Unused
Segment xx
Function Active
LCDM.6 P3.2 to P3.7
P3.0, P3.1
P3.7/S10
P3.6/S11
P3.5/S12
P3.0/S17
P3.1/S16
P3.2/S15
P3.4/S13
P3.3/S14
LCDM.7
LCDM.5
Unused
DVSS
DVSS
P3SEL.1 P3DIR.1 P3OUT.1 P3IN.1
P3SEL.2 P3DIR.2 P3OUT.2 P3IN.2
P3SEL.3 P3DIR.3 P3OUT.3 P3IN.3
P3SEL.4 P3DIR.4 P3OUT.4 P3IN.4
P3SEL.5 P3DIR.5 P3OUT.5 P3IN.5
P3SEL.6 P3DIR.6 P3OUT.6 P3IN.6
P3SEL.7 P3DIR.7 P3OUT.7 P3IN.7
P3DIR.0
P3DIR.1
P3DIR.2
P3DIR.3
P3DIR.4
P3DIR.5
P3DIR.6
P3DIR.7
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P4, P4.0 to P4.7, input/output with Schmitt trigger
P4SEL.0 P4DIR.0 P4OUT.0 P4IN.0
0: Port Active
1: Segment xx
DVSS Unused
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
P4.x
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Module X IN
Module X IN
P4IN.x
Control
NOTE: 0 ≤ x ≤ 7
DVSS
DVSS
DVSS
DVSS
DVSS
Unused
Unused
Unused
Unused
Unused
Unused
Segment xx
Function Active
LCDM.6
LCDM.7
LCDM.5
Unused
DVSS
DVSS
P4.7/S2
P4.6/S3
P4.5/S4
P4.0/S9
P4.1/S8
P4.2/S7
P4.4/S5
P4.3/S6
P4SEL.1 P4DIR.1 P4OUT.1 P4IN.1
P4SEL.2 P4DIR.2 P4OUT.2 P4IN.2
P4SEL.3 P4DIR.3 P4OUT.3 P4IN.3
P4SEL.4 P4DIR.4 P4OUT.4 P4IN.4
P4SEL.5 P4DIR.5 P4OUT.5 P4IN.5
P4SEL.6 P4DIR.6 P4OUT.6 P4IN.6
P4SEL.7 P4DIR.7 P4OUT.7 P4IN.7
P4DIR.0
P4DIR.1
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
P4DIR.6
P4DIR.7
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P5, P5.0, P5.1, input/output with Schmitt trigger
P5SEL.0 P5DIR.0 P5OUT.0 P5IN.0 S1
P5DIR.0
DVSS Unused
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Segment
Module X IN
Control
NOTE: x = 0, 1
0: Port Active
1: Segment
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
P5.x
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
Module X IN
P5IN.x
Segment xx or
Function Active
LCDM.6
LCDM.7
LCDM.5
P5.0/S1
P5.1/S0
COMx or Rxx
DVSS Unused
P5SEL.1 P5DIR.1 P5OUT.1 P5IN.1 S0
P5DIR.1 DVSS Unused
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P5, P5.2 to P5.4, input/output with Schmitt trigger
P5SEL.2 P5DIR.2 P5OUT.2 P5IN.2 COM1
P5DIR.2
DVSS Unused
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x COMx
Module X IN
Control
NOTE: 2 ≤ x ≤ 4
DVSS Unused
0: Port Active
1: COMx Function
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
P5.x
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
Module X IN
P5IN.x
COMx
Active
P5.2/COM1
P5.3/COM2
DVSS Unused
P5SEL.3 P5DIR.3 P5OUT.3 P5IN.3 COM2
P5DIR.3 DVSS Unused
P5SEL.4 P5DIR.4 P5OUT.4 P5IN.4 COM3
P5DIR.4 DVSS Unused
P5.4/COM3
NOTE:
The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port
and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a
3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD
requires only COM0.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P5, P5.5 to P5.7, input/output with Schmitt trigger
P5SEL.5 P5DIR.5 P5OUT.5 P5IN.5 R13
P5DIR.5
DVSS Unused
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Rxx
Module X IN
Control
NOTE: 5 ≤ x ≤ 7
DVSS Unused
0: Port Active
1: Rxx Function
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
P5.x
0
1
1
0
Pad Logic
0: Input
1: Output
Bus
keeper
Module X IN
P5IN.x
Rxx
Active
P5.5/R13
P5.6/R23
DVSS Unused
P5SEL.6 P5DIR.6 P5OUT.6 P5IN.6 R23
P5DIR.6 DVSS Unused
P5SEL.7 P5DIR.7 P5OUT.7 P5IN.7 R33
P5DIR.7 DVSS Unused
P5.7/R33
NOTE:
The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port
and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to
R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P6, P6.0 to P6.6, input/output with Schmitt trigger
P6OUT.x
Module X OUT
P6DIR.x
Direction Control
From Module
P6SEL.x
D
EN
P6.x
0
1
1
0
0: Input
1: Output
Module X IN
P6IN.x
P6.P6.0
P6SEL.0 P6DIR.0 P6OUT.0 P6IN.0
DVSS Unused
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Module X IN
Control
NOTE: 0 ≤ x ≤ 6
DVSS
DVSS
DVSS
DVSS
Unused
Unused
Unused
Unused
Unused
Unused
DVSS
DVSS
P6SEL.1 P6DIR.1 P6OUT.1 P6IN.1
P6SEL.2 P6DIR.2 P6OUT.2 P6IN.2
P6SEL.3 P6DIR.3 P6OUT.3 P6IN.3
P6SEL.4 P6DIR.4 P6OUT.4 P6IN.4
P6SEL.5 P6DIR.5 P6OUT.5 P6IN.5
P6SEL.6 P6DIR.6 P6OUT.6 P6IN.6
P6DIR.0
P6DIR.1
P6DIR.2
P6DIR.3
P6DIR.4
P6DIR.5
P6DIR.6
P6.P6.1
P6.2
P6.P6.4
P6.P6.5
P6.P6.6
P6.3
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P6, P6.7 input/output with Schmitt trigger (MSP430x412/413 only)
P6OUT.7
Module X OUT
P6DIR.7
Direction Control
From Module
P6SEL.7
D
EN
P6.x
0
1
1
0
0: Input
1: Output
Module X IN
P6IN.7
P6.7
PnSEL.x PnDIR.x
Direction
From Module
PnOUT.x Module X
OUT PnIN.x Module X IN
Control
DVSS Unused
P6SEL.7 P6DIR.7 P6OUT.7 P6IN.7
P6DIR.7
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
port P6, P6.7 input/output with Schmitt trigger (MSP430F415/417 only)
P6IN.7
Module X IN
Pad Logic
EN
D
P6OUT.7
P6DIR.7
P6SEL.7
DVss
0
1
0
1
Bus Keeper
To SVS
0: Input
1: Output
P6.7/SVSIN
SVS VLDx=15
1
SVS VLDx=15
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 μA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.
SVS VLDx = 15 P6SEL.7 P6DIR.7 Port Function
0 0 0 P6.7 Input
0 0 1 P6.7 Output
0 1 X Undefined
1 X X SVSIN
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
JTAG
DVCC
DVCC
Burn and Test
Fuse
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
RST/NMI
Test and
Emulation Module
(F versions only)
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
ITF
ITDI/TCLK
Figure 22. Fuse Check Mode Current, MSP430C41x, MSP430F41x
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS340H
Updated functional block diagrams (page 4)
Clarified test conditions in recommended operating conditions table (page 21)
Split Supply voltage during program execution for MSP430x412/413 and MSP430x415/417 (page 21)
Clarified test conditions for I(LPM0) in supply current into AVCC + DVCC table (page 22)
Added P2−P5 to leakage current table (page 23)
Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 37)
SLAS340I Changed all RTD package options for MSP430C41x to RGC package.
NOTE: Page and figure numbers refer to the respective document revision.
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x41x
MIXED SIGNAL MICROCONTROLLER
SLAS340J − MAY 2001 − REVISED DECEMBER 2008
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430C413CY ACTIVE TBD Call TI Call TI
MSP430F412IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F412IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F412IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F412IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F413CY ACTIVE Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
MSP430F413IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F413IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F413IRTD OBSOLETE VQFN RTD 64 TBD Call TI Call TI
MSP430F413IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F413IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F415CY ACTIVE TBD Call TI Call TI
MSP430F415IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F415IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F415IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F415IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F417CY ACTIVE Green (RoHS
& no Sb/Br) Call TI N / A for Pkg Type
MSP430F417IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F417IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F417IRTDR ACTIVE VQFN RTD 64 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
MSP430F417IRTDT ACTIVE VQFN RTD 64 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F412IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F413IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F415IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F415IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F417IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
MSP430F417IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F412IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430F413IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430F415IPMR LQFP PM 64 1000 336.6 336.6 41.3
MSP430F415IPMR LQFP PM 64 1000 367.0 367.0 45.0
MSP430F417IPMR LQFP PM 64 1000 367.0 367.0 45.0
MSP430F417IPMR LQFP PM 64 1000 336.6 336.6 41.3
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PM (S-PQFP-G64) PLASTIC QUAD FLATPACK
4040152/C 11/96
32
17 0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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