Integrated Silicon Solution, Inc. 1
Rev. F
07/22/09
IS61LF25636A IS61VF25636A IS64LF25636A
IS61LF51218A IS61VF51218A
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
FEATURES
• Internalself-timedwritecycle
• IndividualByteWriteControlandGlobalWrite
• Clockcontrolled,registeredaddress,dataand
control
• BurstsequencecontrolusingMODEinput
•
Three chip enable option for simple depth expan-
sion
and address pipelining
• Commondatainputsanddataoutputs
• AutoPower-downduringdeselect
• Singlecycledeselect
• SnoozeMODEforreduced-powerstandby
• JTAGBoundaryScanforPBGApackage
• PowerSupply
LF: Vd d 3.3V + 5%, Vd d q 3.3V/2.5V + 5%
VF: Vd d 2.5V + 5%, Vd d q 2.5V + 5%
• JEDEC100-PinTQFP,119-pinPBGA,and165-
pinPBGApackages
• Lead-freeavailable
• Automotivetemperatureavailable
AUGUST 2009
256K x 36, 512K x 18
9 Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
DESCRIPTION
The ISSI IS61LF/VF25636A,IS64LF25636AandIS61LF/
VF51218A are high-speed, low-power synchronous
static
RAMs
designed to provide burstable,
high-performance
memory for communication and networking applications.
The IS61LF/VF25636AandIS64LF25636Aareorganized
as262,144wordsby36bits.The IS61LF/VF51218A is
organizedas524,288wordsby18bits.Fabricatedwith
ISSI'sadvancedCMOStechnology,thedeviceintegrates
a2-bitburstcounter,high-speedSRAMcore,andhigh-
drive capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Writecyclesareinternallyself-timedandareinitiatedbythe
risingedgeoftheclockinput.Writecyclescanbeoneto
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Bytewriteoperationisperformedbyusingbytewriteen-
able (BWE) input combined with one or more individual
byte write signals (BWx). Inaddition,GlobalWrite(GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
BurstscanbeinitiatedwitheitherADSP (Address Status
Processor)orADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
Themodepinisusedtoselecttheburstsequenceorder,
LinearburstisachievedwhenthispinistiedLOW.Inter-
leaveburstisachievedwhenthispinistiedHIGHorleft
floating.
FAST ACCESS TIME
Symbol Parameter -6.5 -7.5 Units
tk q ClockAccessTime 6.5 7.5 ns
tk c CycleTime 7.5 8.5 ns
Frequency 133 117 MHz
2 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
BLOCK DIAGRAM
18/19
BINARY
COUNTER
GW
CLR
CE
CLK Q0
Q1
MODE
A0'
A0
A1
A1'
CLK
ADV
ADSC
ADSP
16/17 18/19
ADDRESS
REGISTER
CE
D
CLK
Q
DQ(a-d)
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
BWE
BW(a-d)
x18: a,b
x36: a-d
CE
CE2
CE2
256Kx36;
512Kx18;
MEMORY ARRAY
36,
or 18
INPUT
REGISTERS
CLK
OE
2/4/8
OE
DQa - DQd
36,
or 18
36,
or 18
A
POWER
DOWN
ZZ
Integrated Silicon Solution, Inc.3
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
BOTTOMVIEW
BOTTOMVIEW
165-PIN BGA
165-Ball,13x15mmBGA
119-PIN BGA
119-Ball,14x22mmBGA
4 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
119 BGA PACKAGE PIN CONFIGURATION-256k x 36 (TOP VIEW)
PIN DESCRIPTIONS
12345 6 7
AVDDQ A A ADSP A A VDDQ
BNC CE2 AADSC A A NC
CNC A A VDD A A NC
DDQc DQPc Vss NC Vss DQPb DQb
EDQc DQc Vss CE Vss DQb DQb
FVDDQ DQc Vss OE Vss DQb VDDQ
GDQc DQc BWc ADV BWb DQb DQb
HDQc DQc Vss GW Vss DQb DQb
JVDDQ VDD NC VDD NC VDD VDDQ
KDQd DQd Vss CLK Vss DQa DQa
LDQd DQd BWd NC BWa DQa DQa
MVDDQ DQd Vss BWE Vss DQa VDDQ
NDQd DQd Vss A1* Vss DQa DQa
PDQd DQPd Vss A0* Vss DQPa DQa
RNC A MODE VDD NC A NC
TNC NC A A A NC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Symbol Pin Name
A Address Inputs
A0,A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP AddressStatusProcessor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE,CE2 Synchronous Chip Select
BWx(x=a-d) SynchronousByteWriteControls
BWE ByteWriteEnable
Symbol Pin Name
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC No Connect
DQa-DQd DataInputs/Outputs
DQPa-Pd OutputPowerSupply
Vd d PowerSupply
Vd d q OutputPowerSupply
Vss Ground
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
Integrated Silicon Solution, Inc.5
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
119 BGA PACKAGE PIN CONFIGURATION
512kx18 (TOP VIEW)
PIN DESCRIPTIONS
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7
AVDDQ A A ADSP A A VDDQ
BNC CE2 AADSC A A NC
CNC A A VDD A A NC
DDQb NC Vss NC Vss DQPa NC
ENC DQb Vss CE Vss NC DQa
FVDDQ NC Vss OE Vss DQa VDDQ
GNC DQb BWb ADV Vss NC DQa
HDQb NC Vss GW Vss DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb Vss CLK Vss NC DQa
LDQb NC Vss NC BWa DQa NC
MVDDQ DQb Vss BWE Vss NC VDDQ
NDQb NC Vss A1* Vss DQa NC
PNC DQPb Vss A0* Vss NC DQa
RNC A MODE VDD NC A NC
TNC A A NC A A ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP AddressStatusProcessor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE,CE2 Synchronous Chip Select
BWx(x=a,b) SynchronousByteWriteControls
BWE ByteWriteEnable
Symbol Pin Name
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC No Connect
DQa-DQb DataInputs/Outputs
DQPa-Pb OutputPowerSupply
Vd d PowerSupply
Vd d q OutputPowerSupply
Vss Ground
6 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
256k x 36 (TOP VIEW)
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWc BWb CE2 BWE ADSC ADV A NC
BNC A CE2 BWd BWa CLK GW OE ADSP A NC
CDQPc NC Vd d q Vss Vss Vss Vss Vss Vd d q Nc DQPb
DDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
EDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
FDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
GDQc DQc Vd d q Vd d Vss Vss Vss Vd d Vd d q DQb DQb
HNC Vss NC Vd d Vss Vss Vss Vd d Nc Nc ZZ
JDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
KDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
LDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
MDQd DQd Vd d q Vd d Vss Vss Vss Vd d Vd d q dqadqa
NDQPd NC Vd d q Vss NC NC NC Vss Vd d q NC DQPa
PNC NC A A TDI A1*TDO A A A A
RMODE NC A A TMS A0* TCK A A A A
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP AddressStatusProcessor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b,c,d) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
Integrated Silicon Solution, Inc. 7
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
165 PBGA PACKAGE PIN CONFIGURATION
512k x 18 (TOP VIEW)
PIN DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11
ANC A CE BWb NC CE2 BWE ADSC ADV A A
BNC A CE2 NC BWa CLK GW OE ADSP A NC
CNC NC Vd d q Vss Vss Vss Vss Vss Vd d q Nc DQPa
DNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
ENC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
FNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
GNC DQb Vd d q Vd d Vss Vss Vss Vd d Vd d q NC DQa
HNC Vss NC Vd d Vss Vss Vss Vd d Nc Nc ZZ
JDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
KDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
LDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
MDQb NC Vd d q Vd d Vss Vss Vss Vd d Vd d q dqaNc
NDQPb NC Vd d q Vss NC NC NC Vss Vd d q NC NC
PNC NC A A TDI A1*TDO A A A A
RMODE NC A A TMS A0* TCK A A A A
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP AddressStatusProcessor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
TCK,TDO JTAGPins
TMS,TDI
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
8 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
SynchronousProcessorAddressStatus
ADV
SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE, CE2, CE2 SynchronousChipEnable
CLK Synchronous Clock
DQa-DQd SynchronousDataInput/Output
DQPa-DQPd ParityDataInput/Output
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE OutputEnable
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputBufferSupply:
3.3V/2.5V
Vss Ground
ZZ SnoozeEnable
PIN CONFIGURATION
(3 Chip-Enable option)
100-PIN TQFP (256K X 36)
DQPb
DQb
DQb
V
DD
Q
VSS
DQb
DQb
DQb
DQb
VSS
V
DD
Q
DQb
DQb
VSS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
VSS
DQa
DQa
DQa
DQa
VSS
V
DD
Q
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
A
V
DD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
V
DD
Q
VSS
DQc
DQc
DQc
DQc
VSS
V
DD
Q
DQc
DQc
NC
V
DD
NC
VSS
DQd
DQd
V
DD
Q
VSS
DQd
DQd
DQd
DQd
VSS
V
DD
Q
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
(2 Chip-Enable option)
Integrated Silicon Solution, Inc. 9
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
PIN CONFIGURATION
(3 Chip-Enable Option)
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
SynchronousProcessorAddressStatus
ADV
SynchronousBurstAddressAdvance
BWa-BWb SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE,CE2,CE2 SynchronousChipEnable
CLK Synchronous Clock
DQa-DQb SynchronousDataInput/Output
DQPa-DQPb ParityDataI/O;DQPaisparityfor
DQa1-8;DQPbisparityforDQb1-8
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE OutputEnable
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputBufferSupply:
3.3V/2.5V
Vss Ground
ZZ SnoozeEnable
100-PIN TQFP (512K X 18)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
A
A
A
A
A
A
A
A
46 47 48 49 50
(2 Chip-Enable Option)
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
CE
CE2
NC
NC
BWb
BWa
A
V
DD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
NC
VSS
V
DD
NC
NC
A
A
A
A
A
A
A
46 47 48 49 50
10 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
PARTIAL TRUTH TABLE
Function GW BWE BWa BWb BWc BWd
Read H H X X X X
Read H L H H H H
WriteByte1 H L L H H H
WriteAllBytes H L L L L L
WriteAllBytes L X X X X X
TRUTH TABLE(1-8)
OPERATION ADDRESS
CE CE2
CE2 ZZ
ADSP ADSC ADV WRITE OE
CLK DQ
DeselectCycle,Power-Down None H X X L X L X X X L-H High-Z
DeselectCycle,Power-Down None L X L L L X X X X L-H High-Z
DeselectCycle,Power-Down None L H X L L X X X X L-H High-Z
DeselectCycle,Power-Down None L X L L H L X X X L-H High-Z
DeselectCycle,Power-Down None L H X L H L X X X L-H High-Z
SnoozeMode,Power-Down None X X X H X X X X X X High-Z
ReadCycle,BeginBurst External L L H L L X X X L L-H Q
ReadCycle,BeginBurst External L L H L L X X X H L-H High-Z
WriteCycle,BeginBurst External L L H L H L X L X L-H D
ReadCycle,BeginBurst External L L H L H L X H L L-H Q
ReadCycle,BeginBurst External L L H L H L X H H L-H High-Z
ReadCycle,ContinueBurst Next X X X L H H L H L L-H Q
ReadCycle,ContinueBurst Next X X X L H H L H H L-H High-Z
ReadCycle,ContinueBurst Next H X X L X H L H L L-H Q
ReadCycle,ContinueBurst Next H X X L X H L H H L-H High-Z
WriteCycle,ContinueBurst Next X X X L H H L L X L-H D
WriteCycle,ContinueBurst Next H X X L X H L L X L-H D
ReadCycle,SuspendBurst Current X X X L H H H H L L-H Q
ReadCycle,SuspendBurst Current X X X L H H H H H L-H High-Z
ReadCycle,SuspendBurst Current H X X L X H H H L L-H Q
ReadCycle,SuspendBurst Current H X X L X H H H H L-H High-Z
WriteCycle,SuspendBurst Current X X X L H H H L X L-H D
WriteCycle,SuspendBurst Current H X X L X H H L X L-H D
NOTE:
1. Xmeans“Don’tCare.”HmeanslogicHIGH.LmeanslogicLOW.
2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWEareLOWorGWisLOW.WRITE = H for all
BWx, BWE, GWHIGH.
3. BWaenablesWRITEstoDQa’sandDQPa.BWbenablesWRITEstoDQb’sandDQPb.BWcenablesWRITEstoDQc’s and
DQPc.BWdenablesWRITEstoDQd’sandDQPd.DQPaandDQPbareavailableonthex18version. DQPa-DQPdareavail-
ableonthex36version.
4. AllinputsexceptOEandZZmustmeetsetupandholdtimesaroundtherisingedge(LOWtoHIGH)ofCLK.
5. Waitstatesareinsertedbysuspendingburst.
6. ForaWRITEoperationfollowingaREADoperation,OEmustbeHIGHbeforetheinputdatasetuptimeandheldHIGHduring
the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSPLOWalwaysinitiatesaninternalREADattheL-HedgeofCLK.AWRITEisperformedbysettingoneormorebytewrite
enable signals and BWELOWorGWLOWforthesubsequentL-HedgeofCLK.SeeWRITEtimingdiagramforclarication.
Integrated Silicon Solution, Inc. 11
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
INTERLEAVED BURST ADDRESS TABLE (MODE = VD D or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = VSS)
0,0
1,0
0,1A1', A0' = 1,1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Ts T g StorageTemperature –55to+150 °C
Pd PowerDissipation 1.6 W
IO u T OutputCurrent(perI/O) 100 mA
VI N , VO u T VoltageRelativetoVssforI/OPins –0.5toVd d q + 0.5 V
VI N VoltageRelativetoVssfor –0.5toVd d + 0.5 V
for Address and Control Inputs
Vd d Voltage on Vd d SupplyRelativetoVss –0.5to4.6 V
Notes:
1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycauseperma-
nent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specicationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
orelectric elds;however, precautions maybe takentoavoid application of anyvoltage
higher than maximum rated voltages to this high-impedance circuit.
3.ThisdevicecontainscircuitrythatwillensuretheoutputdevicesareinHigh-Zatpowerup.
12 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
POWER SUPPLY CHARACTERISTICS(1) (OverOperatingRange)
6.5
7.5
MAX MAX
Symbol Parameter Test Conditions
Temp. range x18 x36 x18 x36 Uni
t
Ic c ACOperating DeviceSelected, Com. 185 185 175 175 mA
Supply Current OE = VI h , ZZ ≤ VI l , Ind. 190 190 185 185
All Inputs ≤ 0.2V or ≥ Vd d – 0.2V, Au T O . 225 225
Cycle Time ≥ tk c min.
Is b StandbyCurrent DeviceDeselected, Com. 140 140 140 140 mA
TTL Input Vd d = Max., Ind. 150 150 150 150
All Inputs ≤ VI l or ≥ VI h , Au T O . 150 150
ZZ ≤ VI l , f=Max.
Is b I StandbyCurrent DeviceDeselected, Com. 80 80 80 80 mA
cMOs Input Vd d = Max., Ind. 85 85 85 85
VI N
≤
Vs s +0.2Vor≥Vd d – 0.2V Auto. 90 90
f = 0
Note:
1. MODEpinhasaninternalpullupandshouldbetiedtoVd d or Vs s . It exhibits ±100 µA maximum leakage current when tied to ≤ Vs s +0.2Vor≥ Vd d – 0.2V.
DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)
3.3V 2.5V
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
VO h OutputHIGHVoltage IO h = –4.0mA (3.3V) 2.4 — 2.0 — V
IO h = –1.0 mA (2.5V)
VO l OutputLOWVoltage IO l = 8.0mA (3.3V) — 0.4 — 0.4 V
IO l = 1.0 mA (2.5V)
VI h InputHIGHVoltage 2.0 Vd d + 0.3 1.7 Vd d + 0.3 V
VI l InputLOWVoltage –0.3 0.8 –0.3 0.7 V
Il I Input Leakage Current Vs s ≤ VI N ≤ Vd d (1) –5 5 –5 5 µA
Il O OutputLeakageCurrent Vs s ≤ VO u T ≤ Vd d q , OE = VI h –5 5 –5 5 µA
OPERATING RANGE (IS61LFxxxxx)
Range Ambient Temperature VD D VD D q
Commercial 0°Cto+70°C 3.3V±5% 3.3V/2.5V±5%
Industrial -40°Cto+85°C 3.3V±5% 3.3V/2.5V±5%
OPERATING RANGE (IS61VFxxxxx)
Range Ambient Temperature VD D VD D q
Commercial 0°Cto+70°C 2.5V±5% 2.5V±5%
Industrial -40°Cto+85°C 2.5V±5% 2.5V±5%
OPERATING RANGE (IS64LFxxxxx)
Range Ambient Temperature VD D VD D q
Automotive -40°Cto+125°C 3.3V±5% 3.3V/2.5V±5%
Integrated Silicon Solution, Inc. 13
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
cI N Input Capacitance VI N = 0V 6 pF
cO u T Input/OutputCapacitance VO u T = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°c, f=1MHz,Vd d =3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto3.0V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.5V
and Reference Level
OutputLoad SeeFigures1and2
AC TEST LOADS
Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1
OUTPUT
ZO
= 50Ω
1.5V
50Ω
14 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
2.5V I/O AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto2.5V
InputRiseandFallTimes 1.5ns
InputandOutputTiming 1.25V
and Reference Level
OutputLoad SeeFigures3and4
Z
O
= 50Ω
1.25V
50Ω
OUTPUT
Figure 3 Figure 4
2.5V I/O OUTPUT LOAD EQUIVALENT
Integrated Silicon Solution, Inc. 15
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (OverOperatingRange)
6.5 7.5
Symbol Parameter Min. Max. Min. Max. Unit
fmax ClockFrequency — 133 — 117 MHz
tk c CycleTime 7.5 — 8.5 — ns
tk h ClockHighTime 2.2 — 2.5 — ns
tk l ClockLowTime 2.2 — 2.5 — ns
tk q ClockAccessTime — 6.5 — 7.5 ns
tk q x (2) ClockHightoOutputInvalid 2.5 — 2.5 — ns
tk q l Z (2,3) ClockHightoOutputLow-Z 2.5 — 2.5 — ns
tk q h Z (2,3) ClockHightoOutputHigh-Z — 3.8 — 4.0 ns
tO E q OutputEnabletoOutputValid — 3.2 — 3.4 ns
tO E l Z (2,3) OutputEnabletoOutputLow-Z 0 — 0 — ns
tO E h Z (2,3) OutputDisabletoOutputHigh-Z — 3.5 — 3.5 ns
tA s AddressSetupTime 1.5 — 1.5 — ns
ts s AddressStatusSetupTime 1.5 — 1.5 — ns
tW s Read/WriteSetupTime 1.5 — 1.5 — ns
tc E s ChipEnableSetupTime 1.5 — 1.5 — ns
tA V s AddressAdvanceSetupTime 1.5 — 1.5 — ns
td s DataSetupTime 1.5 — 1.5 — ns
tA h Address Hold Time 0.5 — 0.5 — ns
ts h Address Status Hold Time 0.5 — 0.5 — ns
tW h WriteHoldTime 0.5 — 0.5 — ns
tc E h ChipEnableHoldTime 0.5 — 0.5 — ns
tA V h AddressAdvanceHoldTime 0.5 — 0.5 — ns
td h DataHoldTime 0.5 — 0.5 — ns
Notes:
1. CongurationsignalMODEisstaticandmustnotchangeduringnormaloperation.
2. Guaranteedbutnot100%tested.Thisparameterisperiodicallysampled.
3. TestedwithloadinFigure2.
16 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
READ/WRITE CYCLE TIMING
Single Read
Flow-through
Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWd-BWa
BWE
GW
Address
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
tKQX
tKC
tKLtKH
tSS tSH ADSP is blocked by CE inactive
tSS tSH
tAS tAH
tWS tWH
tWS tWH
tWS tWH
RD2 RD3
tCES tCEH
tCES tCEH
tCES tCEH
tOEQ
tOELZ
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
tKQ
tOEHZ
tDS tDH
tKQHZ
tKQLZ
High-Z
tKQLZ
tKQ
tKQX
Integrated Silicon Solution, Inc. 17
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BWd-BWa
BWE
GW
Address
ADV
ADSC
ADSP
CLK
WR1WR2
Unselected
Burst Write
t
KC
tKLtKH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
WR3
t
CES tCEH
tCES tCEH
tCES tCEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
tAVS
ADV must be inactive for ADSP Write
WR1WR2
t
WS tWH
WR3
t
WS tWH
High-Z
High-Z 1a 3a
t
DS tDH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
18 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
SNOOZE MODE TIMING
Don't Care
Deselect or Read Only Deselect or Read Only
tRZZI
CLK
ZZ
Isupply
All Inputs
(except ZZ)
Outputs
(Q)
ISB2
ZZ setup cycle ZZ recovery cycle
Normal
operation
cycle
tPDS tPUS
tZZI
High-Z
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter Conditions Temp. Range Min. Max. Unit
Is b 2 CurrentduringSNOOZEMODE ZZ≥Vih Com. — 55 mA
Ind. — 60
Auto. — 75
tP d s ZZactivetoinputignored — 2 cycle
tP u s ZZinactivetoinputsampled 2 — cycle
tZ Z I ZZactivetoSNOOZEcurrent — 2 cycle
tr Z Z I ZZinactivetoexitSNOOZEcurrent 0 — ns
Integrated Silicon Solution, Inc. 19
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IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61LF/VF25636A and IS61LF/VF51218A have a
serialboundaryscanTestAccessPort(TAP)inthePBGA
package only. This port operates in accordance with
IEEE
Standard1149.1-1900,butdoesnotincludeallfunctions
requiredforfull1149.1compliance.Thesefunctionsfrom
the
IEEE specication
are excluded because they place
addeddelayinthecriticalspeedpathoftheSRAM.The
TAPcontrolleroperatesinamannerthatdoesnotconict
withtheperformanceofotherdevicesusing1149.1fully
compliantTAPs.TheTAPoperatesusingJEDECstandard
2.5VI/Ologiclevels.
DISABLING THE JTAG FEATURE
TheSRAMcanoperatewithoutusingtheJTAGfeature.
To disable the TAP controller, TCK must be tied LOW
(Vss)topreventclockingofthedevice.TDIandTMSare
internally pulled up and may be disconnected. They may
alternately be connected to Vd d through a pull-up resistor.
TDOshouldbeleftdisconnected.Onpower-up,thedevice
will start in a reset state which will not interfere with the
device operation.
TEST ACCESS PORT (TAP) - TEST CLOCK
ThetestclockisonlyusedwiththeTAPcontroller.Allinputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
TheTMS input is used to send commands to theTAP
controller and is sampled on the rising edge of TCK. This
pinmaybeleftdisconnectediftheTAPisnotused.Thepin
isinternallypulledup,resultinginalogicHIGHlevel.
TEST DATA-IN (TDI)
TheTDI pin is used to serially input information to the
registers and can be connected to the input of any regis-
ter.TheregisterbetweenTDIandTDOischosenbythe
instruction loaded into theTAP instruction register. For
informationoninstructionregisterloading,seetheTAP
ControllerStateDiagram.TDIisinternallypulledupand
canbedisconnectediftheTAPisunusedinanapplica-
tion.TDIisconnectedtotheMostSignicantBit(MSB)
on any register.
31 30 29 . . . 2 1 0
2 1 0
0
x . . . . . 2 1 0
Bypass Register
Instruction Register
Identification Register
Boundary Scan
Register*
TAP CONTROLLER
Selection Circuitry Selection Circuitry TDOTDI
TCK
TMS
TAP CONTROLLER BLOCK DIAGRAM
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TEST DATA OUT (TDO)
TheTDOoutputpinisusedtoseriallyclockdata-outfrom
the registers. The output is active depending on the current
state of the
TAP
state machine (see
TAP
Controller State
Diagram).TheoutputchangesonthefallingedgeofTCK
andTDOisconnectedtotheLeastSignicantBit(LSB)
of any register.
PERFORMING A TAP RESET
AResetisperformedbyforcingTMSHIGH(Vd d ) for five
risingedgesofTCK.RESETmaybeperformedwhilethe
SRAMisoperatinganddoesnotaffectitsoperation.At
power-up,theTAPisinternallyresettoensurethatTDO
comes up in a high-Z state.
TAP REGISTERS
RegistersareconnectedbetweentheTDIandTDOpins
andallowdatatobescannedintoandoutoftheSRAM
test circuitry. Onlyoneregistercanbeselectedatatime
throughtheinstructionregisters.Dataisseriallyloaded
intotheTDIpinontherisingedgeofTCKandoutputon
theTDOpinonthefallingedgeofTCK.
Instruction Register
Three-bit instructions can be serially loaded into the in-
struction register. This register is loaded when it is placed
between the
TDI
and
TDO
pins. (See
TAP
ControllerBlock
Diagram) Atpower-up,theinstructionregisterisloaded
with the IDCODE instruction. It is also loaded with the
IDCODEinstructionifthecontrollerisplacedinareset
state as previously described.
WhentheTAPcontrollerisintheCaptureIRstate,thetwo
leastsignicantbitsareloadedwithabinary“01”patternto
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
betweenTDIandTDOpins.Thisallowsdatatobeshifted
through the
SRAM
with minimal delay. The bypass reg-
isterissetLOW(Vss)whentheBYPASS instructionis
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the
SRAM
. Several no connect
(NC)
pins are
also included in the scan register to reserve pins for higher
densitydevices.Thex36congurationhasa75-bit-long
registerandthex18congurationalsohasa75-bit-long
register. The boundary scan register is loaded with the
contentsoftheRAMInputandOutputringwhentheTAP
controllerisintheCapture-DRstateandthenplacedbe-
tween the
TDI
and
TDO
pins when the controller is moved
to the
Shift-DR
state.TheEXTEST,SAMPLE/PRELOAD
andSAMPLE-Zinstructionscanbeusedtocapturethe
contentsoftheInputandOutputring.
TheBoundaryScanOrdertablesshowtheorderinwhich
thebitsareconnected.Eachbitcorrespondstooneofthe
bumpsontheSRAMpackage.TheMSBoftheregisteris
connectedtoTDI,andtheLSBisconnectedtoTDO.
Identification (ID) Register
The ID register is loaded with a vendor-specic, 32-bit
codeduringtheCapture-DRstatewhentheIDCODEcom-
mandisloadedtotheinstructionregister.TheIDCODE
ishardwiredintotheSRAMandcanbeshiftedoutwhen
theTAPcontrollerisintheShift-DRstate.TheIDregister
has vendor code and other information described in the
IdenticationRegisterDenitionstable.
Scan Register Sizes
Register Name Bit Size Bit Size
(x18) (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
BoundaryScan 75 75
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Description 256K x 36 512K x 18
RevisionNumber (31:28) Reservedforversionnumber. xxxx xxxx
DeviceDepth (27:23) DenesdepthofSRAM.256Kor512K 00111 01000
DeviceWidth (22:18) DeneswithoftheSRAM.x36orx18 00100 00011
ISSIDeviceID (17:12) Reservedforfutureuse. xxxxx xxxxx
ISSIJEDECID (11:1) AllowsuniqueidenticationofSRAMvendor. 00011010101 00011010101
IDRegisterPresence (0) IndicatethepresenceofanIDregister. 1 1
Integrated Silicon Solution, Inc. 21
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TAP INSTRUCTION SET
Eightinstructionsarepossiblewiththethree-bitinstruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as
RESERVED
and should not be used and the other five instructions are
describedbelow.TheTAPcontrollerusedinthisSRAM
isnotfullycompliantwiththe1149.1conventionbecause
some mandatory instructions are not fully implemented.
TheTAPcontrollercannotbeusedtoloadaddress,dataor
control signals and cannot preload the
Input
or
Output
buf-
fers. The
SRAM
does not implement the
1149.1
commands
EXTEST
or
INTEST
or the
PRELOAD
portion of
SAMPLE/
PRELOAD
;insteaditperformsacaptureofthe
Inputs and
Output
ring when these instructions are executed. Instruc-
tionsareloadedintotheTAPcontrollerduringtheShift-IR
statewhentheinstructionregisterisplacedbetweenTDI
andTDO.Duringthisstate,instructionsareshiftedfrom
theinstructionregisterthroughtheTDIandTDOpins.To
executeaninstructiononceitisshiftedin,theTAPcontrol-
lermustbemovedintotheUpdate-IRstate.
EXTEST
EXTESTisamandatory1149.1instructionwhichistobe
executed whenever the instruction register is loaded with
all0s.BecauseEXTESTisnotimplementedintheTAP
controller,thisdeviceisnot1149.1standardcompliant.
TheTAPcontrollerrecognizesanall-0instruction.Whenan
EXTESTinstructionisloadedintotheinstructionregister,
theSRAMrespondsasifaSAMPLE/PRELOADinstruction
has been loaded. There is a difference between the instruc-
tions, unlike the
SAMPLE/PRELOAD
instruction,EXTEST
placestheSRAMoutputsinaHigh-Zstate.
IDCODE
The IDCODE instruction causes a vendor-specic, 32-
bit code to be loaded into the instruction register. It also
placestheinstructionregisterbetweentheTDIandTDO
pinsandallowstheIDCODEtobeshiftedoutofthedevice
when theTAP controller enters the Shift-DR state.The
IDCODEinstructionisloadedintotheinstructionregister
uponpower-uporwhenevertheTAPcontrollerisgivena
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
registertobeconnectedbetweentheTDIandTDOpins
whentheTAPcontrollerisinaShift-DRstate.Italsoplaces
allSRAMoutputsintoaHigh-Zstate.
SAMPLE/PRELOAD
SAMPLE/PRELOADisa1149.1mandatoryinstruction.The
PRELOADportionofthisinstructionisnotimplemented,so
theTAPcontrollerisnotfully1149.1compliant.Whenthe
SAMPLE/PRELOADinstructionisloadedtotheinstruc-
tionregisterandtheTAPcontrollerisintheCapture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
ItisimportanttorealizethattheTAPcontrollerclockoper-
atesatafrequencyupto10MHz,whiletheSRAMclock
runsmorethananorderofmagnitudefaster.Becauseof
theclockfrequencydifferences,itispossiblethatduring
theCapture-DRstate,aninputoroutputwillunder-goa
transition.TheTAPmayattemptasignalcapturewhilein
transition (metastable state). The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
thecorrectsignalvalue,theSRAMsignalmustbestabilized
longenoughtomeettheTAPcontroller’scaptureset-up
plus hold times (tc s and tc h ).ToinsurethattheSRAMclock
input is captured correctly, designs need a way to stop (or
slow)theclockduringaSAMPLE/PRELOADinstruction.
If this is not an issue, it is possible to capture all other
signals and simply ignore the value of the CLK and CLK
captured in the boundary scan register.
Oncethedataiscaptured,itispossibletoshiftoutthedata
byputtingtheTAPintotheShift-DRstate.Thisplacesthe
boundaryscanregisterbetweentheTDIandTDOpins.
Note that since the
PRELOAD
part of the command is not
implemented, putting the
TAP
into the
Update
to the
Update-
DR
state while performing a
SAMPLE/PRELOAD
instruction
willhavethesameeffectasthePause-DRcommand.
BYPASS
When the BYPASS instruction is loaded in the instruc-
tionregister and theTAP isplaced in aShift-DR state,
thebypassregisterisplacedbetweentheTDIandTDO
pins.TheadvantageoftheBYPASSinstructionisthatit
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
forfutureuse.Donotusetheseinstructions.
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INSTRUCTION CODES
Code Instruction Description
000 EXTEST CapturestheInput/Outputringcontents.Placestheboundaryscanregisterbe-
tweentheTDIandTDO.ForcesallSRAMoutputstoHigh-Zstate.This
instructionisnot1149.1compliant.
001 IDCODE LoadstheIDregisterwiththevendorIDcodeandplacestheregisterbetweenTDI
andTDO.ThisoperationdoesnotaffectSRAMoperation.
010 SAMPLE-Z CapturestheInput/Outputcontents.Placestheboundaryscanregisterbetween
TDIandTDO.ForcesallSRAMoutputdriverstoaHigh-Zstate.
011 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
100
SAMPLE/PRELOAD
CapturestheInput/Outputringcontents.Placestheboundaryscanregister
between
TDIandTDO.DoesnotaffecttheSRAMoperation.Thisinstructiondoesnot
implement1149.1preloadfunctionandisthereforenot1149.1compliant.
101 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
110 RESERVED DoNotUse:Thisinstructionisreservedforfutureuse.
111 BYPASS PlacesthebypassregisterbetweenTDIandTDO.Thisoperationdoesnot
affectSRAMoperation.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test/Idle 11 1
11
11
1
1
11
11
1
0
0
0
0
1
00
0
0
0
0
0
0
0
0
0
10
TAP CONTROLLER STATE DIAGRAM
Integrated Silicon Solution, Inc. 23
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IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
TAP Electrical Characteristics OvertheOperatingRange(1,2)
Symbol Parameter Test Conditions Min. Max. Units
VO h 1 OutputHIGHVoltage IO h = –2.0 mA 1.7 — V
VO h 2 OutputHIGHVoltage IO h = –100 µA 2.1 — V
VO l 1 OutputLOWVoltage IO l = 2.0 mA — 0.7 V
VO l 2 OutputLOWVoltage IO l = 100 µA — 0.2 V
VI h InputHIGHVoltage 1.7 Vd d +0.3 V
VI l InputLOWVoltage IO l T = 2mA –0.3 0.7 V
Ix Input Load Current Vss ≤ V I ≤ Vd d q –5 5 mA
Notes:
1. AllVoltagereferencedtoGround.
2. Overshoot:VI h (AC) ≤ Vd d +1.5Vfort≤ tT c y c /2,
Undershoot:Vil(AC)≤0.5Vfort≤ tT c y c /2,
Power-up:VI h < 2.6V and Vd d <2.4VandVd d q <1.4Vfort<200ms.
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter Min. Max. Unit
tT c y c TCK Clock cycle time 100 — ns
fT f TCKClockfrequency — 10 MHz
tT h TCKClockHIGH 40— ns
tT l TCKClockLOW 40 — ns
tT M s s TMSsetuptoTCKClockRise 10 — ns
tT d I s TDIsetuptoTCKClockRise 10 — ns
tc s Capture setup to TCK Rise 10 — ns
tT M s h
TMSholdafterTCKClockRise
10 — ns
tT d I h TDIHoldafterClockRise 10 — ns
tc h Capture hold after Clock Rise 10 — ns
tT d O V TCKLOWtoTDOvalid — 20 ns
tT d O x TCKLOWtoTDOinvalid 0 — ns
Notes:
1. Both tc s and tc h refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specied using the load in TAP AC test conditions. tr/tf = 1 ns.
24 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
DON'T CARE
UNDEFINED
TCK
TMS
TDI
TDO
tTHTL
tTLTH
tTHTH
tMVTH tTHMX
tDVTH tTHDX
1 2 3 4 5 6
tTLOX
tTLOV
TAP TIMING
20 pF
TDO
GND
50Ω
1.25V/1.5V
Z
0
= 50Ω
TAP Output Load Equivalent
TAP AC TEST CONDITIONS
Inputpulselevels 0to2.5V/0to3.0V
Input rise and fall times 1ns
Inputtimingreferencelevels 1.25V/1.5V
Outputreferencelevels 1.25V/1.5V
Testloadterminationsupplyvoltage 1.25V/1.5V
Integrated Silicon Solution, Inc. 25
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
119 BGA BOUNDARY SCAN ORDER (256K X 36)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID
1 A 2R 19 DQb 7G 37 BWa 5L 55 DQd 2K
2 A 3T 20 DQb 6F 38 BWb 5G 56 DQd 1L
3 A 4T 21 DQb 7E 39 BWc 3G 57 DQd 2M
4 A 5T 22 DQb 7D 40 BWd 3L 58 DQd 1N
5 A 6R 23 DQb 7H 41 CE2 2B 59 DQd 1P
6 A 3B 24 DQb 6G 42 CE 4E 60 DQd 1K
7 A 5B 25 DQb 6E 43 A 3A 61 DQd 2L
8 DQa 6P 26 DQb 6D 44 A 2A 62 DQd 2N
9 DQa 7N 27 A 6A 45 DQc 2D 63 DQd 2P
10 DQa 6M 28 A 5A 46 DQc 1E 64 MODE 3R
11 DQa 7L 29 ADV 4G 47 DQc 2F 65 A 2C
12 DQa 6K 30 ADSP 4A 48 DQc 1G 66 A 3C
13 DQa 7P 31 ADSC 4B 49 DQc 2H 67 A 5C
14 DQa 6N 32 OE 4F 50 DQc 1D 68 A 6C
15 DQa 6L 33 BWE 4M 51 DQc 2E 69 A1 4N
16 DQa 7K 34 GW 4H 52 DQc 2G 70 A0 4P
17 ZZ 7T 35 CLK 4K 53 DQc 1H
18 DQb 6H 36 A 6B 54 NC 5R
119 BGA BOUNDARY SCAN ORDER (512K X 18)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID
1 A 2R 14 DQa 7G 27 CLK 4K 40 DQb 2K
2 A 2T 15 DQa 6F 28 A 6B 41 DQb 1L
3 A 3T 16 DQa 7E 29 BWa 5L 42 DQb 2M
4 A 5T 17 DQa 6D 30 BWb 3G 43 DQb 1N
5 A 6R 18 A 6T 31 CE2 2B 44 DQb 2P
6 A 3B 19 A 6A 32 CE 4E 45 MODE 3R
7 A 5B 20 A 5A 33 A 3A 46 A 2C
8 DQa 7P 21 ADV 4G 34 A 2A 47 A 3C
9 DQa 6N 22 ADSP 4A 35 DQb 1D 48 A 5C
10 DQa 6L 23 ADSC 4B 36 DQb 2E 49 A 6C
11 DQa 7K 24 OE 4F 37 DQb 2G 50 A1 4N
12 ZZ 7T 25 BWE 4M 38 DQb 1H 51 A0 4P
13 DQa 6H 26 GW 4H 39 NC 5R
26 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
165 PBGA BOUNDARY SCAN ORDER (x 36)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID
1 MODE 1R 21 DQb 11G 41 NC 1A 61 DQd 1J
2 NC 6N 22 DQb 11F 42 CE2 6A 62 DQd 1K
3 A 11P 23 DQb 11E 43 BWa 5B 63 DQd 1L
4 A 8P 24 DQb 11D 44 BWb 5A 64 DQd 1M
5 A 8R 25 DQb 10G 45 BWc 4A 65 DQd 2J
6 A 9R 26 DQb 10F 46 BWd 4B 66 DQd 2K
7 A 9P 27 DQb 10E 47 CE2 3B 67 DQd 2L
8 A 10P 28 DQb 10D 48 CE 3A 68 DQd 2M
9 A 10R 29 DQb 11C 49 A 2A 69 DQd 1N
10 A 11R 30 NC 11A 50 A 2B 70 A 3P
11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R
12 DQa 11N 32 A 10B 52 DQc 1C 72 A 4R
13 DQa 11M 33 ADV 9A 53 DQc 1D 73 A 4P
14 DQa 11L 34 ADSP 9B 54 DQc 1E 74 A1 6P
15 DQa 11K 35 ADSC 8A 55 DQc 1F 75 A0 6R
16 DQa 11J 36 OE 8B 56 DQc 1G
17 DQa 10M 37 BWE 7A 57 DQc 2D
18 DQa 10L 38 GW 7B 58 DQc 2E
19 DQa 10K 39 CLK 6B 59 DQc 2F
20 DQa 10J 40 NC 11B 60 DQc 2G
Integrated Silicon Solution, Inc. 27
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
165 PBGA BOUNDARY SCAN ORDER (x 18)
Signal Bump Signal Bump Signal Bump Signal Bump
Bit # Name ID Bit # Name ID Bit # Name ID Bit # Name ID
1 MODE 1R 21 DQa 11G 41 NC 1A 61 DQb 1J
2 NC 6N 22 DQa 11F 42 CE2 6A 62 DQb 1K
3 A 11P 23 DQa 11E 43 BWa 5B 63 DQb 1L
4 A 8P 24 DQa 11D 44 NC 5A 64 DQb 1M
5 A 8R 25 DQa 11C 45 BWb 4A 65 DQb 1N
6 A 9R 26 NC 10F 46 NC 4B 66 NC 2K
7 A 9P 27 NC 10E 47 CE2 3B 67 NC 2L
8 A 10P 28 NC 10D 48 CE 3A 68 NC 2M
9 A 10R 29 NC 10G 49 A 2A 69 NC 2J
10 A 11R 30 A 11A 50 A 2B 70 A 3P
11 ZZ 11H 31 A 10A 51 NC 1B 71 A 3R
12 NC 11N 32 A 10B 52 NC 1C 72 A 4R
13 NC 11M 33 ADV 9A 53 NC 1D 73 A 4P
14 NC 11L 34 ADSP 9B 54 NC 1E 74 A1 6P
15 NC 11K 35 ADSC 8A 55 NC 1F 75 A0 6R
16 NC 11J 36 OE 8B 56 NC 1G
17 DQa 10M 37 BWE 7A 57 DQb 2D
18 DQa 10L 38 GW 7B 58 DQb 2E
19 DQa 10K 39 CLK 6B 59 DQb 2F
20 DQa 10J 40 NC 11B 60 DQb 2G
28 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
ORDERING INFORMATION (VD D = 3.3V/VD D q = 2.5V/3.3V)
Commercial Range: 0°C to +70°C
Configuration Access Time Order Part Number Package(1)
256Kx36 6.5 IS61LF25636A-6.5TQ 100TQFP,3CE
IS61LF25636A-6.5B2 119PBGA
IS61LF25636A-6.5B3 165PBGA
256Kx36 7.5 IS61LF25636A-7.5TQ 100TQFP,3CE
IS61LF25636A-7.5B2 119PBGA
IS61LF25636A-7.5B3 165PBGA
512Kx18 6.5 IS61LF51218A-6.5TQ 100TQFP,3CE
IS61LF51218A-6.5TQL 100TQFP,3CE,Lead-free
IS61LF51218A-6.5B2 119PBGA
IS61LF51218A-6.5B3 165PBGA
512Kx18 7.5 IS61LF51218A-7.5TQ 100TQFP,3CE
IS61LF51218A-7.5B2 119PBGA
IS61LF51218A-7.5B3 165PBGA
Industrial Range: -40°C to +85°C
Configuration Access Time Order Part Number Package(1)
256Kx36 6.5 IS61LF25636A-6.5TQI 100TQFP,3CE
IS61LF25636A-6.5B2I 119PBGA
IS61LF25636A-6.5B3I 165PBGA
256Kx36 7.5 IS61LF25636A-7.5TQI 100TQFP,3CE
IS61LF25636A-7.5TQLI 100TQFP,3CE,Lead-free
IS61LF25636A-7.5B2I 119PBGA
IS61LF25636A-7.5B3I 165PBGA
512Kx18 6.5 IS61LF51218A-6.5TQI 100TQFP,3CE
IS61LF51218A-6.5B2I 119PBGA
IS61LF51218A-6.5B3I 165PBGA
512Kx18 7.5 IS61LF51218A-7.5TQI 100TQFP,3CE
IS61LF51218A-7.5TQLI 100TQFP,3CE,Lead-free
IS61LF51218A-7.5B2I 119PBGA
IS61LF51218A-7.5B3I 165PBGA
Note:
1.For100TQFP,2CEoptioncontactSRAMMarketingatsram@issi.com
Automotive Range: -40°C to +125°C
Configuration Access Time Order Part Number Package(1)
256Kx36 7.5 IS64LF25636A-7.5TQLA3 100TQFP,3CE,Lead-free
IS64LF25636A-7.5BLA3 165PBGA,Lead-free
Integrated Silicon Solution, Inc. 29
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
ORDERING INFORMATION (VD D = 2.5V /VD D q = 2.5V)
Commercial Range: 0°C to +70°C
Configuration Access Time Order Part Number Package(1)
256Kx36 6.5 IS61VF25636A-6.5TQ 100TQFP,3CE
IS61VF25636A-6.5B2 119PBGA
IS61VF25636A-6.5B3 165PBGA
256Kx36 7.5 IS61VF25636A-7.5TQ 100TQFP,3CE
IS61VF25636A-7.5B2 119PBGA
IS61VF25636A-7.5B3 165PBGA
512Kx18 6.5 IS61VF51218A-6.5TQ 100TQFP,3CE
IS61VF51218A-6.5B2 119PBGA
IS61VF51218A-6.5B3 165PBGA
512Kx18 7.5 IS61VF51218A-7.5TQ 100TQFP,3CE
IS61VF51218A-7.5B2 119PBGA
IS61VF51218A-7.5B3 165PBGA
Industrial Range: -40°C to +85°C
Configuration Access Time Order Part Number Package(1)
256Kx36 6.5 IS61VF25636A-6.5TQI 100TQFP,3CE
IS61VF25636A-6.5B2I 119PBGA
IS61VF25636A-6.5B3I 165PBGA
256Kx36 7.5 IS61VF25636A-7.5TQI 100TQFP,3CE
IS61VF25636A-7.5B2I 119PBGA
IS61VF25636A-7.5B3I 165PBGA
512Kx18 6.5 IS61VF51218A-6.5TQI 100TQFP,3CE
IS61VF51218A-6.5B2I 119PBGA
IS61VF51218A-6.5B3I 165PBGA
512Kx18 7.5 IS61VF51218A-7.5TQI 100TQFP,3CE
IS61VF51218A-7.5B2I 119PBGA
IS61VF51218A-7.5B3I 165PBGA
Note:
1.For100TQFP,2CEoptioncontactSRAMMarketingatsram@issi.com
30 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
Integrated Silicon Solution, Inc. 31
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
1. CONTROLLING DIMENSION : MM .
NOTE :
2. Reference document : JEDEC MS-028
10/02/2008
Package Outline
32 Integrated Silicon Solution, Inc.
Rev. F
07/22/09
IS61/64LF25636A IS61LF51218A IS61VF25636A IS61VF51218A
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/28/2008