Analog Integrated Circuit Device Data
NXP Semiconductors 30
CD1030
7.3 Oscillator and timer control functional block
Two oscillators are generated in this block. A 4.0 MHz clock is used in Normal mode only, as well as a Low-power mode 192 kHz clock,
which is on all the time. All timers are generated from these oscillators. The oscillator accuracy is 15% for both, the 4.0 MHz clock and the
192 kHz clock. No calibration is needed and the accuracy is overvoltage and temperature. The timers in Low-power mode are generated
from a base timer such that all timers coincide with other times. When polling and Interrupt timer coincide, the Interrupt timer wakes the
device and the polling does not occur.
7.4 Temperature monitor and control functional block
The device has multiple thermal limit (tLIM) cells to detect thermal excursions in excess of 155 °C. The tLIM cells from various locations on
the IC are logically ORed together and communicated to the MCU as one tLIM fault. When the tLIM value is detected, the wetting current
is lowered to 2.0 mA until the temperature has decreased beyond the tLIM(HYS) value (the sustain current remains on or as selected). A
hysteresis value of 15 °C exists to keep the device from cycling. A thermal flag also exists to alert the system to increasing temperature.
The thermal flag is set at a typical value of 120 °C.
7.5 WAKE_B control functional block
The WAKE_B functions as an input (wake-up) or an output (open drain) pin. In Normal mode, the WAKE_B pin is low. In Low-power mode,
the WAKE_B pin is pulled high. The WAKE_B pin has an internal pull-up to the VDDQ supply, with an internal series diode to allow an
external pull-up to VBATP, if the specific application requires it.
As an input, with VDDQ present, when the device is in Low-power mode and WAKE_B is pulled high (internally or externally), a falling edge
of the WAKE_B pin brings the CD1030 into Normal mode. In Low-power mode, if VDDQ goes low, the WAKE_B VDDQ check bit in the
Device configuration register can be used to ignore or allow a wake-up event upon a falling edge of the WAKE_B pin. Setting the WAKE_B
VDDQ check bit to 0, ignores the falling edge of WAKE_B when VDDQ is low. Setting the WAKE_B VDDQ check to 1, allows the WAKE_B
falling edge to wake-up the device and go into Normal mode regardless of the status of VDDQ. This allows the user to pull the WAKE_B
pin up to VBATP so it can be used in a setup in which VDDQ is supposed to shut down during Low-power mode.
As an output, WAKE_B pin can drive either an MCU input or the EnableB of a regulator (possibly for VDDQ). WAKE_B is driven LOW
during Normal mode regardless of the state of VDDQ. When the CD1030 is in LPM, the WAKE_B pin is released and is expected to be
pulled up internally to VDDQ or externally to VBATP. When a valid wake-up event is detected, the CD1030 should wake-up from LPM and
the WAKE_B should be driven LOW (regardless of the state of VDDQ).
7.6 INT_B functional block
INT_B is an input/output pin in the CD1030 device to indicate an interrupt event has occurred, as well as receiving interrupts from other
devices when the INT_B pins are wired ORed.The INT_B pin is an open-drain output with an internal pull-up to VDDQ. In Normal mode, a
switch state change triggers the INT_B pin (when enabled). The INT_B pin and INT_B bit in the SPI register are latched on the falling
edge of CS_B, which permits the MCU to determine the origin of the interrupt. When two CD1030 devices are used, only the device
initiating the interrupt has the INT_B bit set. The INT_B pin and INTflg bit are cleared 1.0 μs after the falling edge of CS B. The INT_B pin
does not clear with the rising edge of CS_B if a switch contact change has occurred while CS_B was Low.
In a multiple CD1030 device system with WAKE_B high and VDDQ in Low-power mode, the falling edge of INT_B places all CD1030s in
Normal mode.The INT_B has the option of a pulsed output (pulsed low for INTPULSE duration) or a latched low output.The default case is
the latched low operation; the INT_B operation is selectable via the SPI. An INT_B request by the MCU can be done by a SPI word and
results in an INTPULSE of 100 μs duration on the INT_B pin.
The chip causes an INT_B assertion for the following cases:
1. A change of state is detected
2. Interrupt timer expires
3. Any wake-up event
4. Any faults detected
5. After a POR, the INT_B pin is asserted during startup until the chip is ready to communicate