July 2009 Doc ID 13518 Rev 5 1/68
1
L9952GXP
Power management system IC
Features
■Two 5V low-drop voltage regulators (250mA,
100mA continuous mode
■Low stand-by current: VBAT stby, 7µA; ,V1 stby,
45µA, (75µA in cycl. sense)
■Window watchdog and fail-safe output
■Interrupt output
■Wake-up logic with cyclic contact monitoring
■LIN 2.1 compliant (SAEJ2602 compatible)
transceiver
■24 bit SPI interface for mode control and
diagnostic
■Output drivers
■4 High side drivers for e.g. LED or HALL
(RDSon,typ = 7 Ω )
■1 High side driver Out_HS ( RDSon,typ = 1 Ω )
■2 Relay drivers ( RDSon,typ = 2 Ω )
■Outputs are short circuit protected
■2 Op amp's for current sensing in GND return
lines
■Temperature warning and thermal shutdown
Applications
■Automotive ECU’ s such as door zone and
body control modules.
Description
The L9952GXP is a power management system
IC containing two low drop regulators with
advanced contact monitoring and additional
peripheral functions.
The integrated standard serial peripheral interface
(SPI) controls all L9952GXP operation modes
and provides driver diagnostic functions.
PowerSSO-36
Table 1. Device summary
Package
Order codes
Tube Tape and reel
PowerSSO-36 L9952GXP L9952GXPTR
www.st.com
Contents L9952GXP
2/68 Doc ID 13518 Rev 5
Contents
1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2 Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Hall sensor ports: WU3,4, Dig_Out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9 Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10 Fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.11 Reset – generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.12 V1, V2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.13 Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.14 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.15 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.16 LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.17 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.17.1 Dominant TxD time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.17.2 Short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.17.3 Short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18 Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18.1 Normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18.2 Wake up from short to GND condition . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L9952GXP Contents
Doc ID 13518 Rev 5 3/68
2.18.3 RxD pin in V1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.19 LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.1 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.2 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.3 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.4 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.5 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25
3.3 SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 30
6.3 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3 Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6 Reset generator (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Contents L9952GXP
4/68 Doc ID 13518 Rev 5
7.8 High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8.1 Output (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8.2 Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.9 Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.10 Wake up inputs ( WU1..WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.11 Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.12 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.14 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.1 Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.2 Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.3 Input PWM 2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.14.4 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.14.5 DO, FSO, Dig_Out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.14.6 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.14.7 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1.1 Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.2 Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.3 Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.1.4 Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.1.5 Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
L9952GXP List of tables
Doc ID 13518 Rev 5 5/68
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10. Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Power-on Reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 17. High side outputs (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. High side outputs (OUT 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Relay drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Wake up inputs(WU1...WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. LIN receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. LIN DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. LIN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. LIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 26. LIN DC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 28. SPI (Input CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 29. Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 30. Input PWM2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 32. DO, FSO, Digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 33. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 34. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 35. SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 36. Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. Configuration bit HSxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 38. Configuration bit OUT_HSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 39. Configuration bit RELx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 40. Configuration bit On_V2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 41. Configuration bit TRIG, GO_VBAT, GO_V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 42. Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 43. Configuration bit Wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 44. Configuration bit Ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Configuration bit Lx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 46. Configuration bit Txx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 47. Configuration bit INT_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 48. Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 49. Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and TXD_TOUT. . . . . . . 59
List of tables L9952GXP
6/68 Doc ID 13518 Rev 5
Table 50. Configuration bit LEVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 51. Configuration bit ICxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 52. Configuration bit LIN slope, LS_ovuv and ICMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 53. Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 54. Configuration bit HSx_OL, HSx_OC and Relx_OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 56. Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 57. Configuration bit OV, UV, TW, TSDx and Vx Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 58. Configuration bit STx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 59. Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD . . . . . . . . . . . . . 63
Table 60. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 61. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
L9952GXP List of figures
Doc ID 13518 Rev 5 7/68
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. FSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. NReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area (V1 ON) . . . . . 32
Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON) . . . . . . . . . . . . 32
Figure 12. PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. Watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39
Figure 15. LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. SPI - Edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 18. SPI - CSN low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. SPI - High to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 21. PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 22. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Pin definitions and functions L9952GXP
8/68 Doc ID 13518 Rev 5
1 Pin definitions and functions
Figure 1. Block diagram
Table 2. Pins definitions and functions
Pin
name PowerSS0-36 Function
GND 1 Ground
V2 2 Voltage regulator 2 output : 5 V supply for external loads e.g. IR
receiver, potentiometer
V1 3 Voltage regulator 1 output : 5 V supply e.g. micro controller, Can
transceiver
NReset 4 NReset output to micro controller - Internal pull-up of typ. 100KΩ
( reset state = low )
INH 5 Wake-up input e.g. from CAN transceiver
RxD 6 Receiver output of the LIN 2.1 transceiver
DI
Voltage
Regulator 1
High Side
SPI LOGIC
Window
Watchdog
Vs
GND
V1
WU1
CSN
CLK
DO
OUT_HS
Out 1
Rel1
Rel2
Wake Up IN
High Side
Low Side
Output Clamp
FSO
Voltage
Monitor
Wake Up IN
WU2
INH
Vs
Temp Pr ewarning
& Shutdown
Un dervolta ge -
Overvoltage -
Shutdown
Low Side
Output Clamp
M
VSVBat
Cyclic Contact
Monitoring
Microcontroller
CAN
VBa t
LIN 2.1 1)
SAEJ2602
RxD
TxD
NReset
Voltage
Regulator 2
220nF
V2
220nF
Vs
Wake Up IN
Wake Up IN
WU3
WU4
High Side
High Side
High Side
Out 2
Out 3
Out 4
+
-
LIN
LINPU
PWM1
PWM2
Dig_Out3
Dig_Out 4 /
Interrupt
+
-
ESDLIN1524BJ
Wake U p IN
OP2+
OP2-
OP 2o ut
OP1+
OP1-
OP 1o ut
For detailed information
see
EMC test report from
IBEE Zwickau
µC (A DC)
CAN
LIN
R
1) LIN 2.1 certified
e. g. Bul b,
LED, Hall
Sensor
e. g. LED,
Hall Sensor
Fail-safe Logic
C
R
C
L9952GXP Pin definitions and functions
Doc ID 13518 Rev 5 9/68
TxD 7 Transmitter input of the LIN 2.1 transceiver
OP2+ 8 Non inverting input of operational sense amplifier
OP2- 9 Inverting input of operational sense amplifier
OP2OUT 10 Output of operational sense amplifier
DI 11 SPI : serial data input
DO 12 SPI : serial data output
CLK 13 SPI : serial clock input
CSN 14 SPI : chip select not input
PWM1 15 Pulse width modulation input
PWM2 16 Pulse width modulation input
Dig_Out3 17 Digital output
Dig_Out4/INT 18 Digital output (configurable as Interrupt Output)
Wu4..1 19 to 22 Wake-up input: input pins for static or cyclic monitoring of external
contacts
OP1OUT 23 Output of operational sense amplifier
OP1- 24 Inverting input of operational sense amplifier
OP1+ 25 Non inverting input of operational sense amplifier
Out4..1 26 to 29 High side driver (7 Ω, typ.) - to supply e.g. LED’ s, HALL sensors or
external contacts
Out_HS 30 High side drivers (1 Ω, typ.) - to supply e.g. LED’ s, Bulbs, HALL
sensors or external contacts
Vs 31 Power supply voltage
LINPU 32 LIN master pull up
LIN 33 LIN bus line
Rel1 34 Low side driver (2 Ω, typ.) - e.g. relay
Rel2 35 Low side driver (2 Ω, typ.) - e.g. relay
FSO 36
Fail safe output - used to supervise or control applications in case of
watchdog and/or V1 under-voltage failure (e.g. to activate
emergency lights)
Table 2. Pins definitions and functions (continued)
Pin
name PowerSS0-36 Function
Pin definitions and functions L9952GXP
10/68 Doc ID 13518 Rev 5
Figure 2. Pins configuration
Dig
_
Out 3
Out
4
/
2
OUT
_
HS
GND 1
V 22
V1 3
4
5
OP2+
6
OP2 -
7
8
DI
9
DO
10
CLK
11
CSN
12
PWM
1
13
PWM
2
14
RxD
15
TxD
16
17
18
FSO 36
Vs
35
REL 134
REL 2
33
32
OUT 3
31
OUT 1
30
29
OUT 4
28
OP 1 +
27
OP 1 -
26
OPOUT 1
25
WU 1
24
WU 2
23
WU 3
22
WU 4
21
LINPU
20
LIN
19
OUT 2
PowerSSO-36
L9952GXP
INH
NRESET
OPOUT
Dig INT _
TA B = GN D
L9952GXP Description
Doc ID 13518 Rev 5 11/68
2 Description
2.1 Voltage regulator
The L9952GXP contains 2 independent and fully protected low drop voltage regulators,
which are designed for very fast transient response.
The output voltage is stable with loads capacitors > 220nF.
2.1.1 Voltage regulator: V1
The voltage regulator V1 provides 5V supply voltage and up to 250mA continuous load
current for the external digital logic (micro controller, CAN transceiver ...). In addition the
regulator V1 drives the L9952GXP internal 5V loads. The voltage regulator is protected
against overload and over-temperature. An external reverse current protection has to be
provided by the application circuitry to prevent the output capacitor from being discharged
by negative transients or low input voltage. The output voltage precision is better than +/-2%
(incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3%
during low current mode. Current limitation of the regulator ensures fast charge of external
bypass capacitors. The output voltage is stable for ceramic load capacitors > 220nF.
If device Temperature exceeds TSD1 threshold, all outputs (Hsx, Lsx, V2, LIN) will be
deactivated except V1. Hence the micro controller has the possibility for interaction or error
logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 will be deactivated
(see state chart Fig. 3.1: “Protection and diagnosis”). A timer is started and the voltage
regulator is deactivated for tTSD = 1sec. During this time, all other wakeup sources (CAN,
LIN, and WU1...4) are disabled. After 1 sec, the voltage regulator will try to restart
automatically. If TSD2 occurs within one minute and for 8 consecutive times, the L9952GXP
enters the VBAT - standby mode.
In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L9952GXP
enters the VBAT - standby mode. Reactivation (wake-up) of the device can be achieved with
signals from CAN, LIN, WU1..4, SPI.
2.1.2 Voltage regulator: V2
The voltage regulator V2 supplies additional 5V loads (e.g. Logic components, external
sensors, external potentiometers). The continuous load current is 50mA. The regulator
provides accuracy better than + 3% @ 50mA (4% @ 100mA) load current.
In case of short to GND at “V2” after initial turn on (V2 < 2V for at least 4ms) the V2
regulator is switched off. Micro processor has to send a clear command to reactivate the V2
regulator.
V2 is protected against:
●Overload
●Over temperature
●Short circuit (short to ground and battery supply voltage)
●Reverse biasing
Description L9952GXP
12/68 Doc ID 13518 Rev 5
2.2 Power control in operating modes
The L9952GXP can be operated in 4 different operating modes:
●Active
●Flash
●V1- standby
●VBAT - standby
A cyclic monitoring of wake-up inputs is available in stand-by modes.
2.2.1 Active mode
All functions are available.
2.2.2 Flash mode
To disable the watchdog feature a FLASH program mode is available.
The mode can be entered by VPWM2 ≥ 9V
In this case all other functions are the same as in active mode
Watchdog can be disabled as well as soon as L9952GXP enters the V1 standby mode (see
section 2.9 for details)
Note: “High” level for flash mode selection is VPWM2 ≥ 9V. For all other operation modes, standard
5V logic signals are required. For proper operation PWM1 must not be set to a voltage level
above standard 5V logic.
2.2.3 V1 standby mode
Outputs and internal loads are switched off. To supply the micro controller in a low power
mode, the voltage regulator1 (V1) remains active. The intention of the V1 standby mode is
to preserve the RAM contents. A cyclic contact supply and wake-up input sense feature (for
cyclic monitoring of external contacts) can be activated by SPI.
2.2.4 VBAT standby mode
To achieve minimum current consumption during VBAT standby mode, all L9952GXP
functions (except the ones for wake up functionality) are switched off.
In VBAT - standby mode the current consumption of the L9952GXP is reduced to 7µA, typical
(without cyclic sense feature selected).
The transitions from active mode to either V1-standby or VBAT - standby are controlled by
SPI.
VBAT - standby mode is dominant; i.e. if both bits, V1 - standby and VBAT - standby are set to
“1”, the L9952GXP will enter VBAT - standby mode.
L9952GXP Description
Doc ID 13518 Rev 5 13/68
2.3 Wake up events
A wake-up from standby mode will switch the device to active mode. This can be initiated by
one or more of the following sources:
●Change of the LIN state at LIN bus interfaces
●A current at the INH pin (I ≥200uA) controlled by the CAN-transceiver (the CAN
transceiver is not a part of the IC).
●Positive/negative edge at wake up pins WU1...WU4 -> change of level after going into
stand-by
●Change of open-load state at OUT1 to 4
●SPI access in V1-standby mode (CSN is low and first rising edge on CLK)
All wake-up events (except wake-up by LIN, INH or SPI from V1standby mode) generate a
Reset pulse (NReset low for 2ms).
Wake-up events from V1standby by LIN, INH or SPI do not cause a Reset and the Reset
generation is blocked for 2ms, i. e. a watchdog failure during this timeframe will not cause a
reset.
Table 3. Wake up events
Wake up source Description
LIN Always active
INH Always active
WU1...4 Can be individually disabled via SPI
Open Load at HS outputs Can be individually disabled via SPI
SPI Access Always active
(except in VBAT - standby mode)
High level at PWM2 input VPWM2 > 9V (1)
1. Only if internal oscillator is running (e. g. in cyclic sense configuration or after wake-up request).
Description L9952GXP
14/68 Doc ID 13518 Rev 5
2.4 Functional overview (truth table)
Table 4. Functional overview (truth table)
Function Comments
Operating modes
Active mode
V1-standby
static mode
(cyclic sense)
VBAT-standby
static mode
(cyclic sense)
2.3.1 Voltage-regulator, V1 VOUT= 5V On On (1)
1. Supply the processor in low current mode
Off
2.3.2 Voltage-regulator, V2 VOUT= 5V On / Off (2)
2. Only active when selected via SPI
On (2) / Off On (2) / Off
2.3.3 Reset-generator On On Off
2.3.4 Window watchdog V1 monitor On
Off if
(I_V1 < ICMP
and ICMP=0)
or ICMP = 1
Off
2.3.5 Wake up Off (3)
3. Input Status can be read by SPI (Status Register 0); Inputs should be configured for static sense (Control
Register 2)
Active (4) Active (4)
4. Unless disabled by SPI
2.3.6 HS-cyclic supply Oscillator
timebase On / Off On (2) / Off On (2) / Off
2.3.7 Relay driver On Off Off
2.3.8 Operational amplifiers On Off Off
2.3.9 LIN line driver LIN 2.1 On Off Off
2.3.10 LIN line receiver On On On
2.3.11 FSO Fail-safe
output
Hi – no error
Lo – WD or V1
fail
Hi – no error
Lo – WD or V1
fail (5)
5. Watchdog is active in V1 standby mode, until I(V1) is below ICMP current threshold
Lo -> because
V1= off
2.3.12 Oscillator On (6)
6. Activation = ON if cyclic sense is selected
(6)
2.3.13 Vs-Monitor On (7)
7. Cyclic activation = pulsed ON during cyclic sense
(7)
L9952GXP Description
Doc ID 13518 Rev 5 15/68
Figure 3. Operating modes, main states
Active
Mode
V1: on
Reset Generator: active
Watchdog: active
Fail Safe Out: active
V1 Standb y
Mode
V1: on
Reset Generator: active
Watchdog:
OFF (if Iv 1<Icm p or ICMP = 1)
Fail Safe Out: active
Vbat Standby
Mode
V1: off
V2: according to SPI settings
Reset Generator: off (Nreset=low)
Watchdog: off
Fail Safe Out : low
HSD, LSD: Off
Wake-up
Event
Wake-up
Event
SPI command: ‚Go Vcc’
(D21 CR0)
Vbat startup
All registers
cleared to ‚0',
Cold start bit (D19, SR0)
set to ‚1'
Vs > Vpor
Thermal Shutdown TSD2
OR IV1 > 1mA AND ICMP = 0 AND 15 x WD fail
Flash Mode
Watchdog: OFF
Vpwm2>9V
Note 1
Vpwm2>9V
Vpwm2<7V
Vpwm2>9V
Note 1
SPI command: ‚Go Vbat’ (D20 CR0)
OR
Thermal Shutdown
OR
V1 fail (V1 < 2,5V for 4ms after POR)
=> short to GND
Or
15 x WD Failur e
Note 1: only if internal oscillator is running
Description L9952GXP
16/68 Doc ID 13518 Rev 5
2.5 Wake up inputs
The de-bounced digital inputs WU1...WU4 can be used to wake up the L9952GXP from
standby modes. These inputs are sensitive to any level transition (positive and negative
edge)
For static contact monitoring, a filter time of 64 µs is implemented at WU1-4. The filter is
started when the input voltage passes the specified threshold. At Vin > 1V and Vin < (Vs –
2V), a Wake-up request is processed. During Wake-up request, the internal oscillator and
other circuit blocks are activated in order to allow more accurate monitoring of the inputs.
In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a
cyclic wake up feature is implemented. This feature allows periodical activation of the wake-
up inputs to read the status of the external contacts. The periodical activation can be linked
to Timer 1 (0.5sec to 4.0sec in 0.5sec steps) or Timer 2 (50ms). The input signal is filtered
with a filter time of 16us after a programmable delay (80us or 800us). A Wake-up will be
processed if the status has changed versus the previous cycle.
The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the
timing according to the cyclic monitoring of the wake-up inputs.
If the wake-up inputs are configured for cyclic sense mode (Icxx in control register 2), the
same input filter timing (Timer1 or Timer2) and the corresponding input filter delay (control
register 2) must be used for the HS Outputs (Hsxx in control register 0) which supply the
external contact switches.
In Standby mode, the inputs WU1-4 are SPI configurable for pull-up or pull-down current
source configuration according to the setup of the external contacts (pull-up for active low
contacts, pull-down for active high contacts). In active mode the inputs have a pull down
resistor of 100 kOhm (typ).
In Active mode, the input status can be read by SPI (Status Register 0). Static sense should
be configured (Control Register 2) before the read operation is started (In cyclic sense
configuration, the input status is updated according to the cyclic sense timing; Therefore,
reading the input status in this mode may not reflect the actual status).
2.6 Hall sensor ports: WU3,4, Dig_Out 3,4
Applications like Hall sensor outputs need high processing speed. The 12V signals
connected to the wakeup inputs WU3 and WU4 can be looped through to the digital outputs
Dig_Out 3 and Dig_Out 4 (5V) in order to avoid read out of the input state by SPI.
The setup is programmable by SPI.
The open load states of the High Side Drivers OUT1 and OUT2 can be looped through the
digital outputs Dig_Out3 and Dig_Out4 without delay. In addition, the status of OUT1 and
OUT2 can be accessed through the SPI interface. This feature is intended for 2-pin HALL
sensors. Open Load information is only valid during ON state.
The Open Load threshold at pins OUT1...4 can be switched from IOLD1 = 2mA to
IOLD2 = 8 mA via SPI .
L9952GXP Description
Doc ID 13518 Rev 5 17/68
2.7 Interrupt
Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 /
CR1:INT_enable=’1’.
This configuration will enable the following behaviour:
●INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU
inputs, LIN, INH, SPI, open load HS, Iv1 > ICMP_ris)
●Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled
low)
●The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored
2.8 Cyclic contact supply
In V1 and VBAT - standby mode, any high side driver output (OUT1..4, OUTHS) can be used
to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is X sec, the on-time is 10ms resp. 20ms
With X ∈ {0.5, 1.0, 1.5, ... 4 }
Timer 2: period is 50ms, the on- time is 100us resp. 1ms:
Note: Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register
2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control
register 0).
2.9 Window – watchdog
During normal operation the watchdog monitors the micro controller within a nominal trigger
cycle of 10ms.
In VBAT -standby , V1-standby and Flash program modes, the watchdog circuit is
automatically disabled. However, the watchdog will remain enabled in V1-standby mode
until the current at V1 decreases below ICMP_fall. The V1 current monitoring can be
disabled, if the ICMP bit (CR2, D20) is set to '1'.
After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open
window (65ms). The long open window allows the micro controller to run its own setup and
then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input
becomes HIGH after the transmission of the SPI word.
A correct watchdog trigger will start the window watchdog with a closed window (< 6ms)
followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro
controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The
“negative” or “positive” edge has to meet the open window time. A correct watchdog trigger
signal will immediately start the next closed window.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of
7 further watchdog failures, the V1 regulator is completely turned off and the device goes
into VBAT -standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).
Description L9952GXP
18/68 Doc ID 13518 Rev 5
The watchdog is triggered by toggling the trigger bit (CR0, D19).
Note: The active trigger window will be reset after each correct trigger write operation.
In case of reset (NReset low for 2ms) the trigger bit is set to “0”.
In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low
for 2ms.
Writing to control register 0 without inverting the WD trigger bit is possible at any time.
Figure 4. Watchdog
Watchdog active
With
Normal window
(10ms)
HSD, LSD : acc ording to
CR0
Reset
(Nreset =low for 2ms)
LSD: Off (control bits set to ‚0')
HSD: Off (control bits remain
unchanged)
Watchdog active
with
‚long open window’
(65ms nom )
HS and LS outputs are
off
Watchdog
Inactive
(standby modes,
Flash Mode)
Watchdog Failure (‚long
open window’ passed
without TRIG=1
2ms
Set WD Trigger Bit = ‚1' or
toggle trigger bit if wake-up
from V1standby
Set
WD Trigger Bit = ‚0' or write
non-inverting value to trigger
bit after wake-up from
V1standby mode
Go to standby mode or
Flash Mode (PWM2>9V)
Go to standby mode
or Flash Mode (PWM2>9V)
Power-on
Reset
Toggle WD Trigger Bit
Within nominal window
Wake-up event
or exit Flash Mode
V1 off
for 200 ms
8x WD Failure
Watchdog Failure
Vbatstdby
Mode
8+7
WD Failures
Wake up event
t=200ms
INH, LIN, SPI
I(V1)>1mA and ICMP=0
L9952GXP Description
Doc ID 13518 Rev 5 19/68
2.10 Fail safe output
After power-on (Vs > VPOR) or wakeup from VBAT -standby mode, the output FSO is set to
“HIGH”, if V1 is above the V1 threshold. FSO is set to “LOW” in case of V1 under voltage or
watchdog failure.
During V1-standby mode, FSO is HIGH unless a V1 under-voltage or watchdog reset
occurs. WD remains enabled in V1 standby mode until IV1 drops below 150uA. In VBAT -
standby mode, FSO is low. At exit from VBAT - standby mode, it goes to high as soon as V1
is stable.
At wakeup FSO remains high, provided that the watchdog is triggered successfully. It is set
low if the watchdog is not served during the long open window of if a V1 under-voltage
occurs.
Figure 5. FSO
2.11 Reset – generator
IF V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is switched to “HIGH” after a 2ms reset delay time. This is necessary for a
defined start of the micro controller when the application is switched on.
As soon as an under voltage condition of the output voltage (V1 < VRT) for more than 8us
appears, the reset output is switched low again.
Figure 6. NReset
FSO = 0
Vbatstdby Mode
V1 undervoltage
Watchdog Failure
TSD2
NReset = 0
V1 Undervoltage
Wake-up Event 1)
1) Only if
(INT_en = 0) and (wake-up by WU-input or High Side Open Load)
Vpwm2 < 9V
(Exit Flash Mode)
Watchdog
Failure
Description L9952GXP
20/68 Doc ID 13518 Rev 5
2.12 V1, V2 fail
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the V1, V2 – fail thresholds (V1,2 < 2V,typ for t > 2us), the V1,2 - fail
bits are latched. The fail bits are cleared by a dedicated SPI command.
If 4ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds,
(independent for V1,2 ), the L9952GXP will identify a short circuit condition at the related
regulator output and the regulator will be switched off.
In case of a V1 failure the device enters VBAT - standby mode automatically.
In case of a V2 failure the SHT5V2 bit (SR0 Bit12) is set.
2.13 Low side driver outputs Rel1, Rel2
The outputs Rel1, Rel2 (RDSon = 2 Ω typ. @25 °C) are specially designed to drive relay
loads.
Typical relays used have the following characteristics:
Relay type 1:
– closed armature: R = 160 Ω +10%, L= 300mH
– open armature: R = 160 Ω +10%, L= 240mH
Relay type 2:
– closed armature: R= 220 Ω +10%, L= 420mH
– open armature: R= 220 Ω +10%, L= 330mH
The outputs provide an active output zener clamping (40V) feature for the demagnetisation
of the relay coil, even though a load dump condition exists. In case of watchdog failure the
relay drivers will be switched off and the low side driver control bits are cleared.
Note: 1 Due to relays bouncing, high dV/dt and/or dI/dt transients may occur on the low side driver
outputs. In case high currents are switched (for example window lift motor), due to parasitic
capacitive inductive coupling from load side of relays to the relays coils, the Absolute
Maximum Ratings of the Low Side driver outputs may be exceeded. In order to avoid this, it
is recommended to place a 10nF capacitor at the Rel1, Rel2 outputs to GND.
2 If a hard short circuit to VBAT is possible at the "Low Side Driver" outputs, an RC network is
required with TRC > 1µs, R ≥ 1 Ω (see block diagram, the value is given for an output short
circuit of given di/dt = 5A/µs).
2.14 PWM inputs
The inputs PWM 1,2 can be used to control the output drivers Out1..4 and OUT_HS with a
PWM signal. Each PWM input can be mapped individually to each of the above listed
outputs according to the SPI settings.
L9952GXP Description
Doc ID 13518 Rev 5 21/68
2.15 Operational amplifiers
The operational amplifiers are especially designed to be used for sensing and amplifying the
voltage drop across ground connected shunt resistors. Therefore the input common mode
range includes - 0.2 ... 3V.
The operational amplifiers are designed for GND + 3V... GND – 0.2V input voltage swing
and rail-to-rail output voltage range. All Pins (positive, negative and outputs ) are available
to be able to operate in non-inverting and inverting mode. Both operational amplifiers are
on-chip compensated for stability over the whole operating range within the defined load
impedance.
Figure 7. Lin master pull up
A dedicated built-in switch “Tsw” enables the LIN to act as a master. (see chapter 2.18)
2.16 LIN bus interface
General requirements:
●Speed communication up to 20kbit/s
●LIN 2.0 compliant (SAEJ2602 compatible) transceiver
●Function range from +40V to -18V DC at LIN Pin
●GND disconnection fail safe at module level
●Off mode: does not disturb network
●GND shift operation at system level
●Microcontroller Interface with CMOS compatible I/O pins.
●Pull up resistor internal.
●ESD: immunity against automotive transients per ISO7637 specification (see
application note)
●Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
control
Vs
LIN
control
30k
LIN
Gnd
1k Master node
pull u p
LIN P U
TSW
Description L9952GXP
22/68 Doc ID 13518 Rev 5
2.17 Error handling
The L9952GXP provides the following 3 error handling features which are not described in
the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro
controllers to switch the application back to normal operation mode.
2.17.1 Dominant TxD time out
If TXI is in dominant state (low) for more than 12ms (typ) the transmitter will be disabled until
TXI becomes recessive (high). This feature can be disabled via SPI.
2.17.2 Short to battery time out
If TXI changes to dominant (low) state but RXI signal does not follow within 40µs, the
transmitter will be disabled until TXI becomes recessive (high).
2.17.3 Short to ground mode
A wake up caused by a message on the bus will start the voltage regulator and the micro
controller to switch the application back to normal operation mode.
2.18 Wake up (from LIN)
In standby mode the L9952GXP can receive a wake up from LIN bus. For the wake up
feature the L9952GXP logic differentiates two different conditions.
2.18.1 Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN was
in recessive (high) state. A dominant level at LIN for at least 40µs, will switch the L9952GXP
to active mode.
2.18.2 Wake up from short to GND condition
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for at least 40us, will switch the L9952GXP to active mode.
2.18.3 RxD pin in V1 standby
In V1 standby condition the RxD is a tristate pin.
L9952GXP Description
Doc ID 13518 Rev 5 23/68
2.19 LINPU
The LINPU (LIN pull up) signal is set by L9952GXP logic in order to drive the LIN transceiver
in master mode. The master mode is realized by an internal high side switch and an external
diode in series with an external 1k resistor. In master mode the high side switch is closed
causing an external pull up path in parallel to the internal one (diode & 30k resistor).
HS (high side) characteristics:
●HS does not have an over current protection.
●The HS remains active in standby mode.
●Switch off only in case of over temperature (TSD2 = thermal shutdown #2).
●Typical RDSon, 10 Ω.
The Linpu is activated by default (LIN master mode) and can be switched off with a SPI
command (see register 2) to reduce current in case of LIN shorted to ground.
2.20 Serial Peripheral Interface (SPI)
A 24 bit SPI command (2 adresses + 22 data bits) is used for bi-directional communication
with the micro controller.
During active mode, the SPI:
1) triggers the watchdog
2) controls the modes and status of all L9952GXP modules (incl. input and output drivers)
3) provides driver output diagnostic
4) provide L9952 diagnostic (incl. over temperature warning, L9952GXP operation status)
Note: During stand-by modes, the SPI is generally deactivated.
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL=0 and CPHA=0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a build-in SPI. Only three CMOS-
compatible output pins and one input pin will be needed to communicate with the device. A
fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
global error flag (fault condition) of the device which is a logical -”OR” of all over current, Vs-
over / under voltage, temperature warning/shutdown and V1 Fail bits. The micro controller
can poll the status of the device without the need of a full SPI-communication cycle.
2.20.1 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal activates the output driver and
a serial communication can be started. The state during CSN = 0 is called a communication
frame.
Description L9952GXP
24/68 Doc ID 13518 Rev 5
2.20.2 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety
function is implemented to avoid an activation of the output stages by a wrong
communication frame.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
2.20.3 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the global error flag (fault condition).
The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer
the content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
2.20.4 Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to 1MHz.
2.20.5 Data registers
The device has 3 Control registers and 2 Status registers. The first two bits (D22+D23) at
the DI-Input are used to select one of the Control registers. All bits are first shifted into an
input shift register. After the rising edge of CSN the contents of the input shift register will be
written to the selected Control register only if a frame of exact 24 bits is detected. If the
Control register 1 is selected for data transfer, the Status register 1 will be transferred to the
DO during the current communication frame. For the selection of Control register 0 or
Control register 2, the Status register 0 is transferred to DO.
L9952GXP Protection and diagnosis
Doc ID 13518 Rev 5 25/68
3 Protection and diagnosis
3.1 Power supply fail
Over and under-voltage detection on Vs.
3.1.1 Over voltage
If the supply voltage Vs reaches the over voltage threshold (VSOV)
●The outputs HS1..4, OUT_HS, Rel1,2, and LIN are switched to high impedance state
(load protection)
●The over voltage bit is set and can be cleared with the clear bit (CR1,CLR)
●Automatic recovery after Vs over-voltage; selectable via SPI (CR2, bit4)
3.1.2 Under voltage
If the supply voltage Vs drops below the under voltage threshold voltage(VSUV)
●The outputs HS1..4, OUTHS, Rel1,2, and LIN are switched to high impedance state
(load protection)
●The under voltage bit is set
●Automatic recovery after Vs under-voltage; selectable via SPI (CR2, bit4)
3.2 Temperature warning and thermal shutdown
See state chart: “ Protection and diagnosis”.
3.3 SPI diagnosis
Digital diagnosis features are provided by SPI:
●V1 reset threshold programmable
●Over temperature including pre warning
●Open load separately for each output stage
●Overload status
●Vs-supply over/under voltage
●V1 and V2 fail bit
●Status of the WU1...4, LIN and INH pin
●Cold start bit
●Number of unsuccessful V1 restarts after thermal shutdown
●Number of sequential watchdog failures
●Status of watchdog trigger bit TRIG: (SR1, Bit 16)
●LIN status (short to ground, short to VBAT
, dominant TxD)
See the following state chart: “Protection and diagnosis”.
Protection and diagnosis L9952GXP
26/68 Doc ID 13518 Rev 5
Figure 8. Protection and diagnosis
Active
Mode
Standby Modes
(during cyclic sense )
Vs Lockout
All outputs: off
UV bit set (D1 SR1)
Auto-restart if selected by SPI
Vs Lockout
All outputs: high Impedance
OV Bit set (D0 SR1)
Auto-restart if selected by SPI
Vs Overvoltage
Temperature
Warning
‚Temper ature War n ing'-
Bit set
(D2 SR1)
TSD1
All outputs except V 1: off
‚T SD 1' -Bit is set (D 3 SR1)
Tj > 140°C
SPI command: ‚CLR’
(D21 CR1)
OR
Power-on reset
TSD2
All outputs: off
V1: off for 1 sec
‚TSD2-bit is set (D4 SR1)
Tj > 155°C
Vbatstdby
All outputs incl V 2: off
8x TSD2
(each TSD2
within 1 min)
SPI command: ‚CLR’
(D21 CR1)
OR
Autorestart activated
(D4 CR2)
SPI command: ‚CLR’
(D21 CR1)
OR
Autorestart activated
(D4 CR2)
Vs Undervoltage
Wake-up event
Power-on reset
SPI command: ‚CLR’
(D21 CR1)
OR
Power-on reset
Tj > 130°C
V1 off for
200ms
8 successive watchdog
failures
7 additional watchdog failures
in sequence
Vbatstdby
mode
T > 1sec
L9952GXP Protection and diagnosis
Doc ID 13518 Rev 5 27/68
3.4 High side driver outputs
The component provides a total of 4 high side outputs Out1...4, (7 Ω typ. @ 25C) to drive
e.g. LED' s or hall sensors and 1 high side output OUT_HS with 1 Ω typ. @ 25 C).
The high side outputs are protected against
●Over- and under voltage
●Overload (short circuit)
●Over temperature with pre warning
If the output current exceeds the current shutdown threshold the output transistor is turned
off and the corresponding diagnosis bit of the output is set.
The switches are automatically disabled in case of reset condition, Vs-under, Vs-over
voltage or thermal shutdown (TSD1&2).
For OUT_HS an auto recovery feature is available in active mode.
If the OUT_HS output current exceeds the current shutdown threshold, the output transistor
is turned off and the corresponding diagnosis bit of the output is set.
Via SPI command the auto recovery feature can be enabled in order to restart the driver in
case of over current shutdown. This over current recovery feature is intended for loads
which have an initial current higher than the over current limit of the output (e.g. Inrush
current of cold light bulbs).
The device itself can not distinguish between a real overload and a non linear load like a
light bulb. A real overload condition can only be qualified by time. As an example, the micro
controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.
After clearing the recovery bit, the output will be automatically disabled if the overload
condition still exists.
The status of all high side outputs (over-current, open load) can be monitored by SPI
interface.
In case of a watchdog failure, the high side drivers are switched off. The control bits are not
cleared, i.e. the drivers will go to the previous state once the watchdog failure condition
disappears.
ESD structures are configured for nominal currents only. If external loads are connected to
different grounds, the current load must be limited to this nominal current.
Note: Loss of ground or ground shift with externally grounded loads.
3.5 Low side driver outputs Rel1, Rel2
The outputs provide an active output zener clamping feature for the demagnetisation of the
relay coil, even though a load dump condition exists. For safety reasons the relay drivers
are linked with the Watchdog: in case of failure, or missing trigger signal the relay drivers will
switch off.
Absolute maximum ratings L9952GXP
28/68 Doc ID 13518 Rev 5
4 Absolute maximum ratings
Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit !
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
VSDC supply voltage / “jump start” -0.3 to +28 V
Single pulse / tmax < 400 ms
“transient load dump” -0.3 to +40 V
V1
Stabilized supply voltage, logic
supply -0.3 to +5.25 V
V2Stabilized supply voltage -0.3 to +28 V
VDI VCLK
VTXD VCSN
VDO VRXD
VNRESET VFSO
VDIGOUT3,4
Logic input / output voltage range -0.3 to V1+0.3 V
VINH
VPWM1, VPWM2,
VREL1, VREL2,
Wake up input voltage range
PWM input voltage range
Low side output voltage range
-0.3 to +40 V
VOUT1..4,, VOUTH High side output voltage range -0.3 to VS + 0.3 V
VWU1...4, Wake up input voltage range -0.3 to VS + 0.3 V
VOP1+,VOP1-,
VOP2+, VOP2-,
Opamp1 input voltage range
Opamp2 input voltage range -0.3 to V1 + 0.3 V
VOPOUT1,
VOPOUT2
Analog Output voltage range -0.3 to VS + 0.3 V
VLIN, VLINPU LIN bus I/O voltage range -20 to +40 V
IInput
Current injection into Vs related
input pins 5mA
L9952GXP ESD protection
Doc ID 13518 Rev 5 29/68
5 ESD protection
Table 6. ESD protection
Parameter Value Unit
All pins, except LIN(1)
1. HBM (human body model, 100pF, 1.5 kΩ ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A
+/- 2 kV
All output pins(2)
2. HBM with all none zapped pins grounded
+/- 4 kV
LIN(3)
3. Without external components
+/- 1.5 kV
LIN(4)
4. Acc. DIN EN61000-4-2 (330Ω, 150pF), with external components:
- Diode, type ESDLIN1524BJ
- SMD Ferrite bead, type TDKMMZ2012Y202B
- Capacitor C=220pF
For detailed information please see EMC report from IBEE Zwickau (available on request)
+/- 8 kV
All pins (charge device model) +/- 500 V
Corner pins (charge device model) +/- 750 V
All pins(5)
5. Acc. Machine Model: C=220pF; L=0.75µH; R=10Ω
+/- 200 V
Thermal data L9952GXP
30/68 Doc ID 13518 Rev 5
6 Thermal data
6.1 Operating junction temperature
6.2 Temperature warning and thermal shutdown
Table 7. Operating junction temperature
Item Symbol Parameter Value Unit
6.1.1 Tj Operating junction temperature - 40 to 150 °C
6.1.2 RthjA Thermal resistance junction- ambient See Figure 10. °C/W
Table 8. Temperature warning and thermal shutdown
Item Symbol Parameter Min. Typ. Max. Unit
6.2.1 TW ON
Thermal over temperature
warning threshold Tj (1)
1. Non-overlapping
120 130 140 °C
6.2.2 TSD1 OFF
Thermal shutdown
junction temperature 1 Tj (1) 130 140 150 °C
6.2.3 TSD2OFF
Thermal shutdown
junction temperature 2
Tj (1) 140 155 170 °C
6.2.4 TSD2 ON Hysteresis 5 °C
6.2.5 TSD12hys
L9952GXP Thermal data
Doc ID 13518 Rev 5 31/68
6.3 Package and PCB thermal data
Figure 9. PowerSSO-36 PC board
Note: Layout condition of Rth and Zth measurements ( board finish thickness 1.6 mm +/- 10%
board double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070mm
(front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08
mm, Cu thickness on vias 0.025 mm ).
Thermal data L9952GXP
32/68 Doc ID 13518 Rev 5
Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area
(V1 ON)
Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON)
30
50
70
90
110
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^ 2)
0,1
1
10
100
1000
0,01 0,1 1 10 100 1000
Time ( s)
ZTH ( °C/ W)
Footprint
8 cm
2
2 cm
2
L9952GXP Thermal data
Doc ID 13518 Rev 5 33/68
Equation 1: pulse calculation formula
where δ = tP/T
Figure 12. PowerSSO-36 thermal fitting model (V1 ON)
Table 9. Thermal parameters
Area/island (cm2)Footprint28
R1 (°C/W) 5
R2 (°C/W) 18 10 10
R3 (°C/W) 29 22 7,8
R4 (°C/W) 51 29 21
C1 (W.s/°C) 0,0003
C2 (W.s/°C) 0,35 1 1
C3 (W.s/°C) 1,5 1,3 1,3
C4 (W.s/°C) 5 15 15
ZTHδRTH δZTHtp 1δ–()+⋅=
Electrical characteristics L9952GXP
34/68 Doc ID 13518 Rev 5
7 Electrical characteristics
7.1 Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.8V < V1 < 5.2V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 10. Supply and supply monitoring
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.1.1 VSSupply voltage range 6 13.5 18 V
7.1.2 VSUV VS UV-threshold voltage VS increasing /
decreasing 5.11 5.81 V
7.1.3 Vhyst_UV Undervoltage hysteresis 0.04 0.1 0.15 V
7.1.4 VSOV VS OV-threshold voltage VS increasing /
decreasing 18 22 V
7.1.5 Vhyst_OV Overvoltage hysteresis Hysteresis 0.5 1 1.5 V
7.1.6 IV(act)
Current concumption in
active mode
Vs=12V, TxD LIN
high, V2 on,
Outputs off
Iv1=Iv2=0A
2.7 20 mA
7.1.7 IV(BAT)
Current consumption in
VBAT - standby mode
VS=12V, both
voltage regulators
deactivated, no
wake-up request
1 7 10 µA
7.1.8 IV(BAT)CS
Current consumption in
VBAT - standby mode
VS=12V, both
voltage regulators
deactivated, (cyclic
sense)
40 75 100 µA
7.1.9 IV(V1)
Current consumption in
V1-standby mode
V1=5V, VS=12V,
Voltage regulator
V1 active, without
cyclic sense, no
wake-up request
10 45 70 µA
7.1.10 IV(BATWU)
Current consumption in
VBAT
-standby mode with a
pending wake up request
1.5V<VWU<(Vs-3V) 220 320 µA
7.1.11 IV(V1WU)
Current consumption in
V1- standby mode with a
pending wake up request
1.5V<VWU<(Vs-3V) 300 410 µA
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 35/68
7.2 Oscillator
6V < VS < 18V; all outputs open; Tj = -40°C...130°C, unless otherwise specified.
7.3 Power-on reset (Vs)
All outputs open; Tj = - 40°C...130 °C, unless otherwise specified.
7.4 Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 5.25V < VS < 27V; Tj = -40°C...130°C, unless otherwise specified.
Table 11. Oscillator
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.2.1 FCLK Oscillation frequency Vs = 6V...18V
0.808
1.01 1.35 MHz
Table 12. Power-on Reset (Vs)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.3.1 VTHUP_POR VPOR threshold 2.8 3.45 4.1 V
7.3.2 VHys_POR Hysteresis 200 mV
Table 13. Voltage regulator V1
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.4.1 V1 Output voltage 5.0 V
7.4.2 V1 Output voltage tolerance
Active mode
ILOAD = 1mA...
100mA,
VS = 13.5V
+/- 2 %
7.4.3 Vhc1 Output voltage tolerance
Active mode, high current
ILOAD = 100mA ...
250mA,
VS = 13.5V
+/- 3 %
ILOAD = 250mA
VS = 13.5V,
Tj >80°C
+/- 4 %
7.4.4 VSTB1 Output voltage tolerance
in low current mode
0mA< ILOAD<ICMP
VS = 13.5V +/- 4 %
7.4.5 VDP1 Drop-out voltage in
undervoltage conditions
ILOAD = 50mA,
VS = 4.5V
ILOAD = 100mA,
VS =4.5V
0.2
0.3
0.4
0.5
V
V
7.4.6 ICC1 Output current in active
mode
Max. continuous
load current 250 mA
Electrical characteristics L9952GXP
36/68 Doc ID 13518 Rev 5
7.5 Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 5.25V < VS < 27V; Tj = -40°C...130°C, unless otherwise specified.
7.4.7 ICCmax1 Short circuit output
current Current limitation 400 600 950 mA
7.4.8 Cload1 Load capacitor1 Ceramic(1) 0.22 µF
7.4.9 tTSD V1 deactivation time after
thermal shutdown 1 s
7.4.10 ICMP_ris
Current comp. rising
threshold Rising current 0.9 2.5 4mA
7.4.11 ICMP_fal
Current comp. falling
threshold
Falling current
Tj= -40°C...130°C
Tj= 25°C...130°C
0.75
0.85
1.95
1.95
mA
7.4.12 ICMP_hys Current comp. hysteresis 0.5 mA
7.4.13 V1fail V1 fail threshold V1 forced 2 V
1. Placement close to the PAD
Table 13. Voltage regulator V1 (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Table 14. Voltage regulator V2
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.5.1 V2Output voltage 5.0 V
7.5.2 V2
Output voltage tolerance
Active mode
ILOAD = 1mA ...
50mA, VS = 13.5V +/- 3 %
7.5.3 Vhc1
Output voltage tolerance
Active mode, high current
ILOAD = 50mA ...
100mA, VS = 13,5V +/- 4 %
7.5.4 VSTB2
Output voltage tolerance in
low current mode
ILOAD = 0uA ...1mA
VS = 13,5V +/- 5 %
7.5.5 VDP2 Drop-out voltage
ILOAD = 25mA,
VS = 5 V
ILOAD = 50mA,
VS= 5 V
0,3
0.4
0,4
0.7
V
V
7.5.6 ICC2
Output current in Active
mode
Max. continuous
load current 100 mA
7.5.7 ICCmax2 Short circuit output current Current limitation 200 300 500 mA
7.5.8 Cload Load capacitor Ceramic(1)
1. Placement close to the PAD
0.22 µF
7.5.9 V2fail V2 fail threshold V2 forced 2 V
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 37/68
7.6 Reset generator (V1 supervision)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 5.25V < VS = 18V; Tj = -40 to 130 °C, unless otherwise specified.
7.7 Watchdog
6V < VS < 18V; 4.8V < V1 < 5.2V; Tj = -40 to 130 °C, unless otherwise specified
Table 15. Reset generator
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.6.1 VRT1 Reset threshold voltage1 VS, VV1 inc. /
decreasing 4.5 4.63 4.75 V
7.6.2 VRT2 Reset threshold voltage2 VS, VV1 inc. /
decreasing 4.25 4.37 4.5 V
7.6.3 VRESET
Reset pin low output
voltage
V1 > 1V,
IRESET = 1mA 0,2 0,4 V
7.6.4 RRESET Reset pull up int. resistor 60 110 204 kΩ
7.6.5 tRR Reset reaction time @Iload = 1mA 6 40 µs
7.6.6 V1 under-voltage filter time 16 µs
Table 16. Watchdog (1)
1. See Figure 13.
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.7.1 tLW Long open window 48,75 65 81,25 ms
7.7.2 tCW Closed window 4.5 6 7.5 ms
7.7.3 tOW Open window 7.5 10 12.5 ms
7.7.4 tWDR Watchdog reset pulse time 1.5 2 2. 5 ms
Electrical characteristics L9952GXP
38/68 Doc ID 13518 Rev 5
Figure 13. Watchdog timing
TLW= long window < 65ms
TCW = closed window < 6ms
TOW = open window < 10ms
trigger signal
TWDR = watchdog reset = 2ms
time / ms
time / ms
time / ms
Normal startup operation and timeout failures
WD-
trigger
= correct trigger timing
TLW
TCW+ TOW
Missing uC trigger signal
TCW
TCW+ TOW
NRES-
Out TWDR
TLW
= early trigger timing
= missing trigger
TLW
TWDR
normal operation missing
trigger
early
write
TLW
NRES-
Out TWDR TWDR
WD-
trigger TLW TLW
TWDR
time / ms
0
0
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 39/68
Figure 14. Watchdog, closed and open window tolerances and save trigger area
7.8 High side outputs
7.8.1 Output (Out_HS)
The voltages are referred to gnd and currents are assumed positive, when the current flows
into the pin. 6V < VS < 18V; 4.8V < V1 < 5.2V; Tj = -40°C...130°C, unless otherwise
specified.
4.5 7.5 12 20
save trigger area
TCW, min
TCW, max
TWD= 10ms
TOW, max
TOW, min
TWD = nominal trigger time
TCW = closed window
TOW = open window
time / ms
watchdog failure
undefined
undefined
Table 17. High side outputs (Out_HS)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.8.1 RDSON
OUT_HS
Static Drain Source
On-resistance to supply
(IOUT_HS=150mA)
Tj = 25°C 01.0 1.5 Ω
Tj = 125°C 01.63 Ω
7.8.2 tdONHS Switch on delay time 0.2 VS 10 35 60 µs
7.8.3 tdOFFHS Switch off delay time 0.8VS 40 95 150 µs
7.8.4 tdSDHS Short circuit filter time Tested by scan
chain
64*
TOSC
7.8.5 tdARHS Auto recovery filter time Tested by scan
chain
400*
TOSC
7.8.6 dVout/dt Slew rate 0.2 0.5 0.8 V/µs
7.8.7 IOSDHS
Short circuit shutdown
current 480 900 1320 mA
7.8.8 IOLD
Open load detection
current 40 80 120 mA
Electrical characteristics L9952GXP
40/68 Doc ID 13518 Rev 5
7.8.2 Outputs (OUT1...4)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.8V < V1 < 5.2V; Tj = -40°C...130°C, unless otherwise
specified.
7.9 Relay drivers
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.8V < V1 < 5.2V; Tj = -40 to 130 °C, unless otherwise
specified.
Table 18. High side outputs (OUT 1..4)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.8.11 RDSON On – resistance ILOAD = 60mA @
Tj=+25°C 0712Ω
7.8.12 IOUT
Short circuit shutdown
current 8V < Vs < 16V 140 235 330 mA
7.8.13 IOLD1
Open load detection
current 1 Selectable via SPI 0.8 2 4 mA
7.8.14 IOLD2
Open load detection
current 2 6813mA
7.8.15 SR Slew rate 0.2 0.5 0.8 V/µs
7.8.16 tdONHS Switch ON delay time 0.2 VS 10 35 60 µs
7.8.17 tdOFFHS Switch OFF delay time 0.8 VS 40 95 150 µs
7.8.18 tSCF Short circuit filter time Tested by scan
chain
64*
TOSC
7.8.19 IFW (1)
1. Parameter guaranteed by design
Loss of GND current
(ESD structure) 100 mA
Table 19. Relay drivers
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.9.1 RDSON DC output resistance ILOAD = 100mA @
Tj = +25°C 023Ω
7.9.2 IOUT
Short circuit shutdown
current 8V < Vs < 16V 250 375 500 mA
7.9.3 VZOutput clamp voltage (1) ILOAD = 100mA 40 48 V
7.9.4 tONHL
Turn on delay time to 10%
VOUT
5 50 100 µs
7.9.5 tOFFLH
Turn off delay time to 90%
VOUT
5 50 100 µs
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 41/68
7.10 Wake up inputs ( WU1..WU4)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; Tj = -40 to 130 °C, unless otherwise specified.
7.9.6 tSCF Short circuit filter time Tested by scan
chain
64*
TOSC
7.9.7 SR Slew Rate 0.2 2 4 V/µs
1. The output is capable to switch off relay coils with the impedance of RL=160Ω; L = 300mH
(RL=220Ω; L= 420mH); at VS = 40V (Load dump condition)
Table 19. Relay drivers (continued)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Table 20. Wake up inputs(1)(WU1...WU4)
1. Defines whether the inputs W1..4 are configured with current source or current sink in standby mode.
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.10.1 VWUthp
Wake-up negative
edge threshold voltage 0.4 Vs 0.45 Vs 0.5 Vs V
7.10.2 VWUthn
Wake-up positive edge
threshold voltage 0.5 Vs 0.55 Vs 0.6 Vs V
7.10.3 VHYST Hysteresis 0.05 Vs 0.1 Vs 0.15 Vs V
7.10.4 tWU
Minimum time for
wake-up 51 64 77 µs
7.10.5 IWU_stdby
Input current in standby
mode 1.5V<VIN< (Vs-3V) 10 20 30 µA
7.10.6 RWU_act
Input resistor to GND in
active mode and in
standby mode during
wake-up request
100 275 450 kΩ
7.10.7 Nn Number of samples
During OUT_HS
on, cyclic sense
mode (100us
cyclic HS on time)
2 (at 80µs and 100µs)
7.10.8 Vwuthl
Pending wake up
request low threshold 1.0 1.25 1.5 V
7.10.9 Vwuthh
Pending wake up
request high threshold Vs-3 Vs-2.2 Vs-1.4 V
Electrical characteristics L9952GXP
42/68 Doc ID 13518 Rev 5
7.11 Wake up input (INH)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; Tj = -40 to 130 °C, unless otherwise specified.
7.12 LIN
Compatible to Lin 2.1 for Baud rates up to 20 kBit/s
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6V < VS < 18V; 4.8V < V1 < 5.2V; Tj = -40°C...130°C, unless otherwise specified.
Table 21. Wake up input (INH)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.11.1 IINHth
Wake-up activate
threshold current 30 75 120 µA
7.11.2 IINHUth
Wake-up passive
threshold current 30 70 120 µA
7.11.3 IINHhys
Wake-up current
hysteresis 10 20 µA
7.11.4 tWU Minimum time for wake-up 51 64 77 µs
7.11.5 Nn Number of samples
During OUT_HS
on, cyclic sense
mode (100µs cyclic
HS on time)
2 (at 80us and
100us)
Table 22. LIN receiver
Item
Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN LIN receiver
7.12.1 VTXDLOW
Input voltage
dominant level Normal mode, V1=5V 1 1.3 V
7.12.2 VTXDHIGH
Input voltage
recessive level Normal mode, V1=5V 2.2 2.5 V
7.12.3 VTXDHYS
VTXDHIGH -
VTXDLOW
Normal mode, V1=5V 0.5 0.8 V
7.12.4 ITXDPU
TXD pull up
current
Normal and
V1-standby mode ,
V1=5V
-5 -30 -60 µA
7.12.5 ITXDPD
TXD pull-down
current
VBAT - standby mode,
VTXDHIGH
V1=5V
53060µA
7.12.6 VRXDLOW
Output voltage
dominant level
Normal mode, V1=5V,
2mA 0.2 1.5 V
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 43/68
7.12.7 VRXDHIGH
Output voltage
recessive level
Normal mode, V1=5V,
2mA 4.5 V
7.12.8 VTHdom
Receiver threshold
voltage recessive
to dominant state
0.4
VS
0.45
VS
0.5
VS
V
7.12.9 VTHrec
Receiver threshold
voltage dominant
to recessive state
0.5
VS
0.55
VS
0.6
VS
V
7.12.10 VTHhys
Receiver threshold
hysteresis VTHrec - VTHdom
0.07
VS
0.1
VS
0.175
VS
V
7.12.11 VTHcnt
Receiver tolerance
center value (VTHrec + VTHdom) / 2
0.475
VS
0.5
VS
0.525
VS
V
7.12.12 VTHwkup
Receiver wakeup
threshold voltage 1.0 1.5 2 V
7.12.13 VTHwkdwn
Receiver wakeup
threshold voltage
3.5
Vs
2.5
Vs
1.5
Vs V
7.12.14 Tbus Dominant time for
wakeup via bus
Sleep mode
edge: rez.- dom. 64 µs
Table 23. LIN DC parameters
Item
Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN DC parameters
7.12.15 ILINDomSC
Transmitter input
current limit in
dominant state
VTxD = VTxDlow
VLIN = Vbatmax = 18V 40 100 180 mA
7.12.16 Ibus_PAS_dom
Input leakage
current at the
receiver incl.
Pull-Up resistor
VTxD = VTxDhigh
VLIN = 0V, VBAT =12V,
Slave mode
-1 mA
7.12.17 Ibus_PAS_drec
Transmitter input
current in
recessive state
VTxD = VTxDhigh
8V<VLIN, VBAT<18V;
VLIN ≥ VBAT
20 µA
7.12.18 Ibus_NO_GND
Input current if loss
of GND at Device
GND = Vs,
0V<VLIN<18V
VBAT=12V
-1 1 mA
7.12.19 Ibus
Input current if loss
of Vbat at device
GND = Vs,
0V<VLIN<18V 100 µA
Table 22. LIN receiver (continued)
Item
Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN LIN receiver
Electrical characteristics L9952GXP
44/68 Doc ID 13518 Rev 5
Table 24. LIN transmitter (continued)
Item
Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN LIN transmitter
7.12.20 VLINdom
LIN voltage level in
dominant state
VTxD = VTxDlow
ILIN = 40mA 1.2 V
7.12.21 VLINrec
LIN voltage level in
recessive state
VTxD = VTxDhigh
ILIN = 10µA
0.8
Vs V
7.12.22 RLINup
LIN output pull up
resistor VLIN = 0V 20 40 60 kΩ
Table 25. LIN timing
Item Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN timing
7.12.24 tTXpd_sym
Symmetry of
transmitter
propagation delay
time (rising vs.
falling edge)
tTXpd_sym =
= tTXpdr – tTXpdf
Vs=12V,
Rbus Cbus:
1 kΩ, 1 nF
-2.5 - 2.5 µs
7.12.25 tRXpd
Receiver
propagation delay
time
tRXpd =
= max (tRXpdr tRXpdf)
tRXpdf =
=t(0.5RXD)-t(0.45 VLin)
tRXpdr =
=t(0.5RXD)-t(0.55 VLin)
Crxd = 20pF
Vs = 12V,
Rbus Cbus:
1 kΩ, 1 nF;
660 Ω, 6.8 nF;
500 Ω,10 nF
-6µs
7.12.26 tRXpd_sym
Symmetry of
receiver
propagation delay
time (rising vs.
falling edge)
tRXpd_sym =
= tRXpdr – tRXpdf -2 - 2 µs
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 45/68
7.12.27 D1 Duty cycle 1
THRec(max)=0.744*Vs
THDom(max)=0.581*Vs
Vs= 7...18V, tbit= 50us,
D1=tbus_rec(min)/(2xtbit)
Rbus, Cbus: 1 kΩ, 1 nF;
660 Ω, 6.8 nF;
500 Ω, 10 nF
0.396
-
7.12.28 D2 Duty cycle 2
THRec(min)=0.284*Vs;
THDom(min)=0.422*Vs,
Vs= 7.6 ...18V,
tbit= 50µs,
D1=tbus_rec(max)/(2xtbit)
Rbus, Cbus:
1 kΩ, 1 nF;
660 Ω, 6.8 nF;
500 Ω, 10 nF
-
0.581
7.12.29 D3 Duty cycle 3
THRec(max)=0.778*Vs;
THDom(max)=0.616*V,
Vs= 7...18V tbit= 96µs,
D3 =tbus_rec(min)/(2xtbit)
Rbus, Cbus: 1 kΩ, 1 nF;
660 Ω, 6.8 nF;
500 Ω, 10 nF
0.417
-
7.12.30 D4 Duty cycle 4
THRec(min)=0.251*Vs;
THDom(min)=0.389*Vs,
Vs= 7.6 ...18V,
tbit= 96µs
D1 =tbus_rec(max)/(2xtbit)
Rbus, Cbus:
1 kΩ, 1 nF;
660 Ω, 6.8 nF;
500 Ω,10 nF
- 0.59
Table 26. LIN DC values
Item
Symbol
Parameter
Test condition Min. Typ. Max. Unit
LINPU DC values
7.12.31 RDSon ON resistance 10.5 16 Ω
7.12.32 Ileak Leakage current 1 uA
Table 25. LIN timing (continued)
Item Symbol
Parameter
Test condition Min. Typ. Max. Unit
LIN timing
Electrical characteristics L9952GXP
46/68 Doc ID 13518 Rev 5
Figure 15. LIN transmit, receive timing
tim e
tim e
VTxD
VLIN
VTHrec
VT H dom
80%
20%
tim e
VRxD
VLINdom
VLINr ec
tTXpdf tTXpdr
tRXpdf tR Xpdr
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 47/68
7.13 Operational amplifier
The voltages are referred to gnd and currents are assumed positive, when the current flows
into the pin. 6V < VS < 18V; Tj = -40...130°C, unless otherwise specified.
Note: The operational amplifier is on-chip stabilized for external capacitive loads CL < 25pF (all operating
conditions)
Table 27. Operational amplifier
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.13.1 GBW GBW product 1 3.5 7.0 MHz
7.13.2 AVOLDC DC open loop gain 80 dB
7.13.3 PSRR Power supply rejection DC, Vin =150 mV 80 dB
7.13.4 Voff Input offset voltage -5 +5 mV
7.13.5 VICR
Common mode input
range -0.2 0 3 V
7.13.6 VOH Output voltage range high Iload = 1mA to Gnd 0.2
VS
VSV
7.13.7 VOL Output voltage range low Iload = 1mA to VS 0 0.2 V
7.13.8 Ilim+ Output current limitation + DC 5 10 20 mA
7.13.9 Ilim- Output current limitation - DC -5 -10 -20 mA
7.13.10 SR+ Slew rate positive 1 4 10 V/µs
7.13.11 SR- Slew rate negative -1 -4 -10 V/µs
Electrical characteristics L9952GXP
48/68 Doc ID 13518 Rev 5
7.14 SPI
7.14.1 Input: CSN
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
7.14.2 Inputs: CLK, DI, PWM 1, PWM 2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V< VS <18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 28. SPI (Input CSN)
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.1 VCSNLOW Input voltage low level Active mode,
V1 = 5V 0.5 1.0 1.6 V
7.14.2 VCSNHIGH Input voltage high level Active mode,
V1=5V 1 1.75 2.5 V
7.14.3 VCSNHYS VCSNHIGH - VCSNLOW Active mode,
V1=5V 0.5 1.0 1.5 V
7.14.4 ICSNPU CSN pull up current
Active mode and
V1 Standby
mode,V1=5V
-5 -30 -60 µA
7.14.5 ICSNPD CSN pull-down current In Vbat- standby
mode 53060µA
Table 29. Inputs: CLK, DI, PWM 1, PWM 2
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.6 tset
Delay time from standby
to active mode
Switching from
standby to active
mode. Time until
output drivers are
enabled after CSN
going to high.
160 300 µs
7.14.7 Vin L Input low level V1 = 5 V 1.0 2.05 2.5 V
7.14.8 Vin H Input high level V1 = 5 V 1.5 2.8 3.3 V
7.14.9 Vin Hyst Input hysteresis V1 = 5 V 0.4 0.75 1.5 V
7.14.10 I in Pull down current at input Vin = 1.5 V 5 30 60 µA
7.14.11 Cin(1)
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Input capacitance at input
CSN, CLK, DI and
PWM1,2
0V < V1 < 5.3V 10 15 pF
7.14.12 fCLK
SPI input frequency at
CLK 1MHz
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 49/68
7.14.3 Input PWM 2 Vth for flash mode
The voltages are referred to ground.
6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C, unless otherwise
specified.
7.14.4 DI timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 30. Input PWM2 Vth for flash mode
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.13 Vin L Input low level (Vin rising)) V1 = 5 V 6.1 7.25 8.4 V
7.14.14 Vin H
Input high level
(Vin falling) V1 = 5 V 7.4 8.4 9.4 V
7.14.15 Vin Hyst Input hysteresis V1 = 5 V 0.6 0.8 1.0 V
Table 31. DI timing
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.16 tCLK Clock period V1 = 5 V 1000 - ns
7.14.17 tCLKH Clock high time V1 = 5 V 400 - ns
7.14.18 tCLKL Clock low time V1 = 5 V 400 - ns
7.14.19 tset CSN
CSN setup time, CSN low
before rising edge of CLK V1 = 5 V 400 - ns
7.14.20 tset CLK
CLK setup time, CLK high
before rising edge of CSN V1 = 5 V 400 - ns
7.14.21 tset DI DI setup time V1 = 5 V 200 - ns
7.14.22 thold DI DI hold time V1 = 5 V 200 - ns
7.14.23 tr_in
Rise time of input signal
DI, CLK, CSN V1 = 5 V - 100 ns
7.14.24 tf_in
Fall time of input signal
DI, CLK, CSN V1 = 5 V - 100 ns
Electrical characteristics L9952GXP
50/68 Doc ID 13518 Rev 5
7.14.5 DO, FSO, Dig_Out3,4
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
7.14.6 DO timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 32. DO, FSO, Digout3,4
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.25 VDOL Output low level V1 = 5 V, ID = -4mA 0.5 V
7.14.26 VDOH Output high level V = 5 V, ID = 4 mA 4.5 V
7.14.27 IDOLK(1)
1. Not valid for FSO
Tristate leakage current VCSN = V1,
0 V < VDO <´V1 -10 10 uA
7.14.28 CDO Tristate input capacitance VCSN = V1,
0 V < V1 < 5.3 V 10 15 pF
Table 33. DO timing
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.29 tr DO DO rise time CL = 100 pF,
Iload = -1 mA -50100ns
7.14.30 tf DO DO fall time CL = 100 pF,
Iload = 1 mA -50100ns
7.14.31 ten DO tri L
DO enable time
from tristate to low level
CL = 100 pF,
Iload = 1 mA
pull-up load to V1
-50250ns
7.14.32 tdis DO L tri
DO disable time
from low level to tristate
CL = 100 pF,
Iload = 4 mA
pull-up load to V1
-50250ns
7.14.33 ten DO tri H
DO enable time
from tristate to high level
CL = 100 pF,
Iload = -1 mA
pull- down load to
GND
-50250ns
7.14.34 tdis DO H tri
DO disable time
from high level to tristate
CL = 100 pF,
Iload = -4 mA
pull-down load to
GND
-50250ns
7.14.35 td DO DO delay time
VDO < 0.3 V1,
VDO > 0.7 V1,
CL = 100 pF
-50250ns
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 51/68
7.14.7 CSN timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.5V < V1 < 5.3V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Figure 16. SPI - Input timing
Table 34. CSN timing
Item Symbol Parameter Test condition Min. Typ. Max. Unit
7.14.36 tCSN_HI,min
Minimum CSN HI time,
active mode
Transfer of SPI-
command to input
register
6--µs
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Va l id Valid
CSN
CLK
DI
tset CSN tCLKH tse t CLK
tCLKL
thold DI
tset DI
Electrical characteristics L9952GXP
52/68 Doc ID 13518 Rev 5
Figure 17. SPI - Edges timing
TfCLK TrCLK
CLK
0.8 Vcc
0.5 Vcc
0.2 Vcc
DO
(low to high
0.8 Vcc
0.2 Vcc
TrDO
TdDO
0.8 Vcc
0.2 Vcc
TfDO
DO
(high to low
TfCSN TrCSN
CSN
0.8 Vcc
0.5 Vcc
0.2 Vcc
50 %
50 %
TenDO_tri_L
TenDO_tri_H
TdisDO_L_tri
TdisDO_H_tri
L9952GXP Electrical characteristics
Doc ID 13518 Rev 5 53/68
Figure 18. SPI - CSN low to high transition
Figure 19. SPI - High to low transition
CSN
dON
t
20%
80%
tr in f in
t
OFF
t
dOFF
t
OFF state
ON state OFF state
ON state
ON
t
output current
of a driver
50%
50%
80%
20%
20%
80%
50%
output current
of a driver
C
S
N low to high: data
f
rom shi
f
tregister
is transferred to output power switches
tCSN_HI,min
CSN
CLK
DI
DO
CSN high to lo
w
and CLK sta
y
slo
w
:statusinfo
r
mation of data bit 0 (fault condition) is t
r
ansfe
r
ed to D
O
DI: data is not accepted
DO: status information of data bit 0 (fault condition) will stay as long as CSN is low
time
time
time
time
0
-
SPI control and status registers L9952GXP
54/68 Doc ID 13518 Rev 5
8 SPI control and status registers
8.1 SPI registers
24bit shift register: first 2 bits are address (A1,A0) and 22 bits are data.
During power-on reset, all registers are set to zero.
Note: During the shift in of the address bits, (2 clock periods) an internal error bit (Err) is fed to the
DO output.
D23,D22 -> error flags (seen from DO)
The error flag is generated by logic OR combination of following error bits:
VCC_Fail1,2; TSD1,2; TW; OV,UW; OC_HS1..4; OC_OUTHS; OC_REL1..2; OC_V2
Table 35. SPI registers
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
A1 A0 Data
Address
[write] On5V2 On Signals
Control
Register 0
GO
VCC
GO
VBAT
TRIG ON
V21
ON
V20
REL
2
REL
1
OUT
HS2
OUT
HS1
OUT
HS0
HS
42
HS
41
HS
40
HS
32
HS
31
HS
30
HS
22
HS
21
HS
20
HS
12
HS
11
HS
10
00 Address
[write]
Timer
2
Timer
1Loop Pullup / down Wakeup Sources OL Wakeup Sources
Control
Register 1
CLR
INT_en
T20 T13 T12 T11 T10 L2 L1 L0 U3 U2 U1 U0 W7 W6 W5 W4 W3 W2 W1 W0
01 Address
[write] Input config Reset level LIN Openload treshold
Control
Register 2
RES
I
CMP
LS
OVUV
LIN
Slope
IC
41
IC
40
IC
31
IC
30
IC
21
IC
20
IC
11
IC
10
LEV
1
LEV
0
TXT
TOUT
LINPU
O_HS
REC
VLOCK
OUT
OLT
HS4
OLT
HS3
OLT
HS2
OLT
HS1
10 Address
[read] Reserved Wakeup Wakeup input status Overcurrent Openload
Status
Register 0 RES RES COLD
START
L I N I NH WU4 WU3
WU2
WU1
SHT5
V2
Rel2
OC
Rel1
OC
HS
OC
HS4
OC
HS3
OC
HS2
OC
HS1
OC
HS
OL
HS4
OL
HS3
OL
HS2
OL
HS1
OL
Err Err Address
Reserved LIN State Watchdog Reset 5V Restarts State
Status
Register 1
RES
RES DOM
TXD
SHT
BAT
SHT
GND
TRIG
WD
3
WD
2
WD
1
WD
0R2 R1 R0 ST1 ST0 VCC2
Fail
VCC
1
Fail
TSD
2
TSD
1TW UV OV
Err Err Address
L9952GXP SPI control and status registers
Doc ID 13518 Rev 5 55/68
8.1.1 Control register 0
While writing to the control register 0, the status register 0 can be read at the DO-Output of
the SPI.
x
Table 36. Control register 0
5V2 Driver ON Signals
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access
w w w w w w w w w w w w w w w w w w w w w w
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name GO
V1
GO
Vbat
TRIG ON
V21
ON
V20
REL
2
REL
1
OUT
HS2
OUT
HS1
OUT
HS0
HS
42
HS
41
HS
40
HS
32
HS
31
HS
30
HS
22
HS
21
HS
20
HS
12
HS
11
HS
10
Table 37. Configuration bit HSxx
Name / state Definition/ function
HSx2 HSx1 HSx0 Defines the output configuration of the High Side Drivers 1-4
Table 38. Configuration bit OUT_HSx
Name / state Definition/ function
OUT_HS
2
OUT_HS
1
OUT_HS
0
Defines the output configuration of the High Side Driver OUT_HS
0 0 0 Driver is OFF in all modes
0 0 1 Driver is ON in active mode, off in standby mode
010
Driver is cyclic ON with the timing of Timer 1 in active mode and standby
modes
011
Driver is cyclic ON with the timing of Timer 2 in active mode and standby
modes
1 0 0 Driver is controlled by the PWM1 Input
1 0 1 Driver is controlled by the PWM2 Input
Table 39. Configuration bit RELx
Name / state Definition/ function
RELx Defines the Output configuration of the low side relay drivers 1/2
0 Driver is OFF in all modes
1 Driver is ON in active mode (off in standby mode)
Table 40. Configuration bit On_V2x
Name / state Definition/ function
On_V21 On_V20 Defines in which modes the voltage regulator 2 is on
0 0 Voltage regulator 2 is OFF in all modes
SPI control and status registers L9952GXP
56/68 Doc ID 13518 Rev 5
8.1.2 Control register 1
While writing to the control register 1, the status register 1 can be read at the DO-Output of
the SPI.
01
Voltage regulator 2 is ON in ACTIVE mode;
OFF in V1-standby, VBat-standby
10
Voltage regulator 2 is ON in ACTIVE mode and V1 standby;
OFF in Vbat-standby
1 1 Voltage regulator 2 is ON in all modes
Table 41. Configuration bit TRIG, GO_VBAT, GO_V1
TRIG Trigger bit for watchdog; inverted for each Trigger event invert this bit for a
proper watchdog trigger.
GO_VBAT ”1” enters the Vbat-standby mode. (dominant mode, if both standby modes
are selected)
GO_V1 “1” enters the V1-standby mode.
Table 40. Configuration bit On_V2x (continued)
Name / state Definition/ function
Table 42. Control register 1
Cyclic Timer 1/2 Loop Pull up Wakeup Sources
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access w w w w w w w w w w w w w w w w w w w w w w
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name CLR
INT_EN
T20 T13 T12 T11 T10 L2 L1 L0 U3 U2 U1 U0 W7 W6 W5 W4 W3 W2 W1 W0
Table 43. Configuration bit Wx
Name/state Definition/function
W7 W6 W5 W4 W3 W2 W1 W0 Disables the corresponding wake up sources
x x x x x x x 1 Input WU1 is disabled as wake up source
x x x x x x 1 x Input WU2 is disabled as wake up source
x x x x x 1 x x Input WU3 is disabled as wake up source
x x x x 1 x x x Input WU4 is disabled as wake up source
xxx1xxxx
Open load Appearance / Disappearance at OUT1 is
disabled as wake up source
xx1xxxxx
Open load Appearance / Disappearance at OUT2 is
disabled as wake up source
x1xxxxxx
Open load Appearance / Disappearance at OUT3 is
disabled as wake up source
L9952GXP SPI control and status registers
Doc ID 13518 Rev 5 57/68
1xxxxxxx
Open load Appearance / Disappearance at OUT4 is
disabled as wake up source
0 0 0 0 0 0 0 0 Default: all wake up sources are enabled
Table 44. Configuration bit Ux
Name/state Definition/function
U3 U2 U1 U0 Defines whether the Inputs WU1..4 are configured with current source or
current sink in standby mode.
xxx1
Input WU1 configured with a current source in standby mode
(RWU_act pulldown resistor in active mode - see Table 20.)
xx1x
Input WU2 configured with a current source in standby mode
(RWU_act pulldown resistor in active mode - see Table 20.)
x1xx
Input WU3 configured with a current source in standby mode
(RWU_act pulldown resistor in active mode - see Table 20.)
1xxx
Input WU4 configured with a current source in standby mode
(RWU_act pulldown resistor in active mode - see Table 20.)
0000
Default: All Inputs configured with a current sink in standby
(RWU_act pulldown resistor in active mode - see Table 20.)
Table 45. Configuration bit Lx
Name/state Definition/function
L2 L1 L0 Defines which signal is looped to the Dig_Out3 and Dig_Out4
(see note)
Dig_Out3 Dig_Out4
0 0 0 WU3 (default) WU4 (default)
001 HighZ WU4
010 WU3 HighZ
0 1 1 WU3 Open Load HS2
1 0 0 Open Load HS1 WU4
1 0 1 Open Load HS1 Open Load HS2
1 1 0 Open Load HS1 HighZ
1 1 1 HighZ Open Load HS2
Table 43. Configuration bit Wx (continued)
Name/state Definition/function
SPI control and status registers L9952GXP
58/68 Doc ID 13518 Rev 5
Note: In VBAT standby mode, DigOut 3 and DigOut4 are HighZ.
Table 46. Configuration bit Txx
Name/state Definition/function
T12 T11 T10 Defines the period of the cyclic sense Timer 1 which is selectable for Out
1..4 and Out_HS (see ON signals control register 0)
0 0 0 Period: 0.5 s
0 0 1 Period: 1.0 s
0 1 0 Period: 1.5 s
0 1 1 Period: 2.0 s
1 0 0 Period: 2.5 s
1 0 1 Period: 3.0 s
1 1 0 Period: 3.5 s
1 1 1 Period: 4.0 s
T13 Defines the ON time for the cyclic sense Timer1
0 ON time 10 ms
1 ON time 20 ms
T20 Defines the ON time of the cyclic sense Timer 2 which is selectable for Out
1..4 and OUTHS (see ON Signals control register 0)
0 Period 50 ms / ON time 100 us
1 Period 50 ms / ON time 1ms
Table 47. Configuration bit INT_enable
Name/state Definition/function
INT_enable
0Interrupt Mode disabled ( see Section 2.7 )
1Interrupt Mode enabled
CLR Clears the contents of status register 0 and 1
L9952GXP SPI control and status registers
Doc ID 13518 Rev 5 59/68
8.1.3 Control register 2
While writing to the control register 2, the status register 0 can be read at the DO-Output of
the SPI.
Table 48. Control register 2
Input filter configuration Reset
level LIN Open load threshold
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access W W W W W W W W W W W W W W W W W W W W W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name RES ICMP
LSO
VUV
LIN
Slope
IC
41
IC
40
IC
31
IC
30
IC
21
IC
20
IC
11
IC
10
LEV
1
LEV
0
TXDT
Out
LINP
U
O_HS
REC
VS
Lock
Out
OLT
HS4
OLT
HS3
OLT
HS2
OLT
HS1
Table 49. Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and
TXD_TOUT
Name/state Definition/function
OLT_HSx Open load threshold for the High Side Drivers Out1..4
0: Iopenload = 2mA; 1: Iopenload = 8mA
VSLOCK
Out
Automatic recovery after VS Over/Under voltage
“0” (default): Vs lockout is disabled, i.e. outputs will automatically recover (according
to output settings in CR0) after Vs over / under - voltage conditions has disappeared
“1”: Vs lockout is enabled, i.e. outputs will remain Off after Vs over / under voltage
recovery conditions has disappeared, until the Vs over / under voltage Status Bits
(SR1, bit s0,1) are cleared by CLR command (CR1, bit 21).
O_HS_REC “1” = Recovery mode for OUT_HS Driver.
LINPU “1” will disable the master pull up LINPU
TXD_TOUT “1” will disable the dominant TxD time-out for the LIN Interface.
Table 50. Configuration bit LEVx
Name/state Definition/function
LEV1 LEV0 Controls the reset level
0 0 Set the reset threshold to 4.65V, typ.
0 1 Set the reset threshold to 4.35V, typ.
1 X Reserved (do not use for operation, set LEV1 to “0”)
SPI control and status registers L9952GXP
60/68 Doc ID 13518 Rev 5
Table 51. Configuration bit ICxx
Name/state Definition/function
IC(1..4)1 IC(1..4)0 Selects the filter configuration for the
Wakeup Inputs WU1 to 4
IC11 0 0 Filter with 64 us Filter time (static sense)
IC21 0 1 Enable Filter after 80 us with a Filter time of 16 us (cyclic sensing),
timer2
IC31 1 0 Enable Filter after 800 us with a Filter time of 16 us (cyclic
sensing), timer2
IC41 1 1 Enable Filter after 800 us with a Filter time of 16 us (cyclic
sensing), timer1
Table 52. Configuration bit LIN slope, LS_ovuv and ICMP
Name/state Definition/function
LIN slope Change LIN slope
0 High slew rate (default)
1 Low slew rate
LS_ovuv Vs Over / Under voltage shutdown of REL1,2 (low side drivers)
0 Enable (default): REL1,2 turned Off in case of Vs Over/Undervoltage
1 Disable : REL1,2 remain On in case of Vs Over/Undervoltage
ICMP Current supervision of V1 regulator in V1-standby mode.
0 Enable (default)
1 Disable
RES Reserved
L9952GXP SPI control and status registers
Doc ID 13518 Rev 5 61/68
8.1.4 Status register 0
The contents of the status register 0 can be read implicitly, while accessing the control
register 0 or control register 2.
Table 53. Status register 0
Wakeup Inputs Over current Open load
Bit 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access r r r rrrrrr r r rrrrrrrrrrr
Reset 0 0 0 000000 0 0 00000000000
Name RES RES Cold
Start LIN INH WU
4
WU
3
WU
2
WU
1
SHT5V2
REL
2OC
REL
1OC
HS
OC
HS
4OC
HS
3OC
HS
2OC
HS
10C
HS
O L
HS
4OL
HS
3OL
HS
2OL
HS
1OL
Table 54. Configuration bit HSx_OL, HSx_OC and Relx_OC
Name/state Definition/function
HS1..4_OL Open load status from the High Side Driver OUT1..4.
0 No open load has been detected.
1 Open load has been detected.
HS_OL Open load status from the High Side Driver OUT_HS
0 No open load has been detected.
1 Open load has been detected.
HS1..4_OC Over current status from the High Side Driver OUT1..4.
0 No over current has been detected.
1 Over current has been detected.
HS_OC Over current status from the High Side Driver OUT_HS.
0 No over current has been detected.
1 Over current has been detected.
Rel 1,2_OC Over current status from Relais1,2
0 No over current has been detected.
1 Over current has been detected.
Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start
Name/state Definition/function
SHT5V2 V2 short to ground at turn on; condition: V2 < 2V for more than 4ms. “1” = fail
WU4...WU1 Status of the corresponding Inputs WU1..4 (according to filter settings in CR2)
SPI control and status registers L9952GXP
62/68 Doc ID 13518 Rev 5
Note: RES = reserved bits.
8.1.5 Status register 1
The contents of the status register 1 can be read implicitly, while accessing the control
register 1.
INH Wakeup initiated through INH source
LIN Wakeup initiated through LIN source
Cold Start Set to high when the internal Power on Reset occurs.
Will be cleared with the first SPI access.
Table 55. Configuration bit SHT5V2, WUx, INH, LIN and Cold Start (continued)
Name/state Definition/function
Table 56. Status register 1
LIN state WD resets 5V restarts State
Bit 2120191817161514131211109876543210
Access rr r r r r rrrrrrrrrrrrrrrr
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name RES RES DOM
TXD
SHT
BAT
SHT
GND
TRIG
WD
3
WD
2
WD
1
WD
0R2 R1 R0 ST1 ST0 V2
Fail
V1
Fail
TSD
2
TSD
1TW UV OV
Table 57. Configuration bit OV, UV, TW, TSDx and Vx Fail
Name Definition, function
OV Over voltage failure of Vs.
UV Under voltage failure of Vs.
TW Temperature Warning: the chip temperature exceeds 130°C
TSD1 Thermal shutdown #1: The chip temperature exceeds 140°C
All Outputs, except the voltage regulator 1 are switched off.
TSD2 Thermal shutdown #2: The chip temperature exceeds 155°C
All Outputs, including the voltage regulator 1 are switched off.
V1 Fail The output of Voltage Regulator 1 failed for at least 2µs. Conditions: (V1<2V for >2µs)
OR (V1<2V at 4ms after turn-on). ‘1’= fail
V2 Fail The output of Voltage Regulator 2 failed for at least 2µs. Conditions: (V2<2V for >2µs)
OR (V2<2V at 4ms after turn-on). ‘1’= fail
Table 58. Configuration bit STx
Name Mode
ST1 ST0
0 0 Active mode
0 1 V1-standby -> a readout is wake up condition -> active mode -> 00 is read
L9952GXP SPI control and status registers
Doc ID 13518 Rev 5 63/68
1 0 VBat-standby, a readout is not possible, as V1 is off
1 1 Flash Mode
Table 59. Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD
Name Definition, function
R2 R1 R0 Number of unsuccessfully restarts after thermal shutdown
WD3 WD2 WD1 WD0 Number of Watchdog time-outs (1)
1. Bits are cleared at every valid WD trigger or when forced sleep mode is entered (after 15 WD failures have
been detected)
TRIG Status of the Trigger bit from Control Register 0
SHT_GND LIN Short to ground
SHT_BAT LIN Short to battery
DOM_TXD Dominant TXT
RES Reserved
Table 58. Configuration bit STx (continued)
Name Mode
Package and packing information L9952GXP
64/68 Doc ID 13518 Rev 5
9 Package and packing information
9.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.2 PowerSSO-36 package information
Figure 20. PowerSSO-36 package dimensions
Table 60. PowerSSO-36 mechanical data
Symbol
Millimeters
Min. Typ. Max.
A- -2.45
A2 2.15 - 2.35
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
L9952GXP Package and packing information
Doc ID 13518 Rev 5 65/68
D 10.10 - 10.50
E7.4 - 7.6
e-0.5-
e3 - 8.5 -
F-2.3-
G- -0.1
G1 - - 0.06
H 10.1 - 10.5
h--0.4
k0°-8°
L 0.55 - 0.85
M-4.3-
N - - 10 deg
O-1.2-
Q-0.8-
S-2.9-
T - 3.65 -
U-1.0-
X4.1 - 4.7
Y6.5 - 7.1
Table 60. PowerSSO-36 mechanical data (continued)
Symbol
Millimeters
Min. Typ. Max.
Package and packing information L9952GXP
66/68 Doc ID 13518 Rev 5
9.3 PowerSSO-36 packing information
Figure 21. PowerSSO-36 tube shipment (no suffix)
Figure 22. PowerSSO-36 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
C
B
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
L9952GXP Revision history
Doc ID 13518 Rev 5 67/68
10 Revision history
Table 61. Document revision history
Date Revision Changes
24-Aug-2007 1 Initial release.
07-Sep-2007 2
Table 18: High side outputs (OUT 1..4): modified openload detection
current 1 parameter value (item 7.8.13).
Table 20: Wake up inputs(WU1...WU4): modified Input current in
standby mode test condition (item 7.10.5).
Table 22: LIN receiver: modified symmetry of transmitter propagation
delay time parameter value (item 7.12.24).
Added Section 9.3: PowerSSO-36 packing information.
21-Sep-2007 3
Section 7.2: Oscillator: changed Vs minimum value from 7 to 6 V.
Table 10: Supply and supply monitoring:
– changed parameter 7.1.10 (IV(BATWU)) max value from 300 to 320 µA
– changed parameter 7.1.11 (IV(BATWU)) max value from 380 to 410 µA.
11-Apr-2008 4
Modified Figure 4.: Watchdog
Modified Section 2.13: Low side driver outputs Rel1, Rel2.
Added note to Section 2.2.2: Flash mode.
Section Table 48.: Control register 2: changed definition to VS Lock Out
parameter.
Added Section 6.3: Package and PCB thermal data.
Modified Section 7.14.3: Input PWM 2 Vth for flash mode.
Table 42: Control register 1: modified "pull down" settings for the wake-
up inputs WU1..4 .
08-Jul-2009 5
Table 60: PowerSSO-36 mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added k row
– Changed G (max) value from 0.075 to 0.1
L9952GXP
68/68 Doc ID 13518 Rev 5
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