K4S643232H-TC60 - Samsung Electronics

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

Revision 1.3

February 2004

*Samsung Electronics reserves the right to change products or specification without notice.

64Mb H-die (x32) SDRAM Specification

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

Revision 0.0 (June, 2003)

- Target spec First release.

Revision 0.1 (July, 2003)

- Delete speed 4.5ns.

Revision 0.2 (September, 2003)

- Preliminary spec release.

Revision 1.0 (November, 2003)

- Final spec release.

Revision 1.1 (December, 2003)

- Corrected typo .

Revision 1.2 (December, 2003)

- Modified load cap 50pF -> 30pF & Typo.

Revision 1.3 (February, 2004)

- Corrected typo.

Revision History

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated

with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cyc le control with the use of sy stem clock .

I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable

latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

512K x 32Bit x 4 Banks SDRAM

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period(4K Cycle)

FEATURES

GENERAL DESCRIPTION

Part No. Orgainization Max Freq. Interface Package

K4S643232H-TC/L70

512K x 32

143MHz(CL=3)

LVTTL 86pin TSOP(II)

K4S643232H-TC/L60 166MHz(CL=3)

K4S643232H-TC/L55 183MHz(CL=3)

K4S643232H-TC/L50 200MHz(CL=3)

Ordering Information

Row & Column address configuration

Organization Row Address Column Address

2Mx32 A0~A10 A0-A7

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

0.002

0.05 MIN

0.008

0.21

± 0.002

± 0.05

0.020

0.50

( )

0.005 -0.001

+0.003

0.125 -0.035

+0.075

0.400

10.16

0.45~0.75

0.018~0.030

0.010

0.25 TYP

0~8°C

0.004

0.10 MAX

0.024

0.61

( ) 0.0079

0.20 0.0197

0.50

0.047

1.20 MAX

0.039

1.00

± 0.004

± 0.10

0.891

22.62 MAX

0.875

22.22

± 0.004

± 0.10

+0.07

-0.03

+0.003

-0.001

86Pin TSOP(II) Package Dimension

Package Physical Dimension

11.76±0.20

0.463±0.008

#86 #44

#1 #43

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

FUNCTIONAL BLOC K DIAGRAM

Bank Select

Data Input Register

512K x 32

Sense AMP

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Address Register

Row Buffer

Refresh Counter

Row Decoder Col. Buffer

LRAS

LCBR

LCKE

LRAS LCBR LWE

CLK CKE CS RAS CAS WE DQM

LWE

LDQM

DQi

CLK

ADD

LCAS LWCBR

512K x 32

Timing Register

LDQM

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

PIN CONFIGURATION (Top view)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

N.C

VDD

DQM0

CAS

RAS

N.C

BA0

BA1

A10/AP

DQM2

VDD

N.C

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

N.C

VSS

DQM1

N.C

CLK

CKE

DQM3

VSS

N.C

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS 86Pin TSOP (II)

(400mil x 875mil)

(0.5 mm Pin pitch)

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.

CS Chip select Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM.

CKE Clock enable Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disables input buffers for power down mode.

A0 ~ A10 Address Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

BA0,1 Bank select address Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE Write enable Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.

VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise

immunity.

NC No Connection This pin is recommended to be left No connection on the device.

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V

Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1

Input logic low voltage VIL -0.3 0 0.8 V 2

Output logic high voltage VOH 2.4 - - V IOH = -2mA

Output logic low voltage VOL --0.4VIOL = 2mA

Input leakage current ILI -10 - 10 uA 3

1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ,

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1W

Short circuit current IOS 50 mA

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock CCLK -4pF

RAS, CAS, WE, CS, CKE, DQM CIN -4.5pF

Address CADD -4.5pF

DQ0 ~ DQ31 COUT -6.5pF

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C

Parameter Symbol Test Condition CAS

Latency Speed Unit Note

50 55 60 70

Operating Current

(One Bank Active) ICC1 Burst Length =1

tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA 3 140 140 130 130 mA 2

2110

Precharge Standby Current in

power-down mode ICC2PCKE ≤ VIL(max), tCC = 10ns 2 mA

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞2

Precharge Standby Current

in non power-down mode

ICC2NCKE ≥ VIH(min), C S ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 30ns 12

ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 7

Active Standby Curr ent

in power-down mode ICC3PCKE ≤ VIL(max), tCC = 10ns 4 mA

ICC3PS CKE ≤ VIL(max), tCC = ∞4

Active Standby Curr ent

in non power-down mode

(One Bank Active)

ICC3NCKE ≥ VIH(min), C S ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 30ns 40

ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable 35

Operating Current

(Burst Mode) ICC4 Io = 0 mA, Page Burst

All bank Activated, tCCD = tCCD(min) 3 170 160 150 140 mA 2

2120

Refresh Current ICC5 tRC ≥ tRC(min) 3 150 150 140 120 mA 3

2120

Self Refresh Current ICC6 CKE ≤ 0.2V C2mA4

L450 uA 5

DC CHARACTERISTICS

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.

3. Refresh period is 64ms.

4. K4S643232H-TC

5. K4S643232H-TL

Notes :

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4/0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall time tr/tf = 1/1 ns

Output timing measurement reference level 1.4 V

Output load condition See Fig. 2

3.3V

1200Ω

870Ω

Output

30pF

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Vtt = 1.4V

50Ω

Output

30pF

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Note :

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol Version Unit Note

50 55 60 70

Row active to row active delay tRRD(min) 2CLK1

RAS to CAS delay tRCD(min) 32323232CLK1

Row precharge time tRP(min) 32323232CLK1

Row active time tRAS(min) 85757575CLK1

tRAS(max) 100 us

Row cycle time tRC(min)117107107107CLK1

Last data in to row precharge tRDL(min) 2CLK2

Last data in to new col.address delay tCDL(min) 1CLK2

Last data in to burst stop tBDL(min) 1CLK2

Col. address to col. address delay tCCD(min) 1CLK3

Mode Register Set cycle time tMRS(min) 2CLK

Number of valid

output data CAS Latency=3 2 ea 4

CAS Latency=2 1

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

AC CHARACTERISTICS (AC operating condition s unless otherwise noted)

Parameter Symbol 50 55 60 70 Unit Note

Min Max Min Max Min Max Min Max

CLK cycle time CAS Latency=3 tCC 51000 5.5 1000 61000 71000 ns 1

CAS Latency=210101010

CLK to valid

output delay CAS Latency=3 tSAC -4.5-5.0-5.5-5.5

ns 1, 2

CAS Latency=2 -6-6-6-6

Output data hold time tOH 2-2-2-2-ns2

CLK high pulse

width CAS Latency=3 tCH 2-2-2.5-3-

ns 3

CAS Latency=2 3-3-3-3-

CLK low

pulse width CAS Latency=3 tCL 2-2-2.5-3-

ns 3

CAS Latency=2 3-3-3-3-

Input setup time CAS Latency=3 tSS 1.5 - 1.5 - 1.5 - 1.75 - ns 3

CAS Latency=2 2.5-2.5-2.5-2.5-

Input hold time tSH 1-1-1-1-ns3

CLK to output in Low-Z tSLZ 1-1-1-1-ns2

CLK to output

in Hi-Z CAS latency=3 tSHZ -4.5-5.0-5.5-5.5

ns -

CAS latency=2 -6-6-6-6

CMOS SDRAM

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SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

SIMPLIFIED TRUTH TABLE

(V=V alid, X=Don′t care, H=Logic high, L=Logic low)

Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11,

A9 ~ A0Note

Refresh

Auto refresh HHLL LHX X 3

Self

refresh

Entry L 3

Exit L H LHHHXX3

HX XX 3

Bank active & row addr. H X L L H H X V Row address

Read &

column address Auto precharge disable HXLHLHXVLColumn

address 4

Auto precharge enable H 4,5

Wri te &

column address Auto precharge disable HXLHLLXVLColumn

address 4

Auto precharge enable H 4,5

Burst Stop H X L H H L X X 6

Precharge Bank selection HXLLHLX

VL X

All banks XH

Clock suspend or

active power down Entry H L HX XXXX

LVVV

Exit L H X X X X X

Precharge power down mode

Entry H L HX XXX

LHHH

Exit L H HX XXX

LVVV

DQM H V X 7

No operation command H X HX XXXX

LHHH

1. OP Code : Operand code

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and B A1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Notes :