1
FEATURES
PIN ASSIGNMENTS
APPLICATIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI
AI
AO
E1
BO
BI
BI
GND
VCC
DI
DI
DO
E2
CO
CI
CI
D PACKAGE
(TOP VIEW)
DESCRIPTION
AI AO
BO
CO
DO
AIAI
BI
BI
C1
C1
D1
D1D1
E2
E1
Enable Truth Table
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008www.ti.com
QUAD DIFFERENTIAL PECL RECEIVERS
The power-down loading characteristics of thereceiver input circuit are approximately 8 k Ωrelative•Low-Voltage Functional Replacements for the
to the power supplies; hence they do not load theAgere BRF1A, BRF2A, BRS2A, and BRS2B
transmission line when the circuit is powered down.•Pin-Equivalent to General Trade 26LS32
The package for these differential line receivers is theDevices
16-pin SOIC (D) package.•High-Input Impedance Approximately 8 k Ω
The enable inputs of this device include internal•3.5-ns Maximum Propagation Delay
pullup resistors of approximately 40 k Ωthat are•TB3R1 Provides 50-mV Hysteresis
connected to V
CC
to ensure a logical high level inputif the inputs are open circuited.•TB3R2 With -125-mV Threshold Offset forPreferred State Output•-0.5-V to 5.2-V Common Mode Range•Single 3.3 V 10% Supply•Slew Rate Limited (0.5 ns min 80% to 20%)•TB3R2 Output Defaults to Logic 1 When InputsLeft Open or Shorted to V
CC
or GND•ESD Protection HBM > 3 kV, CDM > 2 kV•Operating Temperature Range: -40 °C to 85 °C•Available SOIC (D) Package
•Digital Data or Clock Transmission OverBalanced Lines
FUNCTIONAL BLOCK DIAGRAM
These quad differential receivers accept digital dataover balanced transmission lines. They translatedifferential input logic levels to TTL output logiclevels.
The TB3R1 is a pin- and function-compatiblereplacement for the Agere Systems BRF1A andBRF2A; it includes 3-kV HBM and 2-kV CDM ESDprotection.
The TB3R2 is a pin- and function-compatiblereplacement for the Agere Systems BRS2A andBRS2B and incorporates a -125-mV receiver input
E1 E2 CONDITIONoffset, preferred state output, 3-kV HBM and 2-kVCDM ESD protection. The TB3R2 preferred state
0 0 Activefeature places the output in the high state when the
1 0 Activeinputs are open, shorted to ground, or shorted to the
0 1 Disabledpower supply.
1 1 Active
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
POWER DISSIPATION RATINGS
ABSOLUTE MAXIMUM RATINGS
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER PART MARKING Package LEAD FIISH STATUS
TB3R1D TB3R1 SOIC NiPdAu ProductionTB3R2D TB3R2 SOIC NiPdAu Production
THERMAL RESISTANCE, DERATINGCIRCUIT BOARD POWER RATING POWER RATINGPACKAGE JUNCTION-TO-AMBIENT FACTOR
(1)MODEL T
A
≤25 °C T
A
= 85 °CWITH NO AIR FLOW T
A
≥25 °C
Low-K
(1)
763 mW 131.1 °C/W 7.6 mW/ °C 305 mWD
High-K
(2)
1190 mW 84.1 °C/W 11.9 mW/C 475 mWLow-K
(1)
831 mW 120.3 °C/W 8.3 mW/ °C 332 mWDW
High-K
(2)
1240 mW 80.8 °C/W 12.4 mW/ °C 494 mW
(1) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.(2) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICs
PARAMETER PACKAGE VALUE UNIT
D 47.5 °C/Wθ
JB
Junction-to-Board Thermal Resistance
DW 53.7 °C/WD 44.2 °C/Wθ
JC
Junction-to-Case Thermal Resistance
DW 47.1 °C/W
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Supply voltage, V
CC
0 V to 6 VMagnitude of differential bus (input) voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V| 6.5 VHuman Body Model
(2)
All pins 3 kVESD
Charged-Device Model
(3)
All pins 2 kVContinuous power dissipation See Dissipation Rating TableStorage temperature, T
stg
-65 °C to 150 °C
(1) Stresses beyond those listed under „ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under „ recommended operatingconditions ” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
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RECOMMENDED OPERATING CONDITIONS
DEVICE ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
MIN Nom MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 VBus pin input voltage, V
AI
, V, V
BI
, V, V
CI
, V, V
DI
, V -0.6
(1)
5.3 VMagnitude of differential input voltage, |V
AI
- V|, |V
BI
- V|, |V
CI
- V|, |V
DI
- V| 0.1 5 VOperating free-air temperature, T
A
-40 85 C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unlessotherwise noted.
over operating free-air temperature range unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Outputs disabled 34 mAI
CC
Supply current
(1)
Outputs enabled 32 mA
(1) Current is dc power draw as measured through GND pin and does not include power delivered to load.
over operating free-air temperature range unless otherwise noted
parameter test conditions min typ max unit
V
OL
Output low voltage V
CC
= 3 V, I
OL
= 8 mA 0.4 VV
OH
Output high voltage V
CC
= 3 V, I
OH
= -400 A 2.4 VV
IL
Low level enable input voltage
(1)
V
CC
= 3.6 V 0.8 VV
IH
High level enable input voltage
(1)
V
CC
= 3.6 V 2 VV
IK
Enable input clamp voltage V
CC
= 3 V, I
I
= -5 mA -1
(2)
VTB3R1 100 mVV
TH+
Positive-going differential input threshold voltage
(1)
, (V
xl
- V) x = A, B, C, or D
TB3R2
(3)
-50 mVTB3R1 -100
(2)
mVV
TH-
Negative-going differential input threshold voltage
(1)
, (V
xl
- V) x = A, B, C, or D
TB3R2
(3)
-200
(2)
mVV
HYST
Differential input threshold voltage hysteresis, (V
TH+
- V
TH_
) TB3R1 50 mVI
OZL
V
O
= 0.4 V -20
(2)
AOutput off-state current, (High-Z) V
CC
= 3.6 VI
OZH
V
O
= 2.4 V 20 AI
OS
Output short circuit current
(4)
V
CC
= 3.6 V -100
(2)
mAI
IL
Enable input low current V
CC
= 3.6 V, V
IN
= 0.4 V -400
(2)
AEnable input high current V
IN
= 2.7 V 20 AI
IH
V
CC
= 3.6 VEnable input reverse current V
IN
= 3.6 V 100 AII
L
Differential input low current V
CC
= 3.6 V, V
IN
= -1.2 V -2
(2)
mAI
IH
Differential input high current V
CC
= 3.6 V, V
IN
= 5.3 V 1 mAR
O
Output resistance 20 Ω
(1) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.(2) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the originalAgere data sheet.(3) Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recomended that all unused positive inputs betied to the positive power supply. No external series resistor is required.)(4) Test must be performed one lead at a time to prevent damage to the device.
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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SWITCHING CHARACTERISTICS
TYPICAL CHARACTERISTICS
0
2
4
6
8
0 50 100 150 200
tpd - Propagation Delay T ime - ns
CL - Load Capacitance - pF
tPHL
tPLH
TA = 255C
VCC = 3.3 V
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
over operating free-air temperature range unless otherwise noted
uniparameter test conditions min typ max
t
t
PLH
Propagation delay time, low-to-high-level output 1.8 3.5C
L
= 0 pF
(1)
, See Figure 2 and Figure 4 nst
PHL
Propagation delay time, high-to-low-level output 1.8 3.5t
PLH
Propagation delay time, low-to-high-level output 2.3 4C
L
= 15 pF, See Figure 2 and Figure 4 nst
PHL
Propagation delay time, high-to-low-level output 2.3 4t
PHZ
Output disable time, high-level-to-high-impedance output
(2)
4.4 12 nsC
L
= 5 pF See Figure 3 and Figure 5t
PLZ
Output disable time, low-level-to-high-impedance output
(2)
3.3 12 nsC
L
= 10 pF, See Figure 2 and Figure 4 0.7 nst
skew1
Pulse width distortion, |t
PHL
- t
PLH
|
C
L
= 150 pF, See Figure 2 and Figure 4 4 nsC
L
= 10 pF, T
A
= 75C, See Figure 2 and
0.8 1.4 nsFigure 4Δt
skew1p-p
Part-to-part output waveform skew
(3)
C
L
= 10 pF, T
A
= -40C to 85C, See
1.5 nsFigure 2 and Figure 4
Δt
skew
Same part output waveform skew
(3)
C
L
= 10 pF, See Figure 2 and Figure 4 0.3 nst
PZH
Output enable time, high-impedance-to-high-level output
(2)
6 12 nsC
L
= 10 pF, See Figure 3 and Figure 4t
PZL
Output enable time, high-impedance-to-low-level output
(2)
4 12 nst
TLH
Rise time (20%-80%) 0.5 2 nsC
L
= 10 pF, See Figure 2 and Figure 4t
THL
Fall time (80%-20%) 0.5 2 ns
(1) The propagation delay values with a 0 pF load are based on design and simulation.(2) See Table 1.(3) Output waveform skews are when devices operate with the same supply voltage, same temperature, have the same packages and thesame test circuits.
TYPICAL PROPAGATION DELAYvsLOAD CAPACITANCE
A. NOTE
:
This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay isthe sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above asthe 0 pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitancerepresents the extrinsic, or external delay contributed by the load.Figure 1. Typical Propagation Delay vs Load Capacitance at 25C
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OUTPUT
3.7 V
2.7 V
3.2 V
VOH
VOL
1.5 V
tTHL
tPHL tPLH
tTLH
20%
80%
20%
80%
INPUT
INPUT
OUTPUT
2.4 V
0.4 V
1.5 V
tPHZ tPZH tPLZ tPZL
0.2 V
0.2 V
0.2 V 0.2 V
0.4 V
2.4 V
1.5 V
E1(A)
E1(B)
VOH
VOL
TO OUTPUT
CL
OF DEVICE
UNDER TEST
CLincludes test-fixture and probe capacitance.
TO OUTPUT
OF DEVICE
UNDER TEST CL
500 W1.5 V
CLincludes test-fixture and probe capacitance.
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
Figure 2. Receiver Propagation Delay Times
A. E2 = 1 while E1 changes states.B. E1 = 0 while E2 changes states.
Figure 3. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the datatransmission driver devices are measured with the following output load circuits.
Figure 4. Receiver Propagation Delay Time and Enable Time (t
PZH
, t
PZL
) Test Circuit
Figure 5. Receiver Disable Time (t
PHZ
, t
PLZ
) Test Circuit
Copyright © 2003 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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1
2
3
4
5
-50 0 50 100 150
- High to Low Propagation Delay - ns
tPHL
VCC = 3.3 V
Nom
Min
Max
TA - Free-Air Temperature - 5C
15
20
25
30
35
-50 0 50 100 150
TA - Free-Air Temperature - 5C
ICC - Supply Current - mA
ICC max at VCC = 3.6 V
ICC Typical at VCC = 3.3 V
0
0.5
1
1.5
2
2.5
3
3.5
-50 0 50 100 150
VCC = 3.3 V VOH min
VOL max
- Output Voltage - V
VO
TA - Free-Air Temperature - °C
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH PROPAGATION DELAY HIGH-TO-LOW PROPAGATION DELAYvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 6. Figure 7.
MINIMUM V
OH
AND MAXIMUM V
OL
TYPICAL AND MAXIMUM I
CCvs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 8. Figure 9.
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APPLICATION INFORMATION
Power Dissipation
ȍǒVSn ISnǓ
(1)
ȍ(VLn ILn)
(2)
TJ+TA)ǒPD qJAǓ
(3)
TJ+TA)ǒPD qJA(S)Ǔ
(4)
qJA(S) +ƪǒqJC)qCAǓ ǒqJB)qBAǓƫ
ǒqJC)qCA)qJB)qBAǓ
(5)
40
60
80
100
120
140
0 100 200 300 400 500
D, Low−K
DW, Low−K
D, High−K
DW, High−K
Thermal Impedance − C/W
Air Flow − LFM
TB3R1 , TB3R2
SLLS587C – NOVEMBER 2003 – REVISED JANUARY 2008
which the device is mounted, and on the airflow overthe device and PCB. JEDEC/EIA has definedstandardized test conditions for measuring θ
JA
. TwoThe power dissipation rating, often listed as the
commonly used conditions are the low-K and thepackage dissipation rating, is a function of the
high-K boards, covered by EIA/JESD51-3 andambient temperature, T
A
, and the airflow around the
EIA/JESD51-7 respectively. Figure 10 shows thedevice. This rating correlates with the device's
low-K and high-K values of θ
JA
versus air flow for thismaximum junction temperature, sometimes listed in
device and its package options.the absolute maximum ratings tables. The maximum
The standardized θ
JA
values may not accuratelyjunction temperature accounts for the processes and
represent the conditions under which the device ismaterials used to fabricate and package the device,
used. This can be due to adjacent devices acting asin addition to the desired life expectancy.
heat sources or heat sinks, to nonuniform airflow, orThere are two common approaches to estimating the
to the system PCB having significantly differentinternal die junction temperature, T
J
. In both of these
thermal characteristics than the standardized testmethods, the device internal power dissipation P
D
PCBs. The second method of system thermalneeds to be calculated This is done by totaling the
analysis is more accurate. This calculation uses thesupply power(s) to arrive at the system power
power dissipation and ambient temperature, alongdissispation:
with two device and two system-level parameters:• θ
JC
, the junction-to-case thermal resistance, indegrees Celsius per wattand then subtracting the total power dissipation of the
• θ
JB
, the junction-to-board thermal resistance, inexternal load(s):
degrees Celsius per watt• θ
CA
, the case-to-ambient thermal resistance, indegrees Celsius per wattThe first T
J
calculation uses the power dissipation
• θ
BA
, the board-to-ambient thermal resistance, inand ambient temperature, along with one parameter:
degrees Celsius per watt.θ
JA
, the junction-to-ambient thermal resistance, in
In this analysis, there are two parallel paths, onedegrees Celsius per watt.
through the case (package) to the ambient, andThe product of P
D
and θ
JA
is the junction temperature
another through the device to the PCB to therise above the ambient temperature. Therefore:
ambient. The system-level junction-to-ambientthermal impedance, θ
JA(S)
, is the equivalent parallelimpedance of the two parallel paths:
where
The device parameters θ
JC
and θ
JB
account for theinternal structure of the device. The system-levelparameters θ
CA
and θ
BA
take into account details ofthe PCB construction, adjacent electrical andmechanical components, and the environmentalconditions including airflow. Finite element (FE), finitedifference (FD), or computational fluid dynamics(CFD) programs can determine θ
CA
and θ
BA
. Detailson using these programs are beyond the scope ofthis data sheet, but are available from the softwaremanufacturers.
Figure 10. Thermal Impedance vs Air Flow
Note that θ
JA
is highly dependent on the PCB on
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TB3R1D ACTIVE SOIC D 16 40 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R1DE4 ACTIVE SOIC D 16 40 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R1DR ACTIVE SOIC D 16 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R1DRE4 ACTIVE SOIC D 16 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2D ACTIVE SOIC D 16 40 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2DE4 ACTIVE SOIC D 16 40 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2DR ACTIVE SOIC D 16 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
TB3R2DRE4 ACTIVE SOIC D 16 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Oct-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TB3R1DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TB3R2DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TB3R1DR SOIC D 16 2500 367.0 367.0 38.0
TB3R2DR SOIC D 16 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
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