REJ09B0104-0100Z 32 H8SX/1520Group Hardware Manual Renesas 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series H8SX/1527 H8SX/1525 Rev.1.00 Revision Date: Mar. 15, 2004 R5F61527 R5F61525 Rev. 1.00, 03/04, page ii of xxxvi Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 1.00, 03/04, page iii of xxxvi General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 1.00, 03/04, page iv of xxxvi Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 1.00, 03/04, page v of xxxvi Preface The H8SX/1520 Group is a single-chip microcomputer made up of the high-speed internal 32-bit H8SX CPU as its core, and the peripheral functions required to configure a system. The H8SX CPU is upward compatible with the H8/300, H8/300H, and H8S CPUs. Target Users: This manual was written for users who will be using the H8SX/1520 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8SX/1520 Group to the target users. Refer to the H8SX Programming Manual for a detailed description of the instruction set. Notes on reading this manual: In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, and peripheral functions. In order to understand the details of the CPU's functions Read the H8SX Programming Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ Rev. 1.00, 03/04, page vi of xxxvi H8SX/1520 Group manuals: Document Title Document No. H8SX/1520 Group Hardware Manual This manual H8/SX Programming Manual REJ09B0102 Rev. 1.00, 03/04, page vii of xxxvi Rev. 1.00, 03/04, page viii of xxxvi Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Features............................................................................................................................. 1 Block Diagram .................................................................................................................. 2 Pin Assignments................................................................................................................ 4 1.3.1 Pin Assignments .................................................................................................. 4 1.3.2 Pin Configuration in Each Operating Mode......................................................... 6 1.3.3 Pin Functions ....................................................................................................... 10 Section 2 CPU....................................................................................................17 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Features............................................................................................................................. 17 CPU Operating Modes...................................................................................................... 19 2.2.1 Normal Mode....................................................................................................... 19 2.2.2 Middle Mode ....................................................................................................... 21 2.2.3 Advanced Mode................................................................................................... 22 2.2.4 Maximum Mode .................................................................................................. 23 Instruction Fetch ............................................................................................................... 25 Address Space................................................................................................................... 25 Registers............................................................................................................................ 26 2.5.1 General Registers................................................................................................. 27 2.5.2 Program Counter (PC) ......................................................................................... 28 2.5.3 Condition-Code Register (CCR).......................................................................... 28 2.5.4 Extended Control Register (EXR) ....................................................................... 29 2.5.5 Vector Base Register (VBR)................................................................................ 30 2.5.6 Short Address Base Register (SBR)..................................................................... 30 2.5.7 Multiply-Accumulate Register (MAC)................................................................ 30 2.5.8 Initial Values of CPU Registers ........................................................................... 30 Data Formats..................................................................................................................... 31 2.6.1 General Register Data Formats ............................................................................ 31 2.6.2 Memory Data Formats ......................................................................................... 32 Instruction Set ................................................................................................................... 33 2.7.1 Instructions and Addressing Modes..................................................................... 35 2.7.2 Table of Instructions Classified by Function ....................................................... 39 2.7.3 Basic Instruction Formats .................................................................................... 50 Addressing Modes and Effective Address Calculation..................................................... 51 2.8.1 Register DirectRn ............................................................................................ 52 2.8.2 Register Indirect@ERn .................................................................................... 52 2.8.3 Register Indirect with Displacement @(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)................................................................................................... 52 Rev. 1.00, 03/04, page ix of xxxvi 2.8.4 2.9 Index Register Indirect with Displacement@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L).................. 52 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement@ERn+, @-ERn, @+ERn, or @ERn- ............................. 53 2.8.6 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32.................................... 54 2.8.7 Immediate#xx .................................................................................................. 55 2.8.8 Program-Counter Relative@(d:8, PC) or @(d:16, PC): .................................. 55 2.8.9 Program-Counter Relative with Index Register@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)......................................................................... 55 2.8.10 Memory Indirect@@aa:8 ................................................................................ 56 2.8.11 Extended Memory Indirect@@vec:7 .............................................................. 57 2.8.12 Effective Address Calculation ............................................................................. 57 2.8.13 MOVA Instruction............................................................................................... 59 Processing States............................................................................................................... 60 Section 3 MCU Operating Modes ..................................................................... 61 3.1 3.2 3.3 3.4 Operating Mode Selection ................................................................................................ 61 Register Descriptions........................................................................................................ 62 3.2.1 Mode Control Register (MDCR) ......................................................................... 62 3.2.2 System Control Register (SYSCR)...................................................................... 63 Operating Mode Descriptions ........................................................................................... 65 3.3.1 Mode 1................................................................................................................. 65 3.3.2 Mode 2................................................................................................................. 65 3.3.3 Mode 3................................................................................................................. 65 Address Map ..................................................................................................................... 66 3.4.1 Address Map (Advanced Mode).......................................................................... 66 Section 4 Exception Handling ........................................................................... 67 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Exception Handling Types and Priority............................................................................ 67 Exception Sources and Exception Handling Vector Table ............................................... 68 Reset ................................................................................................................................. 70 4.3.1 Reset Exception Handling ................................................................................... 70 4.3.2 Interrupts after Reset............................................................................................ 70 4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 71 Traces................................................................................................................................ 72 Address Error.................................................................................................................... 73 4.5.1 Address Error Source........................................................................................... 73 4.5.2 Address Error Exception Handling...................................................................... 74 Interrupts........................................................................................................................... 75 4.6.1 Interrupt Sources.................................................................................................. 75 4.6.2 Interrupt Exception Handling .............................................................................. 76 Instruction Exception Handling ........................................................................................ 77 4.7.1 Trap Instruction ................................................................................................... 77 Rev. 1.00, 03/04, page x of xxxvi 4.8 4.9 4.7.2 Exception Handling by General Illegal Instruction.............................................. 78 Stack Status after Exception Handling.............................................................................. 79 Usage Note........................................................................................................................ 80 Section 5 Interrupt Controller ............................................................................81 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Features............................................................................................................................. 81 Input/Output Pins .............................................................................................................. 83 Register Descriptions ........................................................................................................ 83 5.3.1 Interrupt Control Register (INTCR) .................................................................... 84 5.3.2 CPU Priority Control Register (CPUPCR) .......................................................... 84 5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR).......................... 86 5.3.4 IRQ Enable Register (IER) .................................................................................. 88 5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ............................... 90 5.3.6 IRQ Status Register (ISR).................................................................................... 95 5.3.7 Software Standby Release IRQ Enable Register (SSIER) ................................... 96 Interrupt Sources............................................................................................................... 97 5.4.1 External Interrupts ............................................................................................... 97 5.4.2 Internal Interrupts ................................................................................................ 98 Interrupt Exception Handling Vector Table...................................................................... 99 Interrupt Control Modes and Interrupt Operation ............................................................. 106 5.6.1 Interrupt Control Mode 0 ..................................................................................... 106 5.6.2 Interrupt Control Mode 2 ..................................................................................... 108 5.6.3 Interrupt Exception Handling Sequence .............................................................. 110 5.6.4 Interrupt Response Times .................................................................................... 111 5.6.5 DMAC Activation by Interrupt............................................................................ 112 CPU Priority Control Function Over DMAC ................................................................... 114 Usage Notes ...................................................................................................................... 116 5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 116 5.8.2 Instructions that Disable Interrupts ...................................................................... 117 5.8.3 Times when Interrupts are Disabled .................................................................... 117 5.8.4 Interrupts during Execution of EEPMOV Instruction.......................................... 117 5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions................... 117 5.8.6 Interrupt Flags of Peripheral Modules ................................................................. 118 Section 6 Bus Controller (BSC).........................................................................119 6.1 6.2 6.3 6.4 6.5 Features............................................................................................................................. 119 Register Descriptions ........................................................................................................ 120 6.2.1 Bus Control Register 2 (BCR2) ........................................................................... 120 Bus Configuration............................................................................................................. 121 Multi-Clock Function........................................................................................................ 122 Internal Bus....................................................................................................................... 123 6.5.1 Access to Internal Address Space ........................................................................ 123 Rev. 1.00, 03/04, page xi of xxxvi 6.6 6.7 6.8 6.9 Write Data Buffer Function .............................................................................................. 124 6.6.1 Write Data Buffer Function for External Data Bus ............................................. 124 Bus Arbitration ................................................................................................................. 125 6.7.1 Operation ............................................................................................................. 125 6.7.2 Bus Transfer Timing............................................................................................ 125 Bus Controller Operation in Reset .................................................................................... 126 Usage Notes ...................................................................................................................... 126 Section 7 DMA Controller (DMAC)................................................................. 127 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Features............................................................................................................................. 127 Register Descriptions........................................................................................................ 129 7.2.1 DMA Source Address Register (DSAR) ............................................................. 130 7.2.2 DMA Destination Address Register (DDAR) ..................................................... 131 7.2.3 DMA Offset Register (DOFR)............................................................................. 132 7.2.4 DMA Transfer Count Register (DTCR) .............................................................. 133 7.2.5 DMA Block Size Register (DBSR) ..................................................................... 134 7.2.6 DMA Mode Control Register (DMDR)............................................................... 135 7.2.7 DMA Address Control Register (DACR)............................................................ 142 7.2.8 DMA Module Request Select Register (DMRSR) .............................................. 148 Transfer Modes ................................................................................................................. 148 Operations......................................................................................................................... 149 7.4.1 Address Modes .................................................................................................... 149 7.4.2 Transfer Modes.................................................................................................... 152 7.4.3 Activation Sources............................................................................................... 157 7.4.4 Bus Access Modes............................................................................................... 159 7.4.5 Extended Repeat Area Function .......................................................................... 161 7.4.6 Address Update Function using Offset ................................................................ 163 7.4.7 Register during DMA Transfer............................................................................ 167 7.4.8 Priority of Channels............................................................................................. 127 7.4.9 DMA Basic Bus Cycle......................................................................................... 173 7.4.10 Bus Cycles in Dual Address Mode ...................................................................... 174 7.4.11 Bus Cycles in Single Address Mode.................................................................... 182 DMA Transfer End ........................................................................................................... 187 Relationship among DMAC and Other Bus Masters ........................................................ 189 7.6.1 CPU Priority Control Function Over DMAC ...................................................... 189 7.6.2 Bus Arbitration among DMAC and Other Bus Masters ...................................... 190 Interrupt Sources............................................................................................................... 191 Notes on Usage ................................................................................................................. 194 Section 8 I/O Ports............................................................................................. 195 8.1 Register Descriptions........................................................................................................ 200 8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K)................... 202 8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K)...................................... 202 Rev. 1.00, 03/04, page xii of xxxvi 8.2 8.3 8.4 8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K) ........................................ 203 8.1.4 Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K) ............... 203 8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K)............................ 204 8.1.6 Open-Drain Control Register (PnODR) (n = 2)................................................... 205 8.1.7 Port H Realtime Input Data Register (PHRTIDR)............................................... 205 Output Buffer Control....................................................................................................... 206 8.2.1 Port 1.................................................................................................................... 206 8.2.2 Port 2.................................................................................................................... 208 8.2.3 Port 3.................................................................................................................... 210 8.2.4 Port 6.................................................................................................................... 213 8.2.5 Port A................................................................................................................... 215 8.2.6 Port D................................................................................................................... 217 8.2.7 Port H................................................................................................................... 219 8.2.8 Port J .................................................................................................................... 220 8.2.9 Port K................................................................................................................... 222 Port Function Controller ................................................................................................... 229 8.3.1 Port Function Control Register 9 (PFCR9).......................................................... 229 8.3.2 Port Function Control Register A (PFCRA) ........................................................ 231 8.3.3 Port Function Control Register B (PFCRB)......................................................... 232 Usage Notes ...................................................................................................................... 234 8.4.1 Notes on Input Buffer Control Register (ICR) Setting ........................................ 234 8.4.2 Notes on Port Function Control Register (PFCR) Settings.................................. 234 Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................235 9.1 9.2 9.3 9.4 Features............................................................................................................................. 235 Input/Output Pins .............................................................................................................. 243 Register Descriptions ........................................................................................................ 245 9.3.1 Timer Control Register (TCR)............................................................................. 249 9.3.2 Timer Mode Register (TMDR) ............................................................................ 254 9.3.3 Timer I/O Control Register (TIOR) ..................................................................... 255 9.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 273 9.3.5 Timer Status Register (TSR)................................................................................ 275 9.3.6 Timer Counter (TCNT)........................................................................................ 278 9.3.7 Timer General Register (TGR) ............................................................................ 278 9.3.8 Timer Start Register (TSTR) ............................................................................... 279 9.3.9 Timer Synchronous Register (TSYR).................................................................. 280 Operation .......................................................................................................................... 281 9.4.1 Basic Functions.................................................................................................... 281 9.4.2 Synchronous Operation........................................................................................ 286 9.4.3 Buffer Operation .................................................................................................. 288 9.4.4 Cascaded Operation ............................................................................................. 291 9.4.5 PWM Modes ........................................................................................................ 293 9.4.6 Phase Counting Mode.......................................................................................... 298 Rev. 1.00, 03/04, page xiii of xxxvi 9.5 9.6 9.7 9.8 9.9 Interrupt Sources............................................................................................................... 304 DMAC Activation............................................................................................................. 306 A/D Converter Activation................................................................................................. 307 Operation Timing.............................................................................................................. 307 9.8.1 Input/Output Timing............................................................................................ 307 9.8.2 Interrupt Signal Timing ....................................................................................... 311 Usage Notes ...................................................................................................................... 314 9.9.1 Module Stop Mode Setting .................................................................................. 314 9.9.2 Input Clock Restrictions ...................................................................................... 314 9.9.3 Caution on Cycle Setting ..................................................................................... 315 9.9.4 Conflict between TCNT Write and Clear Operations.......................................... 315 9.9.5 Conflict between TCNT Write and Increment Operations .................................. 316 9.9.6 Conflict between TGR Write and Compare Match.............................................. 316 9.9.7 Conflict between Buffer Register Write and Compare Match............................. 317 9.9.8 Conflict between TGR Read and Input Capture .................................................. 317 9.9.9 Conflict between TGR Write and Input Capture ................................................. 318 9.9.10 Conflict between Buffer Register Write and Input Capture................................. 318 9.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................ 319 9.9.12 Conflict between TCNT Write and Overflow/Underflow ................................... 320 9.9.13 Multiplexing of I/O Pins ...................................................................................... 320 9.9.14 Interrupts and Module Stop Mode ....................................................................... 320 Section 10 Programmable Pulse Generator (PPG)............................................ 321 10.1 Features............................................................................................................................. 321 10.2 Input/Output Pins.............................................................................................................. 322 10.3 Register Descriptions........................................................................................................ 322 10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ........................................ 322 10.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 324 10.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 325 10.3.4 PPG Output Control Register (PCR) ................................................................... 328 10.3.5 PPG Output Mode Register (PMR) ..................................................................... 328 10.4 Operation .......................................................................................................................... 330 10.4.1 Output Timing ..................................................................................................... 330 10.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 331 10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............... 332 10.4.4 Non-Overlapping Pulse Output............................................................................ 333 10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output.............................. 335 10.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) .................................. 336 10.4.7 Inverted Pulse Output .......................................................................................... 338 10.4.8 Pulse Output Triggered by Input Capture ............................................................ 339 10.5 Usage Notes ...................................................................................................................... 339 10.5.1 Module Stop Mode Setting .................................................................................. 339 Rev. 1.00, 03/04, page xiv of xxxvi 10.5.2 Operation of Pulse Output Pins............................................................................ 339 Section 11 Watchdog Timer (WDT)..................................................................341 11.1 Features............................................................................................................................. 341 11.2 Register Descriptions ........................................................................................................ 342 11.2.1 Timer Counter (TCNT)........................................................................................ 342 11.2.2 Timer Control/Status Register (TCSR)................................................................ 342 11.2.3 Reset Control/Status Register (RSTCSR)............................................................ 344 11.3 Operation .......................................................................................................................... 345 11.3.1 Watchdog Timer Mode ........................................................................................ 345 11.3.2 Interval Timer Mode............................................................................................ 346 11.4 Interrupt Source ................................................................................................................ 346 11.5 Usage Notes ...................................................................................................................... 347 11.5.1 Notes on Register Access..................................................................................... 347 11.5.2 Conflict between Timer Counter (TCNT) Write and Increment.......................... 348 11.5.3 Changing Values of Bits CKS2 to CKS0............................................................. 348 11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 348 11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode....................... 349 Section 12 Serial Communication Interface (SCI) ............................................351 12.1 Features............................................................................................................................. 351 12.2 Input/Output Pins .............................................................................................................. 353 12.3 Register Descriptions ........................................................................................................ 354 12.3.1 Receive Shift Register (RSR) .............................................................................. 355 12.3.2 Receive Data Register (RDR) .............................................................................. 355 12.3.3 Transmit Data Register (TDR)............................................................................. 355 12.3.4 Transmit Shift Register (TSR) ............................................................................. 355 12.3.5 Serial Mode Register (SMR) ............................................................................... 356 12.3.6 Serial Control Register (SCR) ............................................................................. 359 12.3.7 Serial Status Register (SSR) ................................................................................ 363 12.3.8 Smart Card Mode Register (SCMR).................................................................... 370 12.3.9 Bit Rate Register (BRR) ...................................................................................... 371 12.4 Operation in Asynchronous Mode .................................................................................... 378 12.4.1 Data Transfer Format........................................................................................... 379 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ........................................................................................ 380 12.4.3 Clock.................................................................................................................... 381 12.4.4 SCI Initialization (Asynchronous Mode) ............................................................. 381 12.4.5 Serial Data Transmission (Asynchronous Mode) ................................................ 383 12.4.6 Serial Data Reception (Asynchronous Mode)...................................................... 384 12.5 Multiprocessor Communication Function......................................................................... 387 12.5.1 Multiprocessor Serial Data Transmission ............................................................ 389 12.5.2 Multiprocessor Serial Data Reception ................................................................. 390 Rev. 1.00, 03/04, page xv of xxxvi 12.6 Operation in Clocked Synchronous Mode ........................................................................ 393 12.6.1 Clock.................................................................................................................... 393 12.6.2 SCI Initialization (Clocked Synchronous Mode)................................................. 394 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) .................................... 395 12.6.4 Serial Data Reception (Clocked Synchronous Mode) ......................................... 397 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. 398 12.7 Operation in Smart Card Interface Mode.......................................................................... 400 12.7.1 Sample Connection.............................................................................................. 400 12.7.2 Data Format (Except in Block Transfer Mode) ................................................... 400 12.7.3 Block Transfer Mode ........................................................................................... 402 12.7.4 Receive Data Sampling Timing and Reception Margin ...................................... 402 12.7.5 Initialization......................................................................................................... 403 12.7.6 Data Transmission (Except in Block Transfer Mode) ......................................... 404 12.7.7 Serial Data Reception (Except in Block Transfer Mode) .................................... 407 12.7.8 Clock Output Control........................................................................................... 408 12.8 Interrupt Sources............................................................................................................... 410 12.8.1 Interrupts in Normal Serial Communication Interface Mode .............................. 410 12.8.2 Interrupts in Smart Card Interface Mode ............................................................. 411 12.9 Usage Notes ...................................................................................................................... 412 12.9.1 Module Stop Mode Setting .................................................................................. 412 12.9.2 Break Detection and Processing .......................................................................... 412 12.9.3 Mark State and Break Detection .......................................................................... 412 12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 412 12.9.5 Relation between Writing to TDR and TDRE Flag ............................................. 412 12.9.6 Restrictions on Using DMAC.............................................................................. 413 12.9.7 SCI Operations during Mode Transitions ............................................................ 413 Section 13 Controller Area Network (HCAN).................................................. 417 13.1 Features............................................................................................................................. 417 13.2 Input/Output Pins.............................................................................................................. 419 13.3 Register Descriptions........................................................................................................ 419 13.3.1 Master Control Register (MCR) .......................................................................... 420 13.3.2 General Status Register (GSR) ............................................................................ 421 13.3.3 Bit Configuration Register (BCR) ....................................................................... 423 13.3.4 Mailbox Configuration Register (MBCR) ........................................................... 425 13.3.5 Transmit Wait Register (TXPR) .......................................................................... 426 13.3.6 Transmit Wait Cancel Register (TXCR).............................................................. 427 13.3.7 Transmit Acknowledge Register (TXACK) ........................................................ 428 13.3.8 Abort Acknowledge Register (ABACK) ............................................................. 429 13.3.9 Receive Complete Register (RXPR).................................................................... 430 13.3.10 Remote Request Register (RFPR) ....................................................................... 431 Rev. 1.00, 03/04, page xvi of xxxvi 13.4 13.5 13.6 13.7 13.8 13.3.11 Interrupt Register (IRR)....................................................................................... 432 13.3.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 435 13.3.13 Interrupt Mask Register (IMR) ............................................................................ 436 13.3.14 Receive Error Counter (REC).............................................................................. 438 13.3.15 Transmit Error Counter (TEC)............................................................................. 438 13.3.16 Unread Message Status Register (UMSR)........................................................... 439 13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 440 13.3.18 Message Control (MC0 to MC15) ....................................................................... 443 13.3.19 Message Data (MD0 to MD15) ........................................................................... 446 13.3.20 HCAN Monitor Register (HCANMON).............................................................. 448 Operation .......................................................................................................................... 449 13.4.1 Hardware and Software Resets ............................................................................ 449 13.4.2 Initialization after Hardware Reset ...................................................................... 449 13.4.3 Message Transmission ......................................................................................... 455 13.4.4 Message Reception .............................................................................................. 458 13.4.5 HCAN Sleep Mode.............................................................................................. 461 13.4.6 HCAN Halt Mode................................................................................................ 462 Interrupt Sources............................................................................................................... 463 DMAC Interface ............................................................................................................... 464 CAN Bus Interface............................................................................................................ 465 Usage Notes ...................................................................................................................... 465 13.8.1 Module Stop Mode Setting .................................................................................. 465 13.8.2 Reset .................................................................................................................... 465 13.8.3 HCAN Sleep Mode.............................................................................................. 466 13.8.4 Interrupts.............................................................................................................. 466 13.8.5 Error Counters...................................................................................................... 466 13.8.6 Register Access.................................................................................................... 466 13.8.7 Register Hold in Standby Modes ......................................................................... 466 13.8.8 Use on Bit Manipulation Instructions .................................................................. 466 13.8.9 HCAN TXCR Operation...................................................................................... 467 13.8.10 HCAN Transmission Setting ............................................................................... 468 13.8.11 Canceling HCAN Reset and HCAN Sleep Mode ................................................ 468 13.8.12 Accessing Mailbox in HCAN Sleep Mode .......................................................... 468 Section 14 Synchronous Serial Communication Unit (SSU) ............................469 14.1 Features............................................................................................................................. 469 14.2 Input/Output Pins .............................................................................................................. 471 14.3 Register Descriptions ........................................................................................................ 472 14.3.1 SS Control Register H (SSCRH) ......................................................................... 474 14.3.2 SS Control Register L (SSCRL) .......................................................................... 476 14.3.3 SS Mode Register (SSMR) .................................................................................. 477 14.3.4 SS Enable Register (SSER) ................................................................................. 478 14.3.5 SS Status Register (SSSR) ................................................................................... 479 Rev. 1.00, 03/04, page xvii of xxxvi 14.3.6 SS Control Register 2 (SSCR2) ........................................................................... 481 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3).................................. 483 14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)................................... 484 14.3.9 SS Shift Register (SSTRSR)................................................................................ 484 14.4 Operation .......................................................................................................................... 485 14.4.1 Transfer Clock ..................................................................................................... 485 14.4.2 Relationship of Clock Phase, Polarity, and Data ................................................. 485 14.4.3 Relationship between Data Input/Output Pins and Shift Register ....................... 486 14.4.4 Communication Modes and Pin Functions .......................................................... 487 14.4.5 SSU Mode............................................................................................................ 489 14.4.6 SCS Pin Control and Arbitration ......................................................................... 497 14.4.7 Clock Synchronous Communication Mode ......................................................... 498 14.5 Interrupt Requests ............................................................................................................. 504 14.6 Usage Note........................................................................................................................ 505 14.6.1 Setting of Module Stop Mode.............................................................................. 505 Section 15 A/D Converter ................................................................................. 507 15.1 Features............................................................................................................................. 507 15.2 Input/Output Pins.............................................................................................................. 510 15.3 Register Descriptions........................................................................................................ 511 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) ............................................. 512 15.3.2 A/D Control/Status Register (ADCSR) ............................................................... 513 15.3.3 A/D Control Register (ADCR) ............................................................................ 515 15.4 Operation .......................................................................................................................... 516 15.4.1 Single Mode......................................................................................................... 516 15.4.2 Scan Mode ........................................................................................................... 517 15.4.3 Input Sampling and A/D Conversion Time ......................................................... 519 15.4.4 External Trigger Input Timing............................................................................. 520 15.5 Interrupt Source ................................................................................................................ 521 15.6 A/D Conversion Accuracy Definitions ............................................................................. 521 15.7 Usage Notes ...................................................................................................................... 523 15.7.1 Module Stop Mode Setting .................................................................................. 523 15.7.2 Permissible Signal Source Impedance ................................................................. 523 15.7.3 Influences on Absolute Accuracy ........................................................................ 523 15.7.4 Setting Range of Analog Power Supply and Other Pins...................................... 524 15.7.5 Notes on Board Design ........................................................................................ 524 15.7.6 Notes on Noise Countermeasures ........................................................................ 524 15.7.7 A/D Input Hold Function in Software Standby Mode ......................................... 525 Section 16 RAM ................................................................................................ 527 Section 17 Flash Memory (0.18-m F-ZTAT Version).................................... 529 17.1 Features............................................................................................................................. 529 Rev. 1.00, 03/04, page xviii of xxxvi 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 17.14 Mode Transition Diagram................................................................................................. 531 Memory MAT Configuration............................................................................................ 533 Block Structure ................................................................................................................. 534 Programming/Erasing Interface ........................................................................................ 535 Input/Output Pins .............................................................................................................. 537 Register Descriptions ........................................................................................................ 537 17.7.1 Programming/Erasing Interface Registers ........................................................... 538 17.7.2 Programming/Erasing Interface Parameters ........................................................ 545 17.7.3 RAM Emulation Register (RAMER)................................................................... 557 On-Board Programming Mode ......................................................................................... 558 17.8.1 Boot Mode ........................................................................................................... 558 17.8.2 User Program Mode............................................................................................. 562 17.8.3 User Boot Mode................................................................................................... 572 17.8.4 On-Chip Program and Storable Area for Program Data ...................................... 576 Protection .......................................................................................................................... 581 17.9.1 Hardware Protection ............................................................................................ 581 17.9.2 Software Protection.............................................................................................. 582 17.9.3 Error Protection.................................................................................................... 582 Flash Memory Emulation Using RAM ............................................................................. 584 Switching between User MAT and User Boot MAT ........................................................ 587 Programmer Mode ............................................................................................................ 588 Standard Serial Communication Interface Specifications for Boot Mode ........................ 588 Usage Notes ...................................................................................................................... 615 Section 18 Clock Pulse Generator .....................................................................617 18.1 Register Description.......................................................................................................... 618 18.1.1 System Clock Control Register (SCKCR) ........................................................... 618 18.2 Oscillator........................................................................................................................... 620 18.2.1 Connecting Crystal Resonator ............................................................................. 620 18.2.2 External Clock Input............................................................................................ 621 18.3 PLL Circuit ....................................................................................................................... 622 18.4 Frequency Divider ............................................................................................................ 622 18.5 Usage Notes ...................................................................................................................... 622 18.5.1 Notes on Clock Pulse Generator .......................................................................... 622 18.5.2 Notes on Resonator.............................................................................................. 623 18.5.3 Notes on Board Design ........................................................................................ 623 18.5.4 Notes on Input Clock Frequency ......................................................................... 624 Section 19 Power-Down Modes ........................................................................625 19.1 Features............................................................................................................................. 625 19.2 Register Descriptions ........................................................................................................ 627 19.2.1 Standby Control Register (SBYCR) .................................................................... 627 19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ............. 629 Rev. 1.00, 03/04, page xix of xxxvi 19.2.3 Module Stop Control Register C (MSTPCRC).................................................... 632 19.3 Multi-Clock Function ....................................................................................................... 633 19.4 Module Stop Mode ........................................................................................................... 633 19.5 Sleep Mode ....................................................................................................................... 634 19.5.1 Transition to Sleep Mode..................................................................................... 634 19.5.2 Clearing Sleep Mode ........................................................................................... 634 19.6 All-Module-Clock-Stop Mode.......................................................................................... 634 19.7 Software Standby Mode.................................................................................................... 635 19.7.1 Transition to Software Standby Mode ................................................................. 635 19.7.2 Clearing Software Standby Mode........................................................................ 635 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode .......... 636 19.7.4 Software Standby Mode Application Example.................................................... 638 19.8 B Clock Output Control.................................................................................................. 639 19.9 Usage Notes ...................................................................................................................... 640 19.9.1 I/O Port Status...................................................................................................... 640 19.9.2 Current Consumption during Oscillation Settling Standby Period ...................... 640 19.9.3 DMAC Module Stop............................................................................................ 640 19.9.4 On-Chip Peripheral Module Interrupts ................................................................ 640 19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC.......................................... 640 Section 20 List of Registers............................................................................... 641 20.1 Register Addresses (Address Order)................................................................................. 642 20.2 Register Bits...................................................................................................................... 662 20.3 Register States in Each Operating Mode .......................................................................... 686 Section 21 Electrical Characteristics ................................................................. 705 21.1 Absolute Maximum Ratings ............................................................................................. 705 21.2 DC Characteristics ............................................................................................................ 706 21.3 AC Characteristics ............................................................................................................ 708 21.3.1 Clock Timing ....................................................................................................... 709 21.3.2 Control Signal Timing ......................................................................................... 711 21.3.3 Timing of On-Chip Peripheral Modules .............................................................. 712 21.3.4 A/D Conversion Characteristics .......................................................................... 719 21.3.5 Flash Memory Characteristics ............................................................................. 720 Appendix A. B. C. ......................................................................................................... 721 Port States in Each Pin State............................................................................................. 721 Product Lineup.................................................................................................................. 722 Package Dimensions ......................................................................................................... 723 Index ......................................................................................................... 725 Rev. 1.00, 03/04, page xx of xxxvi Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Overview Block Diagram of H8SX/1527 ...................................................................................... 2 Block Diagram of H8SX/1525 ...................................................................................... 3 Pin Assignments of H8SX/1527.................................................................................... 4 Pin Assignments of H8SX/1525.................................................................................... 5 Section 2 CPU Figure 2.1 CPU Operating Modes ................................................................................................ 19 Figure 2.2 Exception Vector Table (Normal Mode)..................................................................... 20 Figure 2.3 Stack Structure (Normal Mode) .................................................................................. 20 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) ............................................ 22 Figure 2.5 Stack Structure (Middle and Advanced Modes).......................................................... 23 Figure 2.6 Exception Vector Table (Maximum Modes)............................................................... 24 Figure 2.7 Stack Structure (Maximum Mode) .............................................................................. 24 Figure 2.8 Memory Map............................................................................................................... 25 Figure 2.9 CPU Registers ............................................................................................................. 26 Figure 2.10 Usage of General Registers ....................................................................................... 27 Figure 2.11 Stack .......................................................................................................................... 28 Figure 2.12 General Register Data Formats ................................................................................. 31 Figure 2.13 Memory Data Formats............................................................................................... 32 Figure 2.14 Instruction Formats.................................................................................................... 50 Figure 2.15 Branch Address Specification in Memory Indirect Mode ......................................... 56 Figure 2.16 State Transitions ........................................................................................................ 60 Section 3 MCU Operating Modes Figure 3.1 Address Map (Advanced Mode) ................................................................................. 66 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Exception Handling Reset Sequence (On-Chip ROM Enabled Advanced Mode)....................................... 71 Stack Status after Exception Handling ........................................................................ 79 Operation when SP Value Is Odd................................................................................ 80 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Interrupt Controller Block Diagram of Interrupt Controller........................................................................ 82 Block Diagram of Interrupts IRQn.............................................................................. 98 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0... 107 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2... 109 Interrupt Exception Handling .................................................................................... 110 Block Diagram of DMAC and Interrupt Controller .................................................. 112 Conflict between Interrupt Generation and Disabling............................................... 116 Rev. 1.00, 03/04, page xxi of xxxvi Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Bus Controller (BSC) Block Diagram of Bus Controller.............................................................................. 119 Internal Bus Configuration........................................................................................ 121 Example of Timing when Write Data Buffer Function is Used ................................ 124 Section 7 DMA Controller (DMAC) Figure 7.1 Block Diagram of DMAC ......................................................................................... 128 Figure 7.2 Example of Signal Timing in Dual Address Mode ................................................... 149 Figure 7.3 Operations in Dual Address Mode ............................................................................ 150 Figure 7.4 Data Flow in Single Address Mode........................................................................... 151 Figure 7.5 Example of Signal Timing in Single Address Mode ................................................. 151 Figure 7.6 Operations in Single Address Mode.......................................................................... 152 Figure 7.7 Example of Signal Timing in Normal Transfer Mode............................................... 152 Figure 7.8 Operations in Normal Transfer Mode ....................................................................... 153 Figure 7.9 Operations in Repeat Transfer Mode ........................................................................ 154 Figure 7.10 Operations in Block Transfer Mode ........................................................................ 155 Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) ........................................................................................... 155 Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) .................................................................................... 156 Figure 7.13 Example of Timing in Cycle Stealing Mode ........................................................... 159 Figure 7.14 Example of Timing in Burst Mode.......................................................................... 160 Figure 7.15 Example of Extended Repeat Area Operation......................................................... 161 Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode ................... 162 Figure 7.17 Address Update Method.......................................................................................... 163 Figure 7.18 Operation of Offset Addition .................................................................................. 164 Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode.......... 165 Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode ......... 166 Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred .............. 170 Figure 7.22 Example of Timing for Channel Priority................................................................. 172 Figure 7.23 Example of Bus Timing of DMA Transfer ............................................................. 173 Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing......................... 174 Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment).............. 175 Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement).............. 175 Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access ........................... 176 Figure 7.28 Example of Transfer in Block Transfer Mode......................................................... 177 Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge ........................................................................................... 178 Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level . 179 Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level .... 180 Rev. 1.00, 03/04, page xxii of xxxvi Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1....................................................................... 181 Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) .................................... 182 Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) .................................... 183 Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge ........................................................................................... 184 Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level .............................................................................................. 185 Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1....................................................................... 186 Figure 7.38 Interrupt and Interrupt Sources................................................................................ 193 Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source ............... 193 Section 8 I/O Ports Figure 8.1 Port Block Diagram................................................................................................... 201 Section 9 16-Bit Timer Pulse Unit (TPU) Figure 9.1 Block Diagram of TPU (Unit 0)................................................................................ 241 Figure 9.2 Block Diagram of TPU (Unit 1)................................................................................ 242 Figure 9.3 Example of Counter Operation Setting Procedure .................................................... 281 Figure 9.4 Free-Running Counter Operation .............................................................................. 282 Figure 9.5 Periodic Counter Operation....................................................................................... 282 Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match................ 283 Figure 9.7 Example of 0-Output/1-Output Operation................................................................. 283 Figure 9.8 Example of Toggle Output Operation ....................................................................... 284 Figure 9.9 Example of Setting Procedure for Input Capture Operation...................................... 284 Figure 9.10 Example of Input Capture Operation....................................................................... 285 Figure 9.11 Example of Synchronous Operation Setting Procedure .......................................... 286 Figure 9.12 Example of Synchronous Operation........................................................................ 287 Figure 9.13 Compare Match Buffer Operation........................................................................... 288 Figure 9.14 Input Capture Buffer Operation............................................................................... 289 Figure 9.15 Example of Buffer Operation Setting Procedure..................................................... 289 Figure 9.16 Example of Buffer Operation (1)............................................................................. 290 Figure 9.17 Example of Buffer Operation (2)............................................................................. 291 Figure 9.18 Example of Cascaded Operation Setting Procedure ................................................ 292 Figure 9.19 Example of Cascaded Operation (1)........................................................................ 292 Figure 9.20 Example of Cascaded Operation (2)........................................................................ 293 Figure 9.21 Example of PWM Mode Setting Procedure ............................................................ 295 Figure 9.22 Example of PWM Mode Operation (1) ................................................................... 295 Figure 9.23 Example of PWM Mode Operation (2) ................................................................... 296 Figure 9.24 Example of PWM Mode Operation (3) ................................................................... 297 Figure 9.25 Example of Phase Counting Mode Setting Procedure............................................. 298 Figure 9.26 Example of Phase Counting Mode 1 Operation ...................................................... 299 Figure 9.27 Example of Phase Counting Mode 2 Operation ...................................................... 300 Rev. 1.00, 03/04, page xxiii of xxxvi Figure 9.28 Figure 9.29 Figure 9.30 Figure 9.31 Figure 9.32 Figure 9.33 Figure 9.34 Figure 9.35 Figure 9.36 Figure 9.37 Figure 9.38 Figure 9.39 Figure 9.40 Figure 9.41 Figure 9.42 Figure 9.43 Figure 9.44 Figure 9.45 Figure 9.46 Figure 9.47 Figure 9.48 Figure 9.49 Figure 9.50 Figure 9.51 Figure 9.52 Figure 9.53 Figure 9.54 Figure 9.55 Example of Phase Counting Mode 3 Operation ...................................................... 301 Example of Phase Counting Mode 4 Operation ...................................................... 302 Phase Counting Mode Application Example........................................................... 303 Count Timing in Internal Clock Operation.............................................................. 307 Count Timing in External Clock Operation ............................................................ 308 Output Compare Output Timing ............................................................................. 308 Input Capture Input Signal Timing.......................................................................... 309 Counter Clear Timing (Compare Match) ................................................................ 309 Counter Clear Timing (Input Capture) .................................................................... 310 Buffer Operation Timing (Compare Match) ........................................................... 310 Buffer Operation Timing (Input Capture) ............................................................... 310 TGI Interrupt Timing (Compare Match) ................................................................. 311 TGI Interrupt Timing (Input Capture) ..................................................................... 311 TCIV Interrupt Setting Timing................................................................................ 312 TCIU Interrupt Setting Timing................................................................................ 312 Timing for Status Flag Clearing by CPU ................................................................ 313 Timing for Status Flag Clearing by DMAC Activation (1)..................................... 313 Timing for Status Flag Clearing by DMAC Activation (2)..................................... 314 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode .................. 314 Conflict between TCNT Write and Clear Operations ............................................. 315 Conflict between TCNT Write and Increment Operations...................................... 316 Conflict between TGR Write and Compare Match ................................................. 316 Conflict between Buffer Register Write and Compare Match ................................ 317 Conflict between TGR Read and Input Capture...................................................... 317 Conflict between TGR Write and Input Capture..................................................... 318 Conflict between Buffer Register Write and Input Capture .................................... 319 Conflict between Overflow and Counter Clearing .................................................. 319 Conflict between TCNT Write and Overflow ......................................................... 320 Section 10 Programmable Pulse Generator (PPG) Figure 10.1 Block Diagram of PPG............................................................................................ 321 Figure 10.2 Schematic Diagram of PPG..................................................................................... 330 Figure 10.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 331 Figure 10.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 331 Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) .......................................... 332 Figure 10.6 Non-Overlapping Pulse Output ............................................................................... 333 Figure 10.7 Non-Overlapping Operation and NDR Write Timing ............................................. 334 Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 335 Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) ..................... 336 Figure 10.10 Inverted Pulse Output (Example) .......................................................................... 338 Figure 10.11 Pulse Output Triggered by Input Capture (Example)............................................ 339 Rev. 1.00, 03/04, page xxiv of xxxvi Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Watchdog Timer (WDT) Block Diagram of WDT .......................................................................................... 341 Operation in Watchdog Timer Mode....................................................................... 345 Operation in Interval Timer Mode........................................................................... 346 Writing to TCNT, TCSR, and RSTCSR.................................................................. 347 Conflict between TCNT Write and Increment ........................................................ 348 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI............................................................................................. 352 Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 378 Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 380 Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) ............................................................................................. 381 Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 382 Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)..................................................... 383 Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 384 Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) ........................................................................................................... 385 Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 386 Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 387 Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A).......................................... 388 Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 389 Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ........................................................................ 390 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 391 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 392 Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 393 Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 394 Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode ............. 395 Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 396 Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode................... 397 Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 398 Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 399 Figure 12.21 Pin Connection for Smart Card Interface .............................................................. 400 Figure 12.22 Data Formats in Normal Smart Card Interface Mode............................................ 401 Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 401 Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 401 Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) ............................................. 403 Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode ...................................... 405 Rev. 1.00, 03/04, page xxv of xxxvi Figure 12.27 Figure 12.28 Figure 12.29 Figure 12.30 Figure 12.31 Figure 12.32 Figure 12.33 Figure 12.34 Figure 12.35 TEND Flag Set Timing during Transmission........................................................ 405 Sample Transmission Flowchart ........................................................................... 406 Data Re-Transfer Operation in SCI Reception Mode............................................ 407 Sample Reception Flowchart................................................................................. 408 Clock Output Fixing Timing ................................................................................. 408 Clock Stop and Restart Procedure......................................................................... 409 Sample Transmission using DMAC in Clocked Synchronous Mode.................... 413 Sample Flowchart for Mode Transition during Transmission............................... 414 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) ...................................................... 414 Figure 12.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) .......................................... 415 Figure 12.37 Sample Flowchart for Mode Transition during Reception .................................... 415 Section 13 Controller Area Network (HCAN) Figure 13.1 HCAN Block Diagram ............................................................................................ 418 Figure 13.2 Message Control Register Configuration ................................................................ 443 Figure 13.3 Standard Format ...................................................................................................... 443 Figure 13.4 Extended Format ..................................................................................................... 443 Figure 13.5 Message Data Configuration ................................................................................... 446 Figure 13.6 Hardware Reset Flowchart ...................................................................................... 450 Figure 13.7 Software Reset Flowchart ....................................................................................... 451 Figure 13.8 Detailed Description of One Bit .............................................................................. 452 Figure 13.9 Transmission Flowchart .......................................................................................... 455 Figure 13.10 Transmit Message Cancellation Flowchart ........................................................... 457 Figure 13.11 Reception Flowchart ............................................................................................. 458 Figure 13.12 Unread Message Overwrite Flowchart.................................................................. 460 Figure 13.13 HCAN Sleep Mode Flowchart .............................................................................. 461 Figure 13.14 HCAN Halt Mode Flowchart ................................................................................ 462 Figure 13.15 DMAC Transfer Flowchart ................................................................................... 464 Figure 13.16 High-Speed Interface Using PCA82C250............................................................. 465 Section 14 Synchronous Serial Communication Unit (SSU) Figure 14.1 Block Diagram of SSU............................................................................................ 470 Figure 14.2 Relationship of Clock Phase, Polarity, and Data..................................................... 485 Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register ..................... 486 Figure 14.4 Example of Initial Settings in SSU Mode ............................................................... 489 Figure 14.5 Example of Transmission Operation (SSU Mode).................................................. 491 Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) ......................................... 492 Figure 14.7 Example of Reception Operation (SSU Mode) ....................................................... 494 Figure 14.8 Flowchart Example of Data Reception (SSU Mode) .............................................. 495 Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode).......... 496 Figure 14.10 Arbitration Detection Timing (Before Transfer) ................................................... 497 Figure 14.11 Arbitration Detection Timing (After Transfer End) .............................................. 497 Rev. 1.00, 03/04, page xxvi of xxxvi Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode ........... 498 Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode)......................................................... 499 Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode)......................................................... 500 Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode)... 501 Figure 14.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode)......................................................... 502 Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode)......................................................... 503 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 A/D Converter Block Diagram of A/D Converter (Unit 0/AD_0) ................................................... 508 Block Diagram of A/D Converter (Unit 1/AD_1) ................................................... 509 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 516 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) ........................................... 518 Figure 15.5 A/D Conversion Timing .......................................................................................... 519 Figure 15.6 External Trigger Input Timing ................................................................................ 520 Figure 15.7 A/D Conversion Accuracy Definitions.................................................................... 522 Figure 15.8 A/D Conversion Accuracy Definitions.................................................................... 522 Figure 15.9 Example of Analog Input Circuit ............................................................................ 523 Figure 15.10 Example of Analog Input Protection Circuit ......................................................... 525 Figure 15.11 Analog Input Pin Equivalent Circuit ..................................................................... 525 Section 17 Flash Memory (0.18-mm F-ZTAT Version) Figure 17.1 Block Diagram of Flash Memory............................................................................ 530 Figure 17.2 Mode Transition of Flash Memory.......................................................................... 531 Figure 17.3 Memory MAT Configuration .................................................................................. 533 Figure 17.4 Block Structure of User MAT ................................................................................. 534 Figure 17.5 Procedure for Creating Procedure Program............................................................. 535 Figure 17.6 System Configuration in Boot Mode....................................................................... 558 Figure 17.7 Automatic-Bit-Rate Adjustment Operation............................................................. 559 Figure 17.8 Boot Mode State Transition Diagram...................................................................... 560 Figure 17.9 Programming/Erasing Flow..................................................................................... 562 Figure 17.10 RAM Map when Programming/Erasing is Executed ............................................ 563 Figure 17.11 Programming Procedure in User Program Mode .................................................. 564 Figure 17.12 Erasing Procedure in User Program Mode ............................................................ 569 Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode ........................................................ 571 Figure 17.14 Procedure for Programming User MAT in User Boot Mode ................................ 573 Figure 17.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 574 Figure 17.16 Transitions to Error Protection State ..................................................................... 583 Figure 17.17 RAM Emulation Flow ........................................................................................... 584 Rev. 1.00, 03/04, page xxvii of xxxvi Figure 17.18 Figure 17.19 Figure 17.20 Figure 17.21 Figure 17.22 Figure 17.23 Figure 17.24 Figure 17.25 Figure 17.26 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Address Map of Overlaid RAM Area ................................................................... 585 Programming Tuned Data ..................................................................................... 586 Switching between User MAT and User Boot MAT ............................................ 587 Boot Program States.............................................................................................. 589 Bit-Rate-Adjustment Sequence ............................................................................. 590 Communication Protocol Format .......................................................................... 591 New Bit-Rate Selection Sequence......................................................................... 602 Programming Sequence......................................................................................... 605 Erasure Sequence .................................................................................................. 606 Clock Pulse Generator Block Diagram of Clock Pulse Generator ............................................................... 617 Connection of Crystal Resonator (Example)........................................................... 620 Crystal Resonator Equivalent Circuit...................................................................... 621 External Clock Input (Examples) ............................................................................ 621 Clock Modification Timing..................................................................................... 623 Note on Board Design for Oscillation Circuit ......................................................... 623 Connection Example of Bypass Capacitor .............................................................. 624 Section 19 Power-Down Modes Figure 19.1 Mode Transitions..................................................................................................... 626 Figure 19.2 Software Standby Mode Application Example ....................................................... 638 Section 21 Electrical Characteristics Figure 21.1 Output Load Circuit ................................................................................................ 708 Figure 21.2 System Bus Clock Timing....................................................................................... 709 Figure 21.3 Oscillation Settling Timing after Software Standby Mode ..................................... 710 Figure 21.4 Oscillation Settling Timing ..................................................................................... 710 Figure 21.5 External Input Clock Timing................................................................................... 710 Figure 21.6 Reset Input Timing.................................................................................................. 711 Figure 21.7 Interrupt Input Timing............................................................................................. 712 Figure 21.8 I/O Port Input/Output Timing.................................................................................. 715 Figure 21.9 Data Input Timing for Realtime Input Port ............................................................. 715 Figure 21.10 TPU Input/Output Timing ..................................................................................... 715 Figure 21.11 TPU Clock Input Timing....................................................................................... 715 Figure 21.12 PPG Output Timing............................................................................................... 716 Figure 21.13 SCK Clock Input/Output Timing .......................................................................... 716 Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode ....................................... 716 Figure 21.15 A/D Converter External Trigger Input Timing...................................................... 716 Figure 21.16 HCAN Input/Output Timing ................................................................................. 716 Figure 21.17 SSU Timing (Master, CPHS = 1) .......................................................................... 717 Figure 21.18 SSU Timing (Master, CPHS = 0) .......................................................................... 717 Figure 21.19 SSU Timing (Slave, CPHS = 1) ............................................................................ 718 Figure 21.20 SSU Timing (Slave, CPHS = 0) ............................................................................ 718 Rev. 1.00, 03/04, page xxviii of xxxvi Appendix Figure C.1 Package Dimensions (FP-100M) .............................................................................. 723 Rev. 1.00, 03/04, page xxix of xxxvi Rev. 1.00, 03/04, page xxx of xxxvi Tables Section 1 Overview Table 1.1 Pin Configuration in Each Operating Mode............................................................... 6 Table 1.2 Pin Functions............................................................................................................ 10 Section 2 CPU Table 2.1 Instruction Classification.......................................................................................... 33 Table 2.2 Combinations of Instructions and Addressing Modes (1) ........................................ 35 Table 2.2 Combinations of Instructions and Addressing Modes (2) ........................................ 38 Table 2.3 Operation Notation................................................................................................... 39 Table 2.4 Data Transfer Instructions........................................................................................ 40 Table 2.5 Block Transfer Instructions...................................................................................... 41 Table 2.6 Arithmetic Operation Instructions............................................................................ 42 Table 2.7 Logic Operation Instructions.................................................................................... 44 Table 2.8 Shift Operation Instructions ..................................................................................... 45 Table 2.9 Bit Manipulation Instructions................................................................................... 46 Table 2.10 Branch Instructions .................................................................................................. 48 Table 2.11 System Control Instructions ..................................................................................... 49 Table 2.12 Addressing Modes.................................................................................................... 51 Table 2.13 Absolute Address Access Ranges ............................................................................ 54 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions .................. 58 Table 2.15 Effective Address Calculation for Branch Instructions............................................ 59 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Settings................................................................................ 61 Table 3.2 Settings of Bits MSD3 to MSD0.............................................................................. 63 Section 4 Exception Handling Table 4.1 Exception Types and Priority................................................................................... 67 Table 4.2 Exception Handling Vector Table............................................................................ 68 Table 4.3 Calculation Method of Exception Handling Vector Table Address ......................... 69 Table 4.4 Status of CCR and EXR after Trace Exception Handling........................................ 72 Table 4.5 Bus Cycle and Address Error ................................................................................... 73 Table 4.6 States of CCR and EXR after Address Error Exception Handling........................... 75 Table 4.7 Interrupt Sources ...................................................................................................... 75 Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling ....................... 77 Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling..................... 78 Section 5 Interrupt Controller Table 5.1 Pin Configuration ..................................................................................................... 83 Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority ........................... 99 Table 5.3 Interrupt Control Modes......................................................................................... 106 Table 5.4 Interrupt Response Times....................................................................................... 111 Rev. 1.00, 03/04, page xxxi of xxxvi Table 5.5 Table 5.6 Table 5.7 Table 5.8 Number of Execution States in Interrupt Handling Routine .................................. 112 Interrupt Source Selection and Clear Control ........................................................ 113 CPU Priority Control ............................................................................................. 115 Example of Priority Control Function Setting and Control State........................... 115 Section 6 Bus Controller (BSC) Table 6.1 Synchronization Clocks and Their Corresponding Functions................................ 122 Table 6.2 Number of Access Cycles for On-Chip Memory Spaces....................................... 123 Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules ............. 123 Section 7 DMA Controller (DMAC) Table 7.1 Data Access Size, Valid Bits, and Settable Size .................................................... 134 Table 7.2 Settings and Areas of Extended Repeat Area......................................................... 147 Table 7.3 Transfer Modes ...................................................................................................... 148 Table 7.4 List of On-chip module interrupts to DMAC......................................................... 158 Table 7.5 Priority among DMAC Channels........................................................................... 172 Table 7.6 Interrupt Sources and Priority ................................................................................ 191 Section 8 I/O Ports Table 8.1 Port Functions ........................................................................................................ 195 Table 8.2 Register Configuration in Each Port ...................................................................... 200 Table 8.3 Input Pull-Up MOS State ....................................................................................... 204 Table 8.4 Available Output Signals and Settings in Each Port .............................................. 225 Section 9 16-Bit Timer Pulse Unit (TPU) Table 9.1 Unit Configuration for Each Product ..................................................................... 236 Table 9.2 TPU Functions (Unit 0).......................................................................................... 237 Table 9.3 TPU Functions (Unit 1).......................................................................................... 239 Table 9.4 Pin Configuration................................................................................................... 243 Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 250 Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 250 Table 9.7 Input Clock Edge Selection.................................................................................... 251 Table 9.8 TPSC2 to TPSC0 (Channel 0)................................................................................ 251 Table 9.9 TPSC2 to TPSC0 (Channel 1)................................................................................ 251 Table 9.10 TPSC2 to TPSC0 (Channel 2)................................................................................ 252 Table 9.11 TPSC2 to TPSC0 (Channel 3)................................................................................ 252 Table 9.12 TPSC2 to TPSC0 (Channel 4)................................................................................ 253 Table 9.13 TPSC2 to TPSC0 (Channel 5)................................................................................ 253 Table 9.14 MD3 to MD0.......................................................................................................... 255 Table 9.15 TIORH_0 ............................................................................................................... 257 Table 9.16 TIORL_0................................................................................................................ 258 Table 9.17 TIOR_1 .................................................................................................................. 259 Table 9.18 TIOR_2 .................................................................................................................. 260 Table 9.19 TIORH_3 ............................................................................................................... 261 Table 9.20 TIORL_3................................................................................................................ 262 Rev. 1.00, 03/04, page xxxii of xxxvi Table 9.21 Table 9.22 Table 9.23 Table 9.24 Table 9.25 Table 9.26 Table 9.27 Table 9.28 Table 9.29 Table 9.30 Table 9.31 Table 9.32 Table 9.33 Table 9.34 Table 9.35 Table 9.36 Table 9.37 Table 9.38 Table 9.39 TIOR_4 .................................................................................................................. 263 TIOR_5 .................................................................................................................. 264 TIORH_0 ............................................................................................................... 265 TIORL_0................................................................................................................ 266 TIOR_1 .................................................................................................................. 267 TIOR_2 .................................................................................................................. 268 TIORH_3 ............................................................................................................... 269 TIORL_3................................................................................................................ 270 TIOR_4 .................................................................................................................. 271 TIOR_5 .................................................................................................................. 272 Register Combinations in Buffer Operation........................................................... 288 Cascaded Combinations ......................................................................................... 291 PWM Output Registers and Output Pins................................................................ 294 Clock Input Pins in Phase Counting Mode............................................................. 298 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 299 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 300 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 301 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 302 TPU Interrupts........................................................................................................ 304 Section 10 Programmable Pulse Generator (PPG) Table 10.1 Pin Configuration ................................................................................................... 322 Section 11 Watchdog Timer (WDT) Table 11.1 WDT Interrupt Source............................................................................................ 346 Section 12 Serial Communication Interface (SCI) Table 12.1 Pin Configuration ................................................................................................... 353 Table 12.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 371 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)........ 372 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)........ 373 Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)........... 374 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 374 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 375 Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 376 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372)......................................................... 377 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) ................................................................... 377 Table 12.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 379 Table 12.11 SSR Status Flags and Receive Data Handling ....................................................... 386 Table 12.12 SCI Interrupt Sources............................................................................................. 410 Table 12.13 SCI Interrupt Sources............................................................................................. 411 Rev. 1.00, 03/04, page xxxiii of xxxvi Section 13 Controller Area Network (HCAN) Table 13.1 Pin Configuration................................................................................................... 419 Table 13.2 Limits for the Settable Value ................................................................................. 452 Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR...................................................... 453 Table 13.4 HCAN Interrupt Sources........................................................................................ 463 Table 13.5 Duration between Transmission Setting ................................................................ 468 Section 14 Synchronous Serial Communication Unit (SSU) Table 14.1 Pin Configuration................................................................................................... 471 Table 14.2 Communication Modes and Pin States of SSI and SSO Pins................................. 487 Table 14.3 Communication Modes and Pin States of SSCK Pin ............................................. 488 Table 14.4 Communication Modes and Pin States of SCS Pin ................................................ 488 Table 14.5 Interrupt Sources .................................................................................................... 504 Section 15 A/D Converter Table 15.1 Pin Configuration................................................................................................... 510 Table 15.2 Analog Input Channels and Corresponding ADDR Registers ............................... 512 Table 15.3 A/D Conversion Characteristics (Single Mode)..................................................... 520 Table 15.4 A/D Conversion Characteristics (Scan Mode) ....................................................... 520 Table 15.5 A/D Converter Interrupt Source............................................................................. 521 Table 15.6 Analog Pin Specifications ...................................................................................... 525 Section 17 Flash Memory (0.18-mm F-ZTAT Version) Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode........................................................................................... 532 Table 17.2 Pin Configuration................................................................................................... 537 Table 17.3 Registers/Parameters and Target Modes ................................................................ 538 Table 17.4 Parameters and Target Modes................................................................................ 545 Table 17.5 On-Board Programming Mode Setting .................................................................. 558 Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment.............................. 559 Table 17.7 Executable Memory MAT ..................................................................................... 577 Table 17.8 Usable Area for Programming in User Program Mode.......................................... 577 Table 17.9 Usable Area for Erasure in User Program Mode.................................................... 578 Table 17.10 Usable Area for Programming in User Boot Mode................................................ 579 Table 17.11 Usable Area for Erasure in User Boot Mode ......................................................... 580 Table 17.12 Hardware Protection .............................................................................................. 581 Table 17.13 Software Protection................................................................................................ 582 Table 17.14 Device Types Supported in Programmer Mode ..................................................... 588 Table 17.15 Inquiry and Selection Commands .......................................................................... 592 Table 17.16 Programming/Erasing Commands ......................................................................... 604 Table 17.17 Status Code ............................................................................................................ 614 Table 17.18 Error Code.............................................................................................................. 614 Rev. 1.00, 03/04, page xxxiv of xxxvi Section 18 Clock Pulse Generator Table 18.1 Damping Resistance Value .................................................................................... 620 Table 18.2 Crystal Resonator Characteristics .......................................................................... 621 Section 19 Power-Down Modes Table 19.1 Operating States ..................................................................................................... 626 Table 19.2 Oscillation Settling Time Settings.......................................................................... 636 Table 19.3 B Pin (PA7) State in Each Processing State......................................................... 639 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings................................................................................... 705 Table 21.2 DC Characteristics (1)............................................................................................ 706 Table 21.2 DC Characteristics (2)............................................................................................ 707 Table 21.3 Permissible Output Currents .................................................................................. 708 Table 21.4 Clock Timing ......................................................................................................... 709 Table 21.5 Control Signal Timing............................................................................................ 711 Table 21.6 Timing of On-Chip Peripheral Modules (1)........................................................... 712 Table 21.6 Timing of On-Chip Peripheral Modules (2)........................................................... 714 Table 21.7 A/D Conversion Characteristics............................................................................. 719 Table 21.8 Flash Memory Characteristics................................................................................ 720 Appendix Table A.1 Port States in Each Pin State .................................................................................. 721 Rev. 1.00, 03/04, page xxxv of xxxvi Rev. 1.00, 03/04, page xxxvi of xxxvi Section 1 Overview 1.1 Features * 32-bit high-speed H8SX CPU Upward compatible with the H8/300 CPU, H8/300H CPU, and H8S CPU Sixteen 16-bit general registers 87 basic instructions * Extensive peripheral functions DMA controller (DMAC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG)* Watch dog timer (WDT) Serial communication interface (SCI) can be used in asynchronous and clocked synchronous mode Controller area network (HCAN) Synchronous serial communication unit (SSU) 10-bit A/D converter Clock pulse generator Note: * Supported only by the H8SX/1527. * On-chip memory Product Classification Flash memory version Product Model ROM RAM H8SX/1527 R5F61527 256 kbytes 12 kbytes H8SX/1525 R5F61525 256 kbytes 12 kbytes * General I/O port 65 input/output ports 17 input ports * Supports power-down modes * Small package Package Code Body Size Pin Pitch QFP-100 FP-100M 14.0 x 14.0 mm 0.50 mm Rev. 1.00, 03/04, page 1 of 730 1.2 Block Diagram WDT Port 1 Port 2 TPU (unit 1) x 6 channels Interrupt controller RAM Port 3 SCI x 2 channels ROM BSC Port 4 Internal bus H8SX CPU Peripheral bus Port 5 HCAN Port 6 SSU x 3 channels Port A DMAC x 4 channels A/D (unit 0) x 8 channels Clock pulse generator A/D (unit 1) x 8 channels On-chip debugging function for E10A Port D Port H Port J Port K [Legend] CPU: Central processing unit DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer TPU: 16-bit timer pulse unit SCI: Serial communication interface HCAN: Controller area network SSU: Synchronous communication unit Figure 1.1 Block Diagram of H8SX/1527 Rev. 1.00, 03/04, page 2 of 730 WDT Port 1 Port 2 TPU (unit 1) x 6 channels Interrupt controller RAM Port 3 SCI x 2 channels ROM BSC Port 4 Port 5 Internal bus H8SX CPU Peripheral bus HCAN Port 6 SSU x 3 channels Port A DMAC x 4 channels A/D (unit 0) x 8 channels Clock pulse generator A/D (unit 1) x 8 channels On-chip debugging function for E10A Port D Port H Port J Port K [Legend] CPU: Central processing unit DMAC: DMA controller BSC: Bus controller WDT: Watchdog timer TPU: 16-bit timer pulse unit SCI: Serial communication interface HCAN: Controller area network SSU: Synchronous communication unit Figure 1.2 Block Diagram of H8SX/1525 Rev. 1.00, 03/04, page 3 of 730 Pin Assignments 1.3.1 Pin Assignments PA1/SSCK2 PA2/SSI2 PA3/SSO2 EMLE* Vss EXTAL XTAL Vcc NMI RES P37/PO15/TIOCA2/TIOCB2/TCLKD/TCK* P36/PO14/TIOCA2/TDI* P35/PO13/TIOCA1/TIOCB1/TCLKC/TMS* P34/PO12/TIOCA1/TRST* P33/PO11/TIOCC0/TIOCD0/TCLKB P32/PO10/TIOCC0/TCLKA P31/PO9/TIOCA0/TIOCB0 P30/PO8/TIOCA0 PA4 PA5 PA6 Vcc PA7/B Vss P23/TIOCC3/TIOCD3/IRQ11-A 1.3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 FP-100M 88 38 (top view) 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P22/TIOCC3/IRQ10-A P21/TIOCA3/IRQ9-A/SCS2 P20/TIOCA3/TIOCB3/IRQ8-A P17/ADTRG1/IRQ7 P16/SCK3/IRQ6 P15/RxD3/IRQ5 P14/TxD3/IRQ4 P13/ADTRG0/IRQ3 P12/IRQ2 VCL P11/IRQ1 Vss P10/IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PK7/TIOCA11/TIOCB11 PK6/TIOCA11 PK5/TIOCA10/TIOCB10 PK4/TIOCA10 PD4/SSO1 PD5/SSI1 PD6/SSCK1 PD7/SCS1 P60/TxD4/IRQ8-B P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12/HTxD P65/IRQ13/HRxD P66/IRQ14 PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 PD0/SSO0 PD1/SSI0 PD2/SSCK0 PD3/SCS0 Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Figure 1.3 Pin Assignments of H8SX/1527 Rev. 1.00, 03/04, page 4 of 730 PA1/SSCK2 PA2/SSI2 PA3/SSO2 EMLE* Vss EXTAL XTAL Vcc NMI RES P37/TCK* P36/TDI* P35/TMS* P34/TRST* P33 P32 P31 P30 PA4 PA5 PA6 Vcc PA7/B Vss P23/IRQ11-A 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 FP-100M 88 38 (top view) 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P22/IRQ10-A P21/IRQ9-A/SCS2 P20/IRQ8-A P17/ADTRG1/IRQ7 P16/SCK3/IRQ6 P15/RxD3/IRQ5 P14/TxD3/IRQ4 P13/ADTRG0/IRQ3 P12/IRQ2 VCL P11/IRQ1 Vss P10/IRQ0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PK7/TIOCA11/TIOCB11 PK6/TIOCA11 PK5/TIOCA10/TIOCB10 PK4/TIOCA10 PD4/SSO1 PD5/SSI1 PD6/SSCK1 PD7/SCS1 P60/TxD4/IRQ8-B P61/RxD4/IRQ9-B P62/SCK4/IRQ10-B P63/IRQ11-B/TDO* P64/IRQ12/HTxD P65/IRQ13/HRxD P66/IRQ14 PJ0/TIOCA6 PJ1/TIOCA6/TIOCB6 PJ2/TIOCC6/TCLKE PJ3/TIOCC6/TIOCD6/TCLKF PJ4/TIOCA7 PJ5/TIOCA7/TIOCB7/TCLKG PJ6/TIOCA8 PJ7/TIOCA8/TIOCB8/TCLKH Vss PK0/TIOCA9 Vcc PK1/TIOCA9/TIOCB9 PK2/TIOCC9 PK3/TIOCC9/TIOCD9 MD1 P40/AN12 P41/AN13 P42/AN14 P43/AN15 P44/AN8 P45/AN9 P46/AN10 AVcc1 P47/AN11 AVss P50/AN0 AVcc0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 MD0 PD0/SSO0 PD1/SSI0 PD2/SSCK0 PD3/SCS0 Note: * The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Figure 1.4 Pin Assignments of H8SX/1525 Rev. 1.00, 03/04, page 5 of 730 1.3.2 Table 1.1 Pin Configuration in Each Operating Mode Pin Configuration in Each Operating Mode Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 1 PD4/SSO1 2 PD5/SSI1 3 PD6/SSCK1 4 PD7/SCS1 5 P60/TxD4/IRQ8-B 6 P61/RxD4/IRQ9-B 7 P62/SCK4/IRQ10-B 8 P63/IRQ11-B/TDO*2 9 P64/IRQ12/HTxD 10 P65/IRQ13/HRxD 11 P66/IRQ14 12 PJ0/TIOCA6 13 PJ1/TIOCA6/TIOCB6 14 PJ2/TIOCC6/TCLKE 15 PJ3/TIOCC6/TIOCD6/TCLKF 16 PJ4/TIOCA7 17 PJ5/TIOCA7/TIOCB7/TCLKG 18 PJ6/TIOCA8 19 PJ7/TIOCA8/TIOCB8/TCLKH 20 Vss 21 PK0/TIOCA9 22 Vcc 23 PK1/TIOCA9/TIOCB9 24 PK2/TIOCC9 25 PK3/TIOCC9/TIOCD9 26 PK4/TIOCA10 27 PK5/TIOCA10/TIOCB10 28 PK6/TIOCA11 29 PK7/TIOCA11/TIOCB11 30 PH0 Rev. 1.00, 03/04, page 6 of 730 Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 31 PH1 32 PH2 33 PH3 34 PH4 35 PH5 36 PH6 37 PH7 38 P10/IRQ0 39 Vss 40 P11/IRQ1 41 VCL 42 P12/IRQ2 43 P13/ADTRG0/IRQ3 44 P14/TxD3/IRQ4 45 P15/RxD3/IRQ5 46 P16/SCK3/IRQ6 47 P17/ADTRG1/IRQ7 48 P20/(TIOCA3/TIOCB3)*1/IRQ8-A 49 P21/(TIOCA3)*1/IRQ9-A/SCS2 50 P22/(TIOCC3)*1/IRQ10-A 51 P23/(TIOCC3/TIOCD3)*1/IRQ11-A 52 Vss 53 PA7/B 54 Vcc 55 PA6 56 PA5 57 PA4 58 P30/(PO8/TIOCA0)*1 59 P31/(PO9/TIOCA0/TIOCB0)*1 60 P32/(PO10/TIOCC0/TCLKA)*1 Rev. 1.00, 03/04, page 7 of 730 Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 61 P33/(PO11/TIOCC0/TIOCD0/TCLKB)*1 62 P34/(PO12/TIOCA1)*1/TRST*2 63 P35/(PO13/TIOCA1/TIOCB1/TCLKC)*1/TMS*2 64 P36/(PO14/TIOCA2)*1/TDI*2 65 P37/(PO15/TIOCA2/TIOCB2/TCLKD)*1/TCK*2 66 RES 67 NMI 68 Vcc 69 XTAL 70 EXTAL 71 Vss 72 EMLE*2 73 PA3/SSO2 74 PA2/SSI2 75 PA1/SSCK2 76 MD1 77 P40/AN12 78 P41/AN13 79 P42/AN14 80 P43/AN15 81 P44/AN8 82 P45/AN9 83 P46/AN10 84 AVcc1 85 P47/AN11 86 AVss 87 P50/AN0 88 AVcc0 89 P51/AN1 90 P52/AN2 Rev. 1.00, 03/04, page 8 of 730 Pin No. Abbreviation in Mode 1, Mode 2, and Mode 3 91 P53/AN3 92 P54/AN4 93 P55/AN5 94 P56/AN6 95 P57/AN7 96 MD0 97 PD0/SSO0 98 PD1/SSI0 99 PD2/SSCK0 100 PD3/SCS0 Notes: 1. Not supported by the H8SX/1525. 2. The EMLE (emulator enable) pin enables/disables the on-chip debugging functions. When the EMLE pin is driven high, the TDO, TDI, TCK, TMS, and TRST pins are used specific for the E10A. In this case, other pin functions are disabled. Rev. 1.00, 03/04, page 9 of 730 1.3.3 Table 1.2 Pin Functions Pin Functions Pin Number Classification Power supply Clock Abbreviation H8SX/1527 H8SX/1525 I/O Description VCC 22, 54, 68 22, 54, 68 Input Power supply pins. Connect to the system power supply. VCL 41 41 Input Connect to VSS via a 0.1-uF capacitor (place it close to this pin). VSS 20, 39, 52, 71 20, 39, 52, 71 Input Ground pins. Connect to the system power supply (0 V). Pins for a crystal resonator. External clock can be input to the EXTAL pin. For a connection example, see section 18, Clock Pulse Generator. XTAL 69 69 Input EXTAL 70 70 Input B 53 53 Output Supplies the system clock to external devices. Operating MD1 mode MD0 control 76 76 Input 96 96 Pins for setting the operating mode. The signal levels of these pins must not be changed during operation. RES 66 66 Input Reset signal input pin. This LSI enters the reset state when this signal goes low. EMLE 72 72 Input Input pin for on-chip emulator enable signal. Normally the signal level should be fixed low. NMI 67 67 Input Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. IRQ14 11 11 Input Maskable interrupt request signal. IRQ13 10 10 IRQ12 9 9 System control Interrupts IRQ11-A/IRQ11-B 51/8 51/8 IRQ10-A/IRQ10-B 50/7 50/7 IRQ9-A/IRQ9-B 49/6 49/6 IRQ8-A/IRQ8-B 48/5 48/5 IRQ7 47 47 IRQ6 46 46 IRQ5 45 45 IRQ4 44 44 IRQ3 43 43 IRQ2 42 42 IRQ1 40 40 IRQ0 38 38 Rev. 1.00, 03/04, page 10 of 730 Pin Number Classification Abbreviation Debugging TRST interface TMS 16-bit timer pulse unit (TPU) (unit 0)* 16-bit timer pulse unit (TPU) (unit 1) H8SX/1527 H8SX/1525 I/O Description 62 62 Input 63 63 Input Interface pins for debugging by the on-chip emulator. TDO 8 8 Output TDI 64 64 Input TCK 65 65 Input TCLKA 60 Input Input pins for the external clocks. TCLKB 61 TCLKC 63 TCLKD 65 TIOCA0 58, 59 I/O TIOCB0 59 TIOCC0 60, 61 Signals for TGRA_0 to TGRD_0. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCD0 61 TIOCA1 62, 63 I/O TIOCB1 63 Signals for TGRA_1 and TGRB_1. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA2 64, 65 I/O TIOCB2 65 Signals for TGRA_2 and TGRB_2. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA3 48, 49 I/O TIOCB3 48 TIOCC3 50, 51 Signals for TGRA_3 toTGRD_3. These are used for the input capture inputs/output compare outputs/PWM outputs. Input Input pins for the external clocks. I/O Signals for TGRA_6 toTGRD_6. These are used for the input capture inputs/output compare outputs/PWM outputs. I/O Signals for TGRA_7 toTGRB_7. These are used for the input capture inputs/output compare outputs/PWM outputs. I/O Signals for TGRA_8 toTGRB_8. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCD3 51 TCLKE 14 14 TCLKF 15 15 TCLKG 17 17 TCLKH 19 18 TIOCA6 12, 13 12, 13 TIOCB6 13 13 TIOCC6 14, 15 14, 15 TIOCD6 15 14 TIOCA7 16, 17 16, 17 TIOCB7 17 17 TIOCA8 18, 19 18, 19 TIOCB8 19 19 Rev. 1.00, 03/04, page 11 of 730 Pin Number Classification Abbreviation H8SX/1527 H8SX/1525 I/O Description TIOCA9 21, 23 21, 23 I/O TIOCB9 23 23 Signals for TGRA_9 toTGRD_9. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCC9 24, 25 24, 25 TIOCD9 25 25 TIOCA10 26, 27 26, 27 I/O TIOCB10 27 27 Signals for TGRA_10 toTGRB_10. These are used for the input capture inputs/output compare outputs/PWM outputs. TIOCA11 28, 29 28, 29 I/O TIOCB11 29 29 Signals for TGRA_11 toTGRB_11. These are used for the input capture inputs/output compare outputs/PWM outputs. PO15 65 PO14 64 PO13 63 PO12 62 PO11 61 PO10 60 PO9 59 PO8 58 TxD3 44 44 TxD4 5 5 RxD3 45 45 RxD4 6 6 SCK3 46 46 SCK4 7 7 Controller HTxD area HRxD network (HCAN) 9 9 Output Output pin for CAN bus transmission. 10 10 Input 16-bit timer pulse unit (TPU) (unit 1) Programmable pulse generator (PPG)* Serial communication interface (SCI) Rev. 1.00, 03/04, page 12 of 730 Output Output pins for the pulse signals. Output Output pins for transmit data. Input Input pins for receive data. I/O Input/output pins for clock signals. Input pin for CAN bus reception. Pin Number Classification Synchronous serial communication unit (SSU) A/D converter Abbreviation H8SX/1527 H8SX/1525 I/O Description SSO2 73 73 I/O Input/output pins for data. SSO1 1 1 SSO0 97 97 SSI2 74 74 I/O Input/output pins for data. SSI1 2 2 SSI0 98 98 SSCK2 75 75 I/O Input/output pins for clock. SSCK1 3 3 SSCK0 99 99 SCS2 49 49 I/O Input/output pins for chip select. SCS1 4 4 SCS0 100 100 AN15 80 80 Input AN14 79 79 Input pins for the analog signals for the A/D converter. AN13 78 78 AN12 77 77 AN11 85 85 AN10 83 83 AN9 82 82 AN8 81 81 AN7 95 95 AN6 94 94 AN5 93 93 AN4 92 92 AN3 91 91 AN2 90 90 AN1 89 89 AN0 87 87 ADTRG0 43 43 Input Input pins for the external trigger signal to start A/D conversion. Input Analog power supply and reference power supply pins for the A/D converter. When the A/D converter is not in use, connect to the system power supply. Input Ground pin for the A/D and D/A converters. Connect to the system power supply (0 V). ADTRG1 47 47 AVCC0 88 88 AVCC1 84 84 AVSS 86 86 Rev. 1.00, 03/04, page 13 of 730 Pin Number Classification I/O port Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O 8-bit input/output pins. I/O 4-bit input/output pins. I/O 8-bit input/output pins. Input 8-bit input pins. Input 8-bit input pins. P17 47 47 P16 46 46 P15 45 45 P14 44 44 P13 43 43 P12 42 42 P11 40 40 P10 38 38 P23 51 51 P22 50 50 P21 49 49 P20 48 48 P37 65 65 P36 64 64 P35 63 63 P34 62 62 P33 61 61 P32 60 60 P31 59 59 P30 58 58 P47 85 85 P46 83 83 P45 82 82 P44 81 81 P43 80 80 P42 79 79 P41 78 78 P40 77 77 P57 95 95 P56 94 94 P55 93 93 P54 92 92 P53 91 91 P52 90 90 P51 89 89 P50 87 87 Rev. 1.00, 03/04, page 14 of 730 Pin Number Classification I/O port Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O 7-bit input/output pins. P66 11 11 P65 10 10 P64 9 9 P63 8 8 P62 7 7 P61 6 6 P60 5 5 PA7 53 53 Input 1-bit input pin. I/O 6-bit input/output pins. I/O 8-bit input/output pins. I/O 8-bit input/output pins. PA6 55 55 PA5 56 56 PA4 57 57 PA3 73 73 PA2 74 74 PA1 75 75 PD7 4 4 PD6 3 3 PD5 2 2 PD4 1 1 PD3 100 100 PD2 99 99 PD1 98 98 PD0 97 97 PH7 37 37 PH6 36 36 PH5 35 35 PH4 34 34 PH3 33 33 PH2 32 32 PH1 31 31 PH0 30 30 Rev. 1.00, 03/04, page 15 of 730 Pin Number Classification I/O port Note: * Abbreviation H8SX/1527 H8SX/1525 I/O Description I/O 8-bit input/output pins. I/O 8-bit input/output pins. PJ7 19 19 PJ6 18 18 PJ5 17 17 PJ4 16 16 PJ3 15 15 PJ2 14 14 PJ1 13 13 PJ0 12 12 PK7 29 29 PK6 28 28 PK5 27 27 PK4 26 26 PK3 25 25 PK2 24 24 PK1 23 23 PK0 21 21 Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 16 of 730 Section 2 CPU The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upwardcompatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system. 2.1 Features * Upward-compatible with H8/300, H8/300H, and H8S CPUs Can execute H8/300, H8/300H, and H8S/2000 object programs * Sixteen 16-bit general registers Also usable as sixteen 8-bit registers or eight 32-bit registers * 87 basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Bit field transfer instructions Powerful bit-manipulation instructions Bit condition branch instructions Multiply-and-accumulate instruction * Eleven addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)] Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)] Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @ERn+, @-ERn, or @ERn-] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)] Memory indirect [@@aa:8] Extended memory indirect [@@vec:7] Rev. 1.00, 03/04, page 17 of 730 * Two base registers Vector base register Short address base register * 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes * High-speed operation All frequently-used instructions executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 1 state 16 / 8-bit register-register divide: 10 states 16 x 16-bit register-register multiply: 1 state 32 / 16-bit register-register divide: 18 states 32 x 32-bit register-register multiply: 5 states 32 / 32-bit register-register divide: 18 states * Four CPU operating modes Normal mode Middle mode Advanced mode Maximum mode * Power-down modes Transition is made by execution of SLEEP instruction Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1520 Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1520 Group. 3. In the H8SX/1520 Group, an instruction is fetched in 32-bit mode. Rev. 1.00, 03/04, page 18 of 730 2.2 CPU Operating Modes The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. For details on mode settings, see section 3.1, Operating Mode Selection. Maximum 64 kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program Middle mode area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined CPU operating modes Maximum 16-Mbyte program Advanced mode area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Maximum mode Maximum 4 Gbytes for program and data areas combined Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Note: Normal mode is not supported in this LSI. * Address Space The maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev. 1.00, 03/04, page 19 of 730 * Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2. H'0000 H'0001 H'0002 H'0003 Reset exception vector Exception vector table Reset exception vector Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units. SP PC (16 bits) EXR*1 Reserved*1,*3 CCR CCR*3 SP *2 (SP ) PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.3 Stack Structure (Normal Mode) Rev. 1.00, 03/04, page 20 of 730 2.2.2 Middle Mode The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. * Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended. * Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. Rev. 1.00, 03/04, page 21 of 730 2.2.3 Advanced Mode The data area is extended to 4 Gbytes as compared with that in middle mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. H'00000000 Reserved H'00000001 H'00000002 Reset exception vector H'00000003 H'00000004 Reserved Exception vector table H'00000005 H'00000006 H'00000007 Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. Rev. 1.00, 03/04, page 22 of 730 * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units. EXR*1 Reserved*1,*3 CCR SP Reserved SP PC (24 bits) (a) Subroutine Branch *2 (SP ) PC (24 bits) (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return. Figure 2.5 Stack Structure (Middle and Advanced Modes) 2.2.4 Maximum Mode The program area is extended to 4 Gbytes as compared with that in advanced mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6. Rev. 1.00, 03/04, page 23 of 730 H'00000000 H'00000001 Reset exception vector H'00000002 H'00000003 H'00000004 Exception vector table H'00000005 H'00000006 H'00000007 Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The EXR contents are saved or restored regardless of whether or not EXR is in use. SP SP PC (32 bits) EXR CCR PC (32 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.7 Stack Structure (Maximum Mode) Rev. 1.00, 03/04, page 24 of 730 2.3 Instruction Fetch The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Note: In the H8SX/1520 Group, an instruction is fetched in 32-bit mode. 2.4 Address Space Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode. Normal mode Middle mode H'0000 H'000000 H'FFFF H'007FFF Program area Data area (64 kbytes) Maximum mode Advanced mode H'00000000 H'00000000 Program area (16 Mbytes) Data area (64 kbytes) Program area (16 Mbytes) H'FF8000 H'FFFFFF Program area Data area (4 Gbytes) H'00FFFFFF Data area (4 Gbytes) H'FFFFFFFF H'FFFFFFFF Figure 2.8 Memory Map Rev. 1.00, 03/04, page 25 of 730 2.5 Registers The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC). General Registers and Extended Registers 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers 31 0 PC 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C EXR T -- -- -- -- I2 I1 I0 7 6 5 4 3 2 1 0 31 12 0 (Reserved) VBR 31 8 0 (Reserved) SBR 41 63 Sign extension MAC 32 MACH MACL 31 0 [Legend] SP: PC: CCR: I: UI: H: U: N: Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag User bit Negative flag Z: V: C: EXR: T: I2 to I0: VBR: SBR: MAC: Zero flag Overflow flag Carry flag Extended control register Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register Figure 2.9 CPU Registers Rev. 1.00, 03/04, page 26 of 730 2.5.1 General Registers The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently. * Address registers * 32-bit registers * 32-bit index registers General registers ER (ER0 to ER7) * 16-bit registers General registers E (E0 to E7) * 8-bit registers General registers RH (R0H to R7H) * 16-bit registers * 16-bit index registers General registers R (R0 to R7) * 8-bit registers * 8-bit index registers General registers RL (R0L to R7L) Figure 2.10 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack. Rev. 1.00, 03/04, page 27 of 730 Free area SP (ER7) Stack area Figure 2.11 Stack 2.5.2 Program Counter (PC) PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0. 2.5.3 Condition-Code Register (CCR) CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions. Bit Bit Name Initial Value R/W 7 I 1 R/W Description Interrupt Mask Bit Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. Rev. 1.00, 03/04, page 28 of 730 Bit Bit Name Initial Value 5 H Undefined R/W R/W Description Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit (regarded as sign bit) of data. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types: * Carry from the result of addition * Borrow from the result of subtraction * Carry from the result of shift or rotation The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.5.4 Extended Control Register (EXR) EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see the hardware manual for the corresponding product. Rev. 1.00, 03/04, page 29 of 730 Bit Bit Name Initial Value R/W Description 7 T 0 R/W Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 All 1 R/W Reserved These bits are always read as 1. 2 I2 1 R/W Interrupt Mask Bits 1 I1 1 R/W 0 I0 1 R/W These bits designate the interrupt mask level (0 to 7). 2.5.5 Vector Base Register (VBR) VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions. 2.5.6 Short Address Base Register (SBR) SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions. 2.5.7 Multiply-Accumulate Register (MAC) MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 2.5.8 Initial Values of CPU Registers Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset. Rev. 1.00, 03/04, page 30 of 730 2.6 Data Formats The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.6.1 General Register Data Formats Figure 2.12 shows the data formats in general registers. 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 7 0 7 6 5 4 3 2 1 0 Don't care Don't care 7 0 7 6 5 4 3 2 1 0 43 7 Upper 4-bit BCD data 0 Lower RnL Don't care 7 Upper Don't care Byte data RnH Byte data RnL 7 0 Don't care MSB Word data 43 0 Lower LSB 7 Rn 0 Don't care Word data MSB En 15 Longword data ERn LSB 0 MSB LSB 31 MSB 0 MSB 15 LSB 16 15 En [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH 0 Rn LSB RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.12 General Register Data Formats Rev. 1.00, 03/04, page 31 of 730 2.6.2 Memory Data Formats Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size. Data Type Data Format Address 7 1-bit data Address L Byte data Address L MSB Word data 7 0 6 5 4 3 2 1 0 LSB Address 2M MSB Address 2M + 1 Longword data LSB Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.13 Memory Data Formats Rev. 1.00, 03/04, page 32 of 730 LSB 2.7 Instruction Set The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 6 MOVFPE* , MOVTPE* POP, PUSH* Block transfer Arithmetic operations 6 Size Types B/W/L 6 B 1 W/L LDM, STM L MOVA B/W*2 EEPMOV B MOVMD B/W/L MOVSD B ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC B/W/L DAA, DAS B ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS B/W MULU, DIVU, MULS, DIVS W/L MULU/U, MULS/U L EXTU, EXTS W/L TAS B MAC LDMAC, STMAC CLRMAC 3 27 Logic operations AND, OR, XOR, NOT B/W/L 4 Shift SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST B 20 BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ B BFLD, BFST B Rev. 1.00, 03/04, page 33 of 730 Function Branch Instructions BRA/BS, BRA/BC, BSR/BS, BSR/BC 3 B* Bcc* , JMP, BSR, JSR, RTS RTS/L L*5 BRA/S TRAPA, RTE, SLEEP, NOP 5 System control Size Types 9 10 5 RTE/L L* LDC, STC, ANDC, ORC, XORC B/W/L Total 87 [Legend] B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Not available in this LSI. Rev. 1.00, 03/04, page 34 of 730 2.7.1 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1) Addressing Mode Classification Data transfer Instruction Size #xx Rn @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) MOV B/W/L S SD SD SD SD SD B S/D B MOVFPE, 12 MOVTPE* S/D POP, PUSH W/L S/D S/D* LDM, STM L S/D S/D* MOVA* B/W S EEPMOV B SD* MOVMD B/W/L SD* MOVSD B SD* 4 Block transfer SD @-ERn/ @ERn+/ @aa:16/ @ERn-/ @+ERn @aa:8 @aa:32 Arithmetic ADD, CMP operations B 2 2 S S S S S 3 3 D D D D D D D B S D D D D D D B D S S S W/L S B S SD S S S S SD SD SD SD SD SD SD SD SD SD D D D D D B S D D D D D D B D S S S S S S SD SD SD SD SD SD SD SD SD SD B W/L S SD ADDX, SUBX B/W/L S SD B/W/L S B/W/L S INC, DEC 1 S/D* 3 B SUB S/D B/W/L D SD 5 SD* D ADDS, SUBS L D DAA, DAS B D MULXU, DIVXU B/W S:4 SD MULU, DIVU W/L S:4 SD Rev. 1.00, 03/04, page 35 of 730 Addressing Mode Classification Instruction Arithmetic MULXS, operations DIVXS Size #xx Rn B/W S:4 SD S:4 D D MULS, DIVS W/L B W/L D D D D D D EXTU, EXTS W/L D D D D D D TAS B MAC CLRMAC LDMAC STMAC SD D SHLL, SHLR D D D O S D S D W/L NOT D D B S D D D D D S S S S S SD SD SD SD SD SD SD SD SD B D D D D D W/L D D D D D B D D D D D 6 D D D D D 7 D B/W/L* B/W/L* SHAL, SHAR B ROTL, ROTR W/L ROTXL, ROTXR Bit manipulation @-ERn/ @ERn+/ @ERn-/ @aa:16/ @+ERn @aa:8 @aa:32 NEG Logic AND, OR, XOR B operations B Shift @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) D S SD SD D D D D D D D D D D D D D D D D BSET, BCLR, B BNOT, BTST, BSET/cc, BCLR/cc D D D D BAND, BIAND, B BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ D D D D Rev. 1.00, 03/04, page 36 of 730 D D D Addressing Mode Classification Bit manipulation Branch System control Instruction Size #xx Rn @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) @-ERn/ @ERn+/ @ERn-/ @aa:16/ @+ERn @aa:8 @aa:32 BFLD B D S S S BFST B S D D D BRA/BS, 8 BRA/BC* B S S S BSR/BS, 8 BSR/BC* B S S S LDC (CCR, EXR) B/W* LDC (VBR, SBR) L STC (CCR, EXR) B/W* D STC (VBR, SBR) L D ANDC, ORC, XORC B SLEEP O NOP O 9 S S 10 S 11 D S S S* D D D* S 9 S [Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a source or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn+ as a source operand and @-ERn as a destination operand 3. Specified by ER5 as a source address and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn- is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or register direct, otherwise, word 10. Only @ERn+ is available 11. Only @-ERn is available 12. Not available in this LSI. Rev. 1.00, 03/04, page 37 of 730 Table 2.2 Combinations of Instructions and Addressing Modes (2) Addressing Mode Classification Branch System control @ERn @(RnL. B/Rn.W/ ERn.L, @(d,PC) PC) @aa:24 @ aa:32 @@ aa:8 @@vec:7 Instruction Size BRA/BS, BRA/BC O BSR/BS, BSR/BC O Bcc O BRA O BRA/S O* JMP BSR JSR O O O O O O O O O O O O RTS, RTS/L O O RTE, RTE/L O TRAPA [Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available. Rev. 1.00, 03/04, page 38 of 730 2.7.2 Table of Instructions Classified by Function Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation Operation Notation Description Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register VBR Vector base register SBR Short address base register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition - Subtraction x Multiplication / Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 1.00, 03/04, page 39 of 730 Table 2.4 Data Transfer Instructions Instruction Size Function MOV B/W/L #IMM (EAd), (EAs) (EAd) Transfers data between immediate data, general registers, and memory. MOVFPE* B (EAs) Rd MOVTPE* B Rs (EAs) POP W/L @SP+ Rn Restores the data from the stack to a general register. PUSH W/L Rn @-SP Saves general register contents on the stack. LDM L @SP+ Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified. STM L Rn (register list) @-SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified. MOVA B/W EA Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register. Note: * Not available in this LSI. Rev. 1.00, 03/04, page 40 of 730 Table 2.5 Block Transfer Instructions Instruction Size Function EEPMOV.B EEPMOV.W B Transfers a data block. MOVMD.B B Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. MOVMD.W W Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4. MOVMD.L L Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4. MOVSD.B B Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address. Rev. 1.00, 03/04, page 41 of 730 Table 2.6 Arithmetic Operation Instructions Instruction Size Function ADD B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) SUB ADDX Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. B/W/L SUBX INC Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with postdecrement or register indirect. B/W/L DEC ADDS L Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. B DAS MULXU Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) SUBS DAA (EAd) #IMM C (EAd), (EAd) (EAs) C (EAd) Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. MULU W/L Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. MULU/U L Rd x Rs Rd Performs unsigned multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. MULS W/L Rd x Rs Rd Performs signed multiplication on data in two general registers: either 16 bits x 16 bits 16 bits, or 32 bits x 32 bits 32 bits. MULS/U L Rd x Rs Rd Performs signed multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rev. 1.00, 03/04, page 42 of 730 Instruction Size Function DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVU W/L Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVS W/L Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. CMP B/W/L (EAd) - #IMM, (EAd) - (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. NEG B/W/L 0 - (EAd) (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. EXTU W/L (EAd) (zero extension) (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. EXTS W/L (EAd) (sign extension) (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. TAS B @ERd - 0, 1 (<bit 7> of @EAd) Tests memory contents, and sets the most significant bit (bit 7) to 1. MAC (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to MAC. CLRMAC 0 MAC Clears MAC to zero. Rev. 1.00, 03/04, page 43 of 730 Instruction Size Function LDMAC Rs MAC Loads data from a general register to MAC. STMAC MAC Rd Stores data from MAC to a general register. Table 2.7 Logic Operation Instructions Instruction Size Function AND B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory. OR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory. XOR B/W/L (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory. NOT B/W/L (EAd) (EAd) Takes the one's complement of the contents of a general register or a memory location. Rev. 1.00, 03/04, page 44 of 730 Table 2.8 Shift Operation Instructions Instruction Size Function SHLL B/W/L (EAd) (shift) (EAd) SHLR Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register. SHAL B/W/L SHAR (EAd) (shift) (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible. ROTL B/W/L ROTR (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible. ROTXL ROTXR B/W/L (EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible. Rev. 1.00, 03/04, page 45 of 730 Table 2.9 Bit Manipulation Instructions Instruction Size Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BSET/cc B if cc, 1 (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction sets a specified bit in a memory location to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in the contents of a general register or a memory location to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR/cc B if cc, 0 (<bit-No.> of <EAd>) If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. BNOT B (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B (<bit-No.> of <EAd>) Z Tests a specified bit in the contents of a general register or a memory location and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIAND B C [ (<bit-No.> of <EAd>)] C ANDs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. Rev. 1.00, 03/04, page 46 of 730 Instruction Size Function BIOR B C [~ (<bit-No.> of <EAd>)] C ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BXOR B C (<bit-No.> of <EAd>) C Exclusive-ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BIXOR B C [~ (<bit-No.> of <EAd>)] C Exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BILD B ~ (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data. BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. BSTZ B Z (<bit-No.> of <EAd>) Transfers the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BIST B C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data. Rev. 1.00, 03/04, page 47 of 730 Instruction Size Function BISTZ B Z (<bit-No.> of <EAd>) Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data. BFLD B (EAs) (bit field) Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register. BFST B Rs (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents. Table 2.10 Branch Instructions Instruction Size Function BRA/BS B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. B Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Bcc Branches to a specified address if the specified condition is satisfied. BRA/S Branches unconditionally to a specified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. JMP Branches unconditionally to a specified address. BSR Branches to a subroutine at a specified address. JSR Branches to a subroutine at a specified address. RTS Returns from a subroutine. RTS/L Returns from a subroutine, restoring data from the stack to multiple general registers. BRA/BC BSR/BS BSR/BC Rev. 1.00, 03/04, page 48 of 730 Table 2.11 System Control Instructions Instruction Size Function TRAPA Starts trap-instruction exception handling. RTE Returns from an exception-handling routine. RTE/L Returns from an exception-handling routine, restoring data from the stack to multiple general registers. SLEEP Causes a transition to a power-down state. LDC B/W #IMM CCR, (EAs) CCR, #IMM EXR, (EAs) EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L Rs VBR, Rs SBR Transfers the general register contents to VBR or SBR. STC B/W CCR (EAd), EXR (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L VBR Rd, SBR Rd Transfers the contents of VBR or SBR to a general register. ANDC B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. ORC B CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. XORC B CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. NOP PC + 2 PC Only increments the program counter. Rev. 1.00, 03/04, page 49 of 730 2.7.3 Basic Instruction Formats The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc Figure 2.14 Instruction Formats * Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branch condition of Bcc instructions. Rev. 1.00, 03/04, page 50 of 730 2.8 Addressing Modes and Effective Address Calculation The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) 4 Index register indirect with displacement @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L) 5 Register indirect with post-increment @ERn+ Register indirect with pre-decrement @-ERn Register indirect with pre-increment @+ERn Register indirect with post-decrement @ERn- 6 Absolute address @aa:8/@aa:16/@aa:24/@aa:32 7 Immediate #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 8 Program-counter relative @(d:8,PC)/@(d:16,PC) 9 Program-counter relative with index register @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC) 10 Memory indirect @@aa:8 11 Extended memory indirect @@vec:7 @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L) Rev. 1.00, 03/04, page 51 of 730 2.8.1 Register DirectRn The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.8.2 Register Indirect@ERn The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.8.3 Register Indirect with Displacement ERn) @(d:2, ERn), @(d:16, ERn), or @(d:32, The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 Index Register Indirect with Displacement@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively. Rev. 1.00, 03/04, page 52 of 730 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement@ERn+, @-ERn, @+ERn, or @ERn- * Register indirect with post-increment@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-decrement@-ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-increment@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with post-decrement@ERn- The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. If the contents of a general register which is also used as an address register is written to memory using this addressing mode, data to be written is the contents of the address register after calculating an effective address. Rev. 1.00, 03/04, page 53 of 730 2.8.6 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges Absolute Address Data area Normal Mode Middle Mode Advanced Mode Maximum Mode 8 bits (@aa:8) A consecutive 256-byte area (the upper address is set in SBR) 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF 32 bits (@aa:32) H'FF8000 to H'FFFFFF H'00000000 to H'FFFFFFFF Program area 24 bits (@aa:24) H'000000 to H'FFFFFF H'00000000 to H'00FFFFFF 32 bits (@aa:32) Rev. 1.00, 03/04, page 54 of 730 H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF 2.8.7 Immediate#xx The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. 2.8.8 Program-Counter Relative@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC) This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00, 03/04, page 55 of 730 2.8.10 Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.15 Branch Address Specification in Memory Indirect Mode Rev. 1.00, 03/04, page 56 of 730 2.8.11 Extended Memory Indirect@@vec:7 This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). 2.8.12 Effective Address Calculation Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows: * The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. * The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions. Rev. 1.00, 03/04, page 57 of 730 Table 2.14 Effective Address Calculation for Transfer and Operation Instructions No. Addressing Mode and Instruction Format 1 Immediate 2 Register direct op Effective Address (EA) IMM op 3 Effective Address Calculation rm rn Register indirect 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 0 31 0 0 31 0 0 31 0 General register contents op 4 r Register indirect with 16-bit displacement op r disp 31 31 Register indirect with 32-bit displacement 0 General register contents 15 disp Sign extension 0 31 + 0 General register contents op + r disp 5 Index register indirect with 16-bit displacement op r disp Index register indirect with 32-bit displacement r op disp 6 Register indirect with post-increment or post-decrement disp 31 0 Zero extension Contents of general register (RL, R, or ER) 31 15 Sign extension 1, 2, or 4x 0 + disp 31 0 Zero extension Contents of general register (RL, R, or ER) 31 disp 1, 2, or 4x 0 31 + 0 General register contents op r Register indirect with pre-increment or pre-decrement 1, 2, or 4 0 31 General register contents op r 1, 2, or 4 7 8-bit absolute address 31 op aa 7 aa One extension 16-bit absolute address op 31 aa 15 aa Sign extension 32-bit absolute address op 31 aa Rev. 1.00, 03/04, page 58 of 730 aa Table 2.15 Effective Address Calculation for Branch Instructions No. 1 Addressing Mode and Instruction Format Register indirect Effective Address Calculation Effective Address (EA) 31 0 31 0 31 0 31 0 31 0 0 31 0 0 31 0 31 0 31 0 General register contents op 2 r Program-counter relative with 8-bit displacement 31 0 PC contents 31 op 7 Sign extension disp 0 + disp Program-counter relative with 16-bit displacement 31 31 op disp 3 Program-counter relative with index register op 4 r 24-bit absolute address 0 PC contents 15 Sign extension 0 disp 31 0 Zero extension Contents of general register (RL, R, or ER) x 2 + 0 31 PC contents Zero 31extension23 op + aa aa 32-bit absolute address op 31 aa aa 5 Memory indirect 31 op aa 7 0 aa Zero extension 0 31 Memory contents 6 Extended memory indirect 31 op vec Zero extension 7 1 0 vec 2 or 4 x 31 0 31 0 Memory contents 2.8.13 MOVA Instruction The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Programming Manual. Rev. 1.00, 03/04, page 59 of 730 2.9 Processing States The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. * Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 4, Exception Handling. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state In this state, the bus has been released in response to a bus request from the DMA controller (DMAC). While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters software standby mode. For details, refer to section 19, Power-Down Modes. Reset state* RES = high RES = low Exception-handling state Request for exception handling Interrupt Bus request request End of exception handling Program execution state Note: * Bus-released state Bus request End of bus request End of bus request Program stop state SLEEP instruction A transition to the reset state occurs whenever the RES signal goes low. A transition can also be made to the reset state when the watchdog timer overflows. Figure 2.16 State Transitions Rev. 1.00, 03/04, page 60 of 730 Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has three operating modes (modes 1 to 3). The operating mode is selected by the setting of mode pins (MD1 and MD0). Table 3.1 lists MCU operating mode settings. In this LSI, advanced mode for the CPU operating mode and 16-Mbyte address space are available. LSI initiation mode can be selected from boot mode and user boot mode for programming/erasing the flash memory and single chip initiation mode. Table 3.1 MCU Operating Mode Settings MD0 CPU Operating Mode Address Space Description On-Chip ROM 0 1 Advanced 16 Mbytes User boot mode Enabled 2 1 0 Boot mode Enabled 3 1 1 Single chip initiation mode Enabled MCU Operating Mode MD1 1 In mode 1 and mode 2, which are user boot mode and boot mode, the flash memory can be programmed and erased. For details on user boot mode and boot mode, see section 17, Flash Memory (0.18-m F-ZTAT Version). In mode 3, this LSI operates in single chip mode. Rev. 1.00, 03/04, page 61 of 730 3.2 Register Descriptions The following registers are related to the operating mode setting. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR indicates the current operating mode. When MDCR is read, the states of signals input on pins MD1 and MD0 are latched. The latch is released by a reset. Bit Bit Name 15 14 13 12 11 10 9 8 - - - - MDS3 MDS2 MDS1 MDS0 Initial Value 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit Name - - - - - - - - Initial Value 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R/W R R R R R R R R Note: * Determined by pins MD1 and MD0. Bit Bit Name Initial Value R/W Descriptions 15 0 R Reserved 14 1 R These are read-only bits and cannot be modified. 13 0 R 12 1 R 11 MDS3 Undefined* R Mode Select 3 to 0 10 MDS2 Undefined* R 9 MDS1 Undefined* R These bits indicate the operating mode selected by the mode pins (MD1 and MD0) (see table 3.2). 8 MDS0 Undefined* R Rev. 1.00, 03/04, page 62 of 730 Bit Bit Name Initial Value R/W Descriptions 7 0 R Reserved 6 1 R These are read-only bits and cannot be modified. 5 0 R 4 1 R 3 Undefined* R 2 Undefined* R 1 Undefined* R 0 Undefined* R Note: Determined by pins MD1 and MD0. * Table 3.2 Settings of Bits MSD3 to MSD0 MDCR MCU Operating Mode MD1 MD0 MDS3 MDS2 MDS1 MDS0 1 0 1 1 1 0 1 2 1 0 1 1 0 0 3 1 1 0 1 0 0 3.2.2 System Control Register (SYSCR) SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, and enables/disables the on-chip RAM and the flash memory control registers. Bit Bit Name 15 14 13 12 11 10 9 8 - - MACS - - - - RAME Initial Value 1 1 0 1 0 1 0 1 R/W R R R/W R R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 FLSHE - - - - - - - 0 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15, 14 All 1 R Descriptions Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 63 of 730 Bit Bit Name Initial Value R/W Descriptions 13 MACS 0 R/W MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation 12 1 R Reserved 11 0 R/W Reserved This is a read-only bit and cannot be modified. This bit is always read as 0. The write value should always be 0. 10 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 9 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 8 RAME 1 R/W RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled 7 FLSHE 0 R/W Flash Memory Control Register Enable Controls accesses to the flash memory control registers. Setting this bit to 1 enables to read from and write to the flash memory control registers. Clearing this bit to 0 disables the flash memory control registers. At this time, the contents of the flash memory control registers are retained. The write value should be 0 when the LSI is not the flash memory version. 0: Disables the flash memory control registers 1: Enables the flash memory control registers 6 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1, 0 All 1 R/W Reserved This bit is always read as 1. The write value should always be 1. Rev. 1.00, 03/04, page 64 of 730 3.3 Operating Mode Descriptions 3.3.1 Mode 1 Mode 1 is the user boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory. 3.3.2 Mode 2 Mode 2 is the boot mode for the flash memory. The operations are the same as that in mode 3 other than programming/erasing the flash memory. 3.3.3 Mode 3 Mode 3 is advanced mode in which the address space is 16 Mbytes, and single-chip mode with the on-chip ROM enabled. Rev. 1.00, 03/04, page 65 of 730 3.4 Address Map 3.4.1 Address Map (Advanced Mode) Figure 3.1 shows the address map. Mode 1 to mode 3 Single chip initiation mode (advanced mode) H'000000 On-chip ROM (256 kbytes) H'03FFFF Reserved H'FF9000 On-chip RAM (12 kbytes) H'FFC000 Reserved H'FFEA00 On-chip I/O register H'FFFF00 Reserved H'FFFF20 On-chip I/O register H'FFFFFF Figure 3.1 Address Map (Advanced Mode) Rev. 1.00, 03/04, page 66 of 730 Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, and illegal instructions (general illegal instruction and slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 5, Interrupt Controller. Table 4.1 Exception Types and Priority Priority Exception Type Exception Handling Start Timing High Reset Exception handling starts at the timing of level change from low to high on the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Illegal instruction Exception handling starts when an undefined code is executed. Trace*1 Exception handling starts after execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. Address error After an address error occurs, the exception handling starts on completion of the current instruction execution. Interrupt Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has occurred.*2 Trap instruction*3 Exception handling starts by execution of a trap instruction (TRAPA). Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. Rev. 1.00, 03/04, page 67 of 730 4.2 Exception Sources and Exception Handling Vector Table Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 4.2 shows the correspondence between the exception sources and vector table address offsets. Table 4.3 shows the calculation method of exception handling vector table addresses. Since the usable modes differ depending on the product, for details on the available modes, see section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Table Address Offset*1 Exception Source Vector Number Normal Mode*2 Advanced, Middle, Maximum Modes Reset 0 H'0000 to H'0001 H'0000 to H'0003 Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007 2 H'0004 to H'0005 H'0008 to H'000B 3 H'0006 to H'0007 H'000C to H'000F Illegal instruction 4 H'0008 to H'0009 H'0010 to H'0013 Trace 5 H'000A to H'000B H'0014 to H'0017 Reserved for system use 6 H'000C to H'000D H'0018 to H'001B Interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F (#0) 8 H'0010 to H'0011 H'0020 to H'0023 (#1) 9 H'0012 to H'0013 H'0024 to H'0027 (#2) 10 H'0014 to H'0015 H'0028 to H'002B (#3) 11 H'0016 to H'0017 H'002C to H'002F 12 H'0018 to H'0019 H'0030 to H'0033 13 H'001A to H'001B H'0034 to H'0037 14 63 H'001C to H'001D H'007E to H'007F H'0038 to H'003B H'00FC to H'00FF Trap instruction CPU address error DMA address error* 3 Reserved for system use Rev. 1.00, 03/04, page 68 of 730 Vector Table Address Offset*1 Exception Source External interrupt IRQ0 Advanced, Middle, Maximum Modes 64 H'0080 to H'0081 H'0100 to H'0103 IRQ1 65 H'0082 to H'0083 H'0104 to H'0107 66 H'0084 to H'0085 H'0108 to H'010B IRQ3 67 H'0086 to H'0087 H'010C to H'010F IRQ4 68 H'0088 to H'0089 H'0110 to H'0113 IRQ5 69 H'008A to H'008B H'0114 to H'0117 IRQ6 70 H'008C to H'008D H'0118 to H'011B IRQ7 71 H'008E to H'008F H'011C to H'011F IRQ8 72 H'0090 to H'0091 H'0120 to H'0123 IRQ9 73 H'0092 to H'0093 H'0124 to H'0127 IRQ10 74 H'0094 to H'0095 H'0128 to H'012B IRQ11 75 H'0096 to H'0097 H'012C to H'012F IRQ12 76 H'0098 to H'0099 H'0130 to H'0133 IRQ13 77 H'009A to H'009B H'0134 to H'0137 IRQ14 78 H'009C to H'009D H'0138 to H'013B 79 H'009E to H'009F H'013C to H'013F 80 H'00A0 to H'00A1 H'0140 to H'0143 81 255 H'00A2 to H'00A3 H'01FE to H'01FF H'0144 to H'0147 H'03FC to H'03FF Internal interrupt*4 Table 4.3 Normal Mode*2 IRQ2 Reserved for system use Notes: 1. 2. 3. 4. Vector Number Lower 16 bits of the address. Not available in this LSI. A DMA address error is generated within the DMAC. For details on the interrupt vector table, see section 5.5, Interrupt Exception Handling Vector Table. Calculation Method of Exception Handling Vector Table Address Exception Source Calculation Method of Vector Table Address Reset, CPU address error Vector table address = (vector table address offset) Other than above Vector table address = VBR + (vector table address offset) [Legend] VBR: Vector base register Vector table address offset: See table 4.2. Rev. 1.00, 03/04, page 69 of 730 4.3 Reset A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by overflow of the watchdog timer. For details, see section 11, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figure 4.1 shows an example of the reset sequence. 4.3.2 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). Rev. 1.00, 03/04, page 70 of 730 4.3.3 On-Chip Peripheral Functions after Reset Release After the reset state is released, MSTPCRA, MSTPCRB, and MSTPCRC are initialized to H'0FFF, H'FFFF, and H'FF00 respectively, and all modules except the DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read from or written to. Register reading and writing is enabled when module stop mode is canceled. Vector fetch Internal operation First instruction prefetch I RES Internal address bus (3) (1) Internal read signal Internal write signal Internal data bus (1) (2) (3) (4) High (2) (4) Reset exception handling vector address (when reset, (1) = H'000000) Start address (contents of reset exception handling vector address) Start address ((3) = (2)) First instruction in the exception handling routine Figure 4.1 Reset Sequence (On-Chip ROM Enabled Advanced Mode) Rev. 1.00, 03/04, page 71 of 730 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared to 0. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 4.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 4.4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode I 0 Trace exception handling cannot be used. 2 1 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev. 1.00, 03/04, page 72 of 730 UI EXR I2 to I0 T 0 4.5 Address Error 4.5.1 Address Error Source Instruction fetch, stack operation, data read/write, and single-address transfer shown in table 4.5 may cause an address error. Table 4.5 Bus Cycle and Address Error Bus Cycle Type Bus Master Instruction fetch CPU Stack operation CPU Description Address Error Fetches instructions from even addresses No (normal) Fetches instructions from odd addresses Occurs Fetches instructions from areas other than on-chip peripheral module space*1 No (normal) Fetches instructions from on-chip peripheral 1 module space* Occurs Fetches instructions from external memory space in single-chip mode Occurs Fetches instructions from access reserved area.*2 Occurs Accesses stack when the stack pointer value No (normal) is even address Accesses stack when the stack pointer value Occurs is odd Data read/write CPU Data read/write DMAC Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory space in singlechip mode Occurs Accesses to reserved area*2 Occurs Accesses word data from even addresses No (normal) Accesses word data from odd addresses No (normal) Accesses external memory space in singlechip mode Occurs Accesses to reserved area*2 Occurs Rev. 1.00, 03/04, page 73 of 730 Bus Cycle Type Bus Master Description Address Error Single address transfer DMAC In single address transfer, the device to be accessed with an address is in the external memory space No (normal) In single address transfer, the device to be accessed with an address is not in the external memory space Occurs Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC). 2. For the access reserved area, refer to figure 3.1 in section 3.4, Address Map. An address error will not occur when the reserved area from H'FF8000 to H'FF8FFF is accessed. 4.5.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DMAC. * ERRF bit in DMDR_0 of the DMAC is set to 1 * DTE bits for all the channels of the DMAC are cleared to 0 and the DMAC is forced to halt Table 4.6 shows the states of CCR and EXR after the address error exception handling. Rev. 1.00, 03/04, page 74 of 730 Table 4.6 States of CCR and EXR after Address Error Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1 2 1 0 7 [Legend] 1: Set to 1. 0: Cleared to 0. : Retains the previous value. 4.6 Interrupts 4.6.1 Interrupt Sources Interrupt sources are NMI, IRQ0 to IRQ14, and on-chip peripheral modules, as shown in table 4.7. Table 4.7 Interrupt Sources Type Source Number of Sources NMI NMI pin (external input) 1 IRQ0 to IRQ14 Pins IRQ0 to IRQ11 (external input) 15 On-chip peripheral module Watchdog timer (WDT) 1 A/D converter 2 16-bit timer pulse unit (TPU) 52*1/26*2 DMA controller (DMAC) 8 Serial communications interface (SCI) 8 Synchronous serial communication unit (SSU) 9 Controller area network (HCAN) 4 Notes: 1. The number of interrupts for the H8SX/1527 2. The number of interrupts for the H8SX/1525 Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 5.2 in section 5.5, Interrupt Exception Handling Vector Table. Rev. 1.00, 03/04, page 75 of 730 4.6.2 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. The interrupt exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Rev. 1.00, 03/04, page 76 of 730 4.7 Instruction Exception Handling There are two types of instructions that cause exception handling: trap instruction and illegal instructions. 4.7.1 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Table 4.8 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1 2 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev. 1.00, 03/04, page 77 of 730 4.7.2 Exception Handling by General Illegal Instruction There are two illegal instructions: general illegal instruction and slot illegal instruction. The exception handling by the general illegal instruction starts when an undefined code is decoded. The exception handling by the slot illegal instruction starts when the following instruction which is placed in a delay slot (immediately after a delayed branch instruction) is executed: an instruction which consists of two words or more or which changes the contents of PC. The general illegal and slot illegal instructions are always executable in the program execution state. The exception handling for the general illegal and a slot illegal instructions is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Table 4.9 shows the state of CCR and EXR after execution of illegal instruction exception handling. Table 4.9 Status of CCR and EXR after Illegal Instruction Exception Handling CCR EXR Interrupt Control Mode I UI T I2 to I0 0 1 2 1 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value. Rev. 1.00, 03/04, page 78 of 730 4.8 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of exception handling. Advanced mode SP EXR Reserved* SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Note: * Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 1.00, 03/04, page 79 of 730 4.9 Usage Note When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: * PUSH.W Rn (or MOV.W Rn, @-SP) * PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: * POP.W Rn (or MOV.W @SP+, Rn) * POP.L ERn (or MOV.L @SP+, ERn) Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 4.3 shows an example of operation when the SP value is odd. Address CCR SP R1L SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF TRAP instruction executed SP set to H'FFFEFF MOV.B R1L, @-ER7 executed Data saved above SP Contents of CCR lost (Address error occurred) [Legend] CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.3 Operation when SP Value Is Odd Rev. 1.00, 03/04, page 80 of 730 Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). * Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following six interrupt requests are given priority of 8, therefore they are accepted at all times. NMI General illegal instructions Trace Trap instructions CPU address error DMA address error* * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * 15 external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ14 to IRQ0. * DMAC control DMAC can be activated by means of interrupts. * CPU priority control function The priority levels can be assigned to the CPU and DMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DMAC transfer. Note: * A DMA address error is generated within the DMAC. A block diagram of the interrupt controller is shown in figure 5.1. Rev. 1.00, 03/04, page 81 of 730 INTM1, INTM0 INTCR CPU IPR NMIEG I I2 to I0 NMI input IRQ input unit ISCR Internal interrupt sources WOVI to SSTXI2 IER CPU vector ISR SSIER Source selecter EXR CPU interrupt request NMI input unit IRQ input CCR Priority decision unit DMAC activation enable DMAC DMAC priority control DMDR CPUPCR Interrupt controller [Legend] INTCR: CPUPCR: ISCR: IER: Interrupt control register CPU priority control register IRQ sense control register IRQ enable register ISR: IRQ status register SSIER: Software standby release IRQ enable register IPR: Interrupt priority register Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00, 03/04, page 82 of 730 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable External Interrupt Rising or falling edge can be selected. IRQ14 to IRQ0 Input Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers. * Interrupt control register (INTCR) * CPU priority control register (CPUPCR) * Interrupt priority registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) * IRQ enable register (IER) * IRQ sense control registers H and L (ISCRH, ISCRL) * IRQ status register (ISR) * Software standby release IRQ enable register (SSIER) Rev. 1.00, 03/04, page 83 of 730 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit 7 6 5 4 3 2 1 0 Bit Name - - INTM1 INTM0 NMIEG - - - Initial Value 0 0 0 0 0 0 0 0 R/W R R R/W R/W R/W R R R Bit 7, 6 Bit Name Initial Value All 0 R/W R 5 4 INTM1 INTM0 0 0 R/W R/W 3 NMIEG 0 R/W 2 to 0 All 0 R 5.3.2 CPU Priority Control Register (CPUPCR) Description Reserved These are read-only bits and cannot be modified. Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited. NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input Reserved These are read-only bits and cannot be modified. CPUPCR sets whether or not the CPU has priority over the DMAC. The interrupt exception handling by the CPU can be given priority over that of the DMAC transfer. The priority level of the DMAC for each channel is set by the DMAC control register. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 CPUPCE - - - IPSETE CPUP2 CPUP1 CPUP0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/(W)* R/(W)* R/(W)* Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Rev. 1.00, 03/04, page 84 of 730 Bit Bit Name Initial Value R/W Description 7 CPUPCE 0 R/W CPU Priority Control Enable Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled 6 to 4 All 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 3 IPSETE 0 R/W Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0 2 CPUP2 0 R/(W)* CPU Priority Level 2 to 0 1 CPUP1 0 R/(W)* 0 CPUP0 0 R/(W)* These bits set the CPU priority level. When the CPUPCE is set to 1, the CPU priority control function over the DMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified. Rev. 1.00, 03/04, page 85 of 730 5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R (IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see table 5.2. Bit 11 10 9 8 IPR12 - IPR10 IPR9 IPR8 1 0 1 1 1 R/W R/W R R/W R/W R/W 6 5 4 3 2 1 0 IPR6 IPR5 IPR4 - IPR2 IPR1 IPR0 15 14 13 12 Bit Name - IPR14 IPR13 Initial Value 0 1 1 R/W R R/W Bit 7 Bit Name - Initial Value 0 1 1 1 0 1 1 1 R/W R R/W R/W R/W R R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 0 R Reserved This is a read-only bit and cannot be modified. 14 IPR14 1 R/W 13 IPR13 1 R/W Sets the priority level of the corresponding interrupt source. 12 IPR12 1 R/W 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 11 0 R Reserved This is a read-only bit and cannot be modified. Rev. 1.00, 03/04, page 86 of 730 Bit Bit Name Initial Value R/W Description 10 IPR10 1 R/W 9 IPR9 1 R/W Sets the priority level of the corresponding interrupt source. 8 IPR8 1 R/W 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 7 0 R Reserved This is a read-only bit and cannot be modified. 6 IPR6 1 R/W 5 IPR5 1 R/W Sets the priority level of the corresponding interrupt source. 4 IPR4 1 R/W 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) 3 0 R Reserved This is a read-only bit and cannot be modified. 2 IPR2 1 R/W 1 IPR1 1 R/W Sets the priority level of the corresponding interrupt source. 0 IPR0 1 R/W 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest) Rev. 1.00, 03/04, page 87 of 730 5.3.4 IRQ Enable Register (IER) IER enables or disables interrupt requests IRQ14 to IRQ0. Bit Bit Name Initial Value R/W 13 12 11 10 9 8 - IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W 14 R/W Bit Bit Name 15 Bit Bit Name Initial Value R/W Description 15 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 14 IRQ14E 0 R/W IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable The IRQ13 interrupt request is enabled when this bit is 1. 12 IRQ12E 0 R/W IRQ12 Enable The IRQ12 interrupt request is enabled when this bit is 1. 11 IRQ11E 0 R/W IRQ11 Enable The IRQ11 interrupt request is enabled when this bit is 1. 10 IRQ10E 0 R/W IRQ10 Enable The IRQ10 interrupt request is enabled when this bit is 1. 9 IRQ9E 0 R/W IRQ9 Enable 8 IRQ8E 0 R/W IRQ8 Enable The IRQ9 interrupt request is enabled when this bit is 1. The IRQ8 interrupt request is enabled when this bit is 1. Rev. 1.00, 03/04, page 88 of 730 Bit Bit Name Initial Value R/W Description 7 IRQ7E 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable 1 IRQ1E 0 R/W IRQ1 Enable The IRQ2 interrupt request is enabled when this bit is 1. The IRQ1 interrupt request is enabled when this bit is 1. 0 IRQ0E 0 R/W IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev. 1.00, 03/04, page 89 of 730 5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) ISCRH and ISCRL select the source that generates an interrupt request on pins IRQ14 to IRQ0. Upon changing the setting of ISCR, IRQnF (n = 14 to 0) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0. * ISCRH Bit 15 14 13 12 11 10 9 8 Bit Name - - IRQ14SR IRQ14SF IRQ13SR IRQ13SF IRQ12SR IRQ12SF Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IRQ11SR IRQ11SF IRQ10SR IRQ10SF IRQ9SR IRQ9SF IRQ8SR IRQ8SF 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 IRQ7SR IRQ7SF IRQ6SR IRQ6SF IRQ5SR IRQ5SF IRQ4SR IRQ4SF 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IRQ3SR IRQ3SF IRQ2SR IRQ2SF IRQ1SR IRQ1SF IRQ0SR IRQ0SF 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W * ISCRL Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Rev. 1.00, 03/04, page 90 of 730 * ISCRH Bit Bit Name Initial Value R/W Description 15, 14 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 13 IRQ14SR 0 R/W 12 IRQ14SF 0 R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall 00: Interrupt request generated by low level of IRQ14 01: Interrupt request generated at falling edge of IRQ14 10: Interrupt request generated at rising edge of IRQ14 11: Interrupt request generated at both falling and rising edges of IRQ14 11 IRQ13SR 0 R/W 10 IRQ13SF 0 R/W IRQ13 Sense Control Rise IRQ13 Sense Control Fall 00: Interrupt request generated by low level of IRQ13 01: Interrupt request generated at falling edge of IRQ13 10: Interrupt request generated at rising edge of IRQ13 11: Interrupt request generated at both falling and rising edges of IRQ13 9 IRQ12SR 0 R/W 8 IRQ12SF 0 R/W IRQ12 Sense Control Rise IRQ12 Sense Control Fall 00: Interrupt request generated by low level of IRQ12 01: Interrupt request generated at falling edge of IRQ12 10: Interrupt request generated at rising edge of IRQ12 11: Interrupt request generated at both falling and rising edges of IRQ12 7 IRQ11SR 0 R/W 6 IRQ11SF 0 R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 Rev. 1.00, 03/04, page 91 of 730 Bit Bit Name Initial Value R/W Description 5 IRQ10SR 0 R/W 4 IRQ10SF 0 R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10 3 IRQ9SR 0 R/W 2 IRQ9SF 0 R/W IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9 1 IRQ8SR 0 R/W 0 IRQ8SF 0 R/W IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8 Rev. 1.00, 03/04, page 92 of 730 * ISCRL Bit Bit Name Initial Value R/W Description 15 IRQ7SR 0 R/W 14 IRQ7SF 0 R/W IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 13 IRQ6SR 0 R/W 12 IRQ6SF 0 R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 11 IRQ5SR 0 R/W 10 IRQ5SF 0 R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 9 IRQ4SR 0 R/W 8 IRQ4SF 0 R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 7 IRQ3SR 0 R/W 6 IRQ3SF 0 R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3 Rev. 1.00, 03/04, page 93 of 730 Bit Bit Name Initial Value R/W Description 5 IRQ2SR 0 R/W 4 IRQ2SF 0 R/W IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2 3 IRQ1SR 0 R/W 2 IRQ1SF 0 R/W IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1 1 IRQ0SR 0 R/W 0 IRQ0SF 0 R/W IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0 Rev. 1.00, 03/04, page 94 of 730 5.3.6 IRQ Status Register (ISR) ISR is an IRQ14 to IRQ0 interrupt request register. Bit 15 14 13 12 11 10 9 8 Bit Name - IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial Value 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F R/W Bit Bit Name 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial Value R/W Note: * Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Bit Bit Name Initial Value R/W 15 0 R/(W)* Reserved Description This bit is always read as 0. The write value should always be 0. 14 IRQ14F 0 R/(W)* [Setting condition] 13 IRQ13F 0 R/(W)* * 12 IRQ12F 0 R/(W)* [Clearing conditions] 11 IRQ11F 0 R/(W)* * Writing 0 after reading IRQnF = 1 10 IRQ10F 0 R/(W)* * 9 IRQ9F 0 R/(W)* When interrupt exception handling is executed when low-level sensing is selected and IRQn input is high 8 IRQ8F 0 R/(W)* * 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Note: * When the interrupt selected by ISCR occurs When IRQn interrupt exception handling is executed when falling-, rising-, or both-edge sensing is selected Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. Rev. 1.00, 03/04, page 95 of 730 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects pins used to leave software standby mode from pins IRQ14 to IRQ0. Bit 15 14 13 12 11 10 9 8 Bit Name - SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 R/W Bit Bit Name 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 15 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 14 SSI14 0 R/W Software Standby Release IRQ Setting 13 SSI13 0 R/W 12 SSI12 0 R/W These bits select the IRQn pins used to leave software standby mode (n = 11 to 0). 11 SSI11 0 R/W 10 SSI10 0 R/W 9 SSI9 0 R/W 8 SSI8 0 R/W 7 SSI7 0 R/W 6 SSI6 0 R/W 5 SSI5 0 R/W 4 SSI4 0 R/W 3 SSI3 0 R/W 2 SSI2 0 R/W 1 SSI1 0 R/W 0 SSI0 0 R/W Rev. 1.00, 03/04, page 96 of 730 0: IRQn requests are not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed 5.4 Interrupt Sources 5.4.1 External Interrupts There are sixteen external interrupts: NMI and IRQ14 to IRQ0. These interrupts can be used to leave software standby mode. NMI Interrupts: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. * Sets the ERRF bit in DMDR_0 to 1. * Clears the DTE bits for all the channels of the DMAC and forcibly halts transfer. IRQn Interrupts: An IRQn interrupt is requested by a signal input on pins IRQ14 to IRQ0. IRQn (n = 14 to 0) have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn. * Enabling or disabling of interrupt requests IRQn can be selected by IER. * The interrupt priority can be set by IPR. * The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions or memory operation instructions should be used to clear the flag in ISR. Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. A block diagram of interrupts IRQn is shown in figure 5.2. Rev. 1.00, 03/04, page 97 of 730 Corresponding bit in ICR IRQnE IRQnSF, IRQnSR IRQnF Edge/level detection circuit Input buffer IRQn interrupt request S Q R IRQn input Clear signal [Legend] n = 14 to 0 Figure 5.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins. 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority can be set by means of IPR. * The DMAC can be activated by a TPU, SCI, HCAN, SSU, or other interrupt request. * DMAC activation can be controlled by the CPU priority control function over the DMAC. Rev. 1.00, 03/04, page 98 of 730 5.5 Interrupt Exception Handling Vector Table Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 5.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation External pin NMI 7 H'001C High IRQ0 64 H'0100 IPRA14 to IPRA12 IRQ1 65 H'0104 IPRA10 to IPRA8 IRQ2 66 H'0108 IPRA6 to IPRA4 IRQ3 67 H'010C IPRA2 to IPRA0 IRQ4 68 H'0110 IPRB14 to IPRB12 IRQ5 69 H'0114 IPRB10 to IPRB8 IRQ6 70 H'0118 IPRB6 to IPRB4 IRQ7 71 H'011C IPRB2 to IPRB0 IRQ8 72 H'0120 IPRC14 to IPRC12 IRQ9 73 H'0124 IPRC10 to IPRC8 IRQ10 74 H'0128 IPRC6 to IPRC4 IRQ11 75 H'012C IPRC2 to IPRC0 IRQ12 76 H'0130 IPRD14 to IPRE12 IRQ13 77 H'0134 IPRD10 to IPRD8 IRQ14 78 H'0138 IPRD6 to IPRD4 Reserved for system use 79 H'013C 80 H'0140 WDT WOVI 81 H'0144 IPRE10 to IPRE8 Reserved for system use 82 H'0148 83 H'014C 84 H'0150 85 H'0154 Low Rev. 1.00, 03/04, page 99 of 730 Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation A/D_0 ADI0 86 H'0158 IPRF10 to IPRF8 High ADI1 87 H'015C TGI0A 88 H'0160 TGI0B 89 H'0164 TGI0C 90 H'0168 TGI0D 91 H'016C TCI0V 92 H'0170 TGI1A 93 H'0174 TGI1B 94 H'0178 TCI1V 95 H'017C TCI1U 96 H'0180 TGI2A 97 H'0184 TGI2B 98 H'0188 TCI2V 99 H'018C TCI2U 100 H'0190 TGI3A 101 H'0194 TGI3B 102 H'0198 TGI3C 103 H'019C TGI3D 104 H'01A0 TCI3V 105 H'01A4 TGI4A 106 H'01A8 TGI4B 107 H'01AC TCI4V 108 H'01B0 A/D_1 2 TPU_0* 2 TPU_1* 2 TPU_2* 2 TPU_3* 2 TPU_4* 2 TPU_5* O O IPRF6 to IPRF4 O IPRF2 to IPRF0 O IPRG14 to IPRG12 O IPRG10 to IPRG8 O IPRG6 to IPRG4 TCI4U 109 H'01B4 TGI5A 110 H'01B8 TGI5B 111 H'01BC TCI5V 112 H'01C0 TCI5U 113 H'01C4 Reserved for system use 114 H'01C8 115 H'01CC 116 H'01D0 117 H'01D4 118 H'01D8 Rev. 1.00, 03/04, page 100 of 730 IPRG2 to IPRG0 Low Classification Interrupt Source Vector Number Vector Address 1 Offset* 119 H'01DC 120 H'01E0 121 H'01E4 122 H'01E8 123 H'01EC 124 H'01F0 125 H'01F4 126 H'01F8 127 H'01FC DMTEND0 128 H'0200 IPRI14 to IPRI12 DMTEND1 129 H'0204 IPRI10 to IPRI8 DNTEND2 130 H'0208 IPRI6 to IPRI4 DMTEND3 131 H'020C IPRI2 to IPRI0 Reserved for system use 132 H'0210 133 H'0214 134 H'0218 135 H'021C DMEEND0 136 H'0220 DMEEND1 137 H'0224 DNEEND2 138 H'0228 DMEEND3 139 H'022C Reserved for system use 140 H'0230 141 H'0234 142 H'0238 143 H'023C 144 H'0240 145 H'0244 146 H'0248 147 H'024C 148 H'0250 149 H'0254 150 H'0258 151 H'025C DMAC DMAC Reserved for system use DMAC Priority Activation IPR High IPRK14 to IPRK12 Low Rev. 1.00, 03/04, page 101 of 730 Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation 152 H'0260 High 153 H'0264 154 H'0268 155 H'026C ERI3 156 H'0270 RXI3 157 H'0274 O TXI3 158 H'0278 O SCI_3 SCI_4 TPU_6 TPU_7 TPU_8 TPU_9 Reserved for system use IPRL10 to IPRL8 TEI3 159 H'027C ERI4 160 H'0280 RXI4 161 H'0284 O TXI4 162 H'0288 O TEI4 163 H'028C TGI6A 164 H'0290 TGI6B 165 H'0294 TGI6C 166 H'0298 IPRL6 to IPRL4 IPRL2 to IPRL0 O TGI6D 167 H'029C TCI6V 168 H'02A0 IPRM14 to IPRM12 TGI7A 169 H'02A4 IPRM10 to IPRM8 O TGI7B 170 H'02A8 TCI7V 171 H'02AC TCI7U 172 H'02B0 TGI8A 173 H'02B4 TGI8B 174 H'02B8 IPRM6 to IPRM4 O IPRM2 to IPRM0 TCI8V 175 H'02BC TCI8U 176 H'02C0 TGI9A 177 H'02C4 TGI9B 178 H'02C8 TGI9C 179 H'02CC TGI9D 180 H'02D0 TCI9V 181 H'02D4 Rev. 1.00, 03/04, page 102 of 730 IPRN14 to IPRN12 O IPRN10 to IPRN8 IPRN6 to IPRN4 Low Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation TPU_10 TGI10A 182 H'02D8 IPRN2 to IPRN0 High TGI10B 183 H'02DC Reserved for system use 184 H'02E0 Reserved for system use 185 H'02E4 TCI10V 186 H'02E8 TCI10U 187 H'02EC TGI11A 188 H'02F0 TPU_11 O IPRO14 to IPRO12 O IPRO10 to IPRO8 TGI11B 189 H'02F4 TCI11V 190 H'02F8 TCI11U 191 H'02FC Reserved for system use 192 H'0300 193 H'0304 194 H'0308 195 H'030C 196 H'0310 197 H'0314 198 H'0318 199 H'031C 200 H'0320 201 H'0324 202 H'0328 203 H'032C 204 H'0330 205 H'0334 206 H'0338 207 H'033C 208 H'0340 209 H'0344 210 H'0348 211 H'034C 212 H'0350 213 H'0354 IPRO6 to IPRO4 Low Rev. 1.00, 03/04, page 103 of 730 Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation 214 H'0358 High 215 H'035C 216 H'0360 217 H'0364 218 H'0368 219 H'036C ERS0/OVR0 220 H'0370 RM0 221 H'0374 O RM1 222 H'0378 SLE0 223 H'037C Reserved for system use 224 H'0380 225 H'0384 226 H'0388 SSERI0 227 H'038C SSRXI0 228 H'0390 HCAN SSU_0 SSU_1 SSU_2 Reserved for system use IPRQ2 to IPRQ0 IPRR14 to IPRR12 O IPRR10 to IPRR8 SSTXI0 229 H'0394 O Reserved for system use 230 H'0398 SSERI1 231 H'039C SSRXI1 232 H'03A0 SSTXI1 233 H'03A4 O Reserved for system use 234 H'03A8 SSERI2 235 H'03AC SSRXI2 236 H'03B0 SSTXI2 237 H'03B4 O Reserved for system use 238 H'03B8 239 H'03BC 240 H'03C0 241 H'03C4 242 H'03C8 243 H'03CC 244 H'03D0 245 H'03D4 Reserved for system use Rev. 1.00, 03/04, page 104 of 730 O IPRR6 to IPRR4 O IPRR2 to IPRR0 Low Classification Interrupt Source Vector Number Vector Address 1 Offset* IPR DMAC Priority Activation 246 H'03D8 High 247 H'03DC 248 H'03E0 249 H'03E4 250 H'03E8 251 H'03EC 252 H'03F0 253 H'03F4 254 H'03F8 255 H'03FC Note: Reserved for system use Low 1. Lower 16 bits of the start address in advanced mode. 2. Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 105 of 730 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Priority Setting Control Mode Register Interrupt Mask Bit 0 Default I The priority levels of the interrupt sources are fixed default settings. The interrupts except for NMI is masked by the I bit. 2 IPR I2 to I0 Eight priority levels can be set for interrupt sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0. 5.6.1 Description Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00, 03/04, page 106 of 730 Program execution state No Interrupt generated? Yes Yes NMI No I=0 No Pending Yes No IRQ0 Yes No IRQ1 Yes SSTXI2 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00, 03/04, page 107 of 730 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests has the same priority, an interrupt request is selected according to the default setting shown in table 5.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00, 03/04, page 108 of 730 Program execution state Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Level 1 interrupt? Mask level 5 or below? No No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev. 1.00, 03/04, page 109 of 730 Rev. 1.00, 03/04, page 110 of 730 Figure 5.5 Interrupt Exception Handling (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP - 2 (7) SP - 4 (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal I Interrupt acceptance Interrupt level determination Instruction prefetch Wait for end of instruction (6) (8) (9) (10) (11) (12) (6) (7) (8) (10) (9) Vector fetch (12) (11) Instruction prefetch in interrupt handling routine Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine (5) Stack Internal operation 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in onchip memory. 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing. Table 5.4 Interrupt Response Times 5 Normal Mode* Interrupt Control Mode 0 Execution State Interrupt Control Mode 2 Advanced Mode Interrupt Control Mode 0 Interrupt Control Mode 2 1 Interrupt priority decision* Interrupt Control Mode 0 Interrupt Control Mode 2 2*SK 2*SK 11 to 31 11 to 31 1 to 19 + 2*SI 6 SK to 2*SK* 2*SK 6 SK to 2*SK* Vector fetch 2*SK Sh Instruction fetch* 3 2*SI 4 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. 6. 5 3 Number of states until executing 2 instruction ends* PC, CCR, EXR stacking Maximum Mode 2 10 to 31 11 to 31 10 to 31 11 to 31 Two states for an internal interrupt. In the case of the MULXS or DIVXS instruction Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. Internal operation after interrupt acceptance or after vector fetch Not available in this LSI. When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n + 2, the interrupt response time is 2*SK. Rev. 1.00, 03/04, page 111 of 730 Table 5.5 Number of Execution States in Interrupt Handling Routine Object of Access External Device 8-Bit Bus 16-Bit Bus 32-Bit Bus Symbol On-Chip 2-State Memory Access 3-State Access 2-State Access 3-State Access 2-State Access 3-State Access Vector fetch Sh 1 8 12 + 4m 4 6 + 2m 2 3+m Instruction fetch SI 1 4 6 + 2m 2 3+m 2 3+m Stack manipulation SK 2 8 12 + 4m 4 6 + 2m 2 3+m [Legend] m: Number of wait cycles in an external device access. 5.6.5 DMAC Activation by Interrupt The DMAC can be activated by an interrupt. In this case, the following options are available: * Interrupt request to the CPU * Activation request to the DMAC * Combination of the above For details on interrupt requests that can be used to activate the DMAC, see table 5.2 and section 7, DMA Controller (DMAC). Figure 5.6 shows a block diagram of the DMAC and interrupt controller. Select signal Interrupt request On-chip peripheral Interrupt request clear signal module DMRSR0 TO DMRSR3 Control signal DMAC select circuit Interrupt request IRQ interrupt Interrupt request clear signal DMAC activation request signal DMAC DMAC request clear signal CPU select circuit CPU interrupt request vector number Priority decision I, I2 to I0 Interrupt controller Figure 5.6 Block Diagram of DMAC and Interrupt Controller Rev. 1.00, 03/04, page 112 of 730 CPU Selection of Interrupt Sources: A DMAC activation request source for each channel is specified by DMRSR. The request is passed to the DMAC via a selector. When the DTA bit in DMDR is set to 1, the specified request source cannot be used as a CPU interrupt source. Other interrupt sources, meaning that interrupt sources are not controlled by the DMAC, are used as CPU interrupt sources. When the same interrupt source is set as both the DMAC activation source and CPU interrupt source, the DMAC must be given priority over the CPU. Otherwise, DMAC transfer may not be performed or the DMAC may malfunction. Operation Order: If the same interrupt is selected as both the DMAC activation source and CPU interrupt source, the respective operations are performed independently. Table 5.6 lists the selection of interrupt sources and interrupt source clear control by means of the setting of the DTA bit in DMDR of the DMAC. Table 5.6 Interrupt Source Selection and Clear Control Setting DMAC Interrupt Source Selection/Clear Control DTA DMAC CPU 0 O 1 X [Legend] : The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. Usage Note: The interrupt sources of the SCI and A/D converter are cleared according to the setting shown in table 5.6, when the DMAC reads/writes the prescribed register. To initiate multiple channels for the DMAC with the same interrupt, the same priority should be assigned. Rev. 1.00, 03/04, page 113 of 730 5.7 CPU Priority Control Function Over DMAC The interrupt controller has a function to control the priority among the DMAC and the CPU by assigning priority levels to the DMAC and CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DMAC is assigned to each channel by bits DMAP2 to DMAP0 in the DMA mode control registers 0 to 3 (DMDR_0 to DMDR_3). The priority control function over the DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DMAC activation source is controlled according to the respective priority level. The priority level of the DMAC can be specified for each channel. The DMAC activation source is controlled according to the priority level of the CPU and the priority level of the DMAC indicated by bits DMAP2 to DMAP0. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUCPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). When the different priority levels of the DMAC are assigned for the channels, the channel having higher priority continues to transfer while the channel having lower priority than the CPU is held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level which is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 5.7 shows the CPU priority control. Rev. 1.00, 03/04, page 114 of 730 Table 5.7 CPU Priority Control Control Status Interrupt Control Interrupt Mode Priority Interrupt Mask Bit IPSETE in CPUPCR CPUP2 to CPUP0 Updating of CPUP2 to CPUP0 0 I = any 0 B'111 to B'000 Enabled I=0 1 B'000 Disabled Default I=1 2 IPR setting B'100 I2 to I0 0 B'111 to B'000 Enabled 1 I2 to I0 Disabled Table 5.8 shows an setting example of the priority control function over the DMAC and the transfer request control state. Although the DMAC priority levels can be assigned for each channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be performed independently by assigning the different priority levels. Table 5.8 Example of Priority Control Function Setting and Control State Transfer Request Control State Interrupt Control CPUPCE in Mode CPUPCR CPUP2 to CPUP0 DMAP2 to DMAP0 0 0 Any Any Enabled 1 B'000 B'000 Enabled B'100 B'000 Masked 2 DMAC B'100 B'011 Masked B'100 B'101 Enabled B'000 B'101 Enabled 0 Any Any Enabled 1 B'000 B'000 Enabled B'000 B'101 Enabled B'011 B'101 Enabled B'100 B'101 Enabled B'101 B'101 Enabled B'110 B'101 Masked B'111 B'101 Masked B'101 B'101 Enabled B'101 B'101 Enabled Rev. 1.00, 03/04, page 115 of 730 5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIV exception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.7 Conflict between Interrupt Generation and Disabling Rev. 1.00, 03/04, page 116 of 730 5.8.2 Instructions that Disable Interrupts Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller. 5.8.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: 5.8.5 EEPMOV.W MOV.W R4,R4 BNE L1 Interrupts during Execution of MOVMD and MOVSD Instructions With the MOVMD and MOVSD instructions, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine. Rev. 1.00, 03/04, page 117 of 730 5.8.6 Interrupt Flags of Peripheral Modules To clear an interrupt request flag by the CPU, the flag should be read from after clearing if the peripheral module clock is generated by dividing the system clock. This makes the request signal synchronized with the system clock. For details, see section 18.5.1, Notes on Clock Pulse Generator. Rev. 1.00, 03/04, page 118 of 730 Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that has a bus arbitration function and controls the operation of the internal bus masters; CPU and DMAC. 6.1 Features * Write data buffer function Write access to an on-chip peripheral module and access to the on-chip memory can be performed in parallel. * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DMAC. Bus mastership can be shared between the CPU and DMAC when a conflict occurs. * Multi-clock function On-chip peripheral functions can be synchronized with the on-chip peripheral module clock (P). A block diagram of the bus controller is shown in figure 6.1. Internal bus control signals CPU bus mastership acknowledge signal DMAC bus mastership acknowledge signal CPU bus mastership request signal DMAC bus mastership request signal Internal bus control unit Internal bus arbiter Control register Internal data bus BCR2 [Legend] BCR2: Bus control register 2 Figure 6.1 Block Diagram of Bus Controller Rev. 1.00, 03/04, page 119 of 730 6.2 Register Descriptions The bus controller has the following registers. * Bus control register 2 (BCR2) 6.2.1 Bus Control Register 2 (BCR2) BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the write data buffer function to the peripheral device. Bit 7 6 5 4 3 2 1 0 Bit Name - - - IBCCS - - - PWDBE Initial Value 0 0 0 0 0 0 1 0 R/W R R R/W R/W R R R/W R/W Bit Bit Name Initial Value R/W 7, 6 All 0 R Description Reserved These are read-only bits and cannot be modified. 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 IBCCS 0 R/W Internal Bus Cycle Control Select Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC bus mastership request 3, 2 All 0 R Reserved These are read-only bits and cannot be modified. 1 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used Rev. 1.00, 03/04, page 120 of 730 6.3 Bus Configuration Figure 6.2 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following two types. * Internal system bus 1 A bus that connects the CPU, DMAC, on-chip ROM, on-chip RAM, and internal peripheral bus. * Internal peripheral bus A bus that accesses registers in the DMAC, bus controller and interrupt controller and registers of peripheral modules such as SCI and timer. I synchronization CPU On-chip RAM On-chip ROM Internal system bus 1 Write data buffer Bus controller, interrupt controller, power-down controller DMAC Internal peripheral bus P synchronization Peripheral functions Figure 6.2 Internal Bus Configuration Rev. 1.00, 03/04, page 121 of 730 6.4 Multi-Clock Function The internal functions of this LSI operate synchronously with the system clock (I) or the peripheral module clock (P). Table 6.1 shows the synchronization clock and their corresponding functions. Table 6.1 Synchronization Clocks and Their Corresponding Functions Synchronization Clock Function Name I MCU operating mode Interrupt controller Bus controller CPU DMAC Internal memory Clock pulse generator Power down control P I/O ports TPU PPG WDT SCI HCAN SSU A/D The frequency of each synchronization clock (I and P) is specified by the system clock control register (SCKCR) independently. For further details, see section 18, Clock Pulse Generator. Rev. 1.00, 03/04, page 122 of 730 6.5 Internal Bus 6.5.1 Access to Internal Address Space The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 6.2 shows the number of access cycles for each on-chip memory space. Table 6.2 Number of Access Cycles for On-Chip Memory Spaces Access Space Access Number of Access Cycles On-chip ROM space Read One I cycle On-chip RAM space Read One I cycle Write Two I cycles In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access. Table 6.3 Number of Access Cycles for Registers of On-Chip Peripheral Modules Number of Cycles Module to be Accessed Read DMAC registers Write 2I Write Data Buffer Function Disabled MCU operating mode, clock pulse generator, power-down control, interrupt controller, and bus controller registers 2I 3I Disabled I/O port PFCR registers and WDT registers 2P 3P Disabled TPU, PPG, SCI, and A/D registers and I/O port registers other than PFCR 2P Enabled HCAN registers 4P Enabled SSU registers 3P Enabled Rev. 1.00, 03/04, page 123 of 730 6.6 Write Data Buffer Function 6.6.1 Write Data Buffer Function for External Data Bus This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and on-chip memory accesses in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. Figure 6.3 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write continues for two cycles or longer, and there is an internal access next, an external write only is executed in the first two cycles. However, from the next cycle onward, on-chip memory accesses and the external address space write rather than waiting until it ends are executed in parallel. On-chip memory read Peripheral module write I Internal address bus P Internal peripheral address bus Peripheral module address Internal peripheral data bus Figure 6.3 Example of Timing when Write Data Buffer Function is Used Rev. 1.00, 03/04, page 124 of 730 6.7 Bus Arbitration This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). The internal bus arbiter handles the CPU and DMAC accesses. The bus arbiters decide priority at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. 6.7.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration: (High) DMAC > CPU (Low) If the DMAC accesses continue, the CPU can be given priority over the DMAC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. 6.7.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Note, however, that the bus cannot be transferred in the following cases. * The word or longword access is performed in some divisions. * Stack handling is performed in multiple bus cycles. * Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.) Rev. 1.00, 03/04, page 125 of 730 * From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) DMAC: The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. Once the DMAC takes control of the bus, it continues the transfer processing cycles, or releases the bus every transfer cycle. The bus cannot be transferred in the following cases. * Between a read cycle and the corresponding write cycle in dual address mode While the IBCCS bit in BCR2 is cleared to 0, the bus cannot be transferred in the following cases. * During 1-block data transfer in block transfer mode * During burst access transfer The DMAC releases the bus when the consecutive transfer cycles completed except the above cycles. 6.8 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.9 Usage Notes All-Module-Clock-Stop Mode: In this LSI, if the ACSE bit in MSTPCR is set to 1 with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFFFFFF), a transition is made to the all-module-clock-stop mode. For details, see section 19, Power-Down Modes. Rev. 1.00, 03/04, page 126 of 730 Section 7 DMA Controller (DMAC) This LSI includes a 4-channel DMA controller (DMAC). 7.1 Features * Maximum of 4-G byte address space can be accessed * Byte, word, or longword can be set as data transfer unit * Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed * DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request*: Low level or falling edge detection of the DREQ signal can be selected (external request is available for all four channels) * Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode*: Either source or destination is specified by the DREQ signal and the other is specified by address * Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size * Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas DMAS260A_010020020400 Rev. 1.00, 03/04, page 127 of 730 * Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously * Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred * Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. Note: * An external request and single address mode are not supported by the H8SX/1520 Group. A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal data bus External pins DREQn* Data buffer DACKn* TENDn* Interrupt signals requested to the CPU by each channel Internal activation sources ... Controller Address buffer Operation unit Operation unit DOFR_n DSAR_n Internal activation source detector DDAR_n DMRSR_n DMDR_n DTCR_n DACR_n DBSR_n Module data bus [Legend] DSAR_n: DMA source address register DREQn: DMA transfer request DDAR_n: DMA destination address register DACKn: DMA transfer acknowledge DOFR_n: DMA offset register TENDn: DMA transfer end DTCR_n: DMA transfer count register n = 0 to 3 DBSR_n: DMA block size register DMDR_n: DMA mode control register DACR_n: DMA address control register DMRSR_n: DMA module request select register Note: * Auto request activation and single address mode are not supported by the H8SX/1520 Group. Figure 7.1 Block Diagram of DMAC Rev. 1.00, 03/04, page 128 of 730 7.2 Register Descriptions The DMAC has the following registers. Channel 0 * * * * * * * * DMA source address register_0 (DSAR_0) DMA destination address register_0 (DDAR_0) DMA offset register_0 (DOFR_0) DMA transfer count register_0 (DTCR_0) DMA block size register_0 (DBSR_0) DMA mode control register_0 (DMDR_0) DMA address control register_0 (DACR_0) DMA module request select register_0 (DMRSR_0) Channel 1 * * * * * * * * DMA source address register_1 (DSAR_1) DMA destination address register_1 (DDAR_1) DMA offset register_1 (DOFR_1) DMA transfer count register_1 (DTCR_1) DMA block size register_1 (DBSR_1) DMA mode control register_1 (DMDR_1) DMA address control register_1 (DACR_1) DMA module request select register_1 (DMRSR_1) Channel 2 * * * * * * * * DMA source address register_2 (DSAR_2) DMA destination address register_2 (DDAR_2) DMA offset register_2 (DOFR_2) DMA transfer count register_2 (DTCR_2) DMA block size register_2 (DBSR_2) DMA mode control register_2 (DMDR_2) DMA address control register_2 (DACR_2) DMA module request select register_2 (DMRSR_2) Rev. 1.00, 03/04, page 129 of 730 Channel 3 * * * * * * * * DMA source address register_3 (DSAR_3) DMA destination address register_3 (DDAR_3) DMA offset register_3 (DOFR_3) DMA transfer count register_3 (DTCR_3) DMA block size register_3 (DBSR_3) DMA mode control register_3 (DMDR_3) DMA address control register_3 (DACR_3) DMA module request select register_3 (DMRSR_3) 7.2.1 DMA Source Address Register (DSAR) DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit 31 30 29 28 27 26 25 24 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 130 of 730 7.2.2 DMA Destination Address Register (DDAR) DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit 31 30 29 28 27 26 25 24 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 131 of 730 7.2.3 DMA Offset Register (DOFR) DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel. Bit 31 30 29 28 27 26 25 24 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 132 of 730 7.2.4 DMA Transfer Count Register (DTCR) DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: -1, word: -2, and longword: -4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred. Bit 31 30 29 28 27 26 25 24 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 133 of 730 7.2.5 DMA Block Size Register (DBSR) DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit 31 30 29 28 27 26 25 24 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Bit Name Value R/W 31 to 16 BKSZH31 Undefined R/W to BKSZH16 15 to 0 Table 7.1 Mode BKSZ15 Undefined R/W to BKSZ0 Description Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 7.1). While the DMA is in operation, the setting is fixed. Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits. Data Access Size, Valid Bits, and Settable Size Data Access Size BKSZH Valid Bits BKSZ Valid Bits Repeat transfer Byte and block transfer Word Longword Rev. 1.00, 03/04, page 134 of 730 31 to 16 15 to 0 Settable Size (Byte) 1 to 65,536 2 to 131,072 4 to 262,144 7.2.6 DMA Mode Control Register (DMDR) DMDR controls the DMAC operation. * DMDR_0 Bit Bit Name Initial Value R/W Bit Bit Name 31 30 29 28 27 26 25 DTE DACKE TENDE - DREQS NRD - - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R 23 22 21 20 19 18 17 16 DTIF 24 ACT - - - ERRF - ESIF Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R/(W)* R R/(W)* R/(W)* Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 14 13 12 11 10 9 8 DTSZ1 DTSZ0 MDS1 MDS0 TSEIE - ESIE DTIE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R/W 7 6 5 4 3 2 1 0 DTF1 DTF0 DTA - - DMAP2 DMAP1 DMAP0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R/W R/W R/W 24 Only 0 can be written to this bit after having been read as 1, to clear the flag. * DMDR_1 to DMDR_3 Bit Bit Name Initial Value R/W Bit Bit Name 31 30 29 28 27 26 25 DTE DACKE TENDE - DREQS NRD - - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R 23 22 21 20 19 18 17 16 DTIF ACT - - - - - ESIF Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R/(W)* R/(W)* Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 14 13 12 11 10 9 8 DTSZ1 DTSZ0 MDS1 MDS0 TSEIE - ESIE DTIE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R R/W R/W 7 6 5 4 3 2 1 0 DTF1 DTF0 DTA - - DMAP2 DMAP1 DMAP0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R/W R/W R/W Only 0 can be written to this bit after having been read as 1, to clear the flag. Rev. 1.00, 03/04, page 135 of 730 Bit Initial Bit Name Value R/W Description 31 DTE R/W Data Transfer Enable 0 Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions] * When the specified total transfer size of transfers is completed * When a transfer is stopped by an overflow interrupt by a repeat size end * When a transfer is stopped by an overflow interrupt by an extended repeat size end * When a transfer is stopped by a transfer size error interrupt * When clearing this bit to 0 to stop a transfer In block transfer mode, this bit changes after the current block transfer. Rev. 1.00, 03/04, page 136 of 730 * When an address error or an NMI interrupt is requested * In the reset state or hardware standby mode Bit Initial Bit Name Value R/W Description 30 DACKE R/W DACK Signal Output Enable 0 Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Enables DACK signal output 1: Disables DACK signal output 29 TENDE 0 R/W TEND Signal Output Enable Enables/disables the TEND signal output. 0: Enables TEND signal output 1: Disables TEND signal output 28 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 27 DREQS 0 R/W DREQ Select Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. When a block transfer is performed in external request mode, clear this bit to 0 to select the low level detection. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level) 26 NRD 0 R/W Next Request Delay Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle after completion of the current transfer 25, 24 All 0 R 23 ACT 0 R Reserved These are read-only bits and cannot be modified. Active State Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state 22 to 20 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 137 of 730 Bit Initial Bit Name Value R/W 19 ERRF R/(W)* 0 Description System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition] * When clearing to 0 after reading ERRF = 1 [Setting condition] * When an address error or an NMI interrupt has been generated However, when an address error or an NMI interrupt has been generated in module stop mode, this bit is not set. 18 0 R Reserved This is a read-only bit and cannot be modified. 17 ESIF 0 R/(W)* Transfer Escape Interrupt Flag Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions] * When setting the DTE bit to 1 * When clearing to 0 before reading ESIF = 1 [Setting conditions] Rev. 1.00, 03/04, page 138 of 730 * When a transfer size error interrupt is requested * When a repeat size end interrupt is requested * When a transfer end interrupt by an extended repeat area overflow is requested Bit Initial Bit Name Value R/W 16 DTIF R/(W)* 0 Description Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions] * When setting the DTE bit to 1 * When clearing to 0 after reading DTIF = 1 [Setting condition] * When DTCR reaches 0 and the transfer is completed 15 DTSZ1 0 R/W Data Access Size 1 and 0 14 DTSZ0 0 R/W Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited 13 MDS1 0 R/W Transfer Mode Select 1 and 0 12 MDS0 0 R/W Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited Rev. 1.00, 03/04, page 139 of 730 Bit Initial Bit Name Value R/W Description 11 TSEIE R/W Transfer Size Error Interrupt Enable 0 Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows: * In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size * In block transfer mode, the total transfer size set in DTCR is less than the block size 0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10 0 R Reserved This is a read-only bit and cannot be modified. 9 ESIE 0 R/W Transfer Escape Interrupt Enable Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt 8 DTIE 0 R/W Data Transfer End Interrupt Enable Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt Rev. 1.00, 03/04, page 140 of 730 Bit Initial Bit Name Value R/W Description 7 DTF1 0 R/W Data Transfer Factor 1 and 0 6 DTF0 0 R/W Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request 5 DTA 0 R/W Data Transfer Acknowledge When the on-chip module interrupt is selected as a DMAC activation source, this bit must be set to 1. 4, 3 All 0 R Reserved These are read-only bits and cannot be modified. 2 DMAP2 0 R/W DMA Priority Level 2 to 0 1 DMAP1 0 R/W 0 DMAP0 0 R/W Select the priority level of the DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high) Note: * Only 0 can be written to, to clear the flag. Rev. 1.00, 03/04, page 141 of 730 7.2.7 DMA Address Control Register (DACR) DACR specifies the operating mode and transfer method. Bit Bit Name Initial Value R/W Bit Bit Name 31 30 29 28 27 26 25 24 AMS DIRS - - - RPTIE ARS1 ARS0 0 0 0 0 0 0 0 0 R/W R/W R R R R/W R/W R/W 23 22 21 20 19 18 17 16 - - SAT1 SAT0 - - DAT1 DAT0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R/W R/W R R R/W R/W 15 14 13 12 11 10 9 8 SARIE - - SARA4 SARA3 SARA2 SARA1 SARA0 Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DARIE - - DARA4 DARA3 DARA2 DARA1 DARA0 0 0 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 31 AMS R/W Address Mode Select 0 Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode 30 DIRS 0 R/W Single Address Direction Select Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address 29 to 27 0 R/W Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 142 of 730 Bit Initial Bit Name Value R/W Description 26 RPTIE R/W Repeat Size End Interrupt Enable 0 Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt 25 ARS1 0 R/W Area Select 1 and 0 24 ARS0 0 R/W Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22 All 0 R Reserved These are read-only bits and cannot be modified. 21 SAT1 0 R/W Source Address Update Mode 1 and 0 20 SAT0 0 R/W Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size Rev. 1.00, 03/04, page 143 of 730 Bit Initial Bit Name Value R/W 19, 18 R All 0 Description Reserved These are read-only bits and cannot be modified. 17 DAT1 0 R/W Destination Address Update Mode 1 and 0 16 DAT0 0 R/W Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size 15 SARIE 0 R/W Interrupt Enable for Source Address Extended Area Overflow Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address 14, 13 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 144 of 730 Bit Initial Bit Name Value R/W Description 12 SARA4 0 R/W Source Address Extended Repeat Area 11 SARA3 0 R/W 10 SARA2 0 R/W 9 SARA1 0 R/W 8 SARA0 0 R/W Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area. 7 DARIE 0 R/W Destination Address Extended Repeat Area Overflow Interrupt Enable Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address 6, 5 All 0 R Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 145 of 730 Bit Initial Bit Name Value R/W Description 4 DARA4 0 R/W Destination Address Extended Repeat Area 3 DARA3 0 R/W 2 DARA2 0 R/W 1 DARA1 0 R/W 0 DARA0 0 R/W Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 7.2 shows the settings and areas of the extended repeat area. Rev. 1.00, 03/04, page 146 of 730 Table 7.2 Settings and Areas of Extended Repeat Area SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 Not specified 00001 2 bytes specified as extended repeat area by the lower 1 bit of the address 00010 4 bytes specified as extended repeat area by the lower 2 bits of the address 00011 8 bytes specified as extended repeat area by the lower 3 bits of the address 00100 16 bytes specified as extended repeat area by the lower 4 bits of the address 00101 32 bytes specified as extended repeat area by the lower 5 bits of the address 00110 64 bytes specified as extended repeat area by the lower 6 bits of the address 00111 128 bytes specified as extended repeat area by the lower 7 bits of the address 01000 256 bytes specified as extended repeat area by the lower 8 bits of the address 01001 512 bytes specified as extended repeat area by the lower 9 bits of the address 01010 1 kbyte specified as extended repeat area by the lower 10 bits of the address 01011 2 kbytes specified as extended repeat area by the lower 11 bits of the address 01100 4 kbytes specified as extended repeat area by the lower 12 bits of the address 01101 8 kbytes specified as extended repeat area by the lower 13 bits of the address 01110 16 kbytes specified as extended repeat area by the lower 14 bits of the address 01111 32 kbytes specified as extended repeat area by the lower 15 bits of the address 10000 64 kbytes specified as extended repeat area by the lower 16 bits of the address 10001 128 kbytes specified as extended repeat area by the lower 17 bits of the address 10010 256 kbytes specified as extended repeat area by the lower 18 bits of the address 10011 512 kbytes specified as extended repeat area by the lower 19 bits of the address 10100 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 10101 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 10110 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 10111 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 11000 16 Mbytes specified as extended repeat area by the lower 24 bits of the address 11001 32 Mbytes specified as extended repeat area by the lower 25 bits of the address 11010 64 Mbytes specified as extended repeat area by the lower 26 bits of the address 11011 128 Mbytes specified as extended repeat area by the lower 27 bits of the address 111xx Setting prohibited [Legend] x: Don't care Rev. 1.00, 03/04, page 147 of 730 7.2.8 DMA Module Request Select Register (DMRSR) DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 7.4. Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W 7.3 Transfer Modes Table 7.3 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 7.3 Transfer Modes Address Register Address Mode Transfer mode Dual address * Normal transfer * Repeat transfer * Block transfer Activation Source Common Function Source Destination * * DSAR DDAR On-chip module interrupt Total transfer size: 1 to 4 Gbytes or not specified * Offset addition External request * Extended repeat area function DSAR/ DACK DACK/ DDAR Repeat or block size * = 1 to 65,536 bytes, 1 to 65,536 words, or * 1 to 65,536 longwords Single address Auto request (activated by CPU) * Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin * The same settings as above are available other than address register setting (e.g., above transfer modes can be specified) * One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes) When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count. Rev. 1.00, 03/04, page 148 of 730 7.4 Operations 7.4.1 Address Modes (1) Dual Address Mode In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Figure 7.2 shows an example of the signal timing in dual address mode and figure 7.3 shows the operation in dual address mode. DMA read cycle DMA write cycle B Address bus DSAR DDAR RD WR TEND Figure 7.2 Example of Signal Timing in Dual Address Mode Rev. 1.00, 03/04, page 149 of 730 Transfer Address TA Address TB Address update setting is as follows: Source address increment Fixed destination address Address BA Figure 7.3 Operations in Dual Address Mode (2) Single Address Mode In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 6, Bus Controller (BSC). The DMAC accesses an external device as the transfer source or destination by outputting the strobe signal to the external device (DACK) and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 7.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an example of operation in single address mode. Rev. 1.00, 03/04, page 150 of 730 External address bus External data bus LSI External memory DMAC Data flow External device with DACK DACK DREQ Figure 7.4 Data Flow in Single Address Mode Transfer from external memory to external device with DACK DMA cycle B Address bus DSAR RD Address for external memory space RD signal for external memory space WR DACK Data output by external memory Data bus TEND Transfer from external device with DACK to external memory DMA cycle B Address bus DDAR Address for external memory space RD WR WR signal for external memory space DACK Data bus Data output by external device with DACK TEND Figure 7.5 Example of Signal Timing in Single Address Mode Rev. 1.00, 03/04, page 151 of 730 Address T DACK Transfer Address B Figure 7.6 Operations in Single Address Mode 7.4.2 Transfer Modes (1) Normal Transfer Mode In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. The DACK signal is output every time a transfer request is received and a transfer starts. Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows the operation in normal transfer mode. Auto request transfer in dual address mode: Bus cycle DMA transfer cycle Last DMA transfer cycle Read Read Write Write TEND External request transfer in single address mode: DREQ Bus cycle DMA DMA DACK Figure 7.7 Example of Signal Timing in Normal Transfer Mode Rev. 1.00, 03/04, page 152 of 730 Transfer Address TA Address TB Total transfer size (DTCR) Address BA Address BB Figure 7.8 Operations in Normal Transfer Mode (2) Repeat Transfer Mode In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 x data access size. The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the repeat area returns to the transfer start address when the repeat size of transfers is completed. This operation is repeated until the total transfer size specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0. In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the CPU when the repeat size of transfers is completed. When the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an interrupt is requested to the CPU when the ESIE bit in DMDR is set to 1. The timings of the TEND and DACK signals are the same as in normal transfer mode. Figure 7.9 shows the operation in repeat transfer mode while dual address mode is set. When the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 7.8. In this case, a repeat size end interrupt can also be requested to the CPU when the repeat size of transfers is completed. Rev. 1.00, 03/04, page 153 of 730 Transfer Address TA Address TB Repeat size = BKSZH x data access size Total transfer size (DTCR) Address BA Operation when the repeat area is specified to the source side Address BB Figure 7.9 Operations in Repeat Transfer Mode (3) Block Transfer Mode In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 65536 x data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When the external request is selected as an activation source, the low level detection of the DREQ signal (DREQS = 0) should be selected. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 7.4.5, Extended Repeat Area Function. Rev. 1.00, 03/04, page 154 of 730 Figure 7.10 shows an example of the DMA transfer timing in block transfer mode. The transfer conditions are as follows: * Address mode: single address mode * Data access size: byte * 1-block size: three bytes The block transfer mode operations in single address mode and in dual address mode are shown in figures 7.11 and 7.12, respectively. DREQ Transfer cycles for one block Bus cycle CPU CPU DMAC DMAC DMAC CPU No CPU cycle generated TEND Figure 7.10 Operations in Block Transfer Mode Address T Transfer DACK Block BKSZH x data access size Address B Figure 7.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified) Rev. 1.00, 03/04, page 155 of 730 Address TB Address TA Transfer First block First block BKSZH x data access size Second block Second block Total transfer size (DTCR) Nth block Nth block Address BB Address BA Figure 7.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified) Rev. 1.00, 03/04, page 156 of 730 7.4.3 Activation Sources The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 7.4 is a list of on-chip module interrupts for the DMAC. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated by the activation source which is selected while DTE = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit. Rev. 1.00, 03/04, page 157 of 730 Table 7.4 List of On-chip module interrupts to DMAC On-Chip Module Interrupt Source On-Chip Module DMRSR (Vector Number) ADI0 (A/D conversion end interrupt) ADI1 (A/D conversion end interrupt) TGI0A (TGI0A input capture/compare match) TGI1A (TGI1A input capture/compare match) TGI2A (TGI2A input capture/compare match) TGI3A (TGI3A input capture/compare match) RXI3 (receive data full interrupt for SCI channel 3) TXI3 (transmit data empty interrupt for SCI channel 3) RXI4 (receive data full interrupt for SCI channel 4) TXI4 (transmit data empty interrupt for SCI channel 4) TGI6A (TGI6A input capture/compare match) TGI7A (TGI7A input capture/compare match) TGI8A (TGI8A input capture/compare match) TGI9A (TGI9A input capture/compare match) TGI10A (TGI10A input capture/compare match) TGI11A (TGI11A input capture/compare match) RM0 (message reception in Mailbox 0) SSRXI0 (receive data full interrupt for SSU channel 0) SSTXI0 (transmit data empty interrupt or transmit end for SSU channel 0) SSRXI1 (receive data full interrupt for SSU channel 1) SSTXI1 (transmit data empty interrupt or transmit end for SSU channel 1) SSRXI2 (receive data full interrupt for SSU channel 2) SSTXI2 (transmit data empty interrupt or transmit end for SSU channel 2) A/D_0 A/D_1 TPU_0 TPU_1 TPU_2 TPU_3 SCI_3 SCI_3 SCI_4 SCI_4 TPU_6 TPU_7 TPU_8 TPU_9 TPU_10 TPU_11 HCAN SSU_0 SSU_0 SSU_1 SSU_1 SSU_2 SSU_2 86 87 88 93 97 101 157 158 161 162 164 169 173 177 182 188 221 228 229 232 233 236 237 (3) Activation by External Request A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. To perform a block transfer, select the low level detection. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 8, I/O Ports. When a DMA transfer between on-chip peripheral modules is performed, select an activation source form the auto request and on-chip module interrupt (the external request cannot be used). Rev. 1.00, 03/04, page 158 of 730 7.4.4 Bus Access Modes There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 7.4.8, Priority of Channels. Figure 7.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: * Address mode: Single address mode * Sampling method of the DREQ signal: Low level detection DREQ Bus cycle CPU CPU DMAC CPU DMAC CPU Bus released temporarily for the CPU Figure 7.13 Example of Timing in Cycle Stealing Mode Rev. 1.00, 03/04, page 159 of 730 (2) Burst Access Mode In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until the transfer end condition is satisfied. Even if a transfer is requested from another channel having priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle stealing mode. However, setting the IBCCS bit in IBCR of the bus controller makes the DMAC release the bus to pass the bus to another bus master. In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). The DMAC is always operated in cycle stealing mode. Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends. Figure 7.14 shows an example of timing in burst mode. Bus cycle CPU CPU DMAC DMAC DMAC CPU No CPU cycle generated Figure 7.14 Example of Timing in Burst Mode Rev. 1.00, 03/04, page 160 of 730 CPU 7.4.5 Extended Repeat Area Function The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer. Figure 7.15 shows an example of the extended repeat area operation. ... When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240000 H'240001 H'240001 H'240002 H'240002 H'240003 H'240003 H'240004 H'240004 H'240005 H'240005 H'240006 H'240006 H'240007 H'240007 H'240008 Repeat An interrupt request by extended repeat area overflow can be generated. ... H'240009 Figure 7.15 Example of Extended Repeat Area Operation Rev. 1.00, 03/04, page 161 of 730 When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns. Figure 7.16 shows examples when the extended repeat area function is used in block transfer mode. ... When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in DTCR = 5). External memory Area specified 1st block 2nd block by DSAR transfer transfer H'23FFFE H'23FFFF H'240000 H'240000 H'240000 H'240000 H'240001 H'240001 H'240001 H'240001 H'240002 H'240002 H'240002 H'240003 H'240003 H'240003 H'240004 H'240004 H'240004 H'240005 H'240005 H'240005 H'240006 H'240006 H'240006 H'240007 H'240007 H'240007 H'240008 Block transfer continued ... H'240009 Interrupt request generated Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode Rev. 1.00, 03/04, page 162 of 730 7.4.6 Address Update Function using Offset The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 7.17 shows the address update method. External memory External memory 0 External memory 1, 2, or 4 + offset Address not updated (a) Address fixed Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4 Offset is added to address (addresses are not continuous) (c) Offset addition Figure 7.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size. Rev. 1.00, 03/04, page 163 of 730 The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. (1) Basic Transfer Using Offset Figure 7.18 shows a basic operation of a transfer using the offset addition. Data 1 Address A1 Transfer Offset Data 2 Data 1 Data 2 Data 3 Data 4 Data 5 : Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4 Address A2 = Address A1 + Offset : : : Offset Data 3 Address A3 = Address A2 + Offset Data 4 Address A4 = Address A3 + Offset Data 5 Address A5 = Address A4 + Offset Offset Transfer source: Offset addition Transfer destination: Increment by 4 (longword) Offset Figure 7.18 Operation of Offset Addition In figure 7.18, the offset addition is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means that data at the address which is away from the previous transfer source address by the offset is read from. The data read from the address away from the previous address is written to the consecutive area in the destination side. Rev. 1.00, 03/04, page 164 of 730 (2) XY Conversion Using Offset Figure 7.19 shows the XY conversion using the offset addition in repeat transfer mode. Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 1st transfer Offset Offset Offset Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer Transfer 3rd transfer 4th transfer 2nd transfer Transfer source 3rd transfer addresses changed by CPU Data 1 Data 1 Data 5 Data 5 Address initialized Data 9 Data 9 Address initialized Data 13 Data 13 Data 2 Data 2 Data 6 Data 6 Data 10 Data 10 Data 14 Data 14 Data 3 Data 3 Data 7 Data 7 Data 11 Data 11 Data 15 Data 15 Data 4 Data 4 Data 8 Data 8 Interrupt request Data 12 Data 12 Interrupt generated request Data 16 Data 16 generated Data 1 Data 2 Data 5 Data 9 Data 6 Data 10 Data 3 Data 7 Data 11 Data 4 Data 8 Data 12 Data 13 Data 14 Data 15 Data 16 Transfer Transfer source addresses changed by CPU Interrupt request generated Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16 1st transfer 2nd transfer 3rd transfer 4th transfer Figure 7.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 7.19, the source address side is specified to the repeat area by DACR and the offset addition is selected. The offset value is set to 4 x data access size (when the data access size is longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 x data access size (when the data access size is longword, the repeat size is set to 4 x 4 = 16 bytes, as an example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address. A repeat size end interrupt is requested when the repeat size of transfers is completed. When a transfer starts, the transfer source address is added to the offset every time data is transferred. The transfer data is written to the destination continuous addresses. When data 4 is transferred meaning that the repeat size of transfers is completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are written to the address of data 5 by the CPU (when the data access size is longword, write the data 1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when the transfer is stopped. Accordingly, operations are repeated and the transfer source data is transposed to the destination area (XY conversion). Rev. 1.00, 03/04, page 165 of 730 Figure 7.29 shows a flowchart of the XY conversion. Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt Set DTE bit to 1 Receives transfer request Transfers data Decrements transfer count and repeat size No Transfer count = 0? Yes No Repeat size = 0? Yes Initializes transfer source address Generates repeat size end interrupt request Set transfer source address + 4 (Longword transfer) End : User operation : DMAC operation Figure 7.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode (3) Offset Subtraction When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction. Rev. 1.00, 03/04, page 166 of 730 7.4.7 Register during DMA Transfer The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. Rev. 1.00, 03/04, page 167 of 730 (2) DMA Destination Address Register When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR) A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. Rev. 1.00, 03/04, page 168 of 730 While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR) DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to. (5) DTE Bit in DMDR Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows: * * * * * * * * * When the total size of transfers is completed When a transfer is completed by a transfer size error interrupt When a transfer is completed by a repeat size end interrupt When a transfer is completed by an extended repeat area overflow interrupt When a transfer is stopped by an NMI interrupt When a transfer is stopped by and address error Reset state Hardware standby mode When a transfer is stopped by writing 0 to the DTE bit Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0. Rev. 1.00, 03/04, page 169 of 730 Figure 7.21 show the procedure for changing the register settings for the channel being transferred. Changing register settings of channel during operation [1] Write 0 to the DTE bit in DMDR. [2] Read the DTE bit. Write 0 to DTE bit [1] Read DTE bit [2] DTE = 0? [3] Confirm that DTE = 0. DTE = 1 indicates that DMA is transferring. [4] Write the desired values to the registers. [3] No Yes Change register settings [4] End of changing register settings Figure 7.21 Procedure for Changing Register Setting For Channel being Transferred (6) ACT Bit in DMDR The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. Rev. 1.00, 03/04, page 170 of 730 (7) ERRF Bit in DMDR When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. (8) ESIF Bit in DMDR When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources. (9) DTIF Bit in DMDR The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 7.7, Interrupt Sources. Rev. 1.00, 03/04, page 171 of 730 7.4.8 Priority of Channels The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 7.5 shows the priority levels among the DMAC channels. Table 7.5 Priority among DMAC Channels Channel Priority Channel 0 High Channel 1 Channel 2 Channel 3 Low The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched. Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2. Channel 1 transfer Channel 0 transfer Channel 2 transfer B Address bus DMAC operation Channel 0 Channel 1 Channel 2 Channel 0 Wait Bus released Channel 1 Channel 0 Channel 1 Bus released Channel 2 Request cleared Request cleared Request Selected retained Request Not Request retained selected retained Selected Request cleared Figure 7.22 Example of Timing for Channel Priority Rev. 1.00, 03/04, page 172 of 730 Channel 2 Wait 7.4.9 DMA Basic Bus Cycle Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings. DMAC cycle (one word transfer) CPU cycle T1 T2 T1 T2 T3 T1 CPU cycle T2 T3 B Source address Destination address Address bus RD HHWR, LHWR LLWR Figure 7.23 Example of Bus Timing of DMA Transfer Rev. 1.00, 03/04, page 173 of 730 7.4.10 Bus Cycles in Dual Address Mode (1) Normal Transfer Mode (Cycle Stealing Mode) In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. DMA read cycle DMA read cycle DMA write cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Bus released Bus released Bus released Last transfer cycle Bus released Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary. Rev. 1.00, 03/04, page 174 of 730 DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle DMA byte read cycle DMA word read cycle DMA byte read cycle DMA word write cycle DMA word write cycle 4m + 1 4m + 2 4m + 4 4n 4n +2 4m + 5 4m + 6 4m + 8 4n + 4 4n + 6 B Address bus RD LHWR LLWR TEND Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment) DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4 B Address bus 4m 4m + 2 RD LHWR LLWR TEND Bus released Bus released Last transfer cycle Bus released m and n are integers. Figure 7.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement) Rev. 1.00, 03/04, page 175 of 730 (2) Normal Transfer Mode (Burst Mode) In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 7.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD HHWR, HLWR High LHWR, LLWR TEND Last transfer cycle Bus released Burst transfer Figure 7.27 Example of Transfer in Normal Transfer Mode by Burst Access Rev. 1.00, 03/04, page 176 of 730 Bus released (3) Block Transfer Mode In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 7.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode. DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle B Address bus RD LHWR, LLWR TEND Bus released Block transfer Bus released Last block transfer cycle Bus released Figure 7.28 Example of Transfer in Block Transfer Mode Rev. 1.00, 03/04, page 177 of 730 (4) Activation Timing by DREQ Falling Edge Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle Bus released DMA write cycle DMA read cycle Bus released DMA write cycle Bus released B DREQ Address bus DMA operation Transfer source Transfer destination Read Wait Request [2] [3] Write Wait Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] Read Wait Duration of transfer request disabled Request Channel Write Transfer source Transfer destination [4] [5] Transfer request enable resumed [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge Rev. 1.00, 03/04, page 178 of 730 (5) Activation Timing by DREQ Low Level Figure 7.30 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle Bus released DMA write cycle DMA read cycle Bus released DMA write cycle Bus released B DREQ Transfer source Address bus DMA operation Channel Wait Read Transfer destination Write Wait Duration of transfer request disabled Request Transfer source Read Request [2] Write Wait Duration of transfer request disabled Min. of 3 cycles Min. of 3 cycles [1] Transfer destination [3] [4] [5] Transfer request enable resumed [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.30 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level Rev. 1.00, 03/04, page 179 of 730 Figure 7.31 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. 1-block transfer 1-block transfer DMA read cycle Bus released DMA write cycle DMA write cycle DMA read cycle Bus released Bus released B DREQ Transfer source Address bus DMA operation Channel Wait Read Request Transfer destination Transfer source Wait Write Read Duration of transfer request disabled [1] [2] Write Wait Duration of transfer request disabled Request Min. of 3 cycles Transfer destination Min. of 3 cycles [3] [4] [5] Transfer request enable resumed [6] [7] Transfer request enable resumed [1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) Figure 7.31 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level Rev. 1.00, 03/04, page 180 of 730 (6) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.32 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA read cycle Bus released DMA read cycle DMA read cycle Bus released DMA read cycle Bus released B DREQ Transfer source Address bus Channel Request Duration of transfer request disabled Transfer destination Transfer source Duration of transfer request disabled which is extended by NRD Request Min. of 3 cycles [1] [2] Transfer destination Duration of transfer request disabled Duration of transfer request disabled which is extended by NRD Min. of 3 cycles [3] [4] [5] Transfer request enable resumed [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.32 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1 Rev. 1.00, 03/04, page 181 of 730 7.4.11 Bus Cycles in Single Address Mode (1) Single Address Mode (Read and Cycle Stealing) In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read). DMA read cycle DMA read cycle DMA read cycle DMA read cycle B Address bus RD DACK TEND Bus released Bus released Bus released Bus Last transfer Bus released released cycle Figure 7.33 Example of Transfer in Single Address Mode (Byte Read) Rev. 1.00, 03/04, page 182 of 730 (2) Single Address Mode (Write and Cycle Stealing) In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU are executed in the bus released cycles. In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write). DMA write cycle DMA write cycle DMA write cycle DMA write cycle B Address bus HHWR, HLWR LLWR DACK TEND Bus released Bus released Bus released Last transfer Bus Bus cycle released released Figure 7.34 Example of Transfer in Single Address Mode (Byte Write) Rev. 1.00, 03/04, page 183 of 730 (3) Activation Timing by DREQ Falling Edge Figure 7.35 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the single cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. Bus released DMA single cycle Bus released DMA single cycle Bus released B DREQ Transfer source/ Transfer destination Transfer source/ Transfer destination Address bus DACK DMA operation Single Wait Request Channel Single Wait Duration of transfer request disabled Request Min. of 3 cycles [1] [2] Wait Duration of transfer request disabled Min. of 3 cycles [3] [4] Transfer request enable resumed [5] [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.35 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge Rev. 1.00, 03/04, page 184 of 730 (4) Activation Timing by DREQ Low Level Figure 7.36 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfe is completed. Bus released DMA single cycle Bus released DMA single cycle Bus released B DREQ Transfer source/ Transfer destination Address bus Transfer source/ Transfer destination DACK DMA operation Single Wait Request Channel Single Wait Duration of transfer request disabled [1] [2] Duration of transfer request disabled Request Min. of 3 cycles Wait Min. of 3 cycles [3] [4] Transfer request enable resumed [5] [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.36 Example of Transfer in Single Address Mode Activated by DREQ Low Level Rev. 1.00, 03/04, page 185 of 730 (5) Activation Timing by DREQ Low Level with NRD = 1 When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 7.37 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed. DMA single cycle Bus released DMA single cycle Bus released Bus released B DREQ Channel Transfer source/ Transfer destination Transfer source/ Transfer destination Address bus Request Duration of transfer request disabled which is extended by NRD Duration of transfer Request request disabled Min. of 3 cycles [1] [2] Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled Min. of 3 cycles [3] [4] [5] Transfer request enable resumed [6] [7] Transfer request enable resumed After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1] Figure 7.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1 Rev. 1.00, 03/04, page 186 of 730 7.5 DMA Transfer End Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0 When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMR is cleared to 0 and the ESIF bit in DMDR is set to 1. * In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size * In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below. * In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes * In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes. (3) Transfer End by Repeat Size End Interrupt In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. Rev. 1.00, 03/04, page 187 of 730 (4) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred. (6) Transfer End by NMI Interrupt When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. Rev. 1.00, 03/04, page 188 of 730 (7) Transfer End by Address Error When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed. 7.6 Relationship among DMAC and Other Bus Masters 7.6.1 CPU Priority Control Function Over DMAC The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 5.7, CPU Priority Control Function Over DMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. If the priority level of the transfer request masked by the CPU priority control function is changed or the CPU priority is changed, the transfer request may be received and the transfer is started. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority. Transfer requests masked are suspended. If a transfer request is suspended, it is cleared by clearing the DTE bit to 0. Rev. 1.00, 03/04, page 189 of 730 7.6.2 Bus Arbitration among DMAC and Other Bus Masters When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU, accesses to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 6, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and a refresh cycle or an external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a cycle of refresh or external bus release is inserted by the BSC (when the CPU external access does not have priority over a DMAC transfer, the transfer is not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and an external bus release cycle may be performed at the same time. Rev. 1.00, 03/04, page 190 of 730 7.7 Interrupt Sources The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 7.6 shows interrupt sources and priority. Table 7.6 Interrupt Sources and Priority Abbr. Interrupt Sources Priority DMTEND0 Transfer end interrupt by channel 0 transfer counter High DMTEND1 Transfer end interrupt by channel 1 transfer counter DMTEND2 Transfer end interrupt by channel 2 transfer counter DMTEND3 Transfer end interrupt by channel 3 transfer counter DMEEND0 Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are decided by the interrupt controller and it is shown in table 7.6. For details, see section 5, Interrupt Controller. Rev. 1.00, 03/04, page 191 of 730 Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 7.38 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 7.39 shows procedure to resume the transfer by clearing a interrupt. Rev. 1.00, 03/04, page 192 of 730 TSIE bit DTIE bit DMAC is activated in transfer size error state DTIF bit RPTIE bit Transfer end interrupt [Setting condition] When DTCR becomes 0 and transfer ends DMAC is activated after BKSZ bits are changed from 1 to 0 SARIE bit ESIE bit Extended repeat area overflow occurs in source address Transfer escape end interrupt ESIF bit DARIE bit Setting condition is satisfied Extended repeat area overflow occurs in destination address Figure 7.38 Interrupt and Interrupt Sources Transfer end interrupt handling routine Consecutive transfer processing Transfer resumed after interrupt handling routine Registers are specified [1] DTE bit is set to 1 [2] Interrupt handling routine ends (RTE instruction executed) DTIF and ESIF bits are cleared to 0 [4] Interrupt handling routine ends [5] Registers are specified [6] DTE bit is set to 1 [7] [3] Transfer resume processing end Transfer resume processing end [1] Specify the values in the registers such as transfer counter and address register. [2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or ESIF bit in DMDR to 0 and an interrupt source is cleared. [3] End the interrupt handling routine by the RTE instruction. [4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit. [5] Complete the interrupt handling routine and clear the interrupt mask. [6] Specify the values in the registers such as transfer counter and address register. [7] Set the DTE bit to 1 to resume DMA operation. Figure 7.39 Procedure Example of Resuming Transfer by Clearing Interrupt Source Rev. 1.00, 03/04, page 193 of 730 7.8 Notes on Usage 1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary. TENDE bit in DMDR is 1 (the TEND signal output enabled) DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer. Rev. 1.00, 03/04, page 194 of 730 Section 8 I/O Ports Table 8.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Ports 4 and 5 do not have a DR or a DDR register. Ports D, H, J and K have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Port 2 includes an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. Ports 1, 2, 3, 6, A, D, H, J, and K can drive a single TTL load and capacitive loads up to 30 pF. All of the I/O ports can drive Darlington transistors when functioning as output ports. Schmitt-trigger inputs are enabled when a port is used as the IRQ and TPU inputs. Table 8.1 Port Functions Function Port Description Bit I/O Input Output SchmittTrigger 1 Input* P17 ADTRG1/ IRQ7 IRQ7 Port 1 General I/O port 7 also functioning as interrupt inputs, 6 SCI I/Os, and A/D converter inputs 5 P16/SCK3 IRQ6 IRQ6 P15 RxD3/ IRQ5 IRQ5 4 P14 IRQ4 TxD3 IRQ4 3 P13 ADTRG0/ IRQ3 IRQ3 2 P12 IRQ2 IRQ2 1 P11 IRQ1 IRQ1 0 P10 IRQ0 IRQ0 Input Pull-up MOS Function OpenDrain Output Function Rev. 1.00, 03/04, page 195 of 730 Function Port Description I/O Input Output Port 2 General I/O port 3 also functioning as interrupt inputs, 2 TPU I/Os* , and SSU I/Os 2 P23/ TIOCD3 TIOCC3/ IRQ11-A P23, TIOCC3, TIOCD3, IRQ11-A P22/ TIOCC3 IRQ10-A P22, TIOCC3, IRQ10-A 1 P21/ TIOCA3/ SCS2 IRQ9-A P21, TIOCA3, IRQ9-A 0 P20/ TIOCB3 TIOCA3/ IRQ8-A P20, TIOCA3, TIOCB3, IRQ8-A 7 P37/ TIOCB2 TIOCA2/ TCLKD PO15 P37, TIOCA2, TIOCB2, TCLKD 6 P36/ TIOCA2 PO14 P36, TIOCA2 5 P35/ TIOCB1 TIOCA1/ TCLKC PO13 P35, TIOCA1, TIOCB1, TCLKC 4 P34/ TIOCA1 PO12 P34, TIOCA1 3 P33/ TIOCD0 TIOCC0/ TCLKB PO11 P33, TIOCC0, TIOCD0, TCLKB 2 P32/ TIOCC0 TCLKA PO10 P32, TIOCC0, TCLKA 1 P31/ TIOCB0 TIOCA0 PO9 P31, TIOCA0, TIOCB0 0 P30/ TIOCA0 PO8 P30, TIOCA0 Port 3 General I/O port also functioning 2 as PPG outputs* and TPU I/Os Bit SchmittTrigger 1 Input * Rev. 1.00, 03/04, page 196 of 730 Input Pull-up MOS Function OpenDrain Output Function O Function Port Description Port 4 General I/O port also functioning as A/D converter inputs Port 5 General I/O port also functioning as A/D converter inputs Port 6 General I/O port also functioning as SCI I/Os, interrupt inputs, and HCAN I/Os Port A General I/O port also functioning as SSU I/Os and B output Input Pull-up MOS Function OpenDrain Output Function Bit I/O Input Output SchmittTrigger 1 Input * 7 P47/AN11 6 P46/AN10 5 P45/AN9 4 P44/AN8 3 P43/AN15 2 P42/AN14 1 P41/AN13 0 P40/AN12 7 P57/AN7 6 P56/AN6 5 P55/AN5 4 P54/AN4 3 P53/AN3 2 P52/AN2 1 P51/AN1 0 P50/AN0 6 P66 IRQ14 IRQ14 5 P65 IRQ13/ HRxD IRQ13 4 P64 IRQ12 HTxD IRQ12 O 3 P63 IRQ11-B IRQ11-B 2 P62/SCK4 IRQ10-B IRQ10-B 1 P61 RxD4/ IRQ9-B IRQ9-B 0 P60 IRQ8-B TxD4 IRQ8-B 7 PA7 B 6 PA6 5 PA5 4 PA4 3 PA3/SSO2 2 PA2/SSI2 1 PA1/SSCK2 Only for SSU Rev. 1.00, 03/04, page 197 of 730 Function Port Description Port D General I/O port also functioning as SSU I/Os Port H General I/O port Port J General I/O port also functioning as TPU I/Os Bit I/O Input Output SchmittTrigger 1 Input * 7 PD7/SCS1 6 PD6/SSCK1 5 PD5/SSI1 4 PD4/SSO1 3 PD3/SCS0 2 PD2/SSCK0 1 PD1/SSI0 0 PD0/SSO0 7 PH7 6 PH6 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0 7 PJ7/ TIOCB8 TIOCA8/ TCLKH 6 PJ6/ TIOCA8 5 Input Pull-up MOS Function OpenDrain Output Function O O Only for SSU O PJ7, TIOCA8, TIOCB8, TCLKH O PJ6, TIOCA8 PJ5/ TIOCB7 TIOCA7/ TCLKG PJ5, TIOCA7, TIOCB7, TCLKG 4 PJ4/ TIOCA7 PJ4, TIOCA7 3 PJ3/ TIOCD6 TIOCC6/ TCLKF PJ3, TIOCC6, TIOCD6, TCLKF 2 PJ2/ TIOCC6 TCLKE PJ2, TIOCC6, TCLKE Rev. 1.00, 03/04, page 198 of 730 Function Port Description Port J General I/O port also functioning as TPU I/Os Port K General I/O port also functioning as TPU I/Os SchmittTrigger 1 Input * Input Pull-up MOS Function OpenDrain Output Function O Bit I/O Input Output 1 PJ1/ TIOCB6 TIOCA6 PJ1, TIOCA6, TIOCB6 0 PJ0/ TIOCA6 PJ0, TIOCA6 7 PK7/ TIOCB11 TIOCA11 O PK7, TIOCA11, TIOCB11 6 PK6/ TIOCA11 PK6, TIOCA11 5 PK5/ TIOCB10 TIOCA10 PK5, TIOCA10, TIOCB10 4 PK4/ TIOCA10 PK4, TIOCA10 3 PK3/ TIOCD9 TIOCC9 PK3, TIOCC9, TIOCD9 2 PK2/ TIOCC9 PK2, TIOCC9 1 PK1/ TIOCB9 TIOCA9 PK1, TIOCA9, TIOCB9 0 PK0/ TIOCA9 PK0, TIOCA9 Notes: 1. Pins without Schmitt-trigger input buffer have CMOS input buffer. 2. Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 199 of 730 8.1 Register Descriptions Table 8.2 lists each port registers. Table 8.2 Register Configuration in Each Port Registers Number of Pins DDR DR PORT ICR PCR ODR PHRTIDR 8 O O O O Port 2* 4 O O O O O Port 3 8 O O O O Port 4 8 O O Port Port 1 1 8 O O 2 7 O O O O Port A* 3 7 O O O O Port D 8 O O O O O Port H 8 O O O O O O Port J 8 O O O O O Port K 8 O O O O O Port 5 Port 6* [Legend] O: Register exists : No register exists Notes: 1. The lower four bits are valid and the upper four bits are reserved. The write value should always be the initial value. 2. The lower seven bits are valid and the upper one bit is reserved. The write value should always be the initial value. 3. The upper seven bits are valid and the lower one bit is reserved. The write value should always be the initial value. Rev. 1.00, 03/04, page 200 of 730 Figure 8.1 is a port block diagram. Address output Data output On-chip peripheral module output R Q PCR S CK WPCR RPCR R Q DDR S CK WDDR On-chip peripheral module output enable On-chip peripheral module output signal 1 R Q DR S 0 CK WDR Internal bus R Q ODR S CK WODR RODR RDR 1 RPOR 0 To on-chip Peripheral module Input buffer RPOR R Q ICR S CK WICR [Legend] WDDR: WDR: WICR: WPCR: WODR: DDR write DR write ICR write PCR write ODR write RDR: RPOR: RICR: RPCR: RODR: DR write PORT write ICR write PCR write ODR write RICR Figure 8.1 Port Block Diagram Rev. 1.00, 03/04, page 201 of 730 8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, D, H, J, and K) DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. 7 6 5 4 3 2 1 0 Pn7DDR Pn6DDR Pn5DDR Pn4DDR Pn3DDR Pn2DDR Pn1DDR Pn0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Bit Bit Name Note: 8.1.2 The lower four bits are valid and the upper four bits are reserved for port 2 data direction register (P2DDR). The lower seven bits are valid and the upper one bit is reserved for port 6 data direction register (P6DDR). The upper seven bits are valid and the lower one bit is reserved for port A data direction register (PADDR). Data Register (PnDR) (n = 1 to 3, 6, A, D, H, J, and K) DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00. Bit Bit Name Initial Value R/W Note: 7 6 5 4 3 2 1 0 Pn7DR Pn6DR Pn5DR Pn4DR Pn3DR Pn2DR Pn1DR Pn0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The lower four bits are valid and the upper four bits are reserved for port 2 data register (P2DR). The lower seven bits are valid and the upper one bit is reserved for port 6 data register (P6DR). The upper seven bits are valid and the lower one bit is reserved for port A data register (PADR). Rev. 1.00, 03/04, page 202 of 730 8.1.3 Port Register (PORTn) (n = 1 to 6, A, D, H, J, and K) PORT is an 8-bit read-only register that reflects the port pin status. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin status. Bit Bit Name Initial Value R/W Note: 8.1.4 7 6 5 4 3 2 1 0 Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R The lower four bits are valid and the upper four bits are reserved for port 2 register (PORT2). The lower seven bits are valid and the upper one bit is reserved for port 6 register (PORT6). The upper seven bits are valid and the lower one bit is reserved for port A register (PORTA). Input Buffer Control Register (PnICR) (n = 1 to 6, A, D, H, J, and K) ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin status is always read regardless of the ICR value. On-chip modules are not affected by the pin status when the ICR value is cleared to 0. If ICR is modified, an internal edge may occur depending on the pin status. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, in IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00. Rev. 1.00, 03/04, page 203 of 730 Bit Bit Name Initial Value R/W Note: 7 6 5 4 3 2 1 0 Pn7ICR Pn6ICR Pn5ICR Pn4ICR Pn3ICR Pn2ICR Pn1ICR Pn0ICR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The lower four bits are valid and the upper four bits are reserved for port 2 input buffer control register (P2ICR). The lower seven bits are valid and the upper one bit is reserved for port 6 input buffer control register (P6ICR). The upper seven bits are valid and the lower one bit is reserved for port A input buffer control register (PAICR). 8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D, H, J, and K) PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 8.3 shows the input pull-up MOS status. The initial value of PCR is H'00. Bit Bit Name Initial Value R/W Table 8.3 7 6 5 4 3 2 1 0 Pn7PCR Pn6PCR Pn5PCR Pn4PCR Pn3PCR Pn2PCR Pn1PCR Pn0PCR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Input Pull-Up MOS State Port Pin State Reset Software Standby Mode Other Operation Port D On-chip peripheral module output OFF OFF OFF Port input OFF OFF ON/OFF Port H Port J Port K Port output OFF OFF OFF Port input OFF OFF ON/OFF On-chip peripheral module output OFF OFF OFF Port input OFF OFF ON/OFF On-chip peripheral module output OFF OFF OFF Port input OFF OFF ON/OFF [Legend] OFF: ON/OFF: The input pull-up MOS is always off. If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off. Rev. 1.00, 03/04, page 204 of 730 8.1.6 Open-Drain Control Register (PnODR) (n = 2) ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00. Bit Bit Name Initial Value R/W Note: 8.1.7 7 6 5 4 3 2 1 0 Pn7ODR Pn6ODR Pn5ODR Pn4ODR Pn3ODR Pn2ODR Pn1ODR Pn0ODR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The lower four bits are valid and the upper four bits are reserved for port 2 open drain control register (P2ODR). Port H Realtime Input Data Register (PHRTIDR) PHRTIDR stores the status of port H using pin IRQ14 as a trigger. The detection method is specified by the IRQ14SR and IRQ14SF bits in the IRQ sense control register H (ISCRH) and is selected from a low level, a falling edge, a rising edge of pin, and both edges of pin IRQ14. For details, see section 5.3.5, IRQ Sense Control Registers H and L (ISCRH and ISCRL). Bit Bit Name 7 6 5 4 3 2 1 0 PHRTIDR7 PHRTIDR6 PHRTIDR5 PHRTIDR4 PHRTIDR3 PHRTIDR2 PHRTIDR1 PHRTIDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Rev. 1.00, 03/04, page 205 of 730 8.2 Output Buffer Control This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: MIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 8.4 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 8.3.3, Port Function Control Register B (PFCRB). 8.2.1 Port 1 P17/ADTRG1/IRQ7: The pin function is switched as shown below according to the P17DDR bit setting. Setting I/O Port Module Name Pin Function P17DDR I/O port P17 output 1 P17 input (initial setting) 0 P16/SCK3/IRQ6: The pin function is switched as shown below according to the combination of the SCI_3 and P16DDR bit settings. Setting SCI_3 I/O Port Module Name Pin Function SCK3_OE P16DDR SCI_3 SCK3 output 1 I/O port P16 output 0 1 P16 input (initial setting) 0 0 Rev. 1.00, 03/04, page 206 of 730 P15/RxD3/IRQ5: The pin function is switched as shown below according to the P15DDR bit setting. Setting I/O Port Module Name Pin Function P15DDR I/O port P15 output 1 P15 input (initial setting) 0 P14/TxD3/IRQ4: The pin function is switched as shown below according to the combination of the SCI_3 and P14DDR bit settings. Setting Module Name Pin Function SCI_4 I/O Port TxD3_OE P14DDR SCI_3 TxD3 output 1 I/O port P14 output 0 1 P14 input (initial setting) 0 0 P13/ADTRG0/IRQ3: The pin function is switched as shown below according to the P13DDR bit setting. Setting I/O Port Module Name Pin Function P13DDR I/O port P13 output 1 P13 input (initial setting) 0 P12/IRQ2: The pin function is switched as shown below according to the P12DDR bit setting. Setting I/O Port Module Name Pin Function P12DDR I/O port P12 output 1 P12 input (initial setting) 0 Rev. 1.00, 03/04, page 207 of 730 P11/IRQ1: The pin function is switched as shown below according to the P11DDR bit setting. Setting I/O Port Module Name Pin Function P11DDR I/O port P11 output 1 P11 input (initial setting) 0 P10/IRQ0: The pin function is switched as shown below according to the P10DDR bit setting. Setting I/O Port Module Name Pin Function P10DDR I/O port P10 output 1 P10 input (initial setting) 0 8.2.2 Port 2 P23/TIOCC3/TIOCD3/IRQ11-A: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P23DDR bit settings. Setting TPU_3* I/O Port Module Name Pin Function TIOCD3_OE P23DDR TPU_3* TIOCD3 output 1 I/O port P23 output 0 1 P23 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 208 of 730 P22/TIOCC3/IRQ10-A: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P22DDR bit settings. Setting TPU_3* I/O Port Module Name Pin Function TIOCD3_OE P22DDR TPU_3* TIOCC3 output 1 I/O port P22 output 0 1 P22 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527. P21/TIOCA3/IRQ9-A/SCS2: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), SSU_2, TPU_3, and P21DDR bit settings. Setting SSU_2 TPU_3* I/O Port Module Name Pin Function SCS2_OE TIOCA3_OE P21DDR SSU_2 SCS2 output 1 TPU_3* TIOCA3 output 0 1 I/O port P21 output 0 0 1 P21 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. P20/TIOCA3/TIOCB3/IRQ8-A: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_3, and P20DDR bit settings. Setting TPU_3* I/O Port Module Name Pin Function TIOCB3_OE P20DDR TPU_3* TIOCB3 output 1 I/O port P20 output 0 1 P20 input (initial setting) 0 0 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 209 of 730 8.2.3 Port 3 P37/PO15/TIOCA2/TIOCB2/TCLKD: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P37DDR bit settings. Setting TPU_2* PPG* I/O Port Module Name Pin Function TIOCB2_OE PO15_OE P37DDR TPU_2* TIOCB2 output 1 PPG* PO15 output 0 1 I/O port P37 output 0 0 1 P37 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. P36/PO14/TIOCA2: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_2, PPG, and P36DDR bit settings. Setting TPU_2* PPG* I/O Port Module Name Pin Function TIOCA2_OE PO14_OE P36DDR TPU_2* TIOCA2 output 1 PPG* PO14 output 0 1 I/O port P36 output 0 0 1 P36 input (initial setting) 0 0 0 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 210 of 730 P35/PO13/TIOCA1/TIOCB1/TCLKC: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P35DDR bit settings. Setting TPU_1* PPG* I/O Port Module Name Pin Function TIOCB1_OE PO13_OE P35DDR TPU_1* PPG* I/O port TIOCB1 output PO13 output P35 output P35 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. P34/PO12/TIOCA1: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_1, PPG, and P34DDR bit settings. Setting TPU_1* PPG* I/O Port Module Name Pin Function TIOCA1_OE PO12_OE P34DDR TPU_1* PPG* I/O port TIOCA1 output PO12 output P34 output P34 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. P33/PO11/TIOCC0/TIOCD0/TCLKB: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P33DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCD0_OE PO11_OE P33DDR TPU_0* PPG* I/O port TIOCD0 output PO11 output P33 output P33 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 211 of 730 P32/PO10/TIOCC0/TCLKA: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P32DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCC0_OE PO10_OE P32DDR TPU_0* PPG* I/O port TIOCC0 output PO10 output P32 output P32 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. P31/PO9/TIOCA0/TIOCB0: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P31DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCB0_OE PO9_OE P31DDR TPU_0* PPG* I/O port TIOCB0 output PO9 output P31 output P31 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. P30/PO8/TIOCA0: The pin function is switched as shown below according to the combination of the port function control register 9 (PFCR9), TPU_0, PPG, and P30DDR bit settings. Setting TPU_0* PPG* I/O Port Module Name Pin Function TIOCA0_OE PO8_OE P30DDR TPU_0* PPG* I/O port TIOCA0 output PO8 output P30 output P30 input (initial setting) 1 0 0 0 1 0 0 1 0 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 212 of 730 8.2.4 Port 6 P66/IRQ14: The pin function is switched as shown below according to the P66DDR bit setting. Setting I/O Port Module Name Pin Function P66DDR I/O port P66 output 1 P66 input (initial setting) 0 P65/IRQ13/HRxD: The pin function is switched as shown below according to the P65DDR bit setting. Setting I/O Port Module Name Pin Function P65DDR I/O port P65 output 1 P65 input (initial setting) 0 P64/IRQ12/HTxD: The pin function is switched as shown below according to the combination of the HCAN and P64DDR bit settings. Setting HCAN I/O Port Module Name Pin Function HTxD_OE P64DDR HCAN HTxD output 1 I/O port P64 output 0 1 P64 input (initial setting) 0 0 P63/IRQ11-B: The pin function is switched as shown below according to the P63DDR bit setting. Setting I/O Port Module Name Pin Function P63DDR I/O port P63 output 1 P63 input (initial setting) 0 Rev. 1.00, 03/04, page 213 of 730 P62/SCK4/IRQ10-B: The pin function is switched as shown below according to the combination of the SCI_4 and P62DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function SCK4_OE P62DDR SCI_4 SCK4 output 1 I/O port P62 output 0 1 P62 input (initial setting) 0 0 P61/RxD4/IRQ9-B: The pin function is switched as shown below according to the P61DDR bit setting. Setting I/O Port Module Name Pin Function P61DDR I/O port P61 output 1 P61 input (initial setting) 0 P60/TxD4/IRQ8-B: The pin function is switched as shown below according to the combination of the SCI_4 and P60DDR bit settings. Setting SCI_4 I/O Port Module Name Pin Function TxD4_OE P60DDR SCI_4 TxD4 output 1 I/O port P60 output 0 1 P60 input (initial setting) 0 0 Rev. 1.00, 03/04, page 214 of 730 8.2.5 Port A PA7: The pin function is switched as shown below according to the PA7DDR bit setting. Setting I/O Port Module Name Pin Function PA7DDR I/O port B output 1 PA7 input (initial setting) 0 PA6: The pin function is switched as shown below according to the PA6DDR bit setting. Setting I/O Port Module Name Pin Function PA6DDR I/O port PA6 output 1 PA6 input (initial setting) 0 PA5: The pin function is switched as shown below according to the PA5DDR bit setting. Setting I/O Port Module Name Pin Function PA5DDR I/O port PA5 output 1 PA5 input (initial setting) 0 PA4: The pin function is switched as shown below according to the PA4DDR bit setting. Setting I/O Port Module Name Pin Function PA4DDR I/O port PA4 output 1 PA4 input (initial setting) 0 Rev. 1.00, 03/04, page 215 of 730 PA3/SSO2: The pin function is switched as shown below according to the combination of the SSU_2 and the PA3DDR bit settings. Setting SSU_2 Module Name Pin Function SSO2_OE PA3DDR SSU_2 SSO2 output 1 I/O port PA3 output 0 1 PA3 input (initial setting) 0 0 PA2/SSI2: The pin function is switched as shown below according to the combination of the SSU_2 and the PA2DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SSI2_OE PA2DDR SSU_2 SSI2 output 1 I/O port PA2 output 0 1 PA2 input (initial setting) 0 0 PA1/SSCK2: The pin function is switched as shown below according to the combination of the SSU_2 and the PA1DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SSCK2_OE PA1DDR SSU_2 SSCK2 output 1 I/O port PA1 output 0 1 PA1 input (initial setting) 0 0 Rev. 1.00, 03/04, page 216 of 730 8.2.6 Port D PD7/SCS1: The pin function is switched as shown below according to the combination of the SSU_1 and the PD7DDR bit settings. Setting SSU_2 I/O Port Module Name Pin Function SCS1_OE PD7DDR SSU_1 SCS1 output 1 I/O port PD7 output 0 1 PD7 input (initial setting) 0 0 PD6/SSCK1: The pin function is switched as shown below according to the combination of the SSU_1 and the PD6DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSCK1_OE PD6DDR SSU_1 SSCK1 output 1 I/O port PD6 output 0 1 PD6 input (initial setting) 0 0 PD5/SSI1: The pin function is switched as shown below according to the combination of the SSU_1 and the PD5DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSI1_OE PD5DDR SSU_1 SSI1 output 1 I/O port PD5 output 0 1 PD5 input (initial setting) 0 0 Rev. 1.00, 03/04, page 217 of 730 PD4/SSO1: The pin function is switched as shown below according to the combination of the SSU_1 and the PD4DDR bit settings. Setting SSU_1 I/O Port Module Name Pin Function SSO1_OE PD4DDR SSU_1 SSO1 output 1 I/O port PD4 output 0 1 PD4 input (initial setting) 0 0 PD3/SCS0: The pin function is switched as shown below according to the combination of the SSU_0 and the PD3DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SCS0_OE PD3DDR SSU_0 SCS0 output 1 I/O port PD3 output 0 1 PD3 input (initial setting) 0 0 PD2/SSCK0: The pin function is switched as shown below according to the combination of the SSU_0 and the PD2DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSCK0_OE PD2DDR SSU_0 SSCK0 output 1 I/O port PD2 output 0 1 PD2 input (initial setting) 0 0 Rev. 1.00, 03/04, page 218 of 730 PD1/SSI0: The pin function is switched as shown below according to the combination of the SSU_0 and the PD1DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSI0_OE PD1DDR SSU_0 SSI0 output 1 I/O port PD1 output 0 1 PD1 input (initial setting) 0 0 PD0/SSO0: The pin function is switched as shown below according to the combination of the SSU_0 and the PD0DDR bit settings. Setting SSU_0 I/O Port Module Name Pin Function SSO0_OE PD0DDR SSU_0 SSO0 output 1 I/O port PD0 output 0 1 PD0 input (initial setting) 0 0 8.2.7 Port H PH7, PH6, PH5, PH4, PH3, PH2, PH1, and PH0: Port H functions as an 8-bit I/O port and also functions as a realtime input port. Using port H as the realtime input port, the pin status of port H is stored in PHRTIDR by the following triggers: a low level, a falling edge, a rising edge, or both edges of pin IRQ14. The pin function is switched as shown below according to the PHnDDR bit setting. Setting I/O Port Module Name Pin Function PHnDDR I/O port PHn output 1 PHn input (initial setting) 0 [Legend] n = 7 to 0 Rev. 1.00, 03/04, page 219 of 730 8.2.8 Port J PJ7/TIOCA8/TIOCB8/TCLKH: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ7DDR bit settings. Setting TPU_8 I/O Port Module Name Pin Function TIOCB8_OE PJ7DDR TPU_8 I/O port TIOCB8 output PJ7 output PJ7 input (initial setting) 1 0 0 1 0 PJ6/TIOCA8: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_8, and PJ6DDR bit settings. Setting TPU_8 I/O Port Module Name Pin Function TIOCA8_OE PJ6DDR TPU_8 TIOCA8 output 1 I/O port PJ6 output PJ6 input (initial setting) 0 0 1 0 PJ5/TIOCA7/TIOCB7/TCLKG: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ5DDR bit settings. Setting TPU_7 I/O Port Module Name Pin Function TIOCB7_OE PJ5DDR TPU_7 I/O port TIOCB7 output PJ5 output PJ5 input (initial setting) 1 0 0 1 0 Rev. 1.00, 03/04, page 220 of 730 PJ4/TIOCA7: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_7, and PJ4DDR bit settings. Setting TPU_7 I/O Port Module Name Pin Function TIOCA7_OE PJ4DDR TPU_7 I/O port TIOCA7 output PJ4 output PJ4 input (initial setting) 1 0 0 1 0 PJ3/TIOCC6/TIOCD6/TCLKF: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ3DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCD6_OE PJ3DDR TPU_6 I/O port TIOCD6 output PJ3 output PJ3 input (initial setting) 1 0 0 1 0 PJ2/TIOCC6/TCLKE: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ2DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCC6_OE PJ2DDR TPU_6 I/O port TIOCC6 output PJ2 output PJ2 input (initial setting) 1 0 0 1 0 PJ1/TIOCA6/TIOCB6: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ1DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCB6_OE PJ1DDR TPU_6 I/O port TIOCB6 output PJ1 output PJ1 input (initial setting) 1 0 0 1 0 Rev. 1.00, 03/04, page 221 of 730 PJ0/TIOCA6: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_6, and PJ0DDR bit settings. Setting TPU_6 I/O Port Module Name Pin Function TIOCA6_OE PJ0DDR TPU_6 I/O port TIOCA6 output PJ0 output PJ0 input (initial setting) 1 0 0 1 0 8.2.9 Port K PK7/TIOCA11/TIOCB11: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK7DDR bit settings. Setting TPU_11 I/O Port Module Name Pin Function TIOCB11_OE PK7DDR TPU_11 TIOCB11 output 1 I/O port PK7 output PK7 input (initial setting) 0 0 1 0 PK6/TIOCA11: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_11, and PK6DDR bit settings. Setting TPU_11 I/O Port Module Name Pin Function TIOCA11_OE PK6DDR TPU_11 I/O port TIOCA11 output PK6 output PK6 input (initial setting) 1 0 0 1 0 Rev. 1.00, 03/04, page 222 of 730 PK5/TIOCA10/TIOCB10: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK5DDR bit settings. Setting TPU_10 I/O Port Module Name Pin Function TIOCB10_OE PK5DDR TPU_10 I/O port TIOCB10 output PK5 output PK5 input (initial setting) 1 0 0 1 0 PK4/TIOCA10: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_10, and PK4DDR bit settings. Setting TPU_10 I/O Port Module Name Pin Function TIOCA10_OE PK4DDR TPU_10 I/O port TIOCA10 output PK4 output PK4 input (initial setting) 1 0 0 1 0 PK3/TIOCC9/TIOCD9: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK3DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCD9_OE PK3DDR TPU_9 I/O port TIOCD9 output PK3 output PK3 input (initial setting) 1 0 0 1 0 PK2/TIOCC9: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK2DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCC9_OE PK2DDR TPU_6 I/O port TIOCC9 output PK2 output PK2 input (initial setting) 1 0 0 1 0 Rev. 1.00, 03/04, page 223 of 730 PK1/TIOCA6/TIOCB6: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK1DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCB9_OE PK1DDR TPU_9 I/O port TIOCB9 output PK1 output PK1 input (initial setting) 1 0 0 1 0 PK0/TIOCA9: The pin function is switched as shown below according to the combination of the port function control register A (PFCRA), TPU_9, and PK0DDR bit settings. Setting TPU_9 I/O Port Module Name Pin Function TIOCA9_OE PK0DDR TPU_9 I/O port TIOCA9 output PK0 output PK0 input (initial setting) 1 0 0 1 0 Rev. 1.00, 03/04, page 224 of 730 Table 8.4 Port P1 6 Available Output Signals and Settings in Each Port Output Specification Signal Name Output Signal Name SCK3_OE SCK3 Signal Selection Register Settings Peripheral Module Settings When SCMR_3.SMIF = 1: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR_3.SMIF = 0: SCR_3.TE = 1 or SCR_3.RE = 1 while SMR_3.C/A = 0, SCR_3.CKE [1, 0] = 01 or while SMR_3.C/A = 1, SCR_3.CKE 1 = 0 P2 P3 0 TxD3_OE TxD3 SCR.TE = 1 3 TIOCD3_OE* TIOCD3 TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 2 TIOCC3_OE* TIOCC3 TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 1 SCS2_OE SCS2 SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 0, or SSU.SSCRH_2.CSS1 = 1, SSU.SSCRH_2.CSS0 = 1 while SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1 TIOCA3_OE* TIOCA3 TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 0 TIOCB3_OE* TIOCB3 TPU.TIORH_3.IOB3 = 0, TPU.TIORH_3.IOB[1,0] = 01/10/11 7 TIOCB2_OE* TIOCB2 TPU.TIOR_2.IOB3 = 0, TPU.TIOR_2.IOB[1,0] = 01/10/11 PO15_OE* PO15 NDERH.NDER15 = 1 TPU.TIOR_2.IOA3 = 0, TPU.TIOR_2.IOA[1,0] = 01/10/11 6 5 4 3 2 1 TIOCA2_OE* TIOCA2 PO14_OE* PO14 NDERH.NDER14 = 1 TIOCB1_OE* TIOCB1 TPU.TIOR_1.IOB3 = 0, TPU.TIOR_1.IOB[1,0] = 01/10/11 PO13_OE* PO13 NDERH.NDER13 = 1 TIOCA1_OE* TIOCA1 TPU.TIOR_1.IOA3 = 0, TPU.TIOR_1.IOA[1,0] = 01/10/11 PO12_OE* PO12 NDERH.NDER12 = 1 TIOCD0_OE* TIOCD0 TPU.TMDR_0.BFB = 0, TPU.TIORL_0.IOD3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO11_OE* PO11 NDERH.NDER11 = 1 TIOCC0_OE* TIOCC0 TPU.TMDR_0.BFA = 0, TPU.TIORL_0.IOC3 = 0, TPU.TIORL_0.IOD[1,0] = 01/10/11 PO10_OE* PO10 NDERH.NDER10 = 1 TIOCB0_OE* TIOCB0 TPU.TIORH_0.IOB3 = 0, TPU.TIORH_0.IOB[1,0] = 01/10/11 PO9_OE* PO9 NDERH.NDER9 = 1 Rev. 1.00, 03/04, page 225 of 730 Port Output Specification Signal Name Output Signal Name TIOCA0 Signal Selection Register Settings Peripheral Module Settings P3 0 TIOCA0_OE* TPU.TIORH_0.IOA3 = 0, TPU.TIORH_0.IOA[1,0] = 01/10/11 PO8_OE* PO8 NDERH.NDER8 = 1 P6 4 HTxD_OE HTxD HCAN MBCR.MBCRn = 0, HCAN.TXRP.TXRn = 1 while HCAN.HCANMON.HCANE = 1, HCAN.HCANMON.TxSTP = 0 (n = 1 to 15) 2 SCK4_OE SCK4 When SCMR_4.SMIF = 1: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.GM = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.GM = 1 When SCMR_4.SMIF = 0: SCR_4.TE = 1 or SCR_4.RE = 1 while SMR_4.C/A = 0, SCR_4.CKE [1, 0] = 01 or while SMR_4.C/A = 1, SCR_4.CKE 1 = 0 PA 0 TxD4_OE TxD4 SCR.TE = 1 7 B_OE B PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 0, SCKCR.POSEL1 = 0 3 SSO2_OE SSI02 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 1: SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 or SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_2.TE =1 When SSU.SSCRL_2.SSUMS = 0, SSU.SSCRH_2.MSS = 0: SSU.SSCRH_2.BIDE = 1, SSU.SSER_2.RE = 0, SSU.SSER_1.TE =1 When SSU.SSCRL_2.SSUMS = 1: SSU.SSER_2.TE = 1 2 SSI2_OE SSI2 SSU.SSCRL_2SSUMS = 0, SSU.SSCRH_2.MSS = 0 SSU.SSCRH_2.BIDE = 0, SSU.SSER_2.TE = 1 PD 1 SSCK2_OE SSCK2 7 SCS1_OE SCS1 6 SSCK1_OE SSCK1 SSU.SSCRH_1.MSS = 1, SSU.SSCRH_1.SCKS = 1 5 SSI1_OE SSI1 SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0 SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 Rev. 1.00, 03/04, page 226 of 730 SSU.SSCRH_2.MSS = 1, SSU.SSCRH_2.SCKS = 1 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 Port PD 4 Output Specification Signal Name Output Signal Name SSO1_OE SSO1 Signal Selection Register Settings Peripheral Module Settings When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 1: SSU.SSCRH_1.BIDE = 0, SSU.SSER_1.TE = 1 or SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE =1 When SSU.SSCRL_1.SSUMS = 0, SSU.SSCRH_1.MSS = 0: SSU.SSCRH_1.BIDE = 1, SSU.SSER_1.RE = 0, SSU.SSER_1.TE =1 When SSU.SSCRL_1.SSUMS = 1: SSU.SSER_1.TE = 1 PD 3 SCS0_OE SCS0 SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 0 or SSU.SSCRH_0.CSS1 = 1, SSU.SSCRH_0.CSS0 = 1 while SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1 2 SSCK0_OE SSCK0 SSU.SSCRH_0.MSS = 1, SSU.SSCRH_0.SCKS = 1 1 SSI0_OE SSI0 SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0 SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 0 SSO0_OE SSO0 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 1: SSU.SSCRH_0.BIDE = 0, SSU.SSER_0.TE = 1 or SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE =1 When SSU.SSCRL_0.SSUMS = 0, SSU.SSCRH_0.MSS = 0: SSU.SSCRH_0.BIDE = 1, SSU.SSER_0.RE = 0, SSU.SSER_0.TE =1 When SSU.SSCRL_0.SSUMS = 1: SSU.SSER_0.TE = 1 PJ PK 7 TIOCB8_OE TIOCB8 TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1, 0] = 01/10/11 6 TIOCA8_OE TIOCA8 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1, 0] = 01/10/11 5 TIOCB7_OE TIOCB7 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1, 0] = 01/10/11 4 TIOCA7_OE TIOCA7 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1, 0] = 01/10/11 3 TIOCD6_OE TIOCD6 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 = 0 TPU.TIORL_6.IOD[1, 0] = 01/10/11 2 TIOCC6_OE TIOCC6 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0 TPU.TIORL_6.IOC[1, 0] = 01/10/11 1 TIOCB6_OE TIOCB6 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1, 0] = 01/10/11 0 TIOCA6_OE TIOCA6 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1, 0] = 01/10/11 7 TIOCB11_OE TIOCB11 TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1, 0] = 01/10/11 6 TIOCA11_OE TIOCA11 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1, 0] = 01/10/11 5 TIOCB10_OE TIOCB10 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1, 0] = 01/10/11 Rev. 1.00, 03/04, page 227 of 730 Output Signal Name 4 TIOCA10_OE TIOCA10 TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1, 0] = 01/10/11 3 TIOCD9_OE TIOCD9 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0 TPU.TIORL_9.IOD[1, 0] = 01/10/11 2 TIOCC9_OE TIOCC9 TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0 TPU.TIORL_9.IOC[1, 0] = 01/10/11 1 TIOCB9_OE TIOCB9 TPU.TIOR_9.IOB3 = 0, TPU.TIOR_9.IOB[1, 0] = 01/10/11 TIOCA9_OE TIOCA9 TPU.TIOR_9.IOA3 = 0, TPU.TIOR_9.IOA[1, 0] = 01/10/11 Port PK 0 Note: Signal Selection Register Settings Peripheral Module Settings Output Specification Signal Name * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 228 of 730 8.3 Port Function Controller The port function controller controls the I/O ports. The port function controller incorporates the following registers. * Port function control register 9 (PFCR9)* * Port function control register A (PFCRA) * Port function control register B (PFCRB) Note: * PFCR9 is supported only by the H8SX/1527. 8.3.1 Port Function Control Register 9 (PFCR9) PFCR9 selects the multiple functions for the TPU (unit 0) I/O pins. Bit 7 6 5 4 3 2 1 0 Bit Name - - TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 5 TPUMS3A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA3 function 0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare 4 TPUMS3B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC3 function 0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare Rev. 1.00, 03/04, page 229 of 730 Bit Bit Name Initial Value R/W Description 3 TPUMS2 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA2 function 0: Specifies P36 as output compare output and input capture 1: Specifies P37 as input capture input and P36 as output compare 2 TPUMS1 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA1 function 0: Specifies P34 as output compare output and input capture 1: Specifies P35 as input capture input and P34 as output compare 1 TPUMS0A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA0 function 0: Specifies P30 as output compare output and input capture 1: Specifies P31 as input capture input and P30 as output compare 0 TPUMS0B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC0 function 0: Specifies P32 as output compare output and input capture 1: Specifies P33 as input capture input and P32 as output compare Rev. 1.00, 03/04, page 230 of 730 8.3.2 Port Function Control Register A (PFCRA) PFCRA selects the multiple functions for the TPU (unit 1) I/O pins. 7 6 5 4 3 2 1 0 TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Initial Value Bit Bit Name 7 TPUMS11 0 R/W Description R/W TPU I/O Pin Multiplex Function Select Selects TIOCA11 function 0: Specifies PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare 6 TPUMS10 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA10 function 0: Specifies PK4 as output compare output and input capture 1: Specifies PK5 as input capture input and PK4 as output compare 5 TPUMS9A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA9 function 0: Specifies PK0 as output compare output and input capture 1: Specifies PK1 as input capture input and PK0 as output compare 4 TPUMS9B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC9 function 0: Specifies PK2 as output compare output and input capture 1: Specifies PK3 as input capture input and PK2 as output compare Rev. 1.00, 03/04, page 231 of 730 Bit Bit Name Initial Value R/W Description 3 TPUMS8 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA8 function 0: Specifies PJ6 as output compare output and input capture 1: Specifies PJ7 as input capture input and PJ6 as output compare 2 TPUMS7 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA7 function 0: Specifies PJ4 as output compare output and input capture 1: Specifies PJ5 as input capture input and PJ4 as output compare 1 TPUMS6A 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCA6 function 0: Specifies PJ0 as output compare output and input capture 1: Specifies PJ1 as input capture input and PJ0 as output compare 0 TPUMS6B 0 R/W TPU I/O Pin Multiplex Function Select Selects TIOCC6 function 0: Specifies PJ2 as output compare output and input capture 1: Specifies PJ3 as input capture input and PJ2 as output compare 8.3.3 Port Function Control Register B (PFCRB) PFCRB selects the input pins for IRQ14 to IRQ8. Bit 7 6 5 4 3 2 1 0 Bit Name - ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 232 of 730 Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 6 ITS14 0 R/W IRQ14 Pin Select Selects an input pin for IRQ14. 0: Pin P66 must not be used as IRQ14-A input 1: Pin P66 is used as IRQ14-B input 5 ITS13 0 R/W IRQ13 Pin Select Selects an input pin for IRQ13. 0: Pin P65 must not be used as IRQ13-A input 1: Pin P65 is used as IRQ13-B input 4 ITS12 0 R/W IRQ12 Pin Select Selects an input pin for IRQ12. 0: Pin P64 must not be used as IRQ12-A input 1: Pin P64 is used as IRQ12-B input 3 ITS11 0 R/W IRQ11 Pin Select Selects an input pin for IRQ11. 0: Pin P23 is used as IRQ11-A input 1: Pin P63 is used as IRQ11-B input 2 ITS10 0 R/W IRQ10 Pin Select Selects an input pin for IRQ10. 0: Pin P22 is used as IRQ10-A input 1: Pin P62 is used as IRQ10-B input 1 ITS9 0 R/W IRQ9 Pin Select Selects an input pin for IRQ9. 0: Pin P21 is used as IRQ9-A input 1: Pin P61 is used as IRQ9-B input 0 ITS8 0 R/W IRQ8 Pin Select Selects an input pin for IRQ8. 0: Pin P20 is used as IRQ8-A input 1: Pin P60 is used as IRQ8-B input Rev. 1.00, 03/04, page 233 of 730 8.4 Usage Notes 8.4.1 Notes on Input Buffer Control Register (ICR) Setting * * * When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin states. To change the ICR setting, fix the pin high or disable the input function corresponding to the pin by setting the on-chip module registers. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs of individual modules. Care must be taken for the settings of unused input function on each module side. When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR. 8.4.2 Notes on Port Function Control Register (PFCR) Settings * The PFC controls I/O ports. To specify the function of each pin, specify the input/output destination before enabling the input/output function. * When the input/output destination is changed by the corresponding selection bit, an edge may occur if the previous pin level differs from the pin level after the change. To change the pin direction correctly, follow the procedure shown below. 1. Disable the input function corresponding to the pin by the on-chip module registers. 2. Select the input function by setting PFCR. 3. Enable the input function. * If a pin function has both a selection bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. Rev. 1.00, 03/04, page 234 of 730 Section 9 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU): unit 0 and unit1. Each unit comprises six 16-bit timer channels, that is, there are 12 timer channels in total. However, the H8SX/1525 does not include unit 0. Table 9.1 shows the unit configuration for each product. Table 9.2 is a list of the functions and figure 9.1 is a block diagram for unit 0. Table 9.3 and figure 9.2 are for unit 1. This section describes unit 0, which has the same functions as the other unit. 9.1 Features * Maximum 16-pulse input/output * Selection of eight counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match* Input capture function* Counter clear operation Synchronous operations: * Multiple timer counters (TCNT) can be written to simultaneously * Simultaneous clearing by compare match and input capture possible * Simultaneous input/output for registers possible by counter synchronous operation * Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated (supported only by unit 0) * Conversion start trigger for the A/D converter can be generated (supported only by unit 0) * Module stop mode can be set Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. TIMTPUAA_000020030600 Rev. 1.00, 03/04, page 235 of 730 Table 9.1 Unit Configuration for Each Product Product Unit Configuration Channel Configuration H8SX/1527 Unit 0 Channels 0 to 5 Unit 1 Channels 6 to 11 Unit 1 Channels 6 to 11 H8SX/1525 Note: * The H8SX/1525 does not include unit 0. Rev. 1.00, 03/04, page 236 of 730 Table 9.2 TPU Functions (Unit 0) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKA P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKC P/1 P/4 P/16 P/64 P/256 TCLKA TCLKC TCLKD General registers (TGR) TGRA_0 TGRB_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRC_3 TGRD_3 I/O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4*1 TIOCB4*1 TIOCA5*1 TIOCB5*1 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input 2 capture* TGR compare match or input capture*2 Compare 0 output match 1 output output Toggle output O O O O O*1 O*1 O O O O O*1 O*1 O O O O O* 1 O*1 Input capture function O O O O O*2 O*2 Synchronous operation O O O O O O PWM mode O O O* 1 O*1 O O Phase counting mode O O O O Buffer operation O O DMAC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input 2 capture* TGR compare match or input capture*2 A/D converter trigger TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input 2 capture* TGRA_5 compare match or input capture*2 Rev. 1.00, 03/04, page 237 of 730 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 PPG trigger TGRA_0/ TGRB_0 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture Interrupt sources 5 sources 4 sources 4 sources 5 sources 4 sources 4 sources Compare match or input capture 0A Compare match or input capture 1A Compare match or input capture 2A Compare match or input capture 3A Compare match or input capture 4A Compare match or input capture 5A Compare match or input capture 0B Compare match or input capture 1B Compare match or input capture 2B Compare match or input capture 3B Compare match or input capture 4B Compare match or input capture 5B Overflow Compare Overflow match or Underflow input capture 3C Compare Overflow match or Underflow input capture 0C Underflow Compare match or input capture 0D Compare match or input capture 3D Overflow Overflow Overflow Underflow [Legend] O : Possible : Not possible Notes: 1. The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. 2. The H8SX/1527 does not have the input capture function for channels 4 and 5. Rev. 1.00, 03/04, page 238 of 730 Table 9.3 TPU Functions (Unit 1) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Count clock P/1 P/4 P/16 P/64 TCLKE TCLKF TCLKG TCLKH P/1 P/4 P/16 P/64 P/256 TCLKE TCLKF P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKF TCLKG P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKE P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKG P/1 P/4 P/16 P/64 P/256 TCLKE TCLKG TCLKH General registers (TGR) TGRA_6 TGRB_6 TGRA_7 TGRB_7 TGRA_8 TGRB_8 TGRA_9 TGRB_9 TGRA_10 TGRB_10 TGRA_11 TGRB_11 General registers/ buffer registers TGRC_6 TGRD_6 TGRC_9 TGRD_9 I/O pins TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output O O O O O O O O O O O O O O O O O O Input capture function O O O O O O Synchronous operation O O O O O O PWM mode O O O O O O Phase counting mode O O O O Buffer operation O O DMAC activation TGRA_6 compare match or input capture TGR_7 compare match or input capture TGR_8 compare match or input capture TGR_9 compare match or input capture TGR_10 compare match or input capture TGR_11 compare match or input capture Rev. 1.00, 03/04, page 239 of 730 Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Interrupt sources 5 sources 4 sources 4 sources 5 sources 4 sources Compare match or input capture 6A Compare match or input capture 7A Compare match or input capture 8A Compare match or input capture 9A Compare Compare match or match or input input capture 10A capture 11A Compare match or input capture 6B Compare match or input capture 7B Compare match or input capture 8B Compare match or input capture 9B Compare Compare match or match or input input capture 10B capture 11B Overflow Compare Overflow match or Underflow input capture 9C Compare Overflow match or Underflow input capture 6C Underflow Compare match or input capture 6D Compare match or input capture 9D Overflow Overflow [Legend] O : Possible : Not possible Rev. 1.00, 03/04, page 240 of 730 4 sources Overflow Underflow TGRD TGRB TGRC TGRB Internal data bus A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal TGRC TCNT TCNT TGRA TGRA Bus interface TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TCNT TSR TSR TGRA TIER TIER TIER TSR TIOR TIOR TIORH TIORL TIER: TSR: TGR (A, B, C, D): TCNT: TGRA TSR TIER TSR TIER TSR TSTR TSYR TIER TMDR TIORH TIORL TIOR TIOR Channel 3 TCR TMDR Channel 4 TCR TMDR Channel 5 TCR Control logic TMDR TCR TMDR Channel 1 Channel 0 TCR Common Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TMDR Channel 2 [Legend] TSTR: TSYR: TCR: TMDR: TIOR (H, L): Control logic for channels 0 to 2 Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 TCR Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKA TCLKB TCLKC TCLKD Control logic for channels 3 to 5 Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4* Channel 4: TIOCB4* TIOCA5* Channel 5: TIOCB5* Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. Figure 9.1 Block Diagram of TPU (Unit 0) Rev. 1.00, 03/04, page 241 of 730 TIER: TSR: TGR (A, B, C, D): TCNT: TGRD TGRB TGRC TGRB TGRD TGRB TGRB TGRB Internal data bus TGRC TCNT TCNT TGRA TCNT TGRA TGRA Bus interface TGRB TCNT TCNT TGRA TCNT Module data bus TGRA TGRA TSR TIER TSR TIER TSR TIER TSTRB TSYRB TSR TIER TIER TSR TIOR TIORH TIORL TSR TIER TMDR TIORH TIORL TIOR TIOR TIOR Channel 11 TCR TMDR Channel 10 TCR TMDR Channel 9 TCR Control logic TMDR TCR TMDR Channel 7 Channel 6 TCR Common Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L) TMDR Channel 8 [Legend] TSTRB: TSYRB: TCR: TMDR: TIOR (H, L): Control logic for channels 6 to 8 Input/output pins TIOCA6 Channel 6: TIOCB6 TIOCC6 TIOCD6 TIOCA7 Channel 7: TIOCB7 TIOCA8 Channel 8: TIOCB8 TCR Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKE TCLKF TCLKG TCLKH Control logic for channels 9 to 11 Input/output pins TIOCA9 Channel 9: TIOCB9 TIOCC9 TIOCD9 Channel 10: TIOCA10 TIOCB10 Channel 11: TIOCA11 TIOCB11 Interrupt request signals Channel 6: TGI6A TGI6B TGI6C TGI6D TCI6V Channel 7: TGI7A TGI7B TCI7V TCI7U Channel 8: TGI8A TGI8B TCI8V TCI8U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 9.2 Block Diagram of TPU (Unit 1) Rev. 1.00, 03/04, page 242 of 730 Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U 9.2 Input/Output Pins Table 9.4 shows TPU pin configurations. Table 9.4 Pin Configuration Unit Channel Symbol I/O Function 0 All TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 and 4 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 and 4 phase counting mode B phase input) 0 1 2 3 4 5 TIOCA0 I/O TGRA_0 input capture input/output compare output/PWM output pin TIOCB0 I/O TGRB_0 input capture input/output compare output/PWM output pin TIOCC0 I/O TGRC_0 input capture input/output compare output/PWM output pin TIOCD0 I/O TGRD_0 input capture input/output compare output/PWM output pin TIOCA1 I/O TGRA_1 input capture input/output compare output/PWM output pin TIOCB1 I/O TGRB_1 input capture input/output compare output/PWM output pin TIOCA2 I/O TGRA_2 input capture input/output compare output/PWM output pin TIOCB2 I/O TGRB_2 input capture input/output compare output/PWM output pin TIOCA3 I/O TGRA_3 input capture input/output compare output/PWM output pin TIOCB3 I/O TGRB_3 input capture input/output compare output/PWM output pin TIOCC3 I/O TGRC_3 input capture input/output compare output/PWM output pin TIOCD3 I/O TGRD_3 input capture input/output compare output/PWM output pin TIOCA4* I/O TGRA_4 input capture input/output compare output/PWM output pin TIOCB4* I/O TGRB_4 input capture input/output compare output/PWM output pin TIOCA5* I/O TGRA_5 input capture input/output compare output/PWM output pin TIOCB5* I/O TGRB_5 input capture input/output compare output/PWM output pin Rev. 1.00, 03/04, page 243 of 730 Unit Channel Symbol I/O Function 1 All TCLKE Input External clock A input pin (Channel 7 and 11 phase counting mode A phase input) TCLKF Input External clock B input pin (Channel 7 and 11 phase counting mode B phase input) TCLKG Input External clock C input pin (Channel 8 and 10 phase counting mode A phase input) TCLKH Input External clock D input pin TIOCA6 I/O TGRA_6 input capture input/output compare output/PWM output pin TIOCB6 I/O TGRB_6 input capture input/output compare output/PWM output pin TIOCC6 I/O TGRC_6 input capture input/output compare output/PWM output pin TIOCD6 I/O TGRD_6 input capture input/output compare output/PWM output pin TIOCA7 I/O TGRA_7 input capture input/output compare output/PWM output pin TIOCB7 I/O TGRB_7 input capture input/output compare output/PWM output pin TIOCA8 I/O TGRA_8 input capture input/output compare output/PWM output pin TIOCB8 I/O TGRB_8 input capture input/output compare output/PWM output pin TIOCA9 I/O TGRA_9 input capture input/output compare output/PWM output pin TIOCB9 I/O TGRB_9 input capture input/output compare output/PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/PWM output pin TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM output pin TIOCB10 I/O TGRB_10 input capture input/output compare output/PWM output pin TIOCA11 I/O TGRA_11 input capture input/output compare output/PWM output pin TIOCB11 I/O TGRB_11 input capture input/output compare output/PWM output pin (Channel 8 and 10 phase counting mode B phase input) 6 7 8 9 10 11 Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Rev. 1.00, 03/04, page 244 of 730 9.3 Register Descriptions The TPU has the following registers in each channel. The registers for unit 0 and unit 1 have the same functions except bit 7 (TTGE bit for unit 0 and reserved bit for unit 1) in TIER. This section describes unit 0 registers. * Unit 0 Channel 0: Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Channel 1: Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Channel 2: Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Rev. 1.00, 03/04, page 245 of 730 Channel 3: Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Channel 4: Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) Channel 5: Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) Common Registers Timer start register (TSTR) Timer synchronous register (TSYR) Rev. 1.00, 03/04, page 246 of 730 * Unit 1 Channel 6: Timer control register_6 (TCR_6) Timer mode register_6 (TMDR_6) Timer I/O control register H_6 (TIORH_6) Timer I/O control register L_6 (TIORL_6) Timer interrupt enable register_6 (TIER_6) Timer status register_6 (TSR_6) Timer counter_6 (TCNT_6) Timer general register A_6 (TGRA_6) Timer general register B_6 (TGRB_6) Timer general register C_6 (TGRC_6) Timer general register D_6 (TGRD_6) Channel 7: Timer control register_7 (TCR_7) Timer mode register_7 (TMDR_7) Timer I/O control register _7 (TIOR_7) Timer interrupt enable register_7 (TIER_7) Timer status register_7 (TSR_7) Timer counter_7 (TCNT_7) Timer general register A_7 (TGRA_7) Timer general register B_7 (TGRB_7) Channel 8: Timer control register_8 (TCR_8) Timer mode register_8 (TMDR_8) Timer I/O control register_8 (TIOR_8) Timer interrupt enable register_8 (TIER_8) Timer status register_8 (TSR_8) Timer counter_8 (TCNT_8) Timer general register A_8 (TGRA_8) Timer general register B_8 (TGRB_8) Rev. 1.00, 03/04, page 247 of 730 Channel 9: Timer control register_9 (TCR_9) Timer mode register_9 (TMDR_9) Timer I/O control register H_9 (TIORH_9) Timer I/O control register L_9 (TIORL_9) Timer interrupt enable register_9 (TIER_9) Timer status register_9 (TSR_9) Timer counter_9 (TCNT_9) Timer general register A_9 (TGRA_9) Timer general register B_9 (TGRB_9) Timer general register C_9 (TGRC_9) Timer general register D_9 (TGRD_9) Channel 10: Timer control register_10 (TCR_10) Timer mode register_10 (TMDR_10) Timer I/O control register _10 (TIOR_10) Timer interrupt enable register_10 (TIER_10) Timer status register_10 (TSR_10) Timer counter_10 (TCNT_10) Timer general register A_10 (TGRA_10) Timer general register B_10 (TGRB_10) Channel 11: Timer control register_11 (TCR_11) Timer mode register_11 (TMDR_11) Timer I/O control register_11 (TIOR_11) Timer interrupt enable register_11 (TIER_11) Timer status register_11 (TSR_11) Timer counter_11 (TCNT_11) Timer general register A_11 (TGRA_11) Timer general register B_11 (TGRB_11) Common Registers Timer start register (TSTRB) Timer synchronous register (TSYRB) Rev. 1.00, 03/04, page 248 of 730 9.3.1 Timer Control Register (TCR) TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 9.5 and 9.6 for details. 4 CKEG1 0 R/W Clock Edge 1 and 0 3 CKEG0 0 R/W These bits select the input clock edge. For details, see table 9.7. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. This setting is ignored if the input clock is P/1, or when overflow/underflow of another channel is selected. 2 TPSC2 0 R/W Timer Prescaler 2 to 0 1 TPSC1 0 R/W 0 TPSC0 0 R/W These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 9.8 to 9.13 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports. Rev. 1.00, 03/04, page 249 of 730 Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0, 3 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 0 TCNT clearing disabled 1 0 1 TCNT cleared by TGRC compare match/input 2 capture* 1 1 0 TCNT cleared by TGRD compare match/input capture*2 1 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) Channel Bit 7*2 Reserved Bit 6 CCLR1 Bit 5 CCLR0 Description 1, 2, 4, 5 0 0 0 TCNT clearing disabled 0 0 1 TCNT cleared by TGRA compare match/input capture 0 1 0 TCNT cleared by TGRB compare match/input capture 0 1 1 TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is a read-only bit and cannot be modified. Rev. 1.00, 03/04, page 250 of 730 Table 9.7 Input Clock Edge Selection Clock Edge Selection Input Clock CKEG1 CKEG0 Internal Clock External Clock 0 0 Counted at falling edge Counted at rising edge 0 1 Counted at rising edge Counted at falling edge 1 X Counted at both edges Counted at both edges [Legend] X: Don't care Table 9.8 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 External clock: counts on TCLKD pin input Table 9.9 TPSC2 to TPSC0 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 Internal clock: counts on P/256 1 1 1 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 1.00, 03/04, page 251 of 730 Table 9.10 TPSC2 to TPSC0 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKB pin input 1 1 0 External clock: counts on TCLKC pin input 1 1 1 Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 9.11 TPSC2 to TPSC0 (Channel 3) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 Internal clock: counts on P/1024 1 1 0 Internal clock: counts on P/256 1 1 1 Internal clock: counts on P/4096 Rev. 1.00, 03/04, page 252 of 730 Table 9.12 TPSC2 to TPSC0 (Channel 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P/1024 1 1 1 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 9.13 TPSC2 to TPSC0 (Channel 5) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock: counts on P/1 0 0 1 Internal clock: counts on P/4 0 1 0 Internal clock: counts on P/16 0 1 1 Internal clock: counts on P/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 External clock: counts on TCLKC pin input 1 1 0 Internal clock: counts on P/256 1 1 1 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 1.00, 03/04, page 253 of 730 9.3.2 Timer Mode Register (TMDR) TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped. Bit 7 6 5 4 3 2 1 0 Bit Name - - BFB BFA MD3 MD2 MD1 MD0 Initial Value 1 1 0 0 0 0 0 0 R/W R R R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W 7, 6 All 1 R Description Reserved These are read-only bits and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is a read-only bit and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 MD3 0 R/W Modes 3 to 0 2 MD2 0 R/W Set the timer operating mode. 1 MD1 0 R/W 0 MD0 0 R/W MD3 is a reserved bit. The write value should always be 0. See table 9.14 for details. Rev. 1.00, 03/04, page 254 of 730 Table 9.14 MD3 to MD0 Bit 3 1 MD3* Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 0 0 0 1 Reserved 0 0 1 0 PWM mode 1 0 0 1 1 PWM mode 2 0 1 0 0 Phase counting mode 1 0 1 0 1 Phase counting mode 2 0 1 1 0 Phase counting mode 3 0 1 1 1 Phase counting mode 4 1 X X X [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, the write value should always be 0. 9.3.3 Timer I/O Control Register (TIOR) TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports. Note: The H8SX/1527 does not include TIOR_4 and TIOR_5. Rev. 1.00, 03/04, page 255 of 730 * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Bit Bit Name 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value R/W * TIORL_0, TORL_3 Bit Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description 7 IOB3 0 R/W I/O Control B3 to B0 6 IOB2 0 R/W Specify the function of TGRB. 5 IOB1 0 R/W 4 IOB0 0 R/W For details, see tables 9.15, 9.17, 9.18, 9.19, 9.21, and 9.22. 3 IOA3 0 R/W I/O Control A3 to A0 2 IOA2 0 R/W Specify the function of TGRA. 1 IOA1 0 R/W 0 IOA0 0 R/W For details, see tables 9.23, 9.25, 9.26, 9.27, 9.29, and 9.30. * TIORL_0, TIORL_3: Bit Bit Name Initial Value R/W Description 7 IOD3 0 R/W I/O Control D3 to D0 6 IOD2 0 R/W Specify the function of TGRD. 5 IOD1 0 R/W For details, see tables 9.16, and 9.20. 4 IOD0 0 R/W 3 IOC3 0 R/W I/O Control C3 to C0 2 IOC2 0 R/W Specify the function of TGRC. 1 IOC1 0 R/W For details, see tables 9.24, and 9.28. 0 IOC0 0 R/W Rev. 1.00, 03/04, page 256 of 730 Table 9.15 TIORH_0 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_0 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCB0 pin Input capture at rising edge Capture input source is TIOCB0 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB0 pin Input capture at both edges 1 1 x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 1.00, 03/04, page 257 of 730 Table 9.16 TIORL_0 Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_0 Function 0 0 0 0 0 0 0 1 Output compare register*2 0 0 1 0 TIOCD0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register*2 Capture input source is TIOCD0 pin Input capture at rising edge Capture input source is TIOCD0 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCD0 pin Input capture at both edges 1 1 X X Capture input source is channel 1/count clock 1 Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00, 03/04, page 258 of 730 Table 9.17 TIOR_1 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_1 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCB1 pin Input capture at rising edge Capture input source is TIOCB1 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCB1 pin Input capture at both edges 1 1 X X TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Rev. 1.00, 03/04, page 259 of 730 Table 9.18 TIOR_2 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_2 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 X 0 0 Initial output is 1 output Toggle output at compare match 1 X 0 1 Input capture register Capture input source is TIOCB2 pin Input capture at rising edge Capture input source is TIOCB2 pin Input capture at falling edge 1 X 1 X Capture input source is TIOCB2 pin Input capture at both edges [Legend] X: Don't care Rev. 1.00, 03/04, page 260 of 730 Table 9.19 TIORH_3 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_3 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCB3 pin Input capture at rising edge Capture input source is TIOCB3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB3 pin Input capture at both edges 1 1 x x Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Note: When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 1.00, 03/04, page 261 of 730 Table 9.20 TIORL_3 Description Bit 7 IOD3 Bit 6 IOD2 Bit 5 IOD1 Bit 4 IOD0 TGRD_3 Function 0 0 0 0 0 0 0 1 Output compare register*2 0 0 1 0 TIOCD3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register*2 Capture input source is TIOCD3 pin Input capture at rising edge Capture input source is TIOCD3 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCD3 pin Input capture at both edges 1 1 x x Capture input source is channel 4/count clock 1 Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00, 03/04, page 262 of 730 Table 9.21 TIOR_4 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_4 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCB4 pin Input capture at rising edge Capture input source is TIOCB4 pin Input capture at falling edge 1 0 1 x Capture input source is TIOCB4 pin Input capture at both edges 1 1 x x Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] X: Don't care Rev. 1.00, 03/04, page 263 of 730 Table 9.22 TIOR_5 Description Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 TGRB_5 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCB5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 x 0 0 Initial output is 1 output Toggle output at compare match 1 x 0 1 Input capture register Capture input source is TIOCB5 pin Input capture at rising edge Capture input source is TIOCB5 pin Input capture at falling edge 1 x 1 x Capture input source is TIOCB5 pin Input capture at both edges [Legend] X: Don't care Rev. 1.00, 03/04, page 264 of 730 Table 9.23 TIORH_0 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_0 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 1 Initial output is 1 output Toggle output at compare match 1 0 0 0 Input capture register Capture input source is TIOCA0 pin Input capture at rising edge Capture input source is TIOCA0 pin Input capture at rising edge 1 0 1 X Capture input source is TIOCA0 pin Input capture at both edges 1 1 X X Capture input source is channel 1/count clock Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated. Rev. 1.00, 03/04, page 265 of 730 Table 9.24 TIORL_0 Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_0 Function 0 0 0 0 0 0 0 1 Output compare register*2 0 0 1 0 TIOCC0 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register*2 Capture input source is TIOCC0 pin Input capture at rising edge Capture input source is TIOCC0 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCC0 pin Input capture at both edges 1 1 X X Capture input source is channel 1/count clock 1 Input capture* at TCNT_1 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00, 03/04, page 266 of 730 Table 9.25 TIOR_1 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_1 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA1 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCA1 pin Input capture at rising edge Capture input source is TIOCA1 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA1 pin Input capture at both edges 1 1 X X Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Rev. 1.00, 03/04, page 267 of 730 Table 9.26 TIOR_2 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_2 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA2 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 X 0 0 Initial output is 1 output Toggle output at compare match 1 X 0 1 Input capture register Capture input source is TIOCA2 pin Input capture at rising edge Capture input source is TIOCA2 pin Input capture at falling edge 1 X 1 X Capture input source is TIOCA2 pin Input capture at both edges [Legend] X: Don't care Rev. 1.00, 03/04, page 268 of 730 Table 9.27 TIORH_3 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_3 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCA3 pin Input capture at rising edge Capture input source is TIOCA3 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA3 pin Input capture at both edges 1 1 X X Capture input source is channel 4/count clock Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated. Rev. 1.00, 03/04, page 269 of 730 Table 9.28 TIORL_3 Description Bit 3 IOC3 Bit 2 IOC2 Bit 1 IOC1 Bit 0 IOC0 TGRC_3 Function 0 0 0 0 0 0 0 1 Output compare register*2 0 0 1 0 TIOCC3 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register*2 Capture input source is TIOCC3 pin Input capture at rising edge Capture input source is TIOCC3 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCC3 pin Input capture at both edges 1 1 X X Capture input source is channel 4/count clock 1 Input capture* at TCNT_4 count-up/count-down [Legend] X: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 counter clock, this setting is ignored and an input capture interrupt is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00, 03/04, page 270 of 730 Table 9.29 TIOR_4 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_4 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA4 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 0 0 0 Initial output is 1 output Toggle output at compare match 1 0 0 1 Input capture register Capture input source is TIOCA4 pin Input capture at rising edge Capture input source is TIOCA4 pin Input capture at falling edge 1 0 1 X Capture input source is TIOCA4 pin Input capture at both edges 1 1 X X Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] X: Don't care Rev. 1.00, 03/04, page 271 of 730 Table 9.30 TIOR_5 Description Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 TGRA_5 Function 0 0 0 0 0 0 0 1 Output compare register 0 0 1 0 TIOCA5 Pin Function Output disabled Initial output is 0 output 0 output at compare match Initial output is 0 output 1 output at compare match 0 0 1 1 Initial output is 0 output Toggle output at compare match 0 1 0 0 0 1 0 1 Output disabled Initial output is 1 output 0 output at compare match 0 1 1 0 Initial output is 1 output 1 output at compare match 0 1 1 1 1 X 0 0 Initial output is 1 output Toggle output at compare match 1 X 0 1 Input capture register Input capture source is TIOCA5 pin Input capture at rising edge Input capture source is TIOCA5 pin Input capture at falling edge 1 X 1 X Input capture source is TIOCA5 pin Input capture at both edges [Legend] X: Don't care Rev. 1.00, 03/04, page 272 of 730 9.3.4 Timer Interrupt Enable Register (TIER) TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name 7 6 5 4 3 2 1 0 TTGE* - TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Initial Value R/W 0 1 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0. Bit Bit Name Initial value R/W Description 7 TTGE* 0 R/W A/D Conversion Start Request Enable Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 1 R Reserved This is a read-only bit and cannot be modified. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled Rev. 1.00, 03/04, page 273 of 730 Bit Bit Name Initial value R/W Description 3 TGIED 0 R/W TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a readonly bit and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled 2 TGIEC 0 R/W TGR Interrupt Enable C Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a readonly bit and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Note: * Bit 7 in TIER for unit 1 is a reserved bit and is always read as 0. The write value should always be 0. Rev. 1.00, 03/04, page 274 of 730 9.3.5 Timer Status Register (TSR) TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel. Bit 7 Bit Name 6 5 4 3 2 1 0 TCFD - TCFU TCFV TGFD TGFC TGFB TGFA Initial Value 1 1 0 0 0 0 0 0 R/W R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 5 to 0, to clear flags. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is a read-only bit and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 1 R Reserved This is a read-only bit and cannot be modified. 5 TCFU 0 R/(W)* Underflow Flag Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is a read-only bit and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When a 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W)* Overflow Flag Status flag that indicates that a TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When a 0 is written to TCFV after reading TCFV = 1 Rev. 1.00, 03/04, page 275 of 730 Bit Bit Name Initial value R/W 3 TGFD 0 R/(W)* Input Capture/Output Compare Flag D Description Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is a readonly bit and cannot be modified. [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register [Clearing conditions] * 2 TGFC 0 When 0 is written to TGFD after reading TGFD = 1 R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is a readonly bit and cannot be modified. [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register [Clearing conditions] * Rev. 1.00, 03/04, page 276 of 730 When 0 is written to TGFC after reading TGFC = 1 Bit Bit Name Initial value R/W 1 TGFB 0 R/(W)* Input Capture/Output Compare Flag B Description Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register [Clearing conditions] * 0 TGFA 0 When 0 is written to TGFB after reading TGFB = 1 R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register [Clearing conditions] Note: * * When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 Only 0 can be written to clear the flag. Rev. 1.00, 03/04, page 277 of 730 9.3.6 Timer Counter (TCNT) TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units. Bit 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 9.3.7 Timer General Register (TGR) TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA-TGRC and TGRB-TGRD. Bit 15 14 13 12 11 10 9 8 Bit Name Initial Value R/W Bit 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W Rev. 1.00, 03/04, page 278 of 730 9.3.8 Timer Start Register (TSTR) TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 5 4 3 2 1 0 Bit Name - - CST5 CST4 CST3 CST2 CST1 CST0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial value R/W Description 7, 6 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 5 CST5 0 R/W Counter Start 5 to 0 4 CST4 0 R/W These bits select operation or stoppage for TCNT. 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped 1: TCNT_5 to TCNT_0 performs count operation Rev. 1.00, 03/04, page 279 of 730 9.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7 6 5 4 3 2 1 0 Bit Name | | SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial value R/W Description 7, 6 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 5 SYNC5 0 R/W Timer Synchronization 5 to 0 4 SYNC4 0 R/W 3 SYNC3 0 R/W These bits select whether operation is independent of or synchronized with other channels. 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_5 to TCNT_0 perform synchronous operation (TCNT synchronous presetting/synchronous clearing is possible) Rev. 1.00, 03/04, page 280 of 730 9.4 Operation 9.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. 1. Example of count operation setting procedure Figure 9.3 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Operation selection Select counter clock [1] Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count [5] <Periodic counter> [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. Free-running counter [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count <Free-running counter> [5] [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 9.3 Example of Counter Operation Setting Procedure Rev. 1.00, 03/04, page 281 of 730 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 9.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 9.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 9.5 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DMAC activation TGF Figure 9.5 Periodic Counter Operation Rev. 1.00, 03/04, page 282 of 730 Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. Note: * The H8SX/1527 does not have pins TIOCA4, TIOCB4, TIOCA5, and TIOCB5 for channels 4 and 5. Therefore, 0-, 1-, or toggle-output waveform and PWM waveform at an input capture input and a compare match cannot be output. 1. Example of setting procedure for waveform output by compare match Figure 9.6 shows an example of the setting procedure for waveform output by a compare match. Output selection [1] Select initial value from 0-output or 1-output, and compare match output value from 0-output, 1-output, or toggle-output, by means of TIOR. The set initial value is output on the TIOC pin until the first compare match occurs. Select waveform output mode [1] Set output timing [2] [2] Set the timing for compare match generation in TGR. Start count [3] [3] Set the CST bit in TSTR to 1 to start the count operation. <Waveform output> Figure 9.6 Example of Setting Procedure for Waveform Output by Compare Match 2. Examples of waveform output operation Figure 9.7 shows an example of 0-output and 1-output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1-output TIOCA TIOCB No change No change 0-output Figure 9.7 Example of 0-Output/1-Output Operation Rev. 1.00, 03/04, page 283 of 730 Figure 9.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA Time H'0000 Toggle-output TIOCB Toggle-output TIOCA Figure 9.8 Example of Toggle Output Operation Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. 1. Example of setting procedure for input capture operation Figure 9.9 shows an example of the setting procedure for input capture operation. Select input capture input [1] [1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). Start count [2] [2] Set the CST bit in TSTR to 1 to start the count operation. Input selection <Input capture operation> Figure 9.9 Example of Setting Procedure for Input Capture Operation Rev. 1.00, 03/04, page 284 of 730 2. Example of input capture operation Figure 9.10 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 9.10 Example of Input Capture Operation Rev. 1.00, 03/04, page 285 of 730 9.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 9.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Set TCNT Synchronous clearing [2] Clearing source generation channel? No Yes <Synchronous presetting> Select counter clearing source [3] Set synchronous counter clearing [4] Start count [5] Start count [5] <Counter clearing> <Synchronous clearing> [1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation. Figure 9.11 Example of Synchronous Operation Setting Procedure Rev. 1.00, 03/04, page 286 of 730 Example of Synchronous Operation: Figure 9.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 9.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 Time H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Figure 9.12 Example of Synchronous Operation Rev. 1.00, 03/04, page 287 of 730 9.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 9.31 shows the register combinations used in buffer operation. Table 9.31 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 3 TGRA_3 TGRC_3 TGRB_3 TGRD_3 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 9.13. Compare match signal Buffer register Timer general register Comparator Figure 9.13 Compare Match Buffer Operation Rev. 1.00, 03/04, page 288 of 730 TCNT * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 9.14. Input capture signal Timer general register Buffer register TCNT Figure 9.14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 9.15 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation Select TGR function [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] <Buffer operation> Figure 9.15 Example of Buffer Operation Setting Procedure Rev. 1.00, 03/04, page 289 of 730 Examples of Buffer Operation: 1. When TGR is an output compare register Figure 9.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 9.4.5, PWM Modes. TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 TGRC_0 H'0200 H'0450 H'0520 Transfer TGRA_0 H'0200 H'0450 TIOCA Figure 9.16 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 9.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 1.00, 03/04, page 290 of 730 TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 TGRA TGRC H'0F07 H'09FB H'0532 H'0F07 Figure 9.17 Example of Buffer Operation (2) 9.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 9.32 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 9.32 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 Channels 4 and 5 TCNT_4 TCNT_5 Rev. 1.00, 03/04, page 291 of 730 Example of Cascaded Operation Setting Procedure: Figure 9.18 shows an example of the setting procedure for cascaded operation. [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation. <Cascaded operation> Figure 9.18 Example of Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 H'03A1 H'03A2 TCNT_2 clock TCNT_2 H'FFFF H'0001 H'0000 TIOCA1, TIOCA2 TGRA_1 H'03A2 TGRA_2 H'0000 Figure 9.19 Example of Cascaded Operation (1) Figure 9.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. Rev. 1.00, 03/04, page 292 of 730 TCLKC TCLKD TCNT_2 FFFD TCNT_1 FFFE FFFF 0000 0000 0001 0002 0001 0000 FFFF 0001 0000 Figure 9.20 Example of Cascaded Operation (2) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronous register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 9.33. Rev. 1.00, 03/04, page 293 of 730 Table 9.33 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 0 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TGRC_0 TIOCB0 TIOCC0 TGRD_0 1 TGRA_1 TIOCD0 TIOCA1 TGRB_1 2 TGRA_2 TGRA_3 TIOCA3 TGRA_4 TIOCC3 TGRA_5 TGRB_5 TIOCC3 TIOCD3 TIOCA4 TGRB_4 5 TIOCA3 TIOCB3 TGRD_3 4 TIOCA2 TIOCB2 TGRB_3 TGRC_3 TIOCA1 TIOCB1 TIOCA2 TGRB_2 3 TIOCC0 TIOCA4 TIOCB4 TIOCA5 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set. Rev. 1.00, 03/04, page 294 of 730 Example of PWM Mode Setting Procedure: Figure 9.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] Select waveform output level [3] Set TGR [4] [3] Use TIOR to designate TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in TGR selected in [2], and set the Set PWM mode [5] duty in the other TGRs. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] <PWM mode> Figure 9.21 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 9.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the duty cycle. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 9.22 Example of PWM Mode Operation (1) Rev. 1.00, 03/04, page 295 of 730 Figure 9.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 9.23 Example of PWM Mode Operation (2) Figure 9.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. Rev. 1.00, 03/04, page 296 of 730 TCNT value TGRB changed TGRA TGRB TGRB changed TGRB changed H'0000 Time 0% duty TIOCA Output does not change when compare matches in cycle register and duty register occur simultaneously TCNT value TGRB changed TGRA TGRB changed TGRB changed TGRB H'0000 Time 100% duty TIOCA Output does not change when compare matches in cycle register and duty register occur simultaneously TCNT value TGRB changed TGRA TGRB changed TGRB TGRB changed Time H'0000 TIOCA 100% duty 0% duty Figure 9.24 Example of PWM Mode Operation (3) Rev. 1.00, 03/04, page 297 of 730 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.34 shows the correspondence between external clock pins and channels. Table 9.34 Clock Input Pins in Phase Counting Mode External Clock Pins Channels A-Phase B-Phase When channel 1 or 5 is set to phase counting mode TCLKA TCLKB When channel 2 or 4 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 9.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] <Phase counting mode> Figure 9.25 Example of Phase Counting Mode Setting Procedure Rev. 1.00, 03/04, page 298 of 730 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 9.26 shows an example of phase counting mode 1 operation, and table 9.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 9.26 Example of Phase Counting Mode 1 Operation Table 9.35 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) High level Operation Up-count Low level Low level High level High level Down-count Low level High level Low level [Legend] : Rising edge : Falling edge Rev. 1.00, 03/04, page 299 of 730 2. Phase counting mode 2 Figure 9.27 shows an example of phase counting mode 2 operation, and table 9.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 9.27 Example of Phase Counting Mode 2 Operation Table 9.36 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 1.00, 03/04, page 300 of 730 High level Don't care Low level Down-count 3. Phase counting mode 3 Figure 9.28 shows an example of phase counting mode 3 operation, and table 9.37 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 9.28 Example of Phase Counting Mode 3 Operation Table 9.37 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation High level Don't care Low level Don't care Low level Don't care High level Up-count High level Down-count Low level Don't care High level Don't care Low level Don't care [Legend] : Rising edge : Falling edge Rev. 1.00, 03/04, page 301 of 730 4. Phase counting mode 4 Figure 9.29 shows an example of phase counting mode 4 operation, and table 9.38 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 9.29 Example of Phase Counting Mode 4 Operation Table 9.38 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count High level Low level Low level Don't care High level High level Down-count Low level High level Don't care Low level [Legend] : Rising edge : Falling edge Phase Counting Mode Application Example: Figure 9.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Rev. 1.00, 03/04, page 302 of 730 Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved. Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) + - TGRC_0 (position control cycle) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 9.30 Phase Counting Mode Application Example Rev. 1.00, 03/04, page 303 of 730 9.5 Interrupt Sources There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 5, Interrupt Controller. Table 9.39 lists the TPU interrupt sources. Table 9.39 TPU Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation 0 TGI0A TGRA_0 input capture/compare match TGFA_0 Possible TGI0B TGRB_0 input capture/compare match TGFB_0 Not possible TGI0C TGRC_0 input capture/compare match TGFC_0 Not possible TGI0D TGRD_0 input capture/compare match TGFD_0 Not possible TCI0V TCNT_0 overflow TCFV_0 Not possible TGI1A TGRA_1 input capture/compare match TGFA_1 Possible TGI1B TGRB_1 input capture/compare match TGFB_1 Not possible TCI1V TCNT_1 overflow TCFV_1 Not possible TCI1U TCNT_1 underflow TCFU_1 Not possible TGI2A TGRA_2 input capture/compare match TGFA_2 Possible TGI2B TGRB_2 input capture/compare match TGFB_2 Not possible 1 2 3 TCI2V TCNT_2 overflow TCFV_2 Not possible TCI2U TCNT_2 underflow TCFU_2 Not possible TGI3A TGRA_3 input capture/compare match TGFA_3 Possible TGI3B TGRB_3 input capture/compare match TGFB_3 Not possible TGI3C TGRC_3 input capture/compare match TGFC_3 Not possible TGI3D TGRD_3 input capture/compare match TGFD_3 Not possible TCI3V TCNT_3 overflow TCFV_3 Not possible Rev. 1.00, 03/04, page 304 of 730 Channel Name Interrupt Source Interrupt Flag DMAC Activation 4 TGRA_4 input capture/compare match TGFA_4 Possible 5 6 7 8 9 10 TGI4A* TGI4B* TGRB_4 input capture/compare match TGFB_4 Not possible TCI4V TCNT_4 overflow TCFV_4 Not possible TCI4U TCNT_4 underflow TCFU_4 Not possible TGI5A* TGRA_5 input capture/compare match TGFA_5 Possible TGI5B* TGRB_5 input capture/compare match TGFB_5 Not possible TCI5V TCNT_5 overflow TCFV_5 Not possible TCI5U TCNT_5 underflow TCFU_5 Not possible TGI6A TGRA_0 input capture/compare match TGFA_0 Possible TGI6B TGRB_0 input capture/compare match TGFB_0 Not possible TGI6C TGRC_0 input capture/compare match TGFC_0 Not possible TGI6D TGRD_0 input capture/compare match TGFD_0 Not possible TCI6V TCNT_0 overflow TCFV_0 Not possible TGI7A TGRA_1 input capture/compare match TGFA_1 Possible TGI7B TGRB_1 input capture/compare match TGFB_1 Not possible TCI7V TCNT_1 overflow TCFV_1 Not possible TCI7U TCNT_1 underflow TCFU_1 Not possible TGI8A TGRA_2 input capture/compare match TGFA_2 Possible TGI8B TGRB_2 input capture/compare match TGFB_2 Not possible TCI8V TCNT_2 overflow TCFV_2 Not possible TCI8U TCNT_2 underflow TCFU_2 Not possible TGI9A TGRA_3 input capture/compare match TGFA_3 Possible TGI9B TGRB_3 input capture/compare match TGFB_3 Not possible TGI9C TGRC_3 input capture/compare match TGFC_3 Not possible TGI9D TGRD_3 input capture/compare match TGFD_3 Not possible TCI9V TCNT_3 overflow TCFV_3 Not possible TGI10A TGRA_4 input capture/compare match TGFA_4 Possible TGI10B TGRB_4 input capture/compare match TGFB_4 Not possible TCI10V TCNT_4 overflow TCFV_4 Not possible TCI10U TCNT_4 underflow TCFU_4 Not possible Rev. 1.00, 03/04, page 305 of 730 Channel Name Interrupt Source Interrupt Flag DMAC Activation 11 TGI11A TGRA_5 input capture/compare match TGFA_5 Possible TGI11B TGRB_5 input capture/compare match TGFB_5 Not possible TCI11V TCNT_5 overflow TCFV_5 Not possible TCI11U TCNT_5 underflow TCFU_5 Not possible Note: 1. This table shows the initial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller. 2. The H8SX/1527 does not have the input capture function for channels 4 and 5. Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 9.6 DMAC Activation The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller (DMAC). A total of six TPU input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. Rev. 1.00, 03/04, page 306 of 730 9.7 A/D Converter Activation The TGRA input capture/compare match for each channel of unit 0 can activate the A/D converter (this function is not available for unit 1). If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. The A/D converter cannot be activated by unit 1. 9.8 Operation Timing 9.8.1 Input/Output Timing TCNT Count Timing: Figure 9.31 shows TCNT count timing in internal clock operation, and figure 9.32 shows TCNT count timing in external clock operation. P Internal clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 9.31 Count Timing in Internal Clock Operation Rev. 1.00, 03/04, page 307 of 730 P External clock Falling edge Rising edge Falling edge TCNT input clock N-1 TCNT N+1 N N+2 Figure 9.32 Count Timing in External Clock Operation Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 9.33 shows output compare output timing. P TCNT input clock TCNT N TGR N N+1 Compare match signal TIOC pin Figure 9.33 Output Compare Output Timing Rev. 1.00, 03/04, page 308 of 730 Input Capture Signal Timing: Figure 9.34 shows input capture signal timing. P Input capture input Input capture signal N TCNT N+1 N+2 N+2 N TGR Figure 9.34 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match/Input Capture: Figure 9.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 9.36 shows the timing when counter clearing by input capture occurrence is specified. P Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 9.35 Counter Clear Timing (Compare Match) Rev. 1.00, 03/04, page 309 of 730 P Input capture signal Counter clear signal N TCNT H'0000 TGR N Figure 9.36 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 9.37 and 9.38 show the timings in buffer operation. P TCNT n n+1 TGRA, TGRB n N TGRC, TGRD N Compare match signal Figure 9.37 Buffer Operation Timing (Compare Match) P Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 9.38 Buffer Operation Timing (Input Capture) Rev. 1.00, 03/04, page 310 of 730 9.8.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 9.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. P TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 9.39 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 9.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. P Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 9.40 TGI Interrupt Timing (Input Capture) Rev. 1.00, 03/04, page 311 of 730 TCFV Flag/TCFU Flag Setting Timing: Figure 9.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 9.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 9.41 TCIV Interrupt Setting Timing P TCNT input clock TCNT (underflow) H'0000 H'FFFF Underflow signal TCFU flag TCIU interrupt Figure 9.42 TCIU Interrupt Setting Timing Rev. 1.00, 03/04, page 312 of 730 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is activated, the flag is cleared automatically. Figure 9.43 shows the timing for status flag clearing by the CPU, and figure 9.44 shows the timing for status flag clearing by the DMAC. TSR write cycle T1 T2 P TSR address Address Write Status flag Interrupt request signal Figure 9.43 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with P after the DMAC transfer has started, as shown in figure 9.44. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DMAC transfers, it will take up to five clock cycles (P) for clearing them, as shown in figure 9.45. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (P) from the beginning of the transfer. DMAC read cycle T1 T2 DMAC write cycle T1 T2 P Source address Address Destination address Status flag Period in which the next transfer request is masked Interrupt request signal Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1) Rev. 1.00, 03/04, page 313 of 730 DMAC read cycle DMAC write cycle P Address Source address Destination address Period in which the next transfer request is masked Status flag Period of flag clearing Interrupt request signal Period of interrupt request signal clearing Figure 9.45 Timing for Status Flag Clearing by DMAC Activation (2) 9.9 Usage Notes 9.9.1 Module Stop Mode Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 9.9.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.46 shows the input clock conditions in phase counting mode. Phase Phase difference difference Overlap Overlap Pulse width Pulse width TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Note: Phase difference, Overlap 1.5 states Pulse width 2.5 states Figure 9.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 1.00, 03/04, page 314 of 730 9.9.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= P (N + 1) f: Counter frequency P: Operating frequency N: TGR set value 9.9.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9.47 shows the timing in this case. TCNT write cycle T1 T2 P Address TCNT address Write Counter clear signal TCNT N H'0000 Figure 9.47 Conflict between TCNT Write and Clear Operations Rev. 1.00, 03/04, page 315 of 730 9.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.48 shows the timing in this case. TCNT write cycle T1 T2 P Address TCNT address Write TCNT input clock TCNT N M TCNT write data Figure 9.48 Conflict between TCNT Write and Increment Operations 9.9.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 9.49shows the timing in this case. TGR write cycle T1 T2 P TGR address Address Write Compare match signal TCNT TGR Disabled N N N+1 M TGR write data Figure 9.49 Conflict between TGR Write and Compare Match Rev. 1.00, 03/04, page 316 of 730 9.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 9.50 shows the timing in this case. TGR write cycle T1 T2 P Buffer register address Address Write Compare match signal Data written to buffer register N Buffer register M TGR M Figure 9.50 Conflict between Buffer Register Write and Compare Match 9.9.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9.51 shows the timing in this case. TGR read cycle T1 T2 P Address TGR address Read Input capture signal TGR X Internal data bus M M Figure 9.51 Conflict between TGR Read and Input Capture Rev. 1.00, 03/04, page 317 of 730 9.9.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9.52 shows the timing in this case. TGR write cycle T1 T2 P Address TGR address Write Input capture signal TCNT M TGR M Figure 9.52 Conflict between TGR Write and Input Capture 9.9.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.53 shows the timing in this case. Rev. 1.00, 03/04, page 318 of 730 Buffer register write cycle T1 T2 P Buffer register address Address Write Input capture signal TCNT N TGR M Buffer register N M Figure 9.53 Conflict between Buffer Register Write and Input Capture 9.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. P TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF flag Disabled TCFV flag Figure 9.54 Conflict between Overflow and Counter Clearing Rev. 1.00, 03/04, page 319 of 730 9.9.12 Conflict between TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9.55 shows the operation timing when there is conflict between TCNT write and overflow. TGR write cycle T1 T2 P Address TCNT address Write TCNT TCNT write data H'FFFF M TCFV flag Figure 9.55 Conflict between TCNT Write and Overflow 9.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 9.9.14 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 1.00, 03/04, page 320 of 730 Section 10 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 and 2) that can operate both simultaneously and independently. Figure 10.1 shows a block diagram of the PPG. 10.1 * * * * * * * Features 8-bit output data Two output groups Selectable output trigger signals Non-overlapping mode Can operate together with the DMA controller (DMAC) Inverted output can be set Module stop mode can be set Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH PODRL NDRL Pulse output pins, group 2 Internal data bus Pulse output pins, group 1 Pulse output pins, group 0 [Legend] PMR: PCR: NDERH: NDERL: PPG output mode register PPG output control register Next data enable register H Next data enable register L NDRH: NDRL: PODRH: PODRL: Next data register H Next data register L Output data register H Output data register L Figure 10.1 Block Diagram of PPG PPGX000A_000020030600 Rev. 1.00, 03/04, page 321 of 730 10.2 Input/Output Pins Table 10.1 shows the PPG pin configuration. Table 10.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output 10.3 Group 2 pulse output Register Descriptions The PPG has the following registers. * * * * * * * * Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) 10.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH and NDERL enable/disable pulse output on a bit-by-bit basis. * NDERH Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 322 of 730 * NDERL Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * NDERH Bit Bit Name Initial Value R/W Description 7 NDER15 0 R/W Next Data Enable 15 to 8 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W When a bit is set to 1, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. 3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W * NDERL Bit Bit Name Initial Value R/W Description 7 NDER7 0 R/W Next Data Enable 7 to 0 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W Rev. 1.00, 03/04, page 323 of 730 10.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W * PODRL Bit Bit Name Initial Value R/W * PODRH Bit Bit Name Initial Value R/W Description 7 POD15 0 R/W Output Data Register 15 to 8 6 POD14 0 R/W 5 POD13 0 R/W 4 POD12 0 R/W 3 POD11 0 R/W For bits which have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. 2 POD10 0 R/W 1 POD9 0 R/W 0 POD8 0 R/W Rev. 1.00, 03/04, page 324 of 730 * PODRL Bit Bit Name Initial Value R/W Description 7 POD7 0 R/W Output Data Register 7 to 0 6 POD6 0 R/W 5 POD5 0 R/W 4 POD4 0 R/W 3 POD3 0 R/W For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. 2 POD2 0 R/W 1 POD1 0 R/W 0 POD0 0 R/W 10.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * NDRL Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 325 of 730 * NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 8 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W If pulse output groups 2 and 3 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 12 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0 All 1 R Reserved These are read-only bits and cannot be modified. Bit Bit Name Initial Value R/W 7 to 4 All 1 R Description Reserved These are read-only bits and cannot be modified. 3 NDR11 0 R/W Next Data Register 11 to 8 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Rev. 1.00, 03/04, page 326 of 730 * NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 0 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below. Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 4 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0 All 1 R Reserved These are read-only bits and cannot be modified. Bit Bit Name Initial Value R/W 7 to 4 All 1 R Description Reserved These are read-only bits and cannot be modified. 3 NDR3 0 R/W Next Data Register 3 to 0 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 1.00, 03/04, page 327 of 730 10.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 10.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 - - - - 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 G3CMS1 1 R/W Group 3 Compare Match Select 1 and 0 6 G3CMS0 1 R/W These bits select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 G2CMS1 1 R/W Group 2 Compare Match Select 1 and 0 4 G2CMS0 1 R/W These bits select output trigger of pulse output group 2. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 3 to 0 All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 10.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 10.4.4, Non-Overlapping Pulse Output. Rev. 1.00, 03/04, page 328 of 730 7 6 5 4 3 2 1 0 G3INV G2INV - - G3NOV G2NOV - - Bit Bit Name 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 7 G3INV 1 R/W Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5, 4 All 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 4 G0INV 1 R/W Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) Rev. 1.00, 03/04, page 329 of 730 Bit Bit Name Initial Value R/W Description 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 10.4 Operation Figure 10.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to eight bits is possible by writing new output data to NDR before the next compare match. NDER Q Output trigger signal C Q PODR D Q NDR D Internal data bus Pulse output pin Normal output/inverted output Figure 10.2 Schematic Diagram of PPG 10.4.1 Output Timing If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. Rev. 1.00, 03/04, page 330 of 730 P N TCNT TGRA N+1 N Compare match A signal n NDRH m PODRH n m PO8 to PO15 n Figure 10.3 Timing of Transfer and Output of NDR Contents (Example) 10.4.2 Sample Setup Procedure for Normal Pulse Output Figure 10.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] Set next pulse output data [8] Start counter [9] [1] Set TIOR to make TGRA an output compare register (with output disabled). [2] Set the PPG output trigger cycle. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. TPU setup PPG setup TPU setup Compare match? [10] At each TGIA interrupt, set the next output values in NDR. No Yes Set next pulse output data [10] Figure 10.4 Setup Procedure for Normal Pulse Output (Example) Rev. 1.00, 03/04, page 331 of 730 10.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output) Figure 10.5 shows an example in which pulse output is used for cyclic 5-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 10.5 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00, 03/04, page 332 of 730 10.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * At compare match A, the NDR bits are always transferred to PODR. * At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 10.6 illustrates the non-overlapping pulse output operation. NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 10.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DMAC. Note, however, that the next data must be written before the next compare match B occurs. Figure 10.7 shows the timing of this operation. Rev. 1.00, 03/04, page 333 of 730 Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 10.7 Non-Overlapping Operation and NDR Write Timing Rev. 1.00, 03/04, page 334 of 730 10.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 10.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping pulse output Select TGR functions [1] Set TGR values [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] TPU setup PPG setup TPU setup [1] Set TIOR to make TGRA and TGRB output compare registers (with output disabled). [2] Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the bits in NDER for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. Select output trigger [7] Set non-overlapping groups [8] Set next pulse output data [9] [8] In PMR, select the groups that will operate in non-overlapping mode. Start counter [10] [9] Set the next pulse output values in NDR. Compare match A? No [11] At each TGIA interrupt, set the next output values in NDR. Yes Set next pulse output data [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 1.00, 03/04, page 335 of 730 10.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output) Figure 10.9 shows an example in which pulse output is used for 4-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlapping margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 10.9 Non-Overlapping Pulse Output Example (4-Phase Complementary) Rev. 1.00, 03/04, page 336 of 730 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU. Rev. 1.00, 03/04, page 337 of 730 10.4.7 Inverted Pulse Output If the G3INV and G2INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 10.10 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of figure 10.9. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 10.10 Inverted Pulse Output (Example) Rev. 1.00, 03/04, page 338 of 730 65 10.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 10.11 shows the timing of this output. P TIOC pin Input capture signal NDR N PODR M PO M N N Figure 10.11 Pulse Output Triggered by Input Capture (Example) 10.5 Usage Notes 10.5.1 Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 10.5.2 Operation of Pulse Output Pins Pins PO0 to PO8 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 1.00, 03/04, page 339 of 730 Rev. 1.00, 03/04, page 340 of 730 Section 11 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 11.1 shows a block diagram of the WDT. 11.1 Features * Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows, this LSI can be initialized internally. In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Internal reset signal* Interrupt control Clock Clock select Reset control RSTCSR TCNT P/2 P/64 P/128 P/512 P/2048 P/8192 P/32768 P/131072 Internal clocks TCSR Bus interface Module bus Internal bus Overflow WOVI (interrupt request signal) WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 11.1 Block Diagram of WDT WDT0120A_000020030600 Rev. 1.00, 03/04, page 341 of 730 11.2 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 11.5.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 11.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0. Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W 11.2.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 OVF WT/IT TME - - CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W R R R/W R/W R/W Note:* Only 0 can be written to this bit, to clear the flag. Rev. 1.00, 03/04, page 342 of 730 Bit Bit Name Initial Value R/W 7 OVF 0 R/(W)* Overflow Flag Description Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows while RSTE = 1, this LSI is initialized initially. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 All 1 R 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Select the clock source to be input to TCNT. The overflow cycle for P = 20 MHz is indicated in parentheses. Reserved These are read-only bits and cannot be modified. Note: * 000: Clock P/2 (cycle: 25.6 s) 001: Clock P/64 (cycle: 819.2 s) 010: Clock P/128 (cycle: 1.6 ms) 011: Clock P/512 (cycle: 6.6 ms) 100: Clock P/2048 (cycle: 26.2 ms) 101: Clock P/8192 (cycle: 104.9 ms) 110: Clock P/32768 (cycle: 419.4 ms) 111: Clock P/131072 (cycle: 1.68 s) Only 0 can be written to this bit, to clear the flag. Rev. 1.00, 03/04, page 343 of 730 11.2.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows. 7 6 5 4 3 2 1 0 WOVF RSTE - - - - - - 0 0 0 1 1 1 1 1 R/(W)* R/W R/W R R R R R Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* Watchdog Timer Overflow Flag Description This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF 6 RSTE 0 R/W Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 4 to 0 All 1 R Reserved These are read-only bits and cannot be modified. Note: * Only 0 can be written to this bit, to clear the flag. Rev. 1.00, 03/04, page 344 of 730 11.3 Operation 11.3.1 Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. When the watchdog timer mode is selected and the RSTE bit in RSTCSR is set to 1, if TCNT overflows without being rewritten because of a system crash or other error, this LSI is initialized internally. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow (TCNT has overflowed), the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The internal reset signal is output for 519 cycles of P. When RSTE = 1, a signal to initialize this LSI internally is generated. Since this signal initializes the system click control register (SCKCR), the multiplication ratio of P clock is also initialized. When RSTE = 0, the signal is not generated, meaning that the SCKCR value and multiplication ratio of P clock remain unchanged. TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF = 1 WT/IT = 1 H'00 written TME = 1 to TCNT Internal reset signal* 519 cycles Notes: * If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. Figure 11.2 Operation in Watchdog Timer Mode Rev. 1.00, 03/04, page 345 of 730 11.3.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1. TCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI WOVI: Interval timer interrupt request Figure 11.3 Operation in Interval Timer Mode 11.4 Interrupt Source During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 11.1 WDT Interrupt Source Name Interrupt Source Interrupt Flag DMAC Activation WOVI TCNT overflow OVF Impossible Rev. 1.00, 03/04, page 346 of 730 11.5 Usage Notes 11.5.1 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR: TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 11.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 11.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 11.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit. TCNT write or writing to the RSTE bit in RSTCSR: 15 Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 8 7 H'5A 0 Write data TCSR write: Address: H'FFA4 (TCSR) 15 Writing 0 to the WOVF bit in RSTCSR: 15 Address: H'FFA6 (RSTCSR) 8 7 H'A5 8 H'A5 0 Write data 7 0 H'00 Figure 11.4 Writing to TCNT, TCSR, and RSTCSR Reading from TCNT, TCSR, and RSTCSR: These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. Rev. 1.00, 03/04, page 347 of 730 11.5.2 Conflict between Timer Counter (TCNT) Write and Increment If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.5 shows this operation. TCNT write cycle T1 T2 P Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.5 Conflict between TCNT Write and Increment 11.5.3 Changing Values of Bits CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed. 11.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode. Rev. 1.00, 03/04, page 348 of 730 11.5.5 Transition to Watchdog Timer Mode or Software Standby Mode When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1. Rev. 1.00, 03/04, page 349 of 730 Rev. 1.00, 03/04, page 350 of 730 Section 12 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (IC card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. Figure 12.1 shows a block diagram of the SCI. 12.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DMAC. * Module stop mode can be set Asynchronous Mode: * * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCI0030A_000020030600 Rev. 1.00, 03/04, page 351 of 730 Clocked Synchronous Mode: * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: Module data bus TDR RDR BRR SCMR SSR P SCR RxD RSR TSR Baud rate generator SMR P/4 P/16 Transmission/ reception control TxD Parity generation P/64 Clock Parity check External clock SCK [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register TEI TXI RXI ERI SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register Figure 12.1 Block Diagram of SCI Rev. 1.00, 03/04, page 352 of 730 Internal data bus Bus interface * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on receiving an error signal during transmission * Both direct convention and inverse convention are supported 12.2 Input/Output Pins Table 12.1 lists the pin configuration of the SCI. Table 12.1 Pin Configuration Channel Pin Name* I/O Function 3 SCK3 I/O Channel 3 clock input/output 4 Note: * RxD3 Input Channel 3 receive data input TxD3 Output Channel 3 transmit data output SCK4 I/O Channel 4 clock input/output RxD4 Input Channel 4 receive data input TxD4 Output Channel 4 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev. 1.00, 03/04, page 353 of 730 12.3 Register Descriptions The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modes: Normal serial communication interface mode and smart card interface mode. The bits, therefore, are described separately for each mode in the corresponding register sections. Channel 3: * Receive shift register_3 (RSR_3) * Transmit shift register_3 (TSR_3) * Receive data register_3 (RDR_3) * Transmit data register_3 (TDR_3) * Serial mode register_3 (SMR_3) * Serial control register_3 (SCR_3) * Serial status register_3 (SSR_3) * Smart card mode register_3 (SCMR_3) * Bit rate register_3 (BRR_3) Channel 4: * * * * * * * * * Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4) Serial control register_4 (SCR_4) Serial status register_4 (SSR_4) Smart card mode register_4 (SCMR_4) Bit rate register_4 (BRR_4) Rev. 1.00, 03/04, page 354 of 730 12.3.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 12.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit Bit Name 12.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 12.3.4 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. Rev. 1.00, 03/04, page 355 of 730 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (valid only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. Rev. 1.00, 03/04, page 356 of 730 Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode) When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 R/W Clock Select 1, 0 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). Rev. 1.00, 03/04, page 357 of 730 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 12.7.6, Data Transmission (Except in Block Transfer Mode) and 12.7.8, Clock Output Control. 6 BLK 0 R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 12.7.3, Block Transfer Mode. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 12.7.2, Data Format (Except in Block Transfer Mode). 3 BCP1 0 R/W Basic Clock Pulse 1,0 2 BCP0 0 R/W These bits select the number of basic clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 12.3.9, Bit Rate Register (BRR). Rev. 1.00, 03/04, page 358 of 730 Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1,0 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). Note: etu (Elementary Time Unit): 1-bit transfer time 12.3.6 Serial Control Register (SCR) SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 12.8, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 359 of 730 Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 Sin order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. Rev. 1.00, 03/04, page 360 of 730 Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 12.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled. 2 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0. 1 CKE1 0 R/W Clock Enable 1, 0 0 CKE0 0 R/W These bits select the clock source and SCK pin function. * Asynchronous mode 00: On-chip baud rate generator (SCK pin functions as I/O port.) 01: On-chip baud rate generator (Outputs a clock with the same frequency as the bit rate from the SCK pin.) 1X: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) * Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output.) 1X: External clock (SCK pin functions as clock input.) Note: X: Don't care Rev. 1.00, 03/04, page 361 of 730 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Rev. 1.00, 03/04, page 362 of 730 Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1, 0 0 CKE0 0 R/W These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 12.7.8, Clock Output Control. * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) 01: Clock output 1X: Reserved * When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. * When SMIF in SCMR = 1 Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. Rev. 1.00, 03/04, page 363 of 730 Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0): Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Indicates whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR [Clearing conditions] 6 RDRF 0 * When 0 is written to TDRE after reading TDRE = 1 * When a TXI interrupt request is issued allowing DMAC to write data to TDR R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. Rev. 1.00, 03/04, page 364 of 730 Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. 4 FER 0 R/(W)* Framing Error Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to FER after reading FER = 1 Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value. Rev. 1.00, 03/04, page 365 of 730 Bit Bit Name Initial Value R/W 3 PER 0 R/(W)* Parity Error Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value. 2 TEND 1 R Transmit End [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a transmit character [Clearing conditions] 1 MPB 0 R * When 0 is written to TDRE after reading TDRE = 1 * When a TXI interrupt request is issued allowing DMAC to write data to TDR Multiprocessor Bit Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame. Note: * Only 0 can be written, to clear the flag. Rev. 1.00, 03/04, page 366 of 730 Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1): Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* Transmit Data Register Empty Description Indicates whether TDR contains transmit data. [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR [Clearing conditions] 6 RDRF 0 * When 0 is written to TDRE after reading TDRE = 1 * When a TXI interrupt request is issued allowing DMAC to write data to TDR R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When an RXI interrupt request is issued allowing DMAC to read data from RDR The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. Rev. 1.00, 03/04, page 367 of 730 Bit Bit Name Initial Value R/W 5 ORER 0 R/(W)* Overrun Error Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value. 4 ERS 0 R/(W)* Error Signal Status [Setting condition] * When a low error signal is sampled [Clearing condition] * 3 PER 0 When 0 is written to ERS after reading ERS = 1 R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value. Rev. 1.00, 03/04, page 368 of 730 Bit Bit Name Initial Value R/W 2 TEND 1 R Description Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] * When both the TE and ERS bits in SCR are 0 * When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] 1 MPB 0 R * When 0 is written to TEND after reading TEND = 1 * When a TXI interrupt request is issued allowing DMAC to write the next data to TDR Multiprocessor Bit Not used in smart card interface mode. 0 MPBT 0 R/W Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Note: * Only 0 can be written, to clear the flag. Rev. 1.00, 03/04, page 369 of 730 12.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. 7 Bit 6 5 4 3 2 1 0 Bit Name - - - - SDIR SINV - SMIF Initial Value 1 1 1 1 0 0 1 0 R/W R R R R R/W R/W R R/W Bit Bit Name Initial Value R/W Description 7 to 4 All 1 R Reserved These are read-only bits and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first. 2 SINV 0 R/W Smart Card Data Invert Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR. 1 1 R Reserved This is a read-only bit and cannot be modified. 0 SMIF 0 R/W Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode Rev. 1.00, 03/04, page 370 of 730 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.2 Relationships between N Setting in BRR and Bit Rate B Mode Bit Rate Asynchronous mode N= P x 10 64 x 2 Clocked synchronous mode N= N= 2n - 1 2n - 1 Sx2 P x 106 Error (%) = { B x 64 x 2 2n - 1 - 1 } x 100 x (N + 1) -1 xB P x 106 2n + 1 -1 xB P x 106 8x2 Smart card interface mode Error 6 -1 xB P x 106 Error (%) = { BxSx2 2n + 1 - 1 } x 100 x (N + 1) [Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) P: Operating frequency (MHz) n and S: Determined by the SMR settings shown in the following table. SMR Setting SMR Setting CKS1 CKS0 n BCP1 BCP0 S 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate settable for each operating frequency. Tables 12.6 and 12.8 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of basic clock cycles S in a 1-bit data transfer time can be selected. For details, see section 12.7.4, Receive Data Sampling Timing and Reception Margin. Tables 12.5 and 12.7 show the maximum bit rates with external clock input. Rev. 1.00, 03/04, page 371 of 730 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency P (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 -0.26 2 177 -0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 -1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 -2.34 31250 0 7 0.00 0 9 -1.70 0 9 0.00 0 11 0.00 38400 0 7 0.00 0 7 1.73 0 9 -2.34 Operating Frequency P (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 -0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 39 0.00 0 45 -0.93 0 47 0.00 0 51 0.16 19200 0 19 0.00 0 22 -0.93 0 23 0.00 0 25 0.16 31250 0 11 2.40 0 13 0.00 0 14 -1.70 0 15 0.00 38400 0 9 0.00 0 11 0.00 0 12 0.16 Rev. 1.00, 03/04, page 372 of 730 Table 12.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency P (MHz) 17.2032 18 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 -0.12 3 86 0.31 3 88 -0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.00 0 233 0.16 0 255 0.00 1 64 0.16 4800 0 111 0.00 0 116 0.16 0 127 0.00 0 129 0.16 9600 0 55 0.00 0 58 -0.69 0 63 0.00 0 64 0.16 19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 -1.36 31250 0 16 1.20 0 17 0.00 0 19 -1.70 0 19 0.00 38400 0 13 0.00 0 14 -2.34 0 15 0.00 0 15 1.73 Operating Frequency P (MHz) 25 30 33 35 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 110 -0.02 3 132 0.13 3 145 0.33 3 154 0.23 150 3 80 -0.47 3 97 -0.35 3 106 0.39 3 113 -0.06 300 2 162 0.15 2 194 0.16 2 214 -0.07 2 227 0.00 600 2 80 -0.47 2 97 -0.35 2 106 0.39 2 113 0.00 1200 1 162 0.15 1 194 0.16 1 214 -0.07 1 227 0.00 2400 1 80 -0.47 1 97 -0.35 1 106 0.39 1 113 0.00 4800 0 162 0.15 0 194 0.16 0 214 -0.07 0 227 0.00 9600 0 80 -0.47 0 97 -0.35 0 106 0.39 0 113 0.00 19200 0 40 -0.76 0 48 -0.35 0 53 -0.54 0 56 0.00 31250 0 24 0.00 0 29 0 0 32 0 0 34 0.00 38400 0 19 1.73 0 23 1.73 0 26 -0.54 0 28 -1.78 Rev. 1.00, 03/04, page 373 of 730 Table 12.4 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) P (MHz) Maximum Bit Rate (bit/s) P (MHz) Maximum Bit Rate (bit/s) n N n N 8 250000 0 0 17.2032 537600 0 0 9.8304 307200 10 312500 0 0 18 562500 0 0 0 0 19.6608 614400 0 0 12 375000 0 0 20 625000 0 0 12.288 384000 0 0 25 781250 0 0 14 437500 0 0 30 937500 0 0 14.7456 460800 0 0 33 1031250 0 0 16 500000 0 0 35 1093750 0 0 Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 17.2032 4.3008 268800 9.8304 2.4576 153600 18 4.5000 281250 10 2.5000 156250 19.6608 4.9152 307200 12 3.0000 187500 20 5.0000 312500 12.288 3.0720 192000 25 6.2500 390625 14 3.5000 218750 30 7.5000 468750 14.7456 3.6864 230400 33 8.2500 515625 16 4.0000 250000 35 8.7500 546875 Rev. 1.00, 03/04, page 374 of 730 Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency P (MHz) Bit Rate (bit/s) n 8 10 16 N n N n N 20 n N 110 250 3 124 3 249 500 2 249 3 124 1k 2 124 2 249 2.5k 1 199 1 249 2 99 2 124 5k 1 99 1 124 1 199 1 249 10k 0 199 0 249 1 99 1 124 25k 0 79 0 99 0 159 0 199 50k 0 39 0 49 0 79 0 99 100k 0 19 0 24 0 39 0 49 250k 0 7 0 9 0 15 0 19 500k 0 3 0 4 0 7 0 9 1M 0 1 0 3 0 4 0 1 0 0* 2.5M 5M 0 0* Rev. 1.00, 03/04, page 375 of 730 Operating Frequency P (MHz) Bit Rate (bit/s) n 25 N 30 n N 3 233 33 n N 35 n N 110 250 500 1k 3 97 3 116 3 128 3 136 2.5k 2 155 2 187 2 205 2 218 5k 2 77 2 93 2 102 2 108 10k 1 155 1 187 1 205 1 218 25k 0 249 1 74 1 82 1 87 50k 0 124 0 149 0 164 0 174 100k 0 62 0 74 0 82 0 87 250k 0 24 0 29 0 32 0 34 500k 0 14 1M 2.5M 0 2 5M [Legend] Space : Setting prohibited. : Can be set, but there will be error. * : Continuous transmission or reception is not possible. Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) P (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 20 3.3333 3333333.3 10 1.6667 1666666.7 25 4.1667 4166666.7 12 2.0000 2000000.0 30 5.0000 5000000.0 14 2.3333 2333333.3 33 5.5000 5500000.0 16 2.6667 2666666.7 35 5.8336 5833625.0 18 3.0000 3000000.0 Rev. 1.00, 03/04, page 376 of 730 Table 12.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency P (MHz) 7.1424 Bit Rate 10.00 10.7136 13.00 (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 0 0.00 1 30 1 25 1 8.99 0 0 0 Operating Frequency P (MHz) 14.2848 Bit Rate 16.00 18.00 20.00 (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 0.00 1 12.01 2 15.99 2 6.60 0 0 0 Operating Frequency P (MHz) 25.00 Bit Rate 30.00 33.00 35.00 (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 3 12.49 3 5.01 4 7.59 4 1.99 0 0 0 Table 12.9 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372) P (MHz) Maximum Bit Rate (bit/s) n N P (MHz) Maximum Bit Rate (bit/s) n N 7.1424 9600 0 0 18.00 24194 0 0 10.00 13441 0 0 20.00 26882 0 0 10.7136 14400 0 0 25.00 33602 0 0 13.00 17473 0 0 30.00 40323 0 0 14.2848 19200 0 0 33.00 44355 0 0 16.00 21505 0 0 35.00 47043 0 0 Rev. 1.00, 03/04, page 377 of 730 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Idle state (mark state) LSB 1 Serial data 0 D0 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 1 0/1 1 1 Parity bit Stop bit 1 bit or none 1 or 2 bits One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 1.00, 03/04, page 378 of 730 12.4.1 Data Transfer Format Table 12.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 12.5, Multiprocessor Communication Function. Table 12.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transmit/Receive Format and Frame Length CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP 2 3 4 5 6 7 8 9 10 11 12 [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 1.00, 03/04, page 379 of 730 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3. Thus the reception margin in asynchronous mode is determined by formula (1) below. M = } (0.5 - 1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) } x 100 2N N [%] ... Formula (1) M: Reception margin N: Ratio of bit rate to clock (N = 16) D: Duty cycle of clock (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below. M = ( 0.5 - 1 ) x 100 2 x 16 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Start bit D0 Synchronization sampling timing Data sampling timing Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00, 03/04, page 380 of 730 D1 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.4 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode) 12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Rev. 1.00, 03/04, page 381 of 730 Start initialization [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set data transfer format in SMR and SCMR [3] Set value in BRR [4] When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Wait No 1-bit interval elapsed Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] <Initialization completion> Figure 12.5 Sample SCI Initialization Flowchart Rev. 1.00, 03/04, page 382 of 730 12.4.5 Serial Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 12.6 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00, 03/04, page 383 of 730 Initialization [1] Start transmission [2] Read TDRE flag in SSR TDRE = 1 [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. No Yes [3] Serial transmission continuation procedure: Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? No Yes [3] Read TEND flag in SSR TEND = 1 No Yes Break output Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. No [4] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 12.7 Sample Serial Transmission Flowchart 12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. Rev. 1.00, 03/04, page 384 of 730 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error 1 frame Figure 12.8 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit) Table 12.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flowchart for serial data reception. Rev. 1.00, 03/04, page 385 of 730 Table 12.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error + framing error 1 1 0 1 Lost Overrun error + parity error 0 0 1 1 Transferred to RDR Framing error + parity error 1 1 1 1 Lost Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception. Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No resumed if any of these flags are set to Error processing 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DMAC is initiated by an RXI interrupt and reads data from RDR. <End> Figure 12.9 Sample Serial Reception Flowchart (1) Rev. 1.00, 03/04, page 386 of 730 [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No Clear RE bit in SCR to 0 PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12.9 Sample Serial Reception Flowchart (2) 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Rev. 1.00, 03/04, page 387 of 730 Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with the multiprocessor bit cleared to 0. The receiving station skips data until data with the multiprocessor bit set to 1 is sent. When data with the multiprocessor bit set to 1 is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with the multiprocessor bit set to 1 is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with the multiprocessor bit set to 1 is received. On reception of a receive character with the multiprocessor bit set to 1, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Transmitting station Communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 1.00, 03/04, page 388 of 730 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Initialization [1] Start transmission [2] Read TDRE flag in SSR TDRE = 1 [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? No [3] Yes Read TEND flag in SSR TEND = 1 No Yes Break output? No [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [4] [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0. Yes Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 <End> Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 1.00, 03/04, page 389 of 730 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception. 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data 1) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 Data (ID2) D0 D1 Stop MPB bit D7 1 1 Start bit 0 Data (Data 2) D0 D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 Data 2 ID2 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station's ID, so reception continues, and data is received in RXI interrupt processing routine MPIE bit set to 1 again (b) Data matches station's ID Figure 12.12 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00, 03/04, page 390 of 730 [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Initialization Start reception Set MPIE bit in SCR to 1 [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. Read ORER and FER flags in SSR Yes FER ORER = 1 No [3] Read RDRF flag in SSR No RDRF = 1 [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Yes Read receive data in RDR No [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. This station's ID? Yes Read ORER and FER flags in SSR FER ORER = 1 Yes No Read RDRF flag in SSR RDRF = 1 [4] No Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) <End> Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 1.00, 03/04, page 391 of 730 [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00, 03/04, page 392 of 730 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. One unit of transfer data (character or frame) * * Synchronization clock LSB Bit 0 Serial data MSB Bit 1 Bit 2 Bit 3 Bit 4 Don't care Bit 5 Bit 6 Bit 7 Don't care Note: * Holds a high level except during continuous transfer. Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First) 12.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0. Rev. 1.00, 03/04, page 393 of 730 12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. Start initialization [1] Clear TE and RE bits in SCR to 0 Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set corresponding bit in ICR to 1 [1] Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) [2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [2] [3] Set the data transfer format in SMR and SCMR. Set data transfer format in SMR and SCMR [3] Set value in BRR [4] Wait 1-bit interval elapsed? No [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [5] <Transfer start> Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.15 Sample SCI Initialization Flowchart Rev. 1.00, 03/04, page 394 of 730 12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 12.16 Example of Operation for Transmission in Clocked Synchronous Mode Rev. 1.00, 03/04, page 395 of 730 [1] Initialization Start transmission Read TDRE flag in SSR TDRE = 1 [2] No Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted No Yes [3] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Read TEND flag in SSR TEND = 1 No Yes Clear TE bit in SCR to 0 <End> Figure 12.17 Sample Serial Transmission Flowchart Rev. 1.00, 03/04, page 396 of 730 12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 12.18 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception. Rev. 1.00, 03/04, page 397 of 730 [1] Initialization Start reception [2] Read ORER flag in SSR Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR No [4] RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received Yes Clear RE bit in SCR to 0 <End> [3] [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DMAC is initiated by a receive data full interrupt (RXI) and reads data from RDR. Error processing Overrun error processing Clear ORER flag in SSR to 0 <End> Figure 12.19 Sample Serial Reception Flowchart 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction. Rev. 1.00, 03/04, page 398 of 730 [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [1] Initialization Start transmission/reception Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes [3] Error processing [4] [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to No 0. Also, before the MSB (bit 7) of [5] All data received? the current frame is transmitted, read 1 from the TDRE flag to Yes confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Clear TE and RE bits in SCR to 0 However, the TDRE flag is checked and cleared automatically when the DMAC is initiated by a transmit data <End> empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared automatically Note: When switching from transmit or receive operation to when the DMAC is initiated by a simultaneous transmit and receive operations, first clear the receive data full interrupt (RXI) and TE bit and RE bit to 0, then set both these bits to 1 reads data from RDR. simultaneously. Yes Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception Rev. 1.00, 03/04, page 399 of 730 12.7 Operation in Smart Card Interface Mode The SCI supports the IC card (smart card) interface, conforming to ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 12.7.1 Sample Connection Figure 12.21 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the IC card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits to 1 with the IC card not connected enables closed transmission/reception allowing self diagnosis. To supply the IC card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the IC card. A reset signal can be supplied via the output port of this LSI. VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card Figure 12.21 Pin Connection for Smart Card Interface 12.7.2 Data Format (Except in Block Transfer Mode) Figure 12.22 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu. Rev. 1.00, 03/04, page 400 of 730 In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 DE Output from the transmitting station [Legend] Ds: Start bit D0 to D7: Data bits Output from the receiving station Dp: Parity bit DE: Error signal Figure 12.22 Data Formats in Normal Smart Card Interface Mode For communication with the IC cards of the direct convention and inverse convention types, follow the procedure below. (Z) A Z Z A Z Z Z A A Z Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (Z) state Figure 12.23 Direct Convention (SDIR = SINV = O/E = 0) For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 12.23. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard. (Z) A Z Z A A A A A A Z Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp (Z) state Figure 12.24 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 12.24. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. Rev. 1.00, 03/04, page 401 of 730 12.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. * Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred. 12.7.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the basic clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the basic clock so that it can be latched at the middle of each bit as shown in figure 12.25. The reception margin here is determined by the following formula. M = | (0.5 - 1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) | x 100% 2N N M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Duty cycle of clock (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below. M= ( 0.5 - 1 ) x 100% = 49.866% 2 x 372 Rev. 1.00, 03/04, page 402 of 730 372 clock cycles 186 clock cycles 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 12.25 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 12.7.5 Initialization Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. 2. 3. 4. 5. 6. 7. 8. Clear the TE and RE bits in SCR to 0. Set the ICR bit of the corresponding pin to 1. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. Set the value corresponding to the bit rate in BRR. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis. To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. Rev. 1.00, 03/04, page 403 of 730 12.7.6 Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 12.26 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 12.28 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, TEND remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC). Rev. 1.00, 03/04, page 404 of 730 (n + 1) th transfer frame Retransfer frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR TEND [2] [4] FER/ERS [1] [3] Figure 12.26 Data Re-Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 12.27 shows the TEND flag set timing. Ds I/O data D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time TXI (TEND interrupt) 12.5 etu GM = 0 11.0 etu GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 12.27 TEND Flag Set Timing during Transmission Rev. 1.00, 03/04, page 405 of 730 Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 12.28 Sample Transmission Flowchart Rev. 1.00, 03/04, page 406 of 730 12.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 12.29 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 12.30 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 12.4, Operation in Asynchronous Mode. (n + 1) th transfer frame Retransfer frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF [2] [4] [1] [3] PER Figure 12.29 Data Re-Transfer Operation in SCI Reception Mode Rev. 1.00, 03/04, page 407 of 730 Start Initialization Start reception ORER = 0 and PER = 0? Yes No No Error processing RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 12.30 Sample Reception Flowchart 12.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 12.31 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0. CKE0 SCK Given pulse width Given pulse width Figure 12.31 Clock Output Fixing Timing Rev. 1.00, 03/04, page 408 of 730 At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. * At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output. * At mode switching At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode. At transition from smart card interface mode to software standby mode 1. Clear software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated. Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [6] [7] Figure 12.32 Clock Stop and Restart Procedure Rev. 1.00, 03/04, page 409 of 730 12.8 Interrupt Sources 12.8.1 Interrupts in Normal Serial Communication Interface Mode Table 12.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Table 12.12 SCI Interrupt Sources Name Interrupt Source Interrupt Flag DMAC Activation Priority ERI Receive error ORER, FER, or PER Not possible High RXI Receive data full RDRF Possible TXI Transmit data empty TDRE Possible TEI Transmit end TEND Not possible Rev. 1.00, 03/04, page 410 of 730 Low 12.8.2 Interrupts in Smart Card Interface Mode Table 12.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Table 12.13 SCI Interrupt Sources Name Interrupt Source Interrupt Flag DMAC Activation Priority ERI Receive error or error signal detection ORER, PER, or ERS Not possible High RXI Receive data full RDRF Possible TXI Transmit data empty TDRE Possible Low Data transmission/reception using the DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the SCI automatically re-transmits the same data. During retransmission, the TEND flag remains as 0, thus not activating the DMAC. Therefore, the SCI and DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DMAC, be sure to set and enable the DMAC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller (DMAC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared. Rev. 1.00, 03/04, page 411 of 730 12.9 Usage Notes 12.9.1 Module Stop Mode Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 12.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 12.9.3 Mark State and Break Detection When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 12.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 12.9.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. Rev. 1.00, 03/04, page 412 of 730 12.9.6 Restrictions on Using DMAC * When the external clock source is used as a synchronization clock, update TDR by the DMAC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 12.33). * When using the DMAC to read RDR, be sure to set the receive end interrupt (RXI) as the DMAC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 12.33 Sample Transmission using DMAC in Clocked Synchronous Mode 12.9.7 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop mode or software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during module stop mode or software standby mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 12.34 shows a sample flowchart for mode transition during transmission. Figures 12.35 and 12.36 show the port pin states during mode transition. Reception: Before making the transition to module stop mode or software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Rev. 1.00, 03/04, page 413 of 730 Figure 12.37 shows a sample flowchart for mode transition during reception. Transmission No All data transmitted? [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and clearing the TDRE bit to 0 after clearing software standby mode. Yes Read TEND flag in SSR No TEND = 1 [2] Clear the TIE and TEIE bits to 0 when they are 1. Yes [3] Module stop mode is included. TE = 0 [2] Make transition to software standby mode [3] Cancel software standby mode Change operating mode? No Yes Initialization TE = 1 Start transmission Figure 12.34 Sample Flowchart for Mode Transition during Transmission Transmission start Transition to Software standby Transmission end software standby mode canceled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Port Stop Port input/output Port Figure 12.35 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission) Rev. 1.00, 03/04, page 414 of 730 High output SCI TxD output Transmission start Transmission end Transition to Software standby software standby mode canceled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output Last TxD bit retained SCI TxD output Port Port input/output High output* Port SCI TxD output Note: * Initialized in software standby mode Figure 12.36 Port Pin States during Mode Transition (Internal Clock, Clocked Synchronous Transmission) Reception Read RDRF flag in SSR RDRF = 1 No [1] [1] Data being received will be invalid. Yes Read receive data in RDR [2] Module stop mode is included. RE = 0 Make transition to software standby mode [2] Cancel software standby mode Change operating mode? No Yes Initialization RE = 1 Start reception Figure 12.37 Sample Flowchart for Mode Transition during Reception Rev. 1.00, 03/04, page 415 of 730 Rev. 1.00, 03/04, page 416 of 730 Section 13 Controller Area Network (HCAN) The HCAN is a module for controlling a controller area network (CAN) for real time communication in vehicular and industrial equipment systems, etc. For details on CAN specification, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. The block diagram of the HCAN is shown in figure 13.1. 13.1 Features * CAN version: Bosch 2.0B active compatible Communication systems: NRZ (Non-Return to Zero) system (with bit-stuffing function) Broadcast communication system Transmission path: Bidirectional 2-wire serial communication Communication speed: Max. 1 Mbps Data length: 0 to 8 bytes * Number of channels: 1 * Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception) * Data transmission: Two methods Mailbox (buffer) number order (low-to-high) Message priority (identifier) reverse-order (high-to-low) * Data reception: Two methods Message identifier match (transmit/receive-setting buffers) Reception with message identifier masked (receive-only) * CPU interrupts: 12 Error interrupt Reset processing interrupt Message reception interrupt Message transmission interrupt * HCAN operating modes * Support for various modes Hardware reset Software reset Normal status (error-active, error-passive) Bus off status HCAN configuration mode HCAN sleep mode HCAN halt mode IFCAN00C_000020020900 Rev. 1.00, 03/04, page 417 of 730 * Other features DMAC can be activated by message reception mailbox (HCAN mailbox 0 only) * Module stop mode can be set Peripheral data bus Peripheral address bus HCAN MBI Message buffer Mailboxes Message control, message data, MC0 to MC15, MD0 to MD15 LAFM (CDLC) CAN Data Link Controller Bosch CAN 2.0B active MPI Microprocessor interface Tx buffer HTxD Rx buffer HRxD CPU interface Control register Status register Figure 13.1 HCAN Block Diagram * Message Buffer Interface (MBI) The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages are written by the CPU. For receive messages, the data received by the CDLC is stored automatically. * Microprocessor Interface (MPI) The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN internal data, status, and so forth. * CAN Data Link Controller (CDLC) The CDLC, conforming to the Bosch CAN Ver. 2.0B active standard, performs transmission and reception of messages (data frames, remote frames, error frames, overload frames, interframe spacing), as well as CRC checking, bus arbitration, and other functions. Rev. 1.00, 03/04, page 418 of 730 13.2 Input/Output Pins Table 13.1 shows the HCAN pin configuration. For the use of these pins, the input buffer control registers (ICR) of the port and the HCAN monitor register (HCANMON) must be specified according to other HCAN settings. In addition, when using HCAN pins, settings must be made in the HCAN configuration mode (during initialization: MCR0 = 1 and GSR3 = 1). Table 13.1 Pin Configuration Name Abbreviation Input/Output Function HCAN transmit data pin HTxD Output CAN bus transmission pin HCAN receive data pin HRxD Input CAN bus reception pin A bus driver is necessary for the interface between the pins and the CAN bus. A Philips PCA82C250 compatible model is recommended. 13.3 Register Descriptions The HCAN has the following registers. * * * * * * * * * * * * * * * * * * Master control register (MCR) General status register (GSR) Bit configuration register (BCR) Mailbox configuration register (MBCR) Transmit wait register (TXPR) Transmit wait cancel register (TXCR) Transmit acknowledge register (TXACK) Abort acknowledge register (ABACK) Receive complete register (RXPR) Remote request register (RFPR) Interrupt register (IRR) Mailbox interrupt mask register (MBIMR) Interrupt mask register (IMR) Receive error counter (REC) Transmit error counter (TEC) Unread message status register (UMSR) Local acceptance filter mask H (LAFMH) Local acceptance filter mask L (LAFML) Rev. 1.00, 03/04, page 419 of 730 * Message control (8-bit x 8 registers x 16 sets) (MC0 to MC15) * Message data (8-bit x 8 registers x 16 sets) (MD0 to MD15) * HCAN Monitor Register (HCANMON) 13.3.1 Master Control Register (MCR) MCR controls the HCAN. 7 6 5 4 3 2 1 0 MCR7 - MCR5 - - MCR2 MCR1 MCR0 Bit Bit Name Initial Value R/W 0 0 0 0 0 0 0 1 R/W R R/W R R R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 MCR7 0 R/W HCAN Sleep Mode Release When this bit is set to 1, the HCAN automatically exits HCAN sleep mode on detection of CAN bus operation. 6 0 R Reserved This is a read-only bit and cannot be modified. 5 MCR5 0 R/W HCAN Sleep Mode When this bit is set to 1, the HCAN enters HCAN sleep mode. When this bit is cleared to 0, HCAN sleep mode is released. 4, 3 All 0 R Reserved These are read-only bits and cannot be modified. 2 MCR2 0 R/W Message Transmission Method 0: Transmission order determined by message identifier priority 1: Transmission order determined by mailbox (buffer) number priority (TXPR1 > TXPR15) 1 MCR1 0 R/W Halt Request When this bit is set to 1, the HCAN enters HCAN HALT mode. When this bit is cleared to 0, HCAN HALT mode is released. Rev. 1.00, 03/04, page 420 of 730 Bit Bit Name Initial Value R/W Description 0 MCR0 1 R/W Reset Request When this bit is set to 1, the HCAN enters reset mode. For details, refer to section 13.4.1, Hardware and Software Resets. [Setting conditions] Power-on reset Software standby 1-write (software reset) [Clearing condition] When 0 is written to this bit while bit GSR3 in GSR is 1 13.3.2 General Status Register (GSR) GSR indicates the status of the HCAN. Bit 7 6 5 4 3 2 1 0 Bit Name - - - - GSR3 GSR2 GSR1 GSR0 Initial Value 0 0 0 0 1 1 0 0 R/W R R R R R R R R Bit Bit Name Initial Value R/W Description 7 to 4 All 0 R Reserved 3 GSR3 1 R These are read-only bits and cannot be modified. Reset Status Indicates whether the HCAN module is in the normal operation state or the reset state. This bit cannot be modified. [Setting conditions] * When entering configuration mode after the HCAN internal reset has finished * Sleep mode [Clearing condition] * When entering the normal operation state after bit MCR0 in MCR is cleared (note that there is delay between clearing bits MCR0 and GSR3.) Rev. 1.00, 03/04, page 421 of 730 Bit Bit Name Initial Value R/W 2 GSR2 1 R Description Message Transmission Status Flag Flag that indicates whether the module is currently in the message transmission period. This bit cannot be modified. [Setting condition] Third bit of Intermission after EOF (End of Frame) [Clearing condition] Start of message transmission (SOF) 1 GSR1 0 R Transmit/Receive Warning Flag This bit cannot be modified. [Clearing condition] When TEC < 96 and REC < 96 or TEC 256 [Setting condition] When TEC 96 or REC 96 0 GSR0 0 R Bus Off Flag This bit cannot be modified. [Setting condition] When TEC 256 (bus off state) [Clearing condition] Recovery from bus off state Rev. 1.00, 03/04, page 422 of 730 13.3.3 Bit Configuration Register (BCR) BCR sets HCAN bit timing parameters and the baud rate. For details on parameters, refer to section 13.4.2, Initialization after Hardware Reset. Bit 15 14 13 12 11 10 9 8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 15 BCR7 0 R/W Re-Synchronization Jump Width (SJW) 14 BCR6 0 R/W Set the maximum bit synchronization width. 00: 1 time quantum 01: 2 time quanta 10: 3 time quanta 11: 4 time quanta 13 BCR5 0 R/W Baud Rate Prescaler (BRP) 12 BCR4 0 R/W Set the length of time quanta. 11 BCR3 0 R/W 000000: 2 x system clock 10 BCR2 0 R/W 000001: 4 x system clock 9 BCR1 0 R/W 000010: 6 x system clock 8 BCR0 0 R/W : 111111: 128 x system clock 7 BCR15 0 R/W Bit Sample Point (BSP) Sets the point at which data is sampled. 0: Bit sampling at one point (end of time segment 1 (TSEG1)) 1: Bit sampling at three points (end of TSEG1 and preceding and following time quanta) Rev. 1.00, 03/04, page 423 of 730 Bit Bit Name Initial Value R/W Description 6 BCR14 0 R/W Time Segment 2 (TSEG2) 5 BCR13 0 R/W 4 BCR12 0 R/W Set the TSEG2 width within a range of 2 to 8 time quanta. 000: Setting prohibited 001: 2 time quanta 010: 3 time quanta 011: 4 time quanta 100: 5 time quanta 101: 6 time quanta 110: 7 time quanta 111: 8 time quanta 3 BCR11 0 R/W Time Segment 1 (TSEG1) 2 BCR10 0 R/W 1 BCR9 0 R/W Set the TSEG1 (PRSEG + PHSEG1) width to between 4 and 16 time quanta. 0 BCR8 0 R/W 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: 4 time quanta 0100: 5 time quanta 0101: 6 time quanta 0110: 7 time quanta 0111: 8 time quanta 1000: 9 time quanta 1001: 10 time quanta 1010: 11 time quanta 1011: 12 time quanta 1100: 13 time quanta 1101: 14 time quanta 1110: 15 time quanta 1111: 16 time quanta Rev. 1.00, 03/04, page 424 of 730 13.3.4 Mailbox Configuration Register (MBCR) MBCR sets the transfer direction for each mailbox. Bit Bit Name 15 14 13 12 11 10 9 8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 - Initial Value R/W 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R Bit Bit Name 7 6 5 4 3 2 1 0 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 15 MBCR7 0 R/W 14 MBCR6 0 R/W 13 MBCR5 0 R/W These bits set the transfer direction for the corresponding mailboxes 1 to 15. MBCRn determines the transfer direction for mailbox n (n =1 to 15). 12 MBCR4 0 R/W 0: Corresponding mailbox is set for transmission 11 MBCR3 0 R/W 1: Corresponding mailbox is set for reception 10 MBCR2 0 R/W 9 MBCR1 0 R/W Bit 8 is reserved. This is a read-only bit and cannot be modified. 8 1 R 7 MBCR15 0 R/W 6 MBCR14 0 R/W 5 MBCR13 0 R/W 4 MBCR12 0 R/W 3 MBCR11 0 R/W 2 MBCR10 0 R/W 1 MBCR9 0 R/W 0 MBCR8 0 R/W Rev. 1.00, 03/04, page 425 of 730 13.3.5 Transmit Wait Register (TXPR) TXPR makes transmit messages stored in mailboxes enter the transmit wait state (CAN bus arbitration wait). Bit Bit Name 15 14 13 12 11 10 9 8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 - 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 15 TXPR7 0 R/W 14 TXPR6 0 R/W 13 TXPR5 0 R/W 12 TXPR4 0 R/W These bits set a transmit wait (CAN bus arbitration wait) for the corresponding mailboxes 1 to 15. When TXPRn (n = 1 to 15) is set to 1, the message in mailbox n becomes the transmit wait state. 11 TXPR3 0 R/W [Clearing conditions] 10 TXPR2 0 R/W Completion of message transmission 9 TXPR1 0 R/W Completion of transmission cancellation 8 0 R 7 TXPR15 0 R/W Bit 8 is reserved. This is a read-only bit and cannot be modified. 6 TXPR14 0 R/W 5 TXPR13 0 R/W 4 TXPR12 0 R/W 3 TXPR11 0 R/W 2 TXPR10 0 R/W 1 TXPR9 0 R/W 0 TXPR8 0 R/W Rev. 1.00, 03/04, page 426 of 730 13.3.6 Transmit Wait Cancel Register (TXCR) TXCR cancels transmit wait messages in mailboxes. Bit Bit Name 15 14 13 12 11 10 9 8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 - Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R Bit Bit Name 7 6 5 4 3 2 1 0 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 15 TXCR7 0 R/W 14 TXCR6 0 R/W 13 TXCR5 0 R/W These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15. When TXCRn (n = 1 to 15) is set to 1, the transmit wait message in mailbox n is canceled. 12 TXCR4 0 R/W [Clearing condition] 11 TXCR3 0 R/W 10 TXCR2 0 R/W Completion of TXPR clearing when transmit message is canceled normally 9 TXCR1 0 R/W 8 0 R 7 TXCR15 0 R/W 6 TXCR14 0 R/W 5 TXCR13 0 R/W 4 TXCR12 0 R/W 3 TXCR11 0 R/W 2 TXCR10 0 R/W 1 TXCR9 0 R/W 0 TXCR8 0 R/W Bit 8 is reserved. This is a read-only bit and cannot be modified. Rev. 1.00, 03/04, page 427 of 730 13.3.7 Transmit Acknowledge Register (TXACK) TXACK indicates the normal transmission of transmit messages in mailboxes. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 14 13 12 11 10 9 8 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 - 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description 15 TXACK7 0 R/(W)* 14 TXACK6 0 R/(W)* 13 TXACK5 0 R/(W)* 12 TXACK4 0 R/(W)* These bits are status flags that indicate error-free transmission of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been transmitted error-free, TXACKn is set to 1. 11 TXACK3 0 R/(W)* [Setting condition] 10 TXACK2 0 R/(W)* 9 TXACK1 0 R/(W)* Completion of message transmission for corresponding mailbox 8 0 R 7 TXACK15 0 R/(W)* 6 TXACK14 0 R/(W)* 5 TXACK13 0 R/(W)* 4 TXACK12 0 R/(W)* 3 TXACK11 0 R/(W)* 2 TXACK10 0 R/(W)* 1 TXACK9 0 R/(W)* 0 TXACK8 0 R/(W)* Note: * [Clearing condition] Writing 1 Bit 8 is reserved. This is a read-only bit and cannot be modified. Only 1 can be written to clear the flag. Rev. 1.00, 03/04, page 428 of 730 13.3.8 Abort Acknowledge Register (ABACK) ABACK indicates the normal cancellation of transmit messages in mailboxes. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 15 14 13 12 11 10 9 8 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 - 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R 7 6 5 4 3 2 1 0 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description 15 ABACK7 0 R/(W)* 14 ABACK6 0 R/(W)* 13 ABACK5 0 R/(W)* 12 ABACK4 0 R/(W)* These bits are status flags that indicate error-free cancellation (abortion) of the transmit message in the corresponding mailboxes 1 to 15. When the message in mailbox n (n = 1 to 15) has been canceled error-free, ABACKn is set to 1. 11 ABACK3 0 R/(W)* [Setting condition] 10 ABACK2 0 R/(W)* 9 ABACK1 0 R/(W)* Completion of transmit message cancellation for corresponding mailbox 8 0 R 7 ABACK15 0 R/(W)* 6 ABACK14 0 R/(W)* 5 ABACK13 0 R/(W)* 4 ABACK12 0 R/(W)* 3 ABACK11 0 R/(W)* 2 ABACK10 0 R/(W)* 1 ABACK9 0 R/(W)* 0 ABACK8 0 R/(W)* Note: * [Clearing condition] Writing 1 Bit 8 is reserved. This is a read-only bit and cannot be modified. Only 1 can be written to clear the flag. Rev. 1.00, 03/04, page 429 of 730 13.3.9 Receive Complete Register (RXPR) RXPR indicates the normal reception of messages (data frame or remote frame) in mailboxes. For reception of a remote frame, when a bit in this register is set to 1, the corresponding remote request register (RFPR) bit is also set to 1 simultaneously. Bit Bit Name 15 14 13 12 11 10 9 8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial Value R/W Bit Bit Name Initial Value R/W Note: * 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description 15 RXPR7 0 R/(W)* 14 RXPR6 0 R/(W)* When the message in mailbox n (n = 1 to 15) has been received error-free, RXPRn is set to 1. 13 RXPR5 0 R/(W)* [Setting condition] 12 RXPR4 0 R/(W)* 11 RXPR3 0 R/(W)* Completion of message (data frame or remote frame) reception in corresponding mailbox 10 RXPR2 0 R/(W)* 9 RXPR1 0 R/(W)* 8 RXPR0 0 R/(W)* 7 RXPR15 0 R/(W)* 6 RXPR14 0 R/(W)* 5 RXPR13 0 R/(W)* 4 RXPR12 0 R/(W)* 3 RXPR11 0 R/(W)* 2 RXPR10 0 R/(W)* 1 RXPR9 0 R/(W)* 0 RXPR8 0 R/(W)* Note: * [Clearing condition] Writing 1 Only 1 can be written to clear the flag. Rev. 1.00, 03/04, page 430 of 730 13.3.10 Remote Request Register (RFPR) RFPR indicates the normal reception of remote frames in mailboxes. When a bit in this register is set to 1, the corresponding receive complete register (RXPR) bit is also set to 1 simultaneously. Bit Bit Name 15 14 13 12 11 10 9 8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial Value R/W Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description 15 RFPR7 0 R/(W)* 14 RFPR6 0 R/(W)* 13 RFPR5 0 R/(W)* When mailbox n (n = 0 to 15) has received the remote frame error-free, RFPRn (n = 1 to 15) is set to 1. 12 RFPR4 0 R/(W)* 11 RFPR3 0 R/(W)* Completion of remote frame reception in corresponding mailbox 10 RFPR2 0 R/(W)* [Clearing condition] 9 RFPR1 0 R/(W)* Writing 1 8 RFPR0 0 R/(W)* 7 RFPR15 0 R/(W)* 6 RFPR14 0 R/(W)* 5 RFPR13 0 R/(W)* 4 RFPR12 0 R/(W)* 3 RFPR11 0 R/(W)* 2 RFPR10 0 R/(W)* 1 RFPR9 0 R/(W)* 0 RFPR8 0 R/(W)* Note: * [Setting condition] Only 1 can be written to clear the flag. Rev. 1.00, 03/04, page 431 of 730 13.3.11 Interrupt Register (IRR) IRR is an interrupt status flag register. Bit Bit Name Initial Value 15 14 13 12 11 10 9 8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 0 0 0 0 0 0 0 1 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/(W)* Bit 7 6 5 4 3 2 1 0 Bit Name - - - IRR12 - - IRR9 IRR8 Initial Value 0 0 0 0 0 0 0 0 R/W - - - R/(W)* - - R R/(W)* R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W 15 IRR7 0 R/(W)* Description Overload Frame Interrupt Flag Status flag indicating that the HCAN transmits the overload frame. [Setting condition] When an overload frame is transmitted in error active/passive state [Clearing condition] Writing 1 14 IRR6 0 R/(W)* Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter. [Setting condition] When TEC 256 [Clearing condition] Writing 1 13 IRR5 0 R/(W)* Error Passive Interrupt Flag Status flag indicating the error passive state caused by the transmit/receive error counter. [Setting condition] When TEC 128 or REC 128 [Clearing condition] Writing 1 Rev. 1.00, 03/04, page 432 of 730 Bit Bit Name Initial Value R/W 12 IRR4 0 R/(W)* Description Receive Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the receive error counter. [Setting condition] When REC 96 [Clearing condition] Writing 1 11 IRR3 0 R/(W)* Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter. [Setting condition] When TEC 96 [Clearing condition] Writing 1 10 IRR2 0 R Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a mailbox (buffer). [Setting condition] When remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition] Clearing of all bits in RFPR (remote request register) 9 IRR1 0 R Receive Message Interrupt Flag Status flag indicating that a mailbox (buffer) receive message has been received normally. [Setting condition] When data frame or remote frame reception is completed, when corresponding MBIMR = 0 [Clearing condition] Clearing of all bits in RXPR (receive complete register) Rev. 1.00, 03/04, page 433 of 730 Bit Bit Name Initial Value R/W 8 IRR0 1 R/(W)* Description Reset Interrupt Flag Status flag indicating that the HCAN module has been reset. This bit cannot be masked by the interrupt mask register (IMR). If this bit is not cleared to 0 after entering power-on reset or returning from software standby mode, interrupt processing will start immediately when the interrupt controller enables interrupts. [Setting condition] When the reset operation has finished after entering power-on reset or software standby mode [Clearing condition] Writing 1 7 to 5 All 0 Reserved These bits are always read as 0. The write value should always be 0. 4 IRR12 0 R/(W)* Bus Operation Interrupt Flag Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN sleep mode. [Setting condition] Bus operation (dominant bit) detection in HCAN sleep mode [Clearing condition] Writing 1 3, 2 All 0 Reserved These bits are always read as 0. The write value should always be 0. 1 IRR9 0 R Unread Interrupt Flag Status flag indicating that a receive message has been overwritten before being read. [Setting condition] When UMSR (unread message status register) is set [Clearing condition] Clearing of all bits in UMSR (unread message status register) Rev. 1.00, 03/04, page 434 of 730 Bit Bit Name Initial Value R/W 0 IRR8 0 R/(W)* Description Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox. [Setting condition] When TXPR (transmit wait register) is cleared by completion of transmission or completion of transmission abort [Clearing condition] Writing 1 Note: 13.3.12 Only 1 can be written to clear the flag. * Mailbox Interrupt Mask Register (MBIMR) MBIMR enables or disables interrupt requests by individual mailboxes. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 14 13 12 11 10 9 8 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 435 of 730 Bit Bit Name Initial Value R/W Description 15 MBIMR7 1 R/W Mailbox Interrupt Mask (MBIMRx) 14 MBIMR6 1 R/W 13 MBIMR5 1 R/W 12 MBIMR4 1 R/W When MBIMRn (n = 1 to 15) is cleared to 0, the interrupt request in mailbox n is enabled. When set to 1, the interrupt request is masked. 11 MBIMR3 1 R/W 10 MBIMR2 1 R/W 9 MBIMR1 1 R/W 8 MBIMR0 1 R/W 7 MBIMR15 1 R/W 6 MBIMR14 1 R/W 5 MBIMR13 1 R/W 4 MBIMR12 1 R/W 3 MBIMR11 1 R/W 2 MBIMR10 1 R/W 1 MBIMR9 1 R/W 0 MBIMR8 1 R/W 13.3.13 The interrupt source in a transmit mailbox is TXPR clearing caused by transmission end or transmission cancellation. The interrupt source in a receive mailbox is RXPR setting on reception end. Interrupt Mask Register (IMR) IMR enables or disables interrupt requests by IRR interrupt flags. The reset interrupt flag cannot be masked. Bit Bit Name Initial Value 15 14 13 12 11 10 9 8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 - 1 1 1 1 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R Bit 7 6 5 4 3 2 1 0 Bit Name - - - IMR12 - - IMR9 IMR8 Initial Value 1 1 1 1 1 1 1 1 R/W R R R R/W R R R/W R/W R/W Rev. 1.00, 03/04, page 436 of 730 Bit Bit Name Initial Value R/W 15 IMR7 1 R/W Description Overload Frame Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR7 (OVR0) is enabled. When set to 1, it is masked. 14 IMR6 1 R/W Bus Off Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR6 (ERS0) is enabled. When set to 1, it is masked. 13 IMR5 1 R/W Error Passive Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR5 (ERS0) is enabled. When set to 1, it is masked. 12 IMR4 1 R/W Receive Overload Warning Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR4 (OVR0) is enabled. When set to 1, it is masked. 11 IMR3 1 R/W Transmit Overload Warning Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR3 (OVR0) is enabled. When set to 1, it is masked. 10 IMR2 1 R/W Remote Frame Request Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR2 (OVR0) is enabled. When set to 1, it is masked. 9 IMR1 1 R/W Receive Message Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR1 (RM1) is enabled. When set to 1, it is masked. 8 0 R Reserved This is a read-only bit and cannot be modified. 7 to 5 All 1 R Reserved These are read-only bits and cannot be modified. 4 IMR12 1 R/W Bus Operation Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR12 (OVR0) is enabled. When set to 1, it is masked. Rev. 1.00, 03/04, page 437 of 730 Bit Bit Name Initial Value R/W 3, 2 All 1 R Description Reserved These are read-only bits and cannot be modified. 1 IMR9 1 R/W Unread Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR9 (OVR0) is enabled. When set to 1, it is masked. 0 IMR8 1 R/W Mailbox Empty Interrupt Mask When this bit is cleared to 0, an interrupt request by IRR8 (SLE0) is enabled. When set to 1, it is masked. 13.3.14 Receive Error Counter (REC) REC functions as a counter indicating the number of receive message errors on the CAN bus. The count value is stipulated in the CAN protocol. Bit 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit Name 13.3.15 Transmit Error Counter (TEC) TEC functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol. Bit 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit Name Rev. 1.00, 03/04, page 438 of 730 13.3.16 Unread Message Status Register (UMSR) UMSR indicates that a received message which has not been read is overwritten by a new receive message. In this case, the message which has not been read is lost. Bit Bit Name 15 14 13 12 11 10 9 8 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* 7 6 5 4 3 2 1 0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Initial Value R/W Bit Bit Name Initial Value R/W Note: * Only 1 can be written to these bits, to clear the flags. Bit Bit Name Initial Value R/W Description 15 UMSR7 0 R/(W)* [Setting condition] 14 UMSR6 0 R/(W)* * 13 UMSR5 0 R/(W)* 12 UMSR4 0 R/(W)* [Clearing conditions] 11 UMSR3 0 R/(W)* * Writing 1 10 UMSR2 0 R/(W)* * 9 UMSR1 0 R/(W)* 8 UMSR0 0 R/(W)* When the received message has been overwritten by a new message before being read. 7 UMSR15 0 R/(W)* 6 UMSR14 0 R/(W)* 5 UMSR13 0 R/(W)* 4 UMSR12 0 R/(W)* 3 UMSR11 0 R/(W)* 2 UMSR10 0 R/(W)* 1 UMSR9 0 R/(W)* 0 UMSR8 0 R/(W)* Note: * When a new message is received before RXPR is cleared Only 1 can be written to clear the flag. Rev. 1.00, 03/04, page 439 of 730 13.3.17 Local Acceptance Filter Masks (LAFML, LAFMH) LAFML and LAFMH mask the individual identifier bits of the message to be stored in mailbox 0. For details, refer to section 13.4.4, Message Reception. The relationship between the identifier bits and mask bits are shown in the following. * LAFML Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 14 13 12 11 10 9 8 LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 LAFMH7 LAFMH6 LAFMH5 - - - LAFMH1 LAFMH0 0 0 0 0 0 0 0 0 R/W R/W R/W R R R R/W R/W * LAFMH Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 440 of 730 * LAFML Bit Bit Name Initial Value R/W Description 15 LAFML7 0 R/W When this bit is set to 1, ID-7 of the receive message identifier is not compared. 14 LAFML6 0 R/W When this bit is set to 1, ID-6 of the receive message identifier is not compared. 13 LAFML5 0 R/W When this bit is set to 1, ID-5 of the receive message identifier is not compared. 12 LAFML4 0 R/W When this bit is set to 1, ID-4 of the receive message identifier is not compared. 11 LAFML3 0 R/W When this bit is set to 1, ID-3 of the receive message identifier is not compared. 10 LAFML2 0 R/W When this bit is set to 1, ID-2 of the receive message identifier is not compared. 9 LAFML1 0 R/W When this bit is set to 1, ID-1 of the receive message identifier is not compared. 8 LAFML0 0 R/W When this bit is set to 1, ID-0 of the receive message identifier is not compared. 7 LAFML15 0 R/W When this bit is set to 1, ID-15 of the receive message identifier is not compared. 6 LAFML14 0 R/W When this bit is set to 1, ID-14 of the receive message identifier is not compared. 5 LAFML13 0 R/W When this bit is set to 1, ID-13 of the receive message identifier is not compared. 4 LAFML12 0 R/W When this bit is set to 1, ID-12 of the receive message identifier is not compared. 3 LAFML11 0 R/W When this bit is set to 1, ID-11 of the receive message identifier is not compared. 2 LAFML10 0 R/W When this bit is set to 1, ID-10 of the receive message identifier is not compared. 1 LAFML9 0 R/W When this bit is set to 1, ID-9 of the receive message identifier is not compared. 0 LAFML8 0 R/W When this bit is set to 1, ID-8 of the receive message identifier is not compared. Rev. 1.00, 03/04, page 441 of 730 * LAFMH Bit Bit Name Initial Value R/W Description 15 LAFMH7 0 R/W When this bit is set to 1, ID-20 of the receive message identifier is not compared. 14 LAFMH6 0 R/W When this bit is set to 1, ID-19 of the receive message identifier is not compared. 13 LAFMH5 0 R/W When this bit is set to 1, ID-18 of the receive message identifier is not compared. 12 to 10 All 0 R Reserved These are read-only bits and cannot be modified. 9 LAFMH1 0 R/W When this bit is set to 1, ID-17 of the receive message identifier is not compared. 8 LAFMH0 0 R/W When this bit is set to 1, ID-16 of the receive message identifier is not compared. 7 LAFMH15 0 R/W When this bit is set to 1, ID-28 of the receive message identifier is not compared. 6 LAFMH14 0 R/W When this bit is set to 1, ID-27 of the receive message identifier is not compared. 5 LAFMH13 0 R/W When this bit is set to 1, ID-26 of the receive message identifier is not compared. 4 LAFMH12 0 R/W When this bit is set to 1, ID-25 of the receive message identifier is not compared. 3 LAFMH11 0 R/W When this bit is set to 1, ID-24 of the receive message identifier is not compared. 2 LAFMH10 0 R/W When this bit is set to 1, ID-23 of the receive message identifier is not compared. 1 LAFMH9 0 R/W When this bit is set to 1, ID-22 of the receive message identifier is not compared. 0 LAFMH8 0 R/W When this bit is set to 1, ID-21 of the receive message identifier is not compared. Rev. 1.00, 03/04, page 442 of 730 13.3.18 Message Control (MC0 to MC15) The message control register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message control registers are in RAM, their initial values after power-on are undefined. Be sure to initialize them by writing 0 or 1. Figure 13.2 shows the register names for each mailbox. Mail box 0 MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] Mail box 1 MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] MC1[6] MC1[7] MC1[8] Mail box 2 MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] Mail box 3 MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] Mail box 15 MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] Figure 13.2 Message Control Register Configuration The setting of message control registers are shown below. Figures 13.3 and 13.4 show the correspondence between the identifiers and register bit names. SOF ID-28 ID-27 ID-18 RTR IDE R0 identifier Figure 13.3 Standard Format SOF ID-28 ID-27 ID-18 Standard identifier SRR IDE ID-17 ID-16 ID-0 RTR R1 Extended identifier Figure 13.4 Extended Format Rev. 1.00, 03/04, page 443 of 730 MCx[1] Bit 7 6 5 4 3 2 1 0 Bit Name - - - - DLC3 DLC2 DLC1 DLC0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W MCx[2] Bit Bit Name Initial Value R/W MCx[3] Bit Bit Name Initial Value R/W MCx[4] Bit Bit Name Initial Value R/W MCx[5] Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 ID-20 ID-19 ID-18 RTR IDE - ID-17 ID-16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[6] Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[7] Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W MCx[8] Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W [Legend] x: Mailbox number (0 to 15) Rev. 1.00, 03/04, page 444 of 730 Register Name Bit Bit Name R/W Description MCx[1] 7 to 4 R/W The initial value of these bits is undefined. They must be initialized by writing 0 or 1. 3 to 0 DLC3 to DLC0 R/W Data Length Code Set the data length of a data frame or the data length requested in a remote frame within the range of 0 to 8 bits. 0000: 0 byte 0001: 1 byte 0010: 2 bytes 0011: 3 bytes 0100: 4 bytes 0101: 5 bytes 0110: 6 bytes 0111: 7 bytes 1000: 8 bytes : : 1111: 8 bytes MCx[2] 7 to 0 R/W MCx[3] 7 to 0 R/W MCx[4] 7 to 0 R/W MCx[5] 7 to 5 ID-20 to ID-18 R/W Sets ID-20 to ID-18 in the identifier. 4 RTR R/W Remote Transmission Request The initial value of these bits is undefined; they must be initialized by writing 0 or 1. Used to distinguish between data frames and remote frames. 0: Data frame 1: Remote frame 3 IDE R/W Identifier Extension Used to distinguish between the standard format and extended format of data frames and remote frames. 0: Standard format 1: Extended format 2 R/W The initial value of this bit is undefined. It must be initialized by writing 0 or 1. 1 to 0 ID-17 to ID-16 R/W Sets ID-17 and ID-16 in the identifier. Rev. 1.00, 03/04, page 445 of 730 Register Name Bit Bit Name R/W Description MCx[6] 7 to 0 ID-28 to ID-21 R/W Sets ID-28 to ID-21 in the identifier. MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier. MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier. [Legend] x: Mailbox number 13.3.19 Message Data (MD0 to MD15) The message data register sets consist of eight 8-bit registers for one mailbox. The HCAN has 16 sets of these registers. Because message data registers are in RAM, their initial values after poweron are undefined. Be sure to initialize them by writing 0 or 1. Figure 13.5 shows the register names for each mailbox. Mail box 0 MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] Mail box 1 MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] Mail box 2 MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] Mail box 3 MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] Mail box 15 MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] Figure 13.5 Message Data Configuration Rev. 1.00, 03/04, page 446 of 730 MDx[1] Bit 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Bit Name Initial Value R/W MDx[2] Bit Bit Name Initial Value R/W MDx[3] Bit Bit Name Initial Value R/W MDx[4] Bit Bit Name Initial Value R/W MDx[5] Bit Bit Name Initial Value R/W MDx[6] Bit Bit Name Initial Value R/W MDx[7] Bit Bit Name Initial Value R/W MDx[8] Bit Bit Name Initial Value R/W [Legend] x: Mailbox number (0 to 15) Rev. 1.00, 03/04, page 447 of 730 13.3.20 HCAN Monitor Register (HCANMON) HCANMON enables or disables an HCAN receive interrupt, controls transmission stop of the HTxD pin, and reflects the states of the HCAN pins. Bit 7 6 5 7 7 7 7 7 Bit Name - TxSTP HCANE - - - TxD RxD Initial Value Undefined 0 0 Undefined Undefined Undefined Undefined Undefined - R/W R/W - - - R R R/W Bit Bit Name Initial Value R/W Description 7 Undefined Reserved This bit is always read as undefined value and cannot be modified. 6 TxSTP 0 R/W HTxD Transmission Stop Controls transmission stop of the HTxD pin. 0: Enables transmission from the HTxD pin 1: Fixes an output level of the HTxD pin at 1 and transmission is stopped 5 HCANE 0 R/W HCAN Output Pin Enable 0: P64 is used as an I/O port 1: P64 is used as the HTxD pin. 4 to 2 Undefined Reserved These bits are always read as undefined values and cannot be modified. 1 TxD Undefined R Transmission pin The state of the HTxD pin is read. This bit cannot be modified. 0 RxD Undefined R Reception pin The state of the HRxD pin is read. This bit cannot be modified. Rev. 1.00, 03/04, page 448 of 730 13.4 Operation 13.4.1 Hardware and Software Resets The HCAN can be reset by a hardware reset or software reset. * Hardware Reset At power-on reset or a transition to software standby mode, the HCAN is initialized by automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal registers, except for message control and message data registers, are initialized by a hardware reset. * Software Reset The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In a software reset, the error counters (TEC and REC) are initialized, however other registers are not. If bit MCR0 is set while the CAN controller is performing a communication operation (transmission or reception), the initialization state is not entered until message transfer has been completed. The reset status bit (GSR3) in GSR is set on completion of initialization. 13.4.2 Initialization after Hardware Reset After a hardware reset, the following initialization processing should be carried out: 1. 2. 3. 4. 5. Clearing of bit IRR0 in the interrupt register (IRR) Bit rate setting Mailbox transmit/receive settings Mailbox (RAM) initialization Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode. Configuration mode is a state in which bit GSR3 in GSR is set to 1 by a reset. Configuration mode is exited by clearing bit MCR0 in MCR to 0; when bit MCR0 is cleared to 0, the HCAN automatically clears bit GSR3 in GSR. There is a delay between clearing bit MCR0 and clearing bit GSR3 because the HCAN needs time to be internally reset. After the HCAN exits configuration mode, the power-up sequence begins, and communication with the CAN bus is possible as soon as 11 consecutive recessive bits have been detected. IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery from software standby mode. Since an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0 should be cleared. Rev. 1.00, 03/04, page 449 of 730 Hardware reset : Settings by user : Processing by hardware MCR0 = 1 (automatic) IRR0 = 1 (automatic) GSR3 = 1 (automatic) Initialization of HCAN module Bit configuration mode Period in which BCR, MBCR, etc., are initialized Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization MCR0 = 0 GSR3 = 0? No Yes IMR setting (interrupt mask setting) MBIMR setting (interrupt mask setting) MC[x] setting (receive identifier setting) LAFM setting (receive identifier mask setting) GSR3 = 0 & 11 recessive bits received? No Yes Can bus communication enabled Figure 13.6 Hardware Reset Flowchart Rev. 1.00, 03/04, page 450 of 730 MCR0 = 1 : Settings by user Bus idle? No : Processing by hardware Yes GSR3 = 1 (automatic) Initialization of REC and TEC only Correction BCR setting MBCR setting Mailbox (RAM) initialization Message transmission method initialization OK? No Yes GSR3 = 1? No Yes MCR0 = 0 GSR3 = 0? No Yes Correction IMR setting MBIMR setting MC[x] setting LAFM setting OK? No Yes GSR3 = 0 & 11 recessive bits received? No Yes CAN bus communication enabled Figure 13.7 Software Reset Flowchart Rev. 1.00, 03/04, page 451 of 730 Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit configuration register (BCR). Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the settable time quanta (tq). 1-bit time (8-25 time quanta) SYNC_SEG PRSEG PHSEG1 PHSEG2 Time segment 2 (TSEG2) Time segment 1 (TSEG1) 1 time quanta 2-16 time quanta Figure 13.8 Detailed Description of One Bit SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer segment for correcting phase drift (negative). This segment is shortened when synchronization (resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in table 13.2. Table 13.2 Limits for the Settable Value Name Time segment 1 Abbreviation TSEG1 Min. Value B'0011* 2 3 Max. Value B'1111 Time segment 2 TSEG2 B'001* B'111 Baud rate prescaler BRP B'000000 B'111111 Bit sample point BSP B'0 B'1 Re-synchronization jump width SJW*1 B'00 B'11 Notes: 1. SJW is stipulated in the CAN specifications: 3 SJW 0 2. The minimum value of TSEG2 is stipulated in the CAN specifications: TSEG2 SJW 3. The minimum value of TSEG1 is stipulated in the CAN specifications: TSEG1 > TSEG2 Rev. 1.00, 03/04, page 452 of 730 Time quanta (tq) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. fCLK is the system clock frequency. tq = 2 x (BPR setting + 1)/fCLK The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = tq x (3 + TSEG1 + TSEG2) Bit rate = 1/Bit time = fCLK/{2 x (BPR setting + 1) x (3 + TSEG1 + TSEG2)} Note: fCLK = (system clock) A BCR value is used for BRP, TSEG1, and TSEG2. Example: With a system clock of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of B'0100, and a TSEG2 setting of B'011: Bit rate = 20/{2 x (0 + 1) x (3 + 4 + 3)} = 1 Mbps Table 13.3 Setting Range for TSEG1 and TSEG2 in BCR TSEG2 (BCR14 to BCR12) TSEG1 (BCR11 to BCR8) 001 010 011 100 101 110 111 0011 No Yes No No No No No 0100 Yes* Yes Yes No No No No 0101 Yes* Yes Yes Yes No No No 0110 Yes* Yes Yes Yes Yes No No 0111 Yes* Yes Yes Yes Yes Yes No 1000 Yes* Yes Yes Yes Yes Yes Yes 1001 Yes* Yes Yes Yes Yes Yes Yes 1010 Yes* Yes Yes Yes Yes Yes Yes 1011 Yes* Yes Yes Yes Yes Yes Yes 1100 Yes* Yes Yes Yes Yes Yes Yes 1101 Yes* Yes Yes Yes Yes Yes Yes 1110 Yes* Yes Yes Yes Yes Yes Yes 1111 Yes* Yes Yes Yes Yes Yes Yes Notes: The time quantum values for TSEG1 and TSEG2 are determined by TSEG value + 1. * Settable when bits BRP13 to BRP8 are not B'000000. Rev. 1.00, 03/04, page 453 of 730 Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only, while mailboxes 1 to 15 can be set for transmission or reception. The initial status of mailboxes 1 to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset. Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding mailbox for reception use. When setting mailboxes for reception, in order to improve message reception efficiency, high-priority messages should be set in low-to-high mailbox order. Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and so their initial values are undefined after power is supplied. Initial values must therefore be set in all the mailboxes (by writing 0s or 1s). Setting the Message Transmission Method: The following two kinds of message transmission methods are available. * Transmission order determined by message identifier priority * Transmission order determined by mailbox number priority Either of the message transmission methods can be selected with the message transmission method bit (MCR2) in the master control register (MCR): When messages are set to be transmitted according to the message identifier priority, if several messages are designated as waiting for transmission (TXPR = 1), the message with the highest priority in the message identifier is stored in the transmit buffer. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. When the TXPR bit is set, the highest-priority message is found and stored in the transmit buffer. When messages are set to be transmitted according to the mailbox number priority, if several messages are designated as waiting for transmission (TXPR = 1), messages are stored in the transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the message stored in the transmit buffer, and the message is transmitted when the transmission right is acquired. Rev. 1.00, 03/04, page 454 of 730 13.4.3 Message Transmission Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings is described below, and a transmission flowchart is shown in figure 13.9. Initialization (after hardware reset only) Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method setting : Settings by user : Processing by hardware Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle? No Yes Message transmission GSR2 = 0 (during transmission only) Transmission completed? No Yes TXACK = 1 IRR8 = 1 IMR8 = 1? Yes No Interrupt to CPU Clear TXACK Clear IRR8 End of transmission Figure 13.9 Transmission Flowchart Rev. 1.00, 03/04, page 455 of 730 CPU interrupt source settings: The CPU interrupt source is set by the interrupt mask register (IMR) and mailbox interrupt mask register (MBIMR). Transmission acknowledge and transmission abort acknowledge interrupts can be generated for individual mailboxes in the mailbox interrupt mask register (MBIMR). Arbitration field setting: The arbitration field is set by the message control registers MCx[5] to MCx[8] in a transmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and the RTR bit are set, and the IDE bit is cleared to 0. For an extended format, a 29-bit identifier (ID-28 to ID-0) and the RTR bit are set, and the IDE bit is set to 1. Control field setting: In the control field, the byte length of the data to be transmitted is set within the range of zero to eight bytes. The register to be set is the message control register MCx[1] in a transmit mailbox. Data field setting: In the data field, the data to be transmitted is set within the range zero to eight. The registers to be set are the message data registers MDx[1] to MDx[8]. The byte length of the data to be transmitted is determined by the data length code in the control field. Even if data exceeding the value set in the control field is set in the data field, up to the byte length set in the control field will actually be transmitted. Message transmission: If the corresponding mailbox transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) is set to 1 after message control and message data registers have been set, the message enters transmit wait state. If the message is transmitted error-free, the corresponding acknowledge bit (TXACK1 to TXACK15) in the transmit acknowledge register (TXACK) is set to 1, and the corresponding transmit wait bit (TXPR1 to TXPR15) in the transmit wait register (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. If transmission of a transmit message is aborted in the following cases, the message is retransmitted automatically: * CAN bus arbitration failure (failure to acquire the bus) * Error during transmission (bit error, stuff error, CRC error, frame error, or ACK error) Rev. 1.00, 03/04, page 456 of 730 Message transmission cancellation: Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the bit for the corresponding mailbox (TXCR1 to TXCR15) to 1 in the transmit cancel register (TXCR). Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is set to 1 in the abort acknowledge register (ABACK), and then an interrupt to the CPU can be requested. Also, if the corresponding bit (MBIMR1 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU. However, a transmit wait message cannot be canceled at the following times: * During internal arbitration or CAN bus arbitration * During data frame or remote frame transmission Figure 13.10 shows a flowchart for transmit message cancellation. Message transmit wait TXPR setting : Settings by user : Processing by hardware Set TXCR bit corresponding to message to be canceled No Cancellation possible? Yes Completion of message transmission TXACK = 1 Clear TXCR, TXPR IRR8 = 1 Message not sent Clear TXCR, TXPR ABACK = 1 IRR8 = 1 IMR8 = 1? Yes No Interrupt to CPU Clear TXACK Clear ABACK Clear IRR8 End of transmission/transmission cancellation Figure 13.10 Transmit Message Cancellation Flowchart Rev. 1.00, 03/04, page 457 of 730 13.4.4 Message Reception The reception procedure after initial settings is described below. A reception flowchart is shown in figure 13.11. Initialization : Settings by user Clear IRR0 BCR setting MBCR setting Mailbox (RAM) initialization : Processing by hardware Interrupt settings Receive data setting Arbitration field setting Local acceptance filter settings Message reception (Match of identifier in mailbox?) No Yes Yes Same RXPR = 1? Unread message No Data frame? No Yes RXPR IRR1 = 1 RXPR, RFPR = 1 IRR2 = 1, IRR1 = 1 Yes IMR1 = 1? IMR2 = 1? No No Interrupt to CPU Interrupt to CPU Message control read Message data read Message control read Message data read Clear IRR1 Clear IRR2, IRR1 Transmission of data frame corresponding to remote frame End of reception Figure 13.11 Reception Flowchart Rev. 1.00, 03/04, page 458 of 730 Yes CPU interrupt source settings: CPU interrupt source settings are made in the interrupt mask register (IMR) and mailbox interrupt register (MBIMR). The message to be received is also specified. Data frame and remote frame receive wait interrupt requests can be generated for individual mailboxes in the MBIMR. Arbitration field setting: To receive a message, the message identifier must be set in advance in the message control registers (MCx[1] to MCx[8]) for the receiving mailbox. When a message is received, all the bits in the receive message identifier are compared with those in each message control register identifier, and if a complete match is found, the message is stored in the matching mailbox. Mailbox 0 has a local acceptance filter mask (LAFM) that allows Don't Care settings. The LAFM setting can be made only for mailbox 0. By setting the Don't Care for all the bits in the receive message identifier, messages of multiple identifiers can be received. Examples: * When the identifier of mailbox 1 is 010_1010_1010 (standard format), only one kind of message identifier can be received by mailbox 1: Identifier 1: 010_1010_1010 * When the identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is 000_0000_0011 (0: Care, 1: Don't Care), a total of four kinds of message identifiers can be received by mailbox 0: Identifier 1: 010_1010_1000 Identifier 2: 010_1010_1001 Identifier 3: 010_1010_1010 Identifier 4: 010_1010_1011 Message reception: When a message is received, a CRC check is performed automatically. If the result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether the message can be received or not. * Data frame reception If the received message is confirmed to be error-free by the CRC check, the identifier in the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive message are compared. If a complete match is found, the message is stored in the matching mailbox. The message identifier comparison is carried out on each mailbox in turn, starting with mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at that point, the message is stored in the matching mailbox, and the corresponding receive complete bit (RXPR0 to RXPR15) in the receive complete register (RXPR) is set. However, if the identifier matches that of mailbox 0 LAFM, the mailbox comparison sequence does not end at that point, but continues from mailbox 1. Therefore, the message for mailbox 0 can also be received by another mailbox. Note that the same message cannot be stored in two or more mailbox of the mailboxes 1 to 15. On receiving a message, a CPU interrupt request Rev. 1.00, 03/04, page 459 of 730 may be generated according to the settings of the mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR). * Remote frame reception A mailbox can store two kinds of messages: data frames and remote frames. A remote frame differs from a data frame in the value of the remote transmission request bit (RTR) in the message control register and its 0-byte data field. The data length to be returned in a data frame must be stored in the data length code (DLC) in the message control. When a remote frame (RTR = recessive) is received, the corresponding bit in the remote request wait register (RFPR) is set. Interrupts can be sent to the CPU according to the settings of the corresponding bit (MBIMR0 to MBIMR15) in the mailbox interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the interrupt mask register (IMR). Unread message overwrite: If the receive message identifier matches the mailbox identifier, the receive message is stored in the mailbox regardless of whether the mailbox contains an unread message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR15) in the unread message register (UMSR) is set. In overwriting an unread message, the unread message register (UMSR) is set when a new message is received before the corresponding bit in the receive complete register (RXPR) has been cleared. If the unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU. Figure 13.12 shows a flowchart for unread message overwriting. : Settings by user Unread message overwrite : Processing by hardware UMSR = 1 IRR9 = 1 IMR9 = 1? Yes No Interrupt to CPU Clear IRR9 Message control/message data read End Figure 13.12 Unread Message Overwrite Flowchart Rev. 1.00, 03/04, page 460 of 730 13.4.5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption. Figure 13.13 shows a flowchart of the HCAN sleep mode. MCR5 = 1 Bus idle? No Initialize TEC and REC No Bus operation? Yes IRR12 = 1 No IMR12 = 1? During this time, do not access any Mailbox. CPU interrupt Yes Sleep mode clearing method MCR7 = 0? No (automatic) Yes (manual) Clear sleep mode? No GSR3 = 1? No Yes No GSR3 = 1? Yes Yes MCR5 = 0 MCR5 = 0 11 recessive bits received? No Yes : Settings by user CAN bus communication possible : Processing by hardware Figure 13.13 HCAN Sleep Mode Flowchart Rev. 1.00, 03/04, page 461 of 730 HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is delayed until the bus becomes idle. Either of the following methods of clearing HCAN sleep mode can be selected: * Clearing by software * Clearing by CAN bus operation In order to re-enter CAN bus communication enabled state, eleven recessive bits must be received after HCAN sleep mode was cleared. Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU. Clearing by CAN bus operation: The cancellation method is selected by bit MCR7 setting in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected. In this case, the first message is not stored in a mailbox; messages will be received normally from the second message onward. When a change is detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to enable interrupts at this time, an interrupt can be sent to the CPU. 13.4.6 HCAN Halt Mode The HCAN halt mode is provided to enable mailbox settings to be changed without performing an HCAN hardware or software reset. Figure 13.14 shows a flowchart of the HCAN halt mode. MCR1 = 1 Bus idle? No Yes Set MBCR MCR1 = 0 : Settings by user CAN bus communication possible : Processing by hardware Figure 13.14 HCAN Halt Mode Flowchart Rev. 1.00, 03/04, page 462 of 730 HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until the bus becomes idle. HCAN halt mode is cleared by clearing MCR1 to 0. 13.5 Interrupt Sources Table 13.4 lists the HCAN interrupt sources. These sources can be masked except the reset processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER). For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller. Table 13.4 HCAN Interrupt Sources Name Description Interrupt DMAC Flag Activation ERS0/OVR0 Error passive interrupt (TEC 128 or REC 128) IRR5 Bus off interrupt (TEC 256) IRR6 Reset processing interrupt by power-on reset IRR0 Remote frame reception IRR2 Error warning interrupt (TEC 96) IRR3 Not possible Error warning interrupt (REC 96) IRR4 Overload frame transmission interrupt IRR7 Unread message overwrite IRR9 Detection of CAN bus operation in HCAN sleep mode IRR12 RM0 Mailbox 0 message reception IRR1 Possible RM1 Mailbox 1-15 message reception IRR1 Not possible SLE0 Message transmission/cancellation IRR8 Not possible Rev. 1.00, 03/04, page 463 of 730 13.6 DMAC Interface The DMAC can be activated by the reception of a message in HCAN mailbox 0. When the DMAC activation is set and DMAC transfer ends, flags RXPR0 and RFPR0 are automatically cleared. An interrupt request is not sent to the CPU by a reception interrupt from the HCAN. Figure 13.15 shows a DMAC transfer flowchart. : Settings by user DMAC initialization Activation source, source address, destination address, transfer count, and : Processing by hardware Message reception in HCAN's mailbox 0 DMAC activation End of DMAC transfer? No Yes DMAC transfer end bit setting RXPR and RFPR clearing DMAC interrupt enable = 1? No Yes Interrupt to CPU DMAC interrupt flag clearing End Figure 13.15 DMAC Transfer Flowchart Rev. 1.00, 03/04, page 464 of 730 13.7 CAN Bus Interface A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Philips PCA82C250 transceiver IC is recommended. If any other product is used, confirm that it is compatible with the PCA82C250. Figure 13.16 shows a sample connection diagram. 124 This LSI Vcc PCA82C250 RS Vcc HRxD RxD CANH HTxD TxD CANL Vref CAN bus GND NC 124 Note: NC: No Connection Figure 13.16 High-Speed Interface Using PCA82C250 13.8 Usage Notes 13.8.1 Module Stop Mode Setting HCAN operation can be disabled or enabled using the module stop control register. The HCAN operation is set to be halted initially. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 13.8.2 Reset The HCAN is initialized by a power-on reset and a transition to software standby mode. All the registers are initialized by a reset, however mailboxes (message control (MCx[x])/message data (MDx[x])) are not initialized. Mailboxes (message control (MCx[x])/message data (MDx[x])) are initialized after power-on and at this time, their initial values are undefined. Therefore, always initialize mailboxes after a power-on reset or a transition to software standby mode. After a poweron reset or recovery from software standby mode, the reset interrupt flag (IRR0) is automatically set. Since this bit cannot be masked in the interrupt mask register (IMR), an HCAN interrupt will be initiated immediately after an HCAN interrupt is enabled by the interrupt controller without clearing the flag. IRR0 should therefore be cleared at initialization. Rev. 1.00, 03/04, page 465 of 730 13.8.3 HCAN Sleep Mode The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even in sleep mode. 13.8.4 Interrupts When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are not set by reception completion, transmission completion, or transmission cancellation of the set mailboxes. 13.8.5 Error Counters In the case of error active and error passive, REC and TEC perform count up and down normally. In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC reaches 96 during the count, IRR4 and GSR1 are set. 13.8.6 Register Access Byte or word access can be performed for all HCAN registers. Longword access should be avoided. 13.8.7 Register Hold in Standby Modes All HCAN registers are initialized in hardware standby mode and software standby mode. 13.8.8 Use on Bit Manipulation Instructions Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared. Rev. 1.00, 03/04, page 466 of 730 13.8.9 1. HCAN TXCR Operation When the transmit wait cancel register (TXCR) is used to cancel a transmit wait message in a transmit wait mailbox, the corresponding bit to TXCR and the transmit wait register (TXPR) may not be cleared even if transmission is canceled. This occurs when the following conditions are all satisfied. * The HRxD pin is stacked to 1 because of a CAN bus error, etc. * There is at least one mailbox waiting for transmission or being transmitted. * The message transmission in a mailbox being transmitted is canceled by TXCR. If this occurs, transmission is canceled. However, since TXPR and TXCR states are indicated wrongly that a message is being cancelled, transmission cannot be restarted even if the stack state of the HRxD pin is canceled and the CAN bus recovers the normal state. If there are at least two transmission messages, a message which is not being transmitted is canceled and a message being transmitted retains its state. * To avoid this, one of the following countermeasures must be executed. Transmission must not be canceled by TXCR. When transmission is normally completed after the CAN bus has recovered, TXPR is cleared and the HCAN recovers the normal state. * To cancel transmission, the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0. TXPR and TXCR are cleared and the HCAN recovers the normal state. 2. When the bus-off state is entered while TXPR is set and the transmit wait state is entered, the internal state machine does not operate even if TXCR is set during the bus-off state. Therefore transmission cannot be canceled. The message can be canceled when one message is transmitted or a transmission error occurs after the bus-off state is recovered. To clear a message after the bus-off state is recovered, the following countermeasure must be executed. * A transmit wait message must be cleared by resetting the HCAN during the bus-off period. To reset the HCAN, the module stop bit (MSTPC11 in MSTPCRC) must be set or cleared. In this case, the HCAN is entirely reset. Therefore the initial settings must be made again. Rev. 1.00, 03/04, page 467 of 730 13.8.10 HCAN Transmission Setting With the following conditions satisfied, a previous message identifier (ID) may be collapsed when the next transmission is set or transmission is canceled within 50 s after the previous transmission has been set in the bus idle state. * When the message set at the second transmission setting has priority over the message set at the first transmission setting * When the message canceled at the first transmission setting has priority over any messages The following settings should be performed so that a message ID is not collapsed. * Transmission setting should be performed at a time. The next transmission setting should be set at least 50 s after completion of transmission of all messages (en bloc transmission). * Transmission setting should be performed according to the priority. * Sufficient duration should be taken between transmission setting or cancellation: setting TXPR and setting TXPR or setting TXPR and setting TXCR. Table 13.5 Duration between Transmission Setting Baud Rate (bps) Setting Interval (s) 1M 50 500 k 50 250 k 50 13.8.11 Canceling HCAN Reset and HCAN Sleep Mode Before canceling an HCAN software reset or HCAN sleep mode (clearing bit MCR0 or MCR5 to 0), confirm that the reset status bit (GSR3) has been set to 1. 13.8.12 Accessing Mailbox in HCAN Sleep Mode Do not access any Mailbox in HCAN sleep mode. When the access is attempted, the CPU may stop operating. Accessing registers does not cause the CPU to halt. Accessing a Mailbox in other than HCAN sleep mode does not cause the CPU to halt. Rev. 1.00, 03/04, page 468 of 730 Section 14 Synchronous Serial Communication Unit (SSU) This LSI has three independent synchronous serial communication unit (SSU) channels. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase. Figure 14.1 is a block diagram of the SSU. 14.1 * * * * * * * * * * * Features Choice of SSU mode and clock synchronous mode Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8/16/32-bit width of transmit/receive data Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously. Consecutive serial communication Choice of LSB-first or MSB-first transfer Choice of a clock source P/4, P/8, P/16, P/32, P/64, P/128, P/256, or an external clock Five interrupt sources transmit-end, transmit-data-register-empty, receive-data-full, overrun-error, and conflict error Module stop mode can be set SCISSU0A_000120020900 Rev. 1.00, 03/04, page 469 of 730 Module data bus SSCRH Bus interface Figure 14.1 shows a block diagram of the SSU. Internal data bus SSRDR 0 SSCRL OEI SSTDR 1 SSRDR 1 SSMR CEI SSTDR 2 SSRDR 2 SSER RXI SSRDR 3 SSSR TXI Control circuit TEI SSTDR 0 SSTDR 3 Clock Clock selector Shiftin Shiftout SSTRSR P P/4 P/8 P/16 P/32 P/64 P/128 P/256 Selector SSI [Legend] SSCRH: SSCRL: SSCR2: SSMR: SSER: SSSR: SSTDR0 to SSTDR3: SSRDR0 to SSRDR3: SSTRSR: SSO SCS SSCK (External clock) SS control register H SS control register L SS control register 2 SS mode register SS enable register SS status register SS transmit data registers 0 to 3 SS receive data registers 0 to 3 SS shift register Figure 14.1 Block Diagram of SSU Rev. 1.00, 03/04, page 470 of 730 14.2 Input/Output Pins Table 14.1 shows the SSU pin configuration. Table 14.1 Pin Configuration Channel Abbr.* I/O Function 0 SSCK0 I/O Channel 0 SSU clock input/output SSI0 I/O Channel 0 SSU data input/output SSO0 I/O Channel 0 SSU data input/output SCS0 I/O Channel 0 SSU chip select input/output SSCK1 I/O Channel 1 SSU clock input/output SSI1 I/O Channel 1 SSU data input/output SSO1 I/O Channel 1 SSU data input/output SCS1 I/O Channel 1 SSU chip select input/output SSCK2 I/O Channel 2 SSU clock input/output SSI2 I/O Channel 2 SSU data input/output SSO2 I/O Channel 2 SSU data input/output SCS2 I/O Channel 2 SSU chip select input/output 1 2 Note: * Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS. Rev. 1.00, 03/04, page 471 of 730 14.3 Register Descriptions The SSU has the following registers. (1) Channel 0 * * * * * * * * * * * * * * * SS control register H_0 (SSCRH_0) SS control register L_0 (SSCRL_0) SS mode register_0 (SSMR_0) SS enable register_0 (SSER_0) SS status register_0 (SSSR_0) SS control register 2_0 (SSCR2_0) SS transmit data register 0_0 (SSTDR0_0) SS transmit data register 1_0 (SSTDR1_0) SS transmit data register 2_0 (SSTDR2_0) SS transmit data register 3_0 (SSTDR3_0) SS receive data register 0_0 (SSRDR0_0) SS receive data register 1_0 (SSRDR1_0) SS receive data register 2_0 (SSRDR2_0) SS receive data register 3_0 (SSRDR3_0) SS shift register_0 (SSTRSR_0) (2) Channel 1 * * * * * * * * * * * * * * * SS control register H_1 (SSCRH_1) SS control register L_1 (SSCRL_1) SS mode register_1 (SSMR_1) SS enable register_1 (SSER_1) SS status register_1 (SSSR_1) SS control register 2_1 (SSCR2_1) SS transmit data register 0_1 (SSTDR0_1) SS transmit data register 1_1 (SSTDR1_1) SS transmit data register 2_1 (SSTDR2_1) SS transmit data register 3_1 (SSTDR3_1) SS receive data register 0_1 (SSRDR0_1) SS receive data register 1_1 (SSRDR1_1) SS receive data register 2_1 (SSRDR2_1) SS receive data register 3_1 (SSRDR3_1) SS shift register_1 (SSTRSR_1) Rev. 1.00, 03/04, page 472 of 730 (3) Channel 2 * * * * * * * * * * * * * * * SS control register H_2 (SSCRH_2) SS control register L_2 (SSCRL_2) SS mode register_2 (SSMR_2) SS enable register_2 (SSER_2) SS status register_2 (SSSR_2) SS control register 2_2 (SSCR2_2) SS transmit data register 0_2 (SSTDR0_2) SS transmit data register 1_2 (SSTDR1_2) SS transmit data register 2_2 (SSTDR2_2) SS transmit data register 3_2 (SSTDR3_2) SS receive data register 0_2 (SSRDR0_2) SS receive data register 1_2 (SSRDR1_2) SS receive data register 2_2 (SSRDR2_2) SS receive data register 3_2 (SSRDR3_2) SS shift register_2 (SSTRSR_2) Rev. 1.00, 03/04, page 473 of 730 14.3.1 SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. 7 6 5 4 3 2 1 0 MSS BIDE - SOL SOLP SCKS CSS1 CSS0 Bit Bit Name 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 7 MSS 0 R/W Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected. 6 BIDE 0 R/W Bidirectional Mode Enable Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00, 03/04, page 474 of 730 Bit Bit Name Initial Value R/W Description 4 SOL 0 R/W Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high. 3 SOLP 1 R/W SOL Bit Write Protect When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1. 2 SCKS 0 R/W SSCK Pin Select Selects that the SSCK pin functions as a port or a serial clock pin. When the SSCK pin is used as a serial clock pin, this bit must be set to 1. 0: Functions as an I/O port. 1: Functions as a serial clock. 1 CSS1 0 R/W SCS Pin Select 0 CSS0 0 R/W Select that the SCS pin functions as a port or SCS input or output. However, when MSS = 0, the SCS pin functions as an input pin regardless of the CSS1 and CSS0 settings. 00: I/O port 01: Function as SCS input 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer) Rev. 1.00, 03/04, page 475 of 730 14.3.2 SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. 7 6 5 Bit Name - SSUMS SRES - Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Bit R/W 4 Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved 3 2 1 0 - - DATS1 DATS0 0 0 0 0 R/W R/W R/W This bit is always read as 0. The write value should always be 0. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode. 0: SSU mode 1: Clock synchronous mode 5 SRES 0 R/W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 1 DATS1 0 R/W Transmit/Receive Data Length Select 0 DATS0 0 R/W Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited Rev. 1.00, 03/04, page 476 of 730 14.3.3 SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. 7 6 5 4 3 2 1 0 MLS CPOS CPHS - - CKS2 CKS1 CKS0 Bit Bit Name 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first 6 CPOS 0 R/W 5 CPHS 0 R/W 4, 3 All 0 R/W 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Polarity Select Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode Clock Phase Select (Only for SSU Mode) Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge. Reserved These bits are always read as 0. The write value should always be 0. Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved 001: P/4 010: P/8 011: P/16 100: P/32 101: P/64 110: P/128 111: P/256 Rev. 1.00, 03/04, page 477 of 730 14.3.4 SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. 7 6 5 4 3 2 1 0 TE RE - - TEIE TIE RIE CEIE Bit Bit Name 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W Bit Bit Name Initial Value R/W Description 7 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. 6 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. 5, 4 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 3 TEIE 0 R/W Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 2 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI interrupt request and an OEI interrupt request are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled. Rev. 1.00, 03/04, page 478 of 730 14.3.5 SS Status Register (SSSR) SSSR is a status flag register for interrupts. 7 6 Bit Name - ORER Initial Value 0 0 R/W R/W R/W Bit R/W 5 4 3 2 1 0 - - TEND TDRE RDRF CE 0 0 0 1 0 0 R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0. The write value should always be 0. 6 ORER 0 R/W Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition] When one byte of the next reception is completed with RDRF = 1 [Clearing condition] When writing 0 after reading ORER = 1 5, 4 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 3 TEND 1 R Transmit End [Setting condition] * When the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is cleared to 0 and the TDRE bit is set to 1 * After the last bit of transmit data is transmitted while the TENDSTS bit in SSCR2 is set to 1 and the TDRE bit is set to 1 [Clearing conditions] * When writing 0 after reading TEND = 1 * When writing data to SSTDR Rev. 1.00, 03/04, page 479 of 730 Bit Bit Name Initial Value R/W 2 TDRE 1 R/W Description Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] * When the TE bit in SSER is 0 * When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to. [Clearing conditions] 1 RDRF 0 R/W * When writing 0 after reading TDRE = 1 * When writing data to SSTDR with TE = 1 Receive Data Register Full Indicates whether or not SSRDR contains receive data. [Setting condition] * When receive data is transferred from SSTRSR to SSRDR after successful serial data reception [Clearing conditions] 0 CE 0 R/W * When writing 0 after reading RDRF = 1 * When reading receive data from SSRDR Conflict/Incomplete Error Indicates that a conflict error has occurred when 0 is externally input to the SCS pin with SSUMS = 0 (SSU mode) and MSS = 1 (master mode). If the SCS pin level changes to 1 with SSUMS = 0 (SSU mode) and MSS = 0 (slave mode), an incomplete error occurs because it is determined that a master device has terminated the transfer. Data reception does not continue while the CE bit is set to 1. Serial transmission also does not continue. Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error. [Setting condition] * When a low level is input to the SCS pin in master mode (the MSS bit in SSCRH is set to 1) * When the SCS pin is changed to 1 during transfer in slave mode (the MSS bit in SSCRH is cleared to 0) [Clearing condition] * Rev. 1.00, 03/04, page 480 of 730 When writing 0 after reading CE = 1 14.3.6 SS Control Register 2 (SSCR2) SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit. 7 6 5 4 3 2 1 0 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS - - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Description 7 SDOS 0 R/W Serial Data Pin Open Drain Select Selects whether the serial data output pin is used as a CMOS or an NMOS open drain output. Pins to output serial data differ according to the register setting. For details, 14.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: CMOS output 1: NMOS open drain output 6 SSCKOS 0 R/W SSCK Pin Open Drain Select Selects whether the SSCK pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 5 SCSOS 0 R/W SCS Pin Open Drain Select Selects whether the SCS pin is used as a CMOS or an NMOS open drain output. 0: CMOS output 1: NMOS open drain output 4 TENDSTS 0 R/W Selects the timing of setting the TEND bit (valid in SSU and master mode). 0: Sets the TEND bit when the last bit is being transmitted 1: Sets the TEND bit after the last bit is transmitted 3 SCSATS 0 R/W Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 x tSUcyc 1: Min. values of tLEAD and tLAG are 3/2 x tSUcyc Rev. 1.00, 03/04, page 481 of 730 Bit Bit Name Initial Value R/W Description 2 SSODTS 0 R/W Selects the data output timing of the SSO pin (valid in SSU and master mode) 0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data 1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE = 1, TE = 1, and RE = 0, the SSO pin outputs data while the SCS pin is driven low 1, 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 1.00, 03/04, page 482 of 730 14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, the SSU performs consecutive serial transmission. Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in SSSR is set to 1. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 483 of 730 14.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR function as a double buffer in this way, consecutive receive operations can be performed. Read SSRDR after confirming that the RDRF bit in SSSR is set to 1. SSRDR is a read-only register, therefore, cannot be written to by the CPU. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R 14.3.9 SS Shift Register (SSTRSR) SSTRSR is a shift register that transmits and receives serial data. When data is transferred from SSTDR to SSTRSR, bit 0 of transmit data is bit 0 in the SSTDR contents (MLS = 0: LSB first communication) and is bit 7 in the SSTDR contents (MLS = 1: MSB first communication). The SSU transfers data from the LSB (bit 0) in SSTRSR to the SSO pin to perform serial data transmission. In reception, the SSU sets serial data that has been input via the SSI pin in SSTRSR from the LSB (bit 0). When 1-byte data has been received, the SSTRSR contents are automatically transferred to SSRDR. SSTRSR cannot be directly accessed by the CPU. Rev. 1.00, 03/04, page 484 of 730 14.4 Operation 14.4.1 Transfer Clock A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin. When transfer is started, the clock with the transfer rate set by bits CKS2 to CKS0 in SSMR is output from the SSCK pin. When MSS = 0, an external clock is selected and the SSCK pin is used as an input pin. 14.4.2 Relationship of Clock Phase, Polarity, and Data The relationship of clock phase, polarity, and transfer data depends on the combination of the CPOS and CPHS bits in SSMR. Figure 14.2 shows the relationship. When SSUMS = 1, the CPHS setting is invalid although the CPOS setting is valid. Setting the MLS bit in SSMR selects that MSB or LSB first communication. When MLS = 0, data is transferred from the LSB to the MSB. When MLS = 1, data is transferred from the MSB to the LSB. (1) When CPHS = 0 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (2) When CPHS = 1 SCS SSCK (CPOS = 0) SSCK (CPOS = 1) SSI, SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 14.2 Relationship of Clock Phase, Polarity, and Data Rev. 1.00, 03/04, page 485 of 730 14.4.3 Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 14.3 show the relationship. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with BIDE = 0 and MSS = 1 (standard, master mode) (see figure 14.3 (1)). The SSU transmits serial data from the SSI pin and receives serial data from the SSO pin when operating with BIDE = 0 and MSS = 0 (standard, slave mode) (see figure 14.3 (2)). The SSU transmits and receives serial data from the SSO pin regardless of master or slave mode when operating with BIDE = 1 (bidirectional mode) (see figures 14.3 (3) and (4)). However, even if both the TE and RE bits are set to 1, transmission and reception are not performed simultaneously. Either the TE or RE bit must be selected. The SSU transmits serial data from the SSO pin and receives serial data from the SSI pin when operating with SSUMS = 1. The SSCK pin outputs the internal clock when MSS = 1 and function as an input pin when MSS = 0 (see figures 14.3 (5) and (6)). (1) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 1, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSO (2) When SSUMS = 0, BIDE = 0 (standard mode), MSS = 0, TE = 1, and RE = 1 SSCK Shift register (SSTRSR) SSI SSI (4) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 1, and either TE or RE = 1 SSCK Shift register (SSTRSR) SSO (3) When SSUMS = 0, BIDE = 1 (bidirectional mode), MSS = 0, and either TE or RE = 1 SSCK Shift register (SSTRSR) (6) When SSUMS = 1 and MSS = 0 SSCK SSCK Shift register (SSTRSR) SSO SSI SSI (5) When SSUMS = 1 and MSS = 1 SSO SSO SSI Shift register (SSTRSR) SSO SSI Figure 14.3 Relationship between Data Input/Output Pins and the Shift Register Rev. 1.00, 03/04, page 486 of 730 14.4.4 Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, set the corresponding bit in the input buffer control register (ICR) to 1. The relationship of communication modes and input/output pin functions are shown in tables 14.2 to 14.4. Table 14.2 Communication Modes and Pin States of SSI and SSO Pins Communication Mode SSU communication mode Register Setting Pin State SSUMS BIDE MSS TE RE SSI SSO 0 0 0 0 1 Input 1 0 Output 1 Output Input 0 1 Input 1 0 Output 1 Input Output 1 Input 1 SSU (bidirectional) 0 communication mode Clock synchronous 1 communication mode 1 0 0 0 1 0 Output 1 0 1 Input 1 0 Output 0 1 Input 1 0 Output 1 Input Output 0 1 Input 1 0 Output 1 Input Output 0 1 [Legend] : Not used as SSU pin Rev. 1.00, 03/04, page 487 of 730 Table 14.3 Communication Modes and Pin States of SSCK Pin Communication Mode SSU communication mode Register Setting Pin State SSUMS MSS SCKS SSCK 0 0 0 1 Input 0 1 Clock synchronous 1 communication mode 0 1 1 Output 0 1 Input 0 1 Output [Legend] : Not used as SSU pin Table 14.4 Communication Modes and Pin States of SCS Pin Communication Mode SSU communication mode Register Setting CSS1 CSS0 SCS 0 x x Input 1 0 0 0 1 Input 1 0 Automatic input/output 1 1 Output x x SSUMS MSS 0 Clock synchronous 1 communication mode [Legend] x: Don't care : Not used as SSU pin Rev. 1.00, 03/04, page 488 of 730 Pin State x 14.4.5 SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 14.4 shows an example of the initial settings in SSU mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] Set a bit in ICR to 1 [2] Specify MSS, BIDE, SOL, SCKS, CSS1, and CSS0 bits in SSCRH [1] When the pin is used as an input. [2] Specify master/slave mode selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. [3] Selects SSU mode and specify transmit/receive data length. [4] Specify MSB first/LSB first selection, clock polarity selection, clock phase selection, and transfer clock rate selection. [3] Clear SSUMS in SSCRH to 0 and specify bits DATS1 and DATS0 [4] Specify MLS, CPOS, CPHS, CKS2, CKS1, and CKS0 bits in SSMR [5] Specify TEIE, TIE, RIE, and CEIE bits in SSER [5] Enables/disables interrupt request to the CPU. End Figure 14.4 Example of Initial Settings in SSU Mode Rev. 1.00, 03/04, page 489 of 730 (2) Data Transmission Figure 14.5 shows an example of transmission operation, and figure 14.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. After transmission, the output level of the SSCK pin is fixed high when CPOS = 0 and low when CPOS = 1. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. Rev. 1.00, 03/04, page 490 of 730 (1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame SCS 1 frame SSCK SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 SSTDR0 (LSB first transmission) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 (MSB first transmission) TDRE TEND TXI interrupt TEI interrupt generated LSI operation generated User operation Data written to SSTDR0 TXI interrupt generated Data written to SSTDR0 TEI interrupt generated (2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 SSTDR1 SSO (MSB first) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 1 Bit 0 SSTDR0 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 SSTDR0 Bit 4 Bit 3 SSTDR1 TDRE TEND LSI operation TXI interrupt generated User operation Data written to SSTDR0 and SSTDR1 TEI interrupt generated (3) When 32-bit data length is selected (SSTDR0 and SSTDR3 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSO (LSB first) Bit 0 SSO (MSB first) Bit 7 Bit 7 Bit 0 Bit 0 Bit 7 to Bit 7 Bit 0 Bit 0 Bit 7 SSTDR to to Bit 7 Bit 0 Bit 0 Bit 7 SSTDR to to Bit 7 SSTDR SSTDR SSTDR SSTDR to to SSTDR to Bit 0 SSTDR TDRE TEND LSI operation TXI interrupt generatedTEI interrupt generated User operation Data written to SSTDR0 to SSTDR1 Figure 14.5 Example of Transmission Operation (SSU Mode) Rev. 1.00, 03/04, page 491 of 730 Start [1] [1] Initial setting: Specify the transmit data format. Initial setting [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. TE = 1 (transmission enabled) [2] Read TDRE in SSSR TDRE = 1? No Yes Write transmit data to SSTDR TDRE automatically cleared [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission [3] Consecutive data transmission? Yes No Read TEND in SSSR TEND = 1? No Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes No Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. Figure 14.6 Flowchart Example of Data Transmission (SSU Mode) Rev. 1.00, 03/04, page 492 of 730 (3) Data Reception Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. Rev. 1.00, 03/04, page 493 of 730 (1) When 8-bit data length is selected (SSRDR0 is valid) with CPOS = 0 and CPHS = 0 1 frame SCS 1 frame SSCK Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSI Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSTDR0 (LSB first transmission) SSTDR0 (MSB first transmission) RDRF RXI interrupt generated LSI operation User operation Dummy-read SSRDR0 RXI interrupt generated Read SSRDR0 (2) When 16-bit data length is selected (SSRDR0 and SSRDR1 are valid) with CPOS = 0 and CPHS = 0 1 frame SCS SSCK SSI (LSB first) Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSI (MSB first) Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Bit Bit Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5 6 7 SSRDR1 SSRDR0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 SSRDR0 SSRDR1 RDRF LSI operation RXI interrupt generated User operation Dummy-readSSRDR0 (3) When 32-bit data length is selected (SSRDR0 to SSRDR3 are valid) with CPOS = 0 and CPHS = 0 SCS SSCK SSI (LSB first) Bit 0 SSI (MSB first) Bit 7 to Bit Bit 7 0 SSRDR3 to Bit Bit 7 0 SSRDR2 Bit Bit 0 7 SSRDR0 to to Bit 0 SSRDR1 to Bit 7 SSRDR1 Bit 7 to Bit 0 Bit 7 SSRDR0 Bit Bit 0 7 SSRDR2 to to Bit 0 SSRDR3 RDRF LSI operation User operation Dummy-readSSRDR0 RXI interrupt generated Figure 14.7 Example of Reception Operation (SSU Mode) Rev. 1.00, 03/04, page 494 of 730 Start [1] RE = 1 (reception started) [2] Initial setting: Specify the receive data format. [2] Start reception: When SSRDR is dummy-read with RE = 1, reception is started. Dummy-read SSRDR [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. Read SSSR No [1] Initial setting RDRF = 1? Yes ORER = 1? Yes [3] [4] To continue single reception: When continuing single reception, wait for time of tSUcyc while the RDRF flag is set to 1 and then read receive data in SSRDR. The next single reception starts after reading receive data in SSRDR. [5] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No [4] Consecutive data reception? No Yes Read received data in SSRDR RDRF automatically cleared [5] RE = 0 Read receive data in SSRDR End reception [6] Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. Figure 14.8 Flowchart Example of Data Reception (SSU Mode) (4) Data Transmission/Reception Figure 14.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bit to 1. Rev. 1.00, 03/04, page 495 of 730 Start [1] [1] Initial setting: Specify the transmit/receive data format. Initial setting [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission/ reception is started by writing data to SSTDR. Transmission/reception started (TE = 1, RE = 1) Read TDRE in SSSR. [2] No TDRE = 1? Yes Write transmit data to SSTDR [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. Read SSSR [3] No [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. RDRF = 1? Yes ORER = 1? Yes [4] No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Clear TEND in SSSR to 0 Yes [5] Error processing Clear TE and RE in SSER to 0 End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 14.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode) Rev. 1.00, 03/04, page 496 of 730 14.4.6 SCS Pin Control and Arbitration When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect arbitration. The arbitration detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0. Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0 before resuming the transmission or reception. External input to SCS Internal-clocked SCS MSS Internal signal for transfer enable Data written to SSTDR CE SCS output (Hi-Z) Arbitration detection period Worst time for internally clocking SCS Figure 14.10 Arbitration Detection Timing (Before Transfer) P SCS (Hi-Z) MSS Internal signal for transfer enable CE Transfer end Arbitration detection period Figure 14.11 Arbitration Detection Timing (After Transfer End) Rev. 1.00, 03/04, page 497 of 730 14.4.7 Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 14.12 shows an example of the initial settings in clock synchronous communication mode. Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values. Note: Before changing operating modes and communications formats, clear both the TE and RE bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0 does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the previous values. Start setting initial values Clear TE and RE bits in SSER to 0 [1] Set a bit in ICR to 1 [2] Specify MSS and SCKS in SSCRH [1] When the pin is used as an input. [2] Specify master/slave mode selection and SSCK pin selection. [3] Selects clock synchronous communication mode and specify transmit/receive data length. [4] Specify clock polarity selection and transfer clock rate selection. [3] Set SSUMS in SSCRL to 1 and specify bits DATS1 and DATS0 [4] Specify CPOS, CKS2, CKS1, and CKS0 bits in SSMR [5] Specify TEIE, TIE, RIE, and CEIE bits in SSER [5] Enables/disables interrupt request to the CPU. End Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode Rev. 1.00, 03/04, page 498 of 730 (2) Data Transmission Figure 14.13 shows an example of transmission operation, and figure 14.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU outputs data in synchronization with the transfer clock. Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit in SSSR to 0, and the SSTDR contents are transferred to SSTRSR. After that, the SSU sets the TDRE bit to 1 and starts transmission. At this time, if the TIE bit in SSER is set to 1, a TXI interrupt is generated. When 1-frame data has been transferred with TDRE = 0, the SSTDR contents are transferred to SSTRSR to start the next frame transmission. When the 8th bit of transmit data has been transferred with TDRE = 1, the TEND bit in SSSR is set to 1 and the state is retained. At this time, if the TEIE bit is set to 1, a TEI interrupt is generated. While the ORER bit in SSSR is set to 1, transmission is not performed. Check that the ORER bit is cleared to 0. SSCK SSO Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 1 frame Bit 7 1 frame TDRE TEND LSI operation User operation TXI interrupt generated Data written to SSTDR TXI interrupt generated TEI interrupt generated Data written to SSTDR Figure 14.13 Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 1.00, 03/04, page 499 of 730 Start [1] [4][1] Initial setting: Specify the transmit data format. Initial setting [2] Check that the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. TE = 1 (transmission enabled) [2] Read TDRE in SSSR TDRE = 1? No Yes Write transmit data to SSTDR TDRE automatically cleared [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. [4] Procedure for data transmission end: To end data transmission, confirm that the TEND bit is cleared to 0. After completion of transmitting the last bit, clear the TE bit to 0. Data transferred from SSTDR to SSTRSR Set TDRE to 1 to start transmission [3] Consecutive data transmission? Yes No Read TEND in SSSR TEND = 1? No Yes Clear TEND to 0 Confirm that TEND is cleared to 0 [4] One bit time quantum elapsed? Yes No Clear TE in SSER to 0 End transmission Note: Hatching boxes represent SSU internal operations. Figure 14.14 Flowchart Example of Transmission Operation (Clock Synchronous Communication Mode) Rev. 1.00, 03/04, page 500 of 730 (3) Data Reception Figure 14.15 shows an example of reception operation, and figure 14.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock. When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF bit is automatically cleared to 0 by reading SSRDR. When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To resume the reception, clear the ORER bit to 0. SSCK SSO Bit 0 Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 7 1 frame RDRF LSI operation User operation RXI interrupt generated Dummy-read SSRDR RXI interrupt generated Read data from SSRDR RXI interrupt generated Read data from SSRDR Figure 14.15 Example of Reception Operation (Clock Synchronous Communication Mode) Rev. 1.00, 03/04, page 501 of 730 Start [1] Initial setting [2] RE = 1 (reception started) Initial setting: Specify the receive data format. [2] Start reception: When setting the RE bit to 1, reception is started. [3], [5] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. Read SSSR No [1] RDRF = 1? [4] Yes ORER = 1? Yes [3] To complete reception: To complete reception, read receive data after clearing the RE bit to 0. When reading SSRDR without clearing the RE bit, reception is resumed. No Consecutive data reception? No Yes Read received data in SSRDR RDRF automatically cleared [4] RE = 0 Read receive data in SSRDR End reception [5] Overrun error processing Clear ORER in SSSR End reception Note: Hatching boxes represent SSU internal operations. Figure 14.16 Flowchart Example of Data Reception (Clock Synchronous Communication Mode) (4) Data Transmission/Reception Figure 14.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1. Before switching transmission mode (TE = 1) or reception mode (RE = 1) to transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or RE bits to 1. Rev. 1.00, 03/04, page 502 of 730 Start [1] [1] Initial setting: Specify the transmit/receive data format. Initial setting [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR. Transmission/reception started (TE = 1, RE = 1) Read TDRE in SSSR. [2] No TDRE = 1? Yes Write transmit data to SSTDR [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission [5] Procedure for consecutive data transmission/reception: To continue serial data transmission/reception, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR. Read SSSR [3] No RDRF = 1? Yes ORER = 1? [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt. Yes [4] No Read receive data in SSRDR RDRF automatically cleared Consecutive data transmission/reception? No Clear TEND in SSSR to 0 Yes [5] Error processing Clear TE and RE in SSER to 0 End transmission/reception Note: Hatching boxes represent SSU internal operations. Figure 14.17 Flowchart Example of Simultaneous Transmission/Reception (Clock Synchronous Communication Mode) Rev. 1.00, 03/04, page 503 of 730 14.5 Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive data register full, a transmit data register empty, and a transmit end interrupts can activate the DMAC for data transfer. Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector address, and both a transmit data register empty and a transmit end interrupts are allocated to the SSTXI vector address, the interrupt source should be decided by their flags. Table 14.5 lists the interrupt sources. When an interrupt condition shown in table 14.5 is satisfied, an interrupt is requested. Clear the interrupt source by CPU or DMAC data transfer. Table 14.5 Interrupt Sources Channel Abbreviation Interrupt Source Symbol Interrupt Condition 0 OEI0 1 2 DMAC Activation (RIE = 1) * (ORER = 1) CEI0 (CEIE = 1) * (CE = 1) RXI0 (RIE = 1) * (RDRF = 1) Yes TXI0 (TIE = 1) * (TDRE = 1) Yes Transmit end TEI0 (TEIE = 1) * (TEND = 1) Yes Overrun error OEI1 (RIE = 1) * (ORER = 1) Conflict error CEI1 (CEIE = 1) * (CE = 1) SSRXI1 Receive data register full RXI1 (RIE = 1) * (RDRF = 1) Yes SSTXI1 Transmit data register empty TXI1 (TIE = 1) * (TDRE = 1) Yes Transmit end TEI1 (TEIE = 1) * (TEND = 1) Yes SSERI2 Overrun error OEI2 (RIE = 1) * (ORER = 1) Conflict error CEI2 (CEIE = 1) * (CE = 1) SSRXI2 Receive data register full RXI2 (RIE = 1) * (RDRF = 1) Yes SSTXI2 Transmit data register empty TXI2 (TIE = 1) * (TDRE = 1) Yes Transmit end TEI2 (TEIE = 1) * (TEND = 1) Yes SSERI0 Overrun error Conflict error SSRXI0 Receive data register full SSTXI0 Transmit data register empty SSERI1 Rev. 1.00, 03/04, page 504 of 730 14.6 Usage Note 14.6.1 Setting of Module Stop Mode The SSU can be enabled/disabled by the module stop control register setting and is disabled by the initial value. Canceling module stop mode enables to access the SSU registers. For details, see section 19, Power-Down Modes. Rev. 1.00, 03/04, page 505 of 730 Rev. 1.00, 03/04, page 506 of 730 Section 15 A/D Converter This LSI includes two units (unit 0 and unit 1) of successive approximation type 10-bit A/D converters that allow up to 16 analog input channels to be selected. Figures 15.1 and 15.2 are block diagrams for unit 0 and unit 1, respectively. This section describes unit 0, which has the same functions as the other unit. 15.1 * * * * * * * * * Features 10-bit resolution 16 input channels (eight channels for unit 0 and eight channels for unit 1) Conversion time: 7.4 s per channel (at 35-MHz operation) Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels 16 data registers (eight registers for unit 0 and eight registers for unit 1) A/D conversion results are held in a 16-bit data register for each channel Sample and hold function Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU), or an external trigger signal. Interrupt source A/D conversion end interrupt (ADI) request can be generated. Module stop mode can be set ADCMS70A_000020030600 Rev. 1.00, 03/04, page 507 of 730 Internal data bus AVSS0 Bus interface ADCR_0 ADCSR_0 ADDRH_0 ADDRG_0 ADDRF_0 ADDRE_0 ADDRD_0 ADDRC_0 ADDRB_0 10-bit D/A ADDRA_0 AVCC0 Successive approximation register Module data bus AN0 + AN2 - AN3 AN4 AN5 AN6 Multiplexer AN1 Comparator Control circuit Sample-andhold circuit AN7 ADI0 interrupt signal ADTRG0 [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: Conversion start trigger from the TPU A/D control register_0 A/D control/status register_0 A/D data register A_0 A/D data register B_0 A/D data register C_0 ADDRD_0: ADDRE_0: ADDRF_0: ADDRG_0: ADDRH_0: A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 Figure 15.1 Block Diagram of A/D Converter (Unit 0/AD_0) Rev. 1.00, 03/04, page 508 of 730 Internal data bus AVSS1 Bus interface ADCR_1 ADCSR_1 ADDRH_1 ADDRG_1 ADDRF_1 ADDRE_1 ADDRD_1 ADDRC_1 ADDRB_1 10-bit D/A ADDRA_1 AVCC1 Successive approximation register Module data bus AN8 + AN10 - AN11 AN12 AN13 AN14 Multiplexer AN9 Comparator Control circuit Sample-andhold circuit AN15 ADI1 interrupt signal ADTRG0 [Legend] ADCR_1: ADCSR_1: ADDRA_1: ADDRB_1: ADDRC_1: Conversion start trigger from the TPU A/D control register_1 A/D control/status register_1 A/D data register A_1 A/D data register B_1 A/D data register C_1 ADDRD_1: ADDRE_1: ADDRF_1: ADDRG_1: ADDRH_1: A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 Figure 15.2 Block Diagram of A/D Converter (Unit 1/AD_1) Rev. 1.00, 03/04, page 509 of 730 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the A/D converter. Table 15.1 Pin Configuration Unit Abbr. Pin Name Symbol I/O Function 0 AD_0 Analog input pin 0 AN0 Input Analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input 1 AD_1 Common A/D external trigger input pin 0 ADTRG0 Input External trigger input for starting A/D conversion Analog power supply pin 0 AVCC0 Input Analog block power supply Analog input pin 8 AN8 Input Analog inputs Analog input pin 9 AN9 Input Analog input pin 10 AN10 Input Analog input pin 11 AN11 Input Analog input pin 12 AN12 Input Analog input pin 13 AN13 Input Analog input pin 14 AN14 Input Analog input pin 15 AN15 Input A/D external trigger input pin 1 ADTRG1 Input External trigger input for starting A/D conversion Analog power supply pin 1 AVCC1 Input Analog block power supply Analog ground pin AVSS Input Analog block ground Rev. 1.00, 03/04, page 510 of 730 15.3 Register Descriptions The A/D converter has the following registers. The registers for unit 0 (A/D_0) and unit 1 (A/D_1) have the same functions. In this descriptions, AN8 to AN15 correspond to AN0 to AN7. * Unit 0 (A/D_0) A/D data register A_0 (ADDRA_0) A/D data register B_0 (ADDRB_0) A/D data register C_0 (ADDRC_0) A/D data register D_0 (ADDRD_0) A/D data register E_0 (ADDRE_0) A/D data register F_0 (ADDRF_0) A/D data register G_0 (ADDRG_0) A/D data register H_0 (ADDRH_0) A/D control/status register_0 (ADCSR_0) A/D control register_0 (ADCR_0) * Unit 1 (A/D_1) A/D data register A_1 (ADDRA_1) A/D data register B_1 (ADDRB_1) A/D data register C_1 (ADDRC_1) A/D data register D_1 (ADDRD_1) A/D data register E_1 (ADDRE_1) A/D data register F_1 (ADDRF_1) A/D data register G_1 (ADDRG_1) A/D data register H_1 (ADDRH_1) A/D control/status register_1 (ADCSR_1) A/D control register_1 (ADCR_1) Rev. 1.00, 03/04, page 511 of 730 15.3.1 A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units. Bit 15 14 13 12 11 10 9 8 7 6 Bit Name 5 4 3 2 1 0 - - - - - - Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R Table 15.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel A/D Data Register Which Stores Conversion Result AN0 ADDRA AN1 ADDRB AN2 ADDRC AN3 ADDRD AN4 ADDRE AN5 ADDRF AN6 ADDRG AN7 ADDRH Rev. 1.00, 03/04, page 512 of 730 15.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 6 5 ADF ADIE 0 0 R/(W)* R/W Bit Name Initial Value R/W 4 3 2 1 0 ADST - CH3 CH2 CH1 CH0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W Note: * Only 0 can be written to this bit, to clear the flag. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* A/D End Flag Description A status flag that indicates the end of A/D conversion. [Setting conditions] * When A/D conversion ends in single mode * When A/D conversion ends on all specified channels in scan mode [Clearing conditions] 6 ADIE 0 R/W * When 0 is written after reading ADF = 1 * When the DMAC is activated by an ADI interrupt and ADDR is read A/D Interrupt Enable When this bit is set to 1, ADI interrupts by ADF are enabled. 5 ADST 0 R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, or module stop mode. 4 0 R Reserved This is a read-only bit and cannot be modified. Rev. 1.00, 03/04, page 513 of 730 Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel Select 3 to 0 2 CH2 0 R/W 1 CH1 0 R/W Selects analog input together with bits SCANE and SCANS in ADCR. 0 CH0 0 R/W * When SCANE = 0 and SCANS = X 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1XXX: Setting prohibited [Legend] X: Don't care Note: * Only 0 can be written to this bit, to clear the flag. Rev. 1.00, 03/04, page 514 of 730 15.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name 7 6 5 4 3 2 TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 - - 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R Initial Value R/W 1 0 Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 00: A/D conversion start by external trigger is disabled 01: A/D conversion start by external trigger from TPU is enabled 10: Setting prohibited 11: A/D conversion start by the ADTRG pin is enabled* 5 SCANE 0 R/W Scan Mode 4 SCANS 0 R/W These bits select the A/D conversion operating mode. 0X: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8. 3 CKS1 0 R/W Clock Select 1 and 0 2 CKS0 0 R/W These bits set the A/D conversion time. Set bits CKS1 and CKS0 only while A/D conversion is stopped (ADST = 0). 00: A/D conversion time = 530 states (max) 01: A/D conversion time = 266 states (max) 10: A/D conversion time = 134 states (max) 11: A/D conversion time = 68 states (max) 1, 0 All 0 R Reserved These are read-only bits and cannot be modified. [Legend] X: Don't care Rev. 1.00, 03/04, page 515 of 730 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 15.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters wait state. Set* ADIE Set* ADST Set* A/D conversion start Clear* Clear* ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Waiting for conversion Waiting for conversion A/D conversion 1 Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion Waiting for conversion A/D conversion 2 Waiting for conversion ADDRA Reading A/D conversion result ADDRB A/D conversion result 1 Reading A/D conversion result A/D conversion result 2 ADDRC ADDRD Note: * indicates the timing of instruction execution by software. Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 1.00, 03/04, page 516 of 730 15.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight channels. 1. When the ADST bit in ADCSR is set to 1 by software, TPU, or an external trigger input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 = B'00, on AN4 when CH3 and CH2 = B'01, on AN8 when CH3 and CH2 = B'10, and on AN12 when CH3 and CH2 = B'11. When consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 = B'0 and on AN8 when CH3 = B'1. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. Rev. 1.00, 03/04, page 517 of 730 A/D conversion consecutive execution Clear*1 Set*1 ADST Clear*1 ADF Channel 0 (AN0) operation state Waiting for conversion A/D conversion 1 Channel 1 (AN1) operation state Waiting for conversion Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion Waiting for conversion A/D conversion 5 A/D conversion 3 *2 Waiting for conversion Waiting for conversion Transfer ADDRA A/D conversion result 4 A/D conversion result 1 ADDRB A/D conversion result 2 A/D conversion result 3 ADDRC ADDRD Notes: 1. indicates the timing of instruction execution by software. 2. Data being converted is ignored. Figure 15.4 Example of A/D Conversion (Scan Mode, Three Channels (AN0 to AN2) Selected) Rev. 1.00, 03/04, page 518 of 730 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 15.5 shows the A/D conversion timing. Table 15.3 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.3. In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in table 15.4 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics. (1) P Address (2) Write signal Input sampling timing ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 15.5 A/D Conversion Timing Rev. 1.00, 03/04, page 519 of 730 Table 15.3 A/D Conversion Characteristics (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Item Symbol Min. Typ. Max. A/D conversion start delay time tD 18 33 10 17 6 9 4 5 Input sampling time tSPL 127 63 31 15 A/D conversion time 515 530 259 266 131 134 67 68 Note: tCONV Values in the table are the number of states. Table 15.4 A/D Conversion Characteristics (Scan Mode) CKS1 CKS0 Conversion Time (Number of States) 0 0 512 (Fixed) 1 256 (Fixed) 0 128 (Fixed) 1 64 (Fixed) 1 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to B'11 in ADCR, an external trigger is input from the ADTRG pin. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 15.6 shows the timing. P ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing Rev. 1.00, 03/04, page 520 of 730 15.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The DMA controller (DMAC) can be activated by an ADI interrupt. Having the converted data read by the DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Table 15.5 A/D Converter Interrupt Source Unit Abbr. Interrupt Source Interrupt Flag DMAC Activation 0 ADI0 A/D_0 conversion end ADF Possible 1 ADI1 A/D_1 conversion end ADF Possible 15.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes. * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.7). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.8). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.8). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 15.8). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev. 1.00, 03/04, page 521 of 730 Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.7 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 15.8 A/D Conversion Accuracy Definitions Rev. 1.00, 03/04, page 522 of 730 15.7 Usage Notes 15.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 19, Power-Down Modes. 15.7.2 Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 15.9). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted. This LSI Equivalent circuit of the A/D converter Sensor output impedance R 5 k 10 k Sensor input Low-pass filter C 0.1 F Cin = 15 pF 20 pF Figure 15.9 Example of Analog Input Circuit 15.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that digital signals on the board do not interfere with filter circuits and filter circuits do not act as antennas. Rev. 1.00, 03/04, page 523 of 730 15.7.4 Setting Range of Analog Power Supply and Other Pins If the conditions shown below are not met, the reliability of the LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc0 and AVss VAN AVcc1. * Relation between AVcc0, AVcc1, AVss and Vcc, Vss As the relationship between AVcc0, AVcc1, AVss and Vcc, Vss, set AVcc0 = Vcc 0.3 V, AVcc1 = Vcc 0.3 V, and AVss = Vss. If the A/D converter is not used, set AVcc0 = Vcc, AVcc1 = Vcc, and AVss = Vss. 15.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN15) and analog power supply (AVcc0 and AVcc1) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 15.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) should be connected between AVcc0, AVcc1 and AVss as shown in figure 15.10. Also, the bypass capacitors connected to AVcc0 and AVcc1 and the filter capacitor connected to pins AN0 to AN15 must be connected to AVss. If a filter capacitor is connected, the input currents at pins AN0 to AN15 are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. Rev. 1.00, 03/04, page 524 of 730 AVCC0 and AVCC1 100 Rin* 2 AN0 to AN15 *1 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15.10 Example of Analog Input Protection Circuit Table 15.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance 20 pF Permissible signal source impedance 5 k 5 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 15.11 Analog Input Pin Equivalent Circuit 15.7.7 A/D Input Hold Function in Software Standby Mode When this LSI enters software standby mode with A/D conversion enabled, the A/D conversion are retained, and the analog current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, clear the ADST, TRGS1, and TRGS0 bits all to 0 to disable A/D conversion. Rev. 1.00, 03/04, page 525 of 730 Rev. 1.00, 03/04, page 526 of 730 Section 16 RAM This LSI has a 12-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling 1-state read and 2-state write accesses by the CPU to all byte data, word data, and longword data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). Product Classification Flash memory version RAM Size RAM Addresses H8SX/1527 12 kbytes H'FF9000 to H'FFC000 H8SX/1525 12 kbytes H'FF9000 to H'FFC000 Rev. 1.00, 03/04, page 527 of 730 Rev. 1.00, 03/04, page 528 of 730 Section 17 Flash Memory (0.18-m F-ZTAT Version) The flash memory has the following features. Figure 17.1 is a block diagram of the flash memory. 17.1 Features * Size Product Classification H8SX/1527 R5F61527 H8SX/1525 R5F61525 ROM Size ROM Address 256 kbytes H'000000 to H'03FFFF (modes 1 to 3) * Two memory MATs The start addresses of two memory spaces (memory MATs) are allocated to the same address. The mode setting in the initiation determines which memory MAT is initiated first. The memory MATs can be switched by using the bank-switching method after initiation. User MAT initiated at a power-on reset in user mode: 256 kbytes User boot MAT is initiated at a power-on reset in user boot mode: 10 kbytes * Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasing can be performed by setting the parameters. * Programming/erasing time Programming time: tp ms (typ) for 128-byte simultaneous programming, tp/128 s per byte Erasing time: tE ms (typ) per 1 block (64 kbytes) * Number of programming The number of programming can be up to NWEC times at the minimum. (1 to NWEC times are guaranteed.) * Three on-board programming modes Boot mode: Using the on-chip SCI_4, the user MAT and user boot MAT can be programmed/erased. In boot mode, the bit rate between the host and this LSI can be adjusted automatically. User program mode: Using a desired interface, the user MAT can be programmed/erased. User boot mode: Using a desired interface, the user boot program can be made and the user MAT can be programmed/erased. * Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT and user boot MAT can be programmed/erased. Rev. 1.00, 03/04, page 529 of 730 * Programming/erasing protection Protection against programming/erasing of the flash memory can be set by hardware protection, software protection, or error protection. * Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM. Internal address bus Internal data bus (32 bits) FCCS Module bus FPCS FECS FKEY Memory MAT unit Control unit User MAT: 256 kbytes User boot MAT: 10 kbytes FMATS FTDAR RAMER Flash memory Mode pins Operating mode [Legend] FCCS: Flash code control/status register FPCS: Flash program code select register FECS: Flash erase code select register FKEY: Flash key code register FMATS: Flash MAT select register FTDAR: Flash transfer destination address register RAMER: RAM emulation register Note: To read from or write to the registers, the FLSHE bit in SYSCR must be set to 1. Figure 17.1 Block Diagram of Flash Memory Rev. 1.00, 03/04, page 530 of 730 17.2 Mode Transition Diagram When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 17.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user program mode, user boot mode, and programmer mode. The differences between boot mode, user program mode, user boot mode, and programmer mode are shown in table 17.1. RES = 0 RES = 0 Programmer ROM disabled mode Reset state ROM disabled mode setting =0 ot =0 RES mode RE S= Bo S Us g RE er d mo in ett es ot g bo tin er set Us de mo =0 S RE Programmer mode setting mo de 0 se tt ing *2 User mode *1 User program mode User boot mode Boot mode RAM emulation can be available On-board programming mode Notes: * In this LSI, the user program mode is defined as the period from the timing when a program concerning programming and erasure is started in user mode to the timing when the program is completed. 1. Programming and erasure is started. 2. Programing and erasure is completed. Figure 17.2 Mode Transition of Flash Memory Rev. 1.00, 03/04, page 531 of 730 Table 17.1 Differences between Boot Mode, User Program Mode, User Boot Mode, and Programmer Mode Item Boot Mode User Program Mode User Boot Mode Programmer Mode Programming/ erasing environment On-board programming On-board programming On-board programming Off-board programming Programming/ erasing enable MAT * User MAT * * * User MAT * User boot MAT * User boot MAT Programming/ erasing control Command User MAT Programming/ erasing interface User MAT Programming/ erasing interface Command All erasure O (Automatic) O O O (Automatic) Block division erasure O*1 O O x Program data transfer From host via SCI From desired device via RAM From desired device via RAM Via programmer RAM emulation x O O x Reset initiation MAT Embedded program storage area User MAT User boot MAT* Transition to user mode Changing mode and reset Completing Programming/ erasure*3 Changing mode and reset 2 Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage area. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT. 3. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 17.8.2, User Program Mode. Rev. 1.00, 03/04, page 532 of 730 17.3 Memory MAT Configuration The memory MATs of flash memory in this LSI consists of the 256-kbyte user MAT and 10-kbyte user boot MAT. The start addresses of the user MAT and user boot MAT are allocated to the same address. Therefore, when the program execution or data access is performed between the two memory MATs, the memory MATs must be switched by the flash MAT select register (FMATS). The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed or erased only in boot mode and programmer mode. The size of the user MAT is different from that of the user boot MAT. Addresses which exceed the size of the 10-kbyte user boot MAT should not be accessed. If an attempt is made, data is read as an undefined value. User MAT H'000000 User boot MAT H'000000 10 kbytes H'0027FF 256 kbytes H'03FFFF Figure 17.3 Memory MAT Configuration Rev. 1.00, 03/04, page 533 of 730 17.4 Block Structure Figure 17.4 shows the block structure of the 256-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks. EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes EB10 Erase unit: 64 kbytes EB11 Erase unit: 64 kbytes H'000000 H'000001 H'000002 Programming unit: 128 bytes H'00007F H'000F80 H'001000 H'000F81 H'001001 H'000F82 H'001002 - - - - - - - - - - - - - - Programming unit: 128 bytes H'000FFF H'00107F H'001F80 H'002000 H'001F81 H'002001 H'001F82 H'002002 - - - - - - - - - - - - - - Programming unit: 128 bytes H'001FFF H'00207F H'002F80 H'003000 H'002F81 H'003001 H'002F82 H'003002 - - - - - - - - - - - - - - Programming unit: 128 bytes H'002FFF H'00307F H'003F80 H'003F81 H'003F82 - - - - - - - - - - - - - - H'003FFF H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 Programming unit: 128 bytes H'005F80 H'006000 H'005F81 H'006001 H'005F82 H'006002 Programming unit: 128 bytes H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 Programming unit: 128 bytes H'007F80 H'008000 H'007F81 H'008001 H'007F82 H'008002 Programming unit: 128 bytes H'00FF80 H'010000 H'00FF81 H'010001 - - - - - - - - - - - - - - H'00FF82 H'010002 Programming unit: 128 bytes H'00FFFF H'01FF80 H'020000 H'01FF81 H'020001 - - - - - - - - - - - - - - H'01FF82 H'020002 Programming unit: 128 bytes H'01FFFF H'02007F H'02FF80 H'030000 H'02FF81 H'030001 - - - - - - - - - - - - - - H'02FFFF H'02FF82 H'03007F H'030002 Programming unit: 128 bytes H'03FF80 H'03FF81 H'03FF82 Programming unit: 128 bytes - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Figure 17.4 Block Structure of User MAT Rev. 1.00, 03/04, page 534 of 730 H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'01007F H'03FFFF 17.5 Programming/Erasing Interface Programming/erasing of the flash memory is done by downloading an on-chip programming/erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user program mode and user boot mode is made by the user. Figure 17.5 shows the procedure for creating the procedure program. For details, see section 17.8.2, User Program Mode. Start procedure program for programming/erasing Select on-chip program to be downloaded and specify destination Download on-chip program by setting VBR, FKEY, and SCO bit in FCCS Execute initialization (downloaded program execution) Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution) No Programming/erasing completed? Yes End procedure program Figure 17.5 Procedure for Creating Procedure Program (1) Selection of On-Chip Program to be Downloaded For programming/erasing, the FLSHE bit in the system control register (SYSCR) must be set to 1 to select user program mode. This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR). Rev. 1.00, 03/04, page 535 of 730 (2) Download of On-Chip Program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base register (VBR). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. The VBR contents can be changed after completion of download. (3) Initialization of Programming/Erasing A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasing. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasing For programming/erasing, the FLSHE bit in SYSCR must be set to 1 to make a transition to user program mode. The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasing. (5) When Programming/Erasing is Executed Consecutively When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasing can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasing completes, download and initialization are not required when the same processing is executed consecutively. Rev. 1.00, 03/04, page 536 of 730 17.6 Input/Output Pins The flash memory is controlled through the input/output pins shown in table 17.2. Table 17.2 Pin Configuration Pin Name I/O Function RES Input Reset MD1 and MD0 Input Set operating mode of this LSI TxD4 Output Serial transmit data output (used in boot mode) RxD4 Input Serial receive data input (used in boot mode) 17.7 Register Descriptions The flash memory has the following registers. To access these registers, the FLSHE bit in the system control register (SYSCR) must be set to 1. For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Programming/Erasing Interface Registers: * * * * * * Flash code control/status register (FCCS) Flash program code select register (FPCS) Flash erase code select register (FECS) Flash key code register (FKEY) Flash MAT select register (FMATS) Flash transfer destination address register (FTDAR) Programming/Erasing Interface Parameters: * * * * * * Download pass and fail result parameter (DPFR) Flash pass and fail result parameter (FPFR) Flash program/erase frequency parameter (FPEFEQ) Flash multipurpose address area parameter (FMPAR) Flash multipurpose data destination area parameter (FMPDR) Flash erase block select parameter (FEBS) * RAM emulation register (RAMER) There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence between operating modes and registers/parameters for use is shown in table 17.3. Rev. 1.00, 03/04, page 537 of 730 Table 17.3 Registers/Parameters and Target Modes Download Initialization Programming Erasure Read RAM Emulation FCCS O FPCS O FECS O FKEY O O O FMATS O*1 O*1 O*2 FTDAR O DPFR O FPFR O O O FPEFEQ O FMPAR O FMPDR O FEBS O RAMER O Register/Parameter Programming/ erasing interface registers Programming/ erasing interface parameters RAM emulation Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target memory MAT. 17.7.1 Programming/Erasing Interface Registers The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a power-on reset. (1) Flash Code Control/Status Register (FCCS) FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM. Bit 7 6 5 4 3 2 1 0 Bit Name - - - FLER - - - SCO Initial Value 1 0 0 0 0 0 0 0 R/W R R R R R R R (R)/W Rev. 1.00, 03/04, page 538 of 730 Bit Initial Bit Name Value R/W Description 7 1 R Reserved 6 0 R These are read-only bits and cannot be modified. 5 0 R 4 FLER 0 R Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] * At a power-on reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] 3 to 1 All 0 R * When an interrupt, such as NMI, occurs during programming/erasing. * When the flash memory is read during programming/erasing (including a vector read and an instruction fetch). * When the SLEEP instruction is executed during programming/erasing (including software standby mode). * When a bus master other than the CPU, such as the DMAC, obtains bus mastership during programming/erasing. Reserved These are read-only bits and cannot be modified. Rev. 1.00, 03/04, page 539 of 730 Bit Initial Bit Name Value R/W 0 SCO (R)/W* 0 Description Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, the RAM emulation mode must be canceled, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bankswitching of the program storage area is executed. Before a download request, initialize the VBR contents to H'00000000. After download is completed, the VBR contents can be changed. 0: Download of the programming/erasing program is not requested. [Clearing condition] * When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied) Note: * * Not in RAM emulation mode (the RAMS bit in RAMER is cleared to 0) * H'A5 is written to FKEY * Setting of this bit is executed in the on-chip RAM This is a write-only bit. This bit is always read as 0. Rev. 1.00, 03/04, page 540 of 730 (2) Flash Program Code Select Register (FPCS) FPCS selects the programming program to be downloaded. Bit 7 6 5 4 3 2 1 0 Bit Name - - - - - - - PPVS Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R/W Bit Initial Bit Name Value R/W Description 7 to 1 All 0 R Reserved 0 PPVS 0 R/W Program Pulse Verify These are read-only bits and cannot be modified. Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected. (3) Flash Erase Code Select Register (FECS) FECS selects the erasing program to be downloaded. Bit 7 6 5 4 3 2 1 0 Bit Name - - - - - - - EPVB Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R/W Bit Initial Bit Name Value R/W 7 to 1 R All 0 Description Reserved These are read-only bits and cannot be modified. 0 EPVB 0 R/W Erase Pulse Verify Block Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected. Rev. 1.00, 03/04, page 541 of 730 (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasing of the flash memory. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 7 K7 0 R/W Key Code 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W Only when H'5A is written can programming/erasing of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasing cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasing of the flash memory is enabled. (When FKEY is a value other than H'A5, the software protection state is entered.) H'00: Initial value Rev. 1.00, 03/04, page 542 of 730 (5) Flash MAT Select Register (FMATS) FMATS selects the user MAT or user boot MAT. Writing to FMATS should be done when a program in the on-chip RAM is being executed. Bit 7 6 5 4 3 2 1 0 Bit Name MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 Initial Value 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0. Bit Initial Bit Name Value R/W Description 7 MS7 0/1* R/W MAT Select 6 MS6 0 R/W 5 MS5 0/1* R/W The memory MATs can be switched by writing a value to FMATS. 4 MS4 0 R/W 3 MS3 0/1* R/W 2 MS2 0 R/W 1 MS1 0/1* R/W 0 MS0 0 R/W When H'AA is written to FMATS, the user boot MAT is selected. When a value other than H'AA is written, the user MAT is selected. Switch the MATs following the memory MAT switching procedure in section 17.11, Switching between User MAT and User Boot MAT. The user boot MAT cannot be selected by FMATS in user programming mode. The user boot MAT can be selected in boot mode or programmer mode. H'AA: The user boot MAT is selected. (The user MAT is selected when FMATS is a value other than H'AA.) (Initial value when initiated in user boot mode.) H'00: The user MAT is selected. (Initial value when initiated in a mode except for user boot mode.) Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0. Rev. 1.00, 03/04, page 543 of 730 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1. Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 7 TDER R/W Transfer Destination Address Setting Error 0 This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'02 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H'00 to H'02. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'03 and H'FF and download has stopped. 6 TDA6 0 R/W Transfer Destination Address 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'02, and up to 4 kbytes can be specified as the start address of the on-chip RAM. 2 TDA2 0 R/W H'00: 1 TDA1 0 R/W H'FF9000 is specified as the start address. 0 TDA0 0 R/W H'01: H'FFA000 is specified as the start address. H'02: H'FFB000 is specified as the start address. H'03 to H'7F: Setting prohibited. (Specifying a value from H'03 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.) Rev. 1.00, 03/04, page 544 of 730 17.7.2 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a power-on reset or a transition to software standby mode. Since registers of the CPU except for R0 are saved in the stack area during download of an onchip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 17.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 17.4 Parameters and Target Modes Parameter Download Initialization Programming Erasure R/W Initial Value Allocation DPFR O R/W Undefined On-chip RAM* FPFR O O O O R/W Undefined R0L of CPU FPEFEQ O R/W Undefined ER0 of CPU FMPAR O R/W Undefined ER1 of CPU FMPDR O R/W Undefined ER0 of CPU FEBS O R/W Undefined ER0 of CPU Note: * A single byte of the start address of the on-chip RAM specified by FTDAR Download Control: The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value. Rev. 1.00, 03/04, page 545 of 730 Initialization before Programming/Erasing: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. Programming: When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 17.8.2, User Program Mode. Erasure: When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 11 as the erase block number. For details on the erasing procedure, see section 17.8.2, User Program Mode. Rev. 1.00, 03/04, page 546 of 730 (1) Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR) DPFR indicates the return value of the download result. The DPFR value is used to determine the download result. Bit 7 6 5 4 3 2 1 0 Bit Name - - - - - SS FK SF Bit Initial Bit Name Value R/W Description 7 to 3 Unused 2 SS R/W Source Select Error Detect These bits return 0. Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal 1 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5) 0 SF R/W Success/Fail Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs) Rev. 1.00, 03/04, page 547 of 730 (2) Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU) FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before programming/erasing FPFR indicates the return value of the initialization result. Bit 7 6 5 4 3 2 1 0 Bit Nam - - - - - - FQ SF Bit Initial Bit Name Value R/W Description 7 to 2 Unused These bits return 0. 1 FQ R/W Frequency Error Detect Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal 0 SF R/W Success/Fail Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs) Rev. 1.00, 03/04, page 548 of 730 (b) Programming FPFR indicates the return value of the programming result. Bit 7 6 5 4 3 2 1 0 Bit Nam - MD EE FK - WD WA SF Bit Initial Bit Name Value R/W Description 7 Unused 6 MD R/W Programming Mode Related Setting Error Detect Returns 0. Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT have not been written to. Programming the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed) 4 FK R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 Unused Returns 0. Rev. 1.00, 03/04, page 549 of 730 Bit Initial Bit Name Value 2 WD R/W Description R/W Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal 1 WA R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * An area other than flash memory * The specified address is not aligned with the 128byte boundary (lower eight bits of the address are other than H'00 and H'80) 0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal 0 SF R/W Success/Fail Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) Rev. 1.00, 03/04, page 550 of 730 (c) Erasure FPFR indicates the return value of the erasure result. Bit 7 6 5 4 3 2 1 0 Bit Nam - MD EE FK EB - - SF Bit Initial Bit Name Value R/W Description 7 Unused 6 MD R/W Erasure Mode Related Setting Error Detect Returns 0. Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 17.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1) 5 EE R/W Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT have not been erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally Rev. 1.00, 03/04, page 551 of 730 Bit Initial Bit Name Value 4 FK R/W Description R/W Flash Key Register Error Detect Checks the FKEY value (H'A5) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A) 3 EB R/W Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal 2, 1 Unused These bits return 0. 0 SF R/W Success/Fail Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) Rev. 1.00, 03/04, page 552 of 730 (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU) FPEFEQ sets the operating frequency of the CPU. The CPU operating frequency available in this LSI ranges from 8 MHz to 40 MHz. Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 F15 F14 F13 F12 F11 F10 F9 F8 7 6 5 4 3 2 1 0 F7 F6 F5 F4 F3 F2 F1 F0 Initial Bit Name Value 31 to 16 R/W Description Unused These bits should be cleared to 0. 15 to 0 F15 to F0 R/W Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 33.000 MHz, the value is as follows: 1. The number of three decimal places of 33.000 is rounded. 2. The formula of 33.00 x 100 = 3300 is converted to the binary digit and B'0000 1100 1110 0100 (H'0CE4) is set to ER0. Rev. 1.00, 03/04, page 553 of 730 (4) Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU) FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR. Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit 31 to 0 31 30 29 28 27 26 25 24 MOA31 MOA30 MOA29 MOA28 MOA27 MOA26 MOA25 MOA24 23 22 21 20 19 18 17 16 MOA23 MOA22 MOA21 MOA20 MOA19 MOA18 MOA17 MOA16 15 14 13 12 11 10 9 8 MOA15 MOA14 MOA13 MOA12 MOA11 MOA10 MOA9 MOA8 7 6 5 4 3 2 1 0 MOA7 MOA6 MOA5 MOA4 MOA3 MOA2 MOA1 MOA0 Initial Bit Name Value MOA31 to MOA0 R/W Description R/W These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0. Rev. 1.00, 03/04, page 554 of 730 (5) Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU) FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR. Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit 31 to 0 31 30 29 28 27 26 25 24 MOD31 MOD30 MOD29 MOD28 MOD27 MOD26 MOD25 MOD24 23 22 21 20 19 18 17 16 MOD23 MOD22 MOD21 MOD20 MOD19 MOD18 MOD17 MOD16 15 14 13 12 11 10 9 8 MOD15 MOD14 MOD13 MOD12 MOD11 MOD10 MOD9 MOD8 7 6 5 4 3 2 1 0 MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Initial Bit Name Value MOD31 to MOD0 R/W Description R/W These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address. Rev. 1.00, 03/04, page 555 of 730 (6) Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU) FEBS specifies the erase block number. Only one block number can be specified at one time. Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name Bit 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - EBS11 EBS10 EBS9 EBS8 7 6 5 4 3 2 1 0 EBS7 EBS6 EBS5 EBS4 EBS3 EBS2 EBS1 EBS0 Initial Bit Name Value 31 to 12 R/W Description Unused These bits should be cleared to 0. 11 EBS11 R/W Erase Block 10 EBS10 R/W 9 EBS9 R/W 8 EBS8 R/W These bits set the erase block number in the range from 0 to 11. Number 0 corresponds to block EB0 and number 11 corresponds to block EB11. An error occurs when a number other than 0 to 11 is set. 7 EBS7 R/W 6 EBS6 R/W 5 EBS5 R/W 4 EBS4 R/W 3 EBS3 R/W 2 EBS2 R/W 1 EBS1 R/W 0 EBS0 R/W Rev. 1.00, 03/04, page 556 of 730 17.7.3 RAM Emulation Register (RAMER) RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user program mode. To ensure dependable emulation, the memory MAT to be emulated must not be accessed immediately after changing the RAMER contents. When accessed at such a timing, correct operation is not guaranteed. 7 Bit 6 5 4 3 2 1 0 Bit Name - - - - RAMS RAM2 RAM1 RAM0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R/W R/W R/W R/W Bit Initial Bit Name Value R/W Description 7 to 4 R Reserved 0 These are read-only bits and cannot be modified. 3 RAMS 0 R/W RAM Select Selects the function which emulates the flash memory using the on-chip RAM. 0: Disables RAM emulation function 1: Enables RAM emulation function (all blocks of the user MAT are protected against programming and erasing) 2 RAM2 0 R/W Flash Memory Area Select 1 RAM1 0 R/W 0 RAM0 0 R/W These bits select the user MAT area overlaid with the on-chip RAM when RAMS = 1. The following areas correspond to the 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) Rev. 1.00, 03/04, page 557 of 730 17.8 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has three operating modes: boot mode, user boot mode, and user program mode. Table 17.5 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see figure 17.2. Table 17.5 On-Board Programming Mode Setting Mode Setting MD1 MD0 User boot mode 0 1 Boot mode 1 0 User program mode 1 1 17.8.1 Boot Mode Boot mode executes programming/erasing of the user MAT or user boot MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_4. In boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in boot mode is shown in figure 17.6. Interrupts are ignored in boot mode. Configure the user system so that interrupts do not occur. This LSI Software for analyzing control commands (on-chip) Host Programming tool and program data Flash memory Control command, program data Response RxD4 SCI_4 TxD4 Figure 17.6 System Configuration in Boot Mode Rev. 1.00, 03/04, page 558 of 730 On-chip RAM (1) Serial Interface Setting by Host The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 17.6. Start bit D0 D1 D2 D3 D4 D5 D6 D7 Measure low period (9 bits) (data is H'00) Stop bit High period of at least 1 bit Figure 17.7 Automatic-Bit-Rate Adjustment Operation Table 17.6 System Clock Frequency for Automatic-Bit-Rate Adjustment Bit Rate of Host System Clock Frequency of This LSI External Clock Frequency 9,600 bps 8 to 18 MHz 4 to 9 MHz 19,200 bps 16 to 18 MHz 8 to 9 MHz Rev. 1.00, 03/04, page 559 of 730 (2) State Transition Diagram The state transition after boot mode is initiated is shown in figure 17.8. (Bit rate adjustment) H'00, ..., H'00 reception Boot mode initiation (reset by boot mode) H'00 transmission (adjustment completed) Bit rate adjustment 1. n eptio 5 rec H'5 Inquiry command reception Wait for inquiry setting command 2. Inquiry command response 3. 4. All user MAT and user boot MAT erasure Wait for programming/erasing command (Programming completion) Processing of inquiry setting command Read/check command reception Processing of read/check command Command response (Erasure completion) (Erasure selection command reception) (Erasure selection command reception) (Erase-block specification) Wait for erase-block data (Program data transmission) Wait for program data Figure 17.8 Boot Mode State Transition Diagram Rev. 1.00, 03/04, page 560 of 730 1. After boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Memory read of the user MAT/user boot MAT can only read the data programmed after all user MAT/user boot MAT has automatically been erased. No other data can be read. Rev. 1.00, 03/04, page 561 of 730 17.8.2 User Program Mode Programming/erasing of the user MAT is executed by downloading an on-chip program. The user boot MAT cannot be programmed/erased in user program mode. The programming/erasing flow is shown in figure 17.9. Since high voltage is applied to the internal flash memory during programming/erasing, a transition to the reset state or hardware standby mode must not be made during programming/erasing. A transition to the reset state or hardware standby mode during programming/erasing may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. Programming/erasing start When programming, program data is prepared Programming/erasing procedure program is transferred to the on-chip RAM and executed 1. Exit RAM emulation mode beforehand. Download is not allowed in emulation mode. 2. When the program data is adjusted in emulation mode, select the download destination specified by FTDAR carefully. Make sure that the download area does not overlap the emulation area. 3. Programming/erasing is executed only in the on-chip RAM. 4. After programming/erasing is finished, protect the flash memory by the hardware protection. Programming/erasing end Figure 17.9 Programming/Erasing Flow Rev. 1.00, 03/04, page 562 of 730 (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that is made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 17.10 shows the area of the on-chip program to be downloaded. DPFR (Return value: 1 byte) FTDAR setting System use area (15 bytes) Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing Programming/erasing program entry FTDAR setting + 16 bytes Initialization program entry FTDAR setting + 32 bytes Initialization + programming program or Initialization + erasing program RAM emulation area or area that can be used by user Area that can be used by user H'FFBFFF Figure 17.10 RAM Map when Programming/Erasing is Executed Rev. 1.00, 03/04, page 563 of 730 (2) Programming Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and programming are shown in figure 17.11. Start programming procedure program 1. Set FKEY to H'A5 2. Set SCO to 1 after initializing VBR and execute download 3. Clear FKEY to 0 4. 5. DPFR = 0? Yes No Initialization 6. Initialization JSR FTDAR setting + 32 Yes 7. Disable interrupts and bus master operation other than CPU 9. Set FKEY to H'5A 10. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 11. Programming JSR FTDAR setting + 16 12. FPFR = 1? Download error processing Set the FPEFEQ parameter FPFR = 0? Programming Download 1 Select on-chip program to be downloaded and specify download destination by FTDAR Yes No 13. No Clear FKEY and programming error processing Required data programming is completed? 14. Yes 8. Clear FKEY to 0 No Initialization error processing 1 15. End programming procedure program Figure 17.11 Programming Procedure in User Program Mode The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area. Rev. 1.00, 03/04, page 564 of 730 The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. 3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the SCO bit to 1, all of the following conditions must be satisfied. RAM emulation mode has been canceled. H'A5 is written to FKEY. Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1. The user-MAT space is switched to the on-chip program storage area. After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM. FPCS, FECS, and the SCO bit in FCCS are cleared to 0. The return value is set in the DPFR parameter. After the on-chip program storage area is returned to the user-MAT space, the procedure program is resumed. After that, VBR can be set again. The values of general registers of the CPU are held. During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested. To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. Rev. 1.00, 03/04, page 565 of 730 4. 5. 6. 7. If access to the flash memory is requested by the DMAC during download, the operation cannot be guaranteed. Make sure that an access request by the DMAC is not generated. FKEY is cleared to H'00 for protection. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 40 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 17.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ). Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is in the area from #DLTOP (start address of the download destination specified by FTDAR) + 32 bytes. Call the subroutine to execute initialization by using the following steps. MOV.L #DLTOP+32,ER2 ; Set entry address to ER2 JSR ; Call initialization routine @ER2 NOP The general registers other than R0L are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM. Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. Rev. 1.00, 03/04, page 566 of 730 8. The return value in the initialization program, the FPFR parameter is determined. 9. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasing. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasing, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. When the bus mastership is moved to other than the CPU, such as to the DMAC, the error protection state is entered. Therefore, make sure the DMAC does not acquire the bus. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. 11. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0. Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary. Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. Rev. 1.00, 03/04, page 567 of 730 12. Programming is executed. The entry point of the programming program is in the area from #DLTOP (start address of the download destination specified by FTDAR) + 16 bytes. Call the subroutine to execute programming by using the following steps. MOV.L #DLTOP+16,ER2 ; Set entry address to ER2 JSR @ER2 ; Call programming routine NOP The general registers other than R0L are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, the FPFR parameter is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev. 1.00, 03/04, page 568 of 730 (3) Erasing Procedure in User Program Mode The procedures for download of the on-chip program, initialization, and erasing are shown in figure 17.12. Start erasing procedure program 1 Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 after initializing VBR and execute download Set FEBS parameter 2. Erasing JSR FTDAR setting + 16 3. Clear FKEY to 0 DPFR = 0? Yes Yes Download error processing No Initialization JSR FTDAR setting + 32 4. FPFR = 1 ? No Set the FPEFEQ parameter Initialization Disable interrupts and bus master operation other than CPU 1. Erasing Download Select on-chip program to be downloaded and specify download destination by FTDAR No Clear FKEY and erasing error processing Required block erasing is completed? Yes Clear FKEY to 0 FPFR = 0 ? Yes 5. No Initialization error processing 6. End erasing procedure program 1 Figure 17.12 Erasing Procedure in User Program Mode Rev. 1.00, 03/04, page 569 of 730 The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. For the downloaded on-chip program area, see figure 17.10. One erasure processing erases one block. For details on block divisions, refer to figure 17.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 17.8.2 (2), Programming Procedure in User Program Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is in the area from #DLTOP (start address of the download destination specified by FTDAR) + 16 bytes. Call the subroutine to execute erasure by using the following steps. MOV.L #DLTOP+16, ER2 ; Set entry address to ER2 JSR ; Call erasing routine @ER2 NOP * * * The general registers other than R0L are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 s. Rev. 1.00, 03/04, page 570 of 730 (4) Procedure of Erasing, Programming, and RAM Emulation in User Program Mode By changing the on-chip RAM start address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 17.13 shows a repeating procedure of erasing, programming, and RAM emulation. 1 download Set FTDAR to H'02 (specify download destination H'FFB000) Emulation/Erasing/Programming Download erasing program Initialize erasing program Programming program Make a transition to RAM emulation mode and tuning parameters in on-chip RAM Set FTDAR to H'00 (specify download destination to H'FF9000) download Erasing program Start procedure program Exit emulation mode Erase relevant block (execute erasing program) Set FMPDR to H'FFA000 and program relevant block (execute programming program) Download programming program Confirm operation Initialize programming program End ? No Yes 1 End procedure program Figure 17.13 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Program Mode Rev. 1.00, 03/04, page 571 of 730 In figure 17.13, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program. * Be careful not to overwrite data in the on-chip RAM with overlay settings. In addition to the programming program area, erasing program area, and RAM emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: #DLTOP (start address of download destination for erasing program) + 32 bytes, and #DLTOP (start address of download destination for programming program) + 32 bytes. 17.8.3 User Boot Mode Branching to a programming/erasing program prepared by the user enables user boot mode which is a user-arbitrary boot mode to be used. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) Initiation in User Boot Mode When the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user MAT and user boot MAT states. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, the user boot MAT is selected (FMATS = H'AA) as the execution memory MAT. (2) User MAT Programming in User Boot Mode Figure 17.14 shows the procedure for programming the user MAT in user boot mode. The difference between the programming procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.14. For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after programming completes. Rev. 1.00, 03/04, page 572 of 730 Start programming procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 Set FKEY to H'A5 Set parameter to ER0 and ER1 (FMPAR and FMPDR) Clear FKEY to 0 Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting + 32 Yes No No No Clear FKEY and programming error processing Required data programming is completed? Clear FKEY to 0 Initialization error processing Set FMATS to H'AA to select user boot MAT Disable interrupts and bus master operation other than CPU 1 FPFR = 0 ? Yes FPFR = 0 ? Yes Programming No Yes User-MAT selection state Programming JSR FTDAR setting + 16 DPFR = 0 ? Initialization User-boot-MAT selection state Download Set SCO to 1 after initializing VBR and execute download MAT switchover End programming procedure program User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT. Figure 17.14 Procedure for Programming User MAT in User Boot Mode In user boot mode, though the user boot MAT can be seen in the flash memory space, the user MAT is hidden in the background. Therefore, the user MAT and user boot MAT are switched while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After programming completes, switch the memory MATs again to return to the first state. Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Rev. 1.00, 03/04, page 573 of 730 Except for memory MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. (3) User MAT Erasing in User Boot Mode Figure 17.15 shows the procedure for erasing the user MAT in user boot mode. The difference between the erasing procedures in user program mode and user boot mode is the memory MAT switching as shown in figure 17.15. For erasing the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after erasing completes. Start erasing procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Set FKEY to H'A5 Set FKEY to H'A5 Set FEBS parameter Clear FKEY to 0 No Download error processing Set the FPEFEQ and FUBRA parameters Initialization JSR FTDAR setting + 32 Erasing Yes User-MAT selection state Programming JSR FTDAR setting + 16 DPFR = 0 ? Initialization User-boot-MAT selection state Download Set SCO to 1 after initializing VBR and execute download Yes No No Clear FKEY and erasing error processing Required block erasing is completed? Yes FPFR = 0 ? No Yes FPFR = 0 ? Clear FKEY to 0 Initialization error processing Set FMATS to H'AA to select user boot MAT Disable interrupts and bus master operation other than CPU 1 End erasing procedure program User-boot-MAT selection state Note: The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT. Figure 17.15 Procedure for Erasing User MAT in User Boot Mode Rev. 1.00, 03/04, page 574 of 730 MAT switchover Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 17.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the erasing procedure is the same as that in user program mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.8.4, On-Chip Program and Storable Area for Program Data. Rev. 1.00, 03/04, page 575 of 730 17.8.4 On-Chip Program and Storable Area for Program Data In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied. * The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use. * Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area. * Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs. * In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasing starts (download result is determined). * The flash memory is not accessible during programming/erasing. Programming/erasing is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory. * After programming/erasing starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 s when the operating mode is changed and the reset start executed on completion of programming/erasing. Transitions to the reset state are inhibited during programming/erasing. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 s is needed before the reset signal is released. * Switching of the memory MATs by FMATS should be needed when programming/erasing of the user MAT is operated in user boot mode. The program which switches the memory MATs should be executed from the on-chip RAM. For details, see section 17.11, Switching between User MAT and User Boot MAT. Make sure you know which memory MAT is currently selected when switching them. * When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 17.7 to 17.11. Rev. 1.00, 03/04, page 576 of 730 Table 17.7 Executable Memory MAT Operating Mode Processing Contents User Program Mode User Boot Mode* Programming See table 17.8 See table 17.10 Erasing See table 17.9 See table 17.11 Note: * Programming/Erasing is possible to the user MAT. Table 17.8 Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT Embedded Program User MAT Storage MAT Storage area for program data O x* Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O x Operation for clearing FKEY O O O Decision of download result O O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O x O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O x O Operation for disabling interrupts O O O Operation for writing H'5A to FKEY O O O Operation for setting programming parameter O x O Execution of programming O x O Decision of programming result O x O Operation for programming error O x O Operation for clearing FKEY O x O Note: * Transferring the program data to the on-chip RAM beforehand enables this area to be used. Rev. 1.00, 03/04, page 577 of 730 Table 17.9 Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Item On-Chip RAM User MAT Embedded Program User MAT Storage MAT Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O x Operation for clearing FKEY O O O Decision of download result O O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O x O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O x O Operation for disabling interrupts O O O Operation for writing H'5A to FKEY O O O Operation for setting erasure parameter O x O Execution of erasure O x O Decision of erasure result O x O Operation for erasure error O x O Operation for clearing FKEY O x O Rev. 1.00, 03/04, page 578 of 730 Table 17.10 Usable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT Item On-Chip RAM User Boot User MAT MAT User Boot MAT Embedded Program Storage MAT Storage area for program data O x*1 Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O x Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O x O O Decision of initialization result O O O Operation for initialization error O O O NMI handling routine O x O Operation for disabling interrupts O O O Switching memory MATs by FMATS O x O Operation for writing H'5A to FKEY O x O Operation for setting programming parameter O x O Execution of programming O x O Decision of programming result O x Operation for programming error O x* Operation for clearing FKEY O x Switching memory MATs by FMATS O x O 2 O O O Notes: 1. Transferring the program data to the on-chip RAM beforehand enables this area to be used. 2. Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00, 03/04, page 579 of 730 Table 17.11 Usable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT On-Chip RAM User Boot User MAT MAT User Boot MAT Operation for selecting on-chip program to be downloaded O O O Operation for writing H'A5 to FKEY O O O Execution of writing 1 to SCO bit in FCCS (download) O x Operation for clearing FKEY O O O Decision of download result O O O Operation for download error O O O Operation for setting initialization parameter O O O Execution of initialization O x O Decision of initialization result O O O Item Embedded Program Storage MAT O Operation for initialization error O O O NMI handling routine O x O Operation for disabling interrupts O O O Switching memory MATs by FMATS O x O Operation for writing H'5A to FKEY O x O Operation for setting erasure parameter O x O Execution of erasure O x O Decision of erasure result O x O Operation for erasure error O x* O Operation for clearing FKEY O x O Switching memory MATs by FMATS O x O Note: Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used. Rev. 1.00, 03/04, page 580 of 730 17.9 Protection There are three types of protection against the flash memory programming/erasing: hardware protection, software protection, and error protection. 17.9.1 Hardware Protection Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasing is indicated by the FPFR parameter. Table 17.12 Hardware Protection Function to be Protected Item Description Download Programming/ Erasing Reset protection * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered. O O * The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Rev. 1.00, 03/04, page 581 of 730 17.9.2 Software Protection The software protection protects the flash memory against programming/erasing by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 17.13 Software Protection Function to be Protected Item Description Download Programming/ Erasing Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. O Protection by FKEY The programming/erasing protection state is entered because download and programming/erasing are disabled unless the required key code is written in FKEY. O O Emulation protection The programming/erasing protection state is O entered when the RAMS bit in the RAM emulation register (RAMER) is set to 1. O 17.9.3 Error Protection Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasing of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasing of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered. * When an interrupt request, such as NMI, occurs during programming/erasing. * When the flash memory is read from during programming/erasing (including a vector read or an instruction fetch). * When a SLEEP instruction is executed (including software-standby mode) during programming/erasing. * When a bus master other than the CPU, such as the DMAC, obtains bus mastership during programming/erasing. Rev. 1.00, 03/04, page 582 of 730 Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100 s has passed. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 17.16 shows transitions to and from the error protection state. Programming/erasing mode Reset (hardware protection) RES = 0 Read disabled Programming/erasing enabled FLER = 0 Er ror oc cu rre d oft wa re sta nd by S= RE (S Error occurrence 0 Read disabled Programming/erasing disabled FLER = 0 RES = 0 Programming/erasing interface register is in its initial state. ) Error-protection mode Read enabled Programming/erasing disabled FLER = 1 Software standby mode Cancel software standby mode Error-protection mode (software standby) Read disabled Programming/erasing disabled FLER = 1 Programming/erasing interface register is in its initial state. Figure 17.16 Transitions to Error Protection State Rev. 1.00, 03/04, page 583 of 730 17.10 Flash Memory Emulation Using RAM For realtime emulation of the data written to the flash memory using the on-chip RAM, the onchip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER). The overlaid area can be accessed from both the user MAT area specified by RAMER and the overlaid RAM area. The emulation can be performed in user mode and user program mode. Figure 17.17 shows an example of emulating realtime programming of the user MAT. Emulation program start Set RAMER Write tuning data to overlaid RAM area Execute application program No Tuning OK? Yes Cancel setting in RAMER Program emulation block in user MAT Emulation program end Figure 17.17 RAM Emulation Flow Rev. 1.00, 03/04, page 584 of 730 Figure 17.18 shows an example of overlaying flash memory block area EB0. This area can be accessed via both the on-chip RAM and flash memory area. H'00000 H'01000 EB0 EB1 H'02000 EB2 H'03000 EB3 H'04000 H'05000 H'06000 H'07000 EB4 EB5 EB6 H'FF9000 EB7 H'08000 Flash memory user MAT H'FFA000 H'FFAFFF On-chip RAM EB8 to EB11 H'3FFFF H'FFBFFF Figure 17.18 Address Map of Overlaid RAM Area The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in RAMER from among the eight blocks, EB0 to EB7, of the user MAT. To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in RAMER to 1 and bits RAM2 to RAM0 to B'000. For programming/erasing the user MAT, the procedure programs including a download program of the on-chip program must be executed. At this time, the download area should be specified so that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the tuned data must be saved in an unused area beforehand. Figure 17.19 shows an example of the procedure to program the tuned data in block EB0 of the user MAT. Rev. 1.00, 03/04, page 585 of 730 (1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. H'00000 H'01000 EB0 EB2 H'03000 EB3 H'05000 H'06000 H'07000 specified by FTDAR. FTDAR setting should avoid the tuned data area. EB1 H'02000 H'04000 (3) Download the on-chip programming/erasing program to the area (4) Program after erasing, if necessary. EB4 EB5 EB6 EB7 H'08000 Flash memory user MAT Download area EB8 to EB11 Tuned data area Area for programming/ erasing program etc. H'3FFFF Specified by FTDAR H'FFA000 H'FFAFFF H'FFB000 H'FFBFFF Figure 17.19 Programming Tuned Data 1. After tuning program data is completed, clear the RAMS bit in RAMER to 0 to cancel the overlaid RAM. 2. Transfer the user-created procedure program to the on-chip RAM. 3. Start the procedure program and download the on-chip program to the on-chip RAM. The start address of the download destination should be specified by FTDAR so that the tuned data area does not overlay the download area. 4. When block EB0 of the user MAT has not been erased, the programming program must be downloaded after block EB0 is erased. Specify the tuned data saved in the FMPAR and FMPDR parameters and then execute programming. Note: Setting the RAMS bit to 1 makes all the blocks of the user MAT enter the programming/erasing protection state (emulation protection state) regardless of the setting of the RAM2 to RAM0 bits. Under this condition, the on-chip program cannot be downloaded. When data is to be actually programmed and erased, clear the RAMS bit to 0. Rev. 1.00, 03/04, page 586 of 730 17.11 Switching between User MAT and User Boot MAT It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because the start addresses of these MATs are allocated to the same address. Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode. 1. Memory MAT switching by FMATS should always be executed from the on-chip RAM. 2. When accessing the memory MAT immediately after switching the memory MATs by FMATS from the on-chip RAM, similarly execute the NOP instruction in the on-chip RAM for eight times (this prevents access to the flash memory during memory MAT switching). 3. If an interrupt request has occurred during memory MAT switching, there is no guarantee of which memory MAT is accessed. Always mask the maskable interrupts before switching memory MATs. In addition, configure the system so that NMI interrupts do not occur during memory MAT switching. 4. After the memory MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after memory MAT switching, transfer the interrupt processing routines to the on-chip RAM and specify VBR to place the interrupt vector table in the on-chip RAM. 5. Memory sizes of the user MAT and user boot MAT are different. When accessing the user boot MAT, do not access addresses which exceed the 10-kbyte memory space. If an access is equal to or greater than 10 kbytes, the read values are undefined. <User MAT> <On-chip RAM> <User boot MAT> Procedure for switching to user boot MAT Procedure for switching to user MAT Procedure for switching to the user boot MAT 1. Inhibit interrupts (mask). 2. Write H'AA to FMATS. 3. Before access to the user boot MAT, execute the NOP instruction for eight times. Procedure for switching to the user MAT 1. Inhibit interrupts (mask). 2. Write other than H'AA to FMATS. 3. Before access to the user MAT, execute the NOP instruction for eight times. Figure 17.20 Switching between User MAT and User Boot MAT Rev. 1.00, 03/04, page 587 of 730 17.12 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 17.14 can be used to write programs to the on-chip ROM without any limitation. Table 17.14 Device Types Supported in Programmer Mode Target Memory MAT Size Device Type User MAT 256 kbytes FZTAT256V5A User boot MAT 10 kbytes FZTATUSBTV5A 17.13 Standard Serial Communication Interface Specifications for Boot Mode The boot program initiated in boot mode performs serial communication using the host and onchip SCI_4. The serial communication interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communication with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rateadjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs and user boot MATs before the transition. 3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. Rev. 1.00, 03/04, page 588 of 730 These boot program states are shown in figure 17.21. Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs and user boot MATs Programming/erasing wait Erasing Programming Operations for programming Checking Operations for erasing Operations for checking Figure 17.21 Boot Program States Rev. 1.00, 03/04, page 589 of 730 (1) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 17.22. Host Boot program H'00 (30 times maximum) Measuring the 1-bit length H'00 (completion of adjustment) H'55 H'E6 (boot response) (H'FF (error)) Figure 17.22 Bit-Rate-Adjustment Sequence (2) Communications Protocol After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry. 5. Memory read response This response consists of four bytes of data. Rev. 1.00, 03/04, page 590 of 730 One-byte command or one-byte response Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Command Memory read response Size Checksum Data Response Checksum Figure 17.23 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Data (n bytes): Detailed data of a command or response * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read Rev. 1.00, 03/04, page 591 of 730 (3) Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 17.15 lists the inquiry and selection commands. Table 17.15 Inquiry and Selection Commands Command Command Name Description H'20 Supported device inquiry Inquiry regarding device codes H'10 Device selection Selection of device code H'21 Clock mode inquiry Inquiry regarding numbers of clock modes and values of each mode H'11 Clock mode selection Indication of the selected clock mode H'22 Multiplication ratio inquiry Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple H'23 Operating clock frequency inquiry Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks H'24 User boot MAT information inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H'25 User MAT information inquiry Inquiry regarding the a number of user MATs and the start and last addresses of each MAT H'26 Block for erasing information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block H'27 Programming unit inquiry Inquiry regarding the unit of program data H'3F New bit rate selection Selection of new bit rate H'40 Transition to programming/erasing state Erasing of user MAT and user boot MAT, and entry to programming/erasing state H'4F Boot program status inquiry Inquiry into the operated status of the boot program Rev. 1.00, 03/04, page 592 of 730 The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry. Command H'20 * Command, H'20, (one byte): Inquiry regarding supported devices Response H'30 Size Number of devices Number of characters Device code Product name *** SUM * Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00. Rev. 1.00, 03/04, page 593 of 730 (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM * Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 2 * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR * Error response, H'90, (one byte): Error response to the device selection command ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry. Command H'21 * Command, H'21, (one byte): Inquiry regarding clock mode Response H'31 Size Number of modes Mode *** SUM * Response, H'31, (one byte): Response to the clock-mode inquiry * Size (one byte): Amount of data that represents the number of modes and modes * Number of clock modes (one byte): The number of supported clock modes H'00 indicates no clock mode or the device allows to read the clock mode. * Mode (one byte): Values of the supported clock modes (i.e. H'01 means clock mode 1.) * SUM (one byte): Checksum Rev. 1.00, 03/04, page 594 of 730 (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command * * * * H'11 Size Mode SUM Command, H'11, (one byte): Selection of clock mode Size (one byte): Amount of data that represents the modes Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches. Error Response H'91 ERROR * Error response, H'91, (one byte) : Error response to the clock mode selection command * ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. Rev. 1.00, 03/04, page 595 of 730 (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios. Command H'22 * Command, H'22, (one byte): Inquiry regarding multiplication ratio Response H'32 Size Number of types Number of multiplication ratios Multiplication ratio *** *** SUM * Response, H'32, (one byte): Response to the multiplication ratio inquiry * Size (one byte): The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios * Number of types (one byte): The number of supported multiplied clock types (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (one byte): The number of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types. * SUM (one byte): Checksum Rev. 1.00, 03/04, page 596 of 730 (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 * Command, H'23, (one byte): Inquiry regarding operating clock frequencies Response H'33 Size Minimum value of operating clock frequency Number of operating clock frequencies Maximum value of operating clock frequency *** SUM * Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 17.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (one byte): Checksum Rev. 1.00, 03/04, page 597 of 730 (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses. Command H'24 * Command, H'24, (one byte): Inquiry regarding user boot MAT information Response H'34 Size Number of areas Area-start address Area-last address *** SUM * Response, H'34, (one byte): Response to user boot MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address * Number of Areas (one byte): The number of consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. * Area-start address (four byte): Start address of the area * Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (h) User MAT Information Inquiry The boot program will return the number of user MATs and their addresses. Command H'25 * Command, H'25, (one byte): Inquiry regarding user MAT information Response H'35 Size Number of areas Start address area Last address area *** SUM * Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area * Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum Rev. 1.00, 03/04, page 598 of 730 (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 * Command, H'26, (two bytes): Inquiry regarding erased block information Response H'36 Size Number of blocks Block start address Block last address *** SUM * Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block start address (four bytes): Start address of a block * Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (j) Programming Unit Inquiry The boot program will return the programming unit used to program data. Command H'27 * Command, H'27, (one byte): Inquiry regarding programming unit Response H'37 Size Programming unit SUM * Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming. * SUM (one byte): Checksum Rev. 1.00, 03/04, page 599 of 730 (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Number of multiplication ratios Multiplication ratio 1 Multiplication ratio 2 Input frequency SUM * Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The number of bytes that represents the bit rate, input frequency, number of multiplication ratios, and multiplication ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Number of multiplication ratios (one byte): The number of multiplication ratios to which the device can be set. * Multiplication ratio 1 (one byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Rev. 1.00, 03/04, page 600 of 730 Error Response H'BF ERROR * Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. (4) Receive Data Check The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an inputfrequency error is generated. 3. Operating frequency error Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: Rev. 1.00, 03/04, page 601 of 730 Error (%) = {[ x 106 (N + 1) x B x 64 x 2(2xn - 1) ] - 1} x 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate. Confirmation H'06 * Confirmation, H'06, (one byte): Confirmation of a new bit rate Response H'06 * Response, H'06, (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 17.24. Boot program Host Setting a new bit rate H'06 (ACK) Waiting for one-bit period at the specified bit rate Setting a new bit rate Setting a new bit rate H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate Figure 17.24 New Bit-Rate Selection Sequence (5) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data. Rev. 1.00, 03/04, page 602 of 730 Command H'40 * Command, H'40, (one byte): Transition to programming/erasing state Response H'06 * Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program. Error Response H'C0 H'51 * Error response, H'C0, (one byte): Error response for user boot MAT blank check * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. (6) Command Error A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples. Error Response H'80 H'xx * Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command (7) Command Order The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). Rev. 1.00, 03/04, page 603 of 730 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state. (8) Programming/Erasing State A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 17.16 lists the programming/erasing commands. Table 17.16 Programming/Erasing Commands Command Command Name H'42 User boot MAT programming selection Transfers the user boot MAT programming program H'43 User MAT programming selection Transfers the user MAT programming program H'50 128-byte programming Programs 128 bytes of data H'48 Erasing selection Transfers the erasing program H'58 Block erasing Erases a block of data H'52 Memory read Reads the contents of memory H'4A User boot MAT sum check Checks the checksum of the user boot MAT H'4B User MAT sum check Checks the checksum of the user MAT H'4C User boot MAT blank check Checks the blank data of the user boot MAT H'4D User MAT blank check Checks the blank data of the user MAT H'4C User boot MAT blank check Checks whether the contents of the user boot MAT are blank H'4D User MAT blank check Checks whether the contents of the user MAT are blank H'4F Boot program status inquiry Inquires into the boot program's status Rev. 1.00, 03/04, page 604 of 730 Description * Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 17.25. Boot program Host Programming selection (H'42, H'43, H'44) Transfer of the programming program ACK 128-byte programming (address, data) Repeat Programming ACK 128-byte programming (H'FFFFFFFF) ACK Figure 17.25 Programming Sequence Rev. 1.00, 03/04, page 605 of 730 * Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 17.26. Host Boot program Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erasure block number) Erasure Repeat ACK Erasure (H'FF) ACK Figure 17.26 Erasure Sequence Rev. 1.00, 03/04, page 606 of 730 (a) User Boot MAT Programming Selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 * Command, H'42, (one byte): User boot-program programming selection Response H'06 * Response, H'06, (one byte): Response to user boot-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C2 ERROR * Error response : H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) User MAT Programming Selection The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming. Command H'43 * Command, H'43, (one byte): User-program programming selection Response H'06 * Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK. Error Response H'C3 ERROR * Error response : H'C3 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) Rev. 1.00, 03/04, page 607 of 730 (c) 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming. Command H'50 Address Data *** *** SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'01000000) * Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Rev. 1.00, 03/04, page 608 of 730 Command H'50 Address SUM * Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK. Error Response H'D0 ERROR * Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (d) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 * Command, H'48, (one byte): Erasure selection Response H'06 * Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK. Error Response H'C8 ERROR * Error Response, H'C8, (one byte): Error response to erasure selection * ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) Rev. 1.00, 03/04, page 609 of 730 (e) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK. Error Response H'D8 ERROR * Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command. Command H'58 Size Block number SUM * Command, H'58, (one byte): Erasure * Size, (one byte): The number of bytes that represents the block number This is fixed to 1. * Block number (one byte): H'FF Stop code for erasure * SUM (one byte): Checksum Response H'06 * Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Rev. 1.00, 03/04, page 610 of 730 (f)* Memory Read The boot program will return the data in the specified address. Command H'52 Size Area Read size Read address SUM * Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum Response H'52 Read size Data *** SUM * * * * Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (1 byte): Checksum Error Response H'D2 ERROR * Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. Rev. 1.00, 03/04, page 611 of 730 (g) User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value. Command H'4A * Command, H'4A, (one byte): Sum check for user-boot program Response H'5A Size Checksum of user boot program SUM * Response, H'5A, (one byte): Response to the sum check of user-boot program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (h) User-Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user program. Command H'4B * Command, H'4B, (one byte): Sum check for user program Response H'5B Size Checksum of user program SUM * Response, H'5B, (one byte): Response to the sum check of the user program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (i) User Boot MAT Blank Check The boot program will check whether or not all user boot MATs are blank and return the result. Command H'4C * Command, H'4C, (one byte): Blank check for user boot MAT Response H'06 * Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Rev. 1.00, 03/04, page 612 of 730 Error Response H'CC H'52 * Error Response, H'CC, (one byte): Response to blank check for user boot MAT * Error Code, H'52, (one byte): Erasure has not been completed. (j) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D * Command, H'4D, (one byte): Blank check for user MATs Response H'06 * Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CD H'52 * Error Response, H'CD, (one byte): Error response to the blank check of user MATs. * Error code, H'52, (one byte): Erasure has not been completed. (k) Boot Program State Inquiry The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state. Command H'4F * Command, H'4F, (one byte): Response * * * * H'5F Size Inquiry regarding boot program's state Status ERROR SUM Response, H'5F, (one byte): Response to boot program state inquiry Size (one byte): The number of bytes. This is fixed to 2. Status (one byte): State of the boot program ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. * SUM (one byte): Sum check Rev. 1.00, 03/04, page 613 of 730 Table 17.17 Status Code Code Description H'11 Device selection wait H'12 Clock mode selection wait H'13 Bit rate selection wait H'1F Programming/erasing state transition wait (bit rate selection is completed) H'31 Programming state for erasure H'3F Programming/erasing selection wait (erasure is completed) H'4F Program data receive wait H'5F Erase block specification wait (erasure is completed) Table 17.18 Error Code Code Description H'00 No error H'11 Sum check error H'12 Program size error H'21 Device code mismatch error H'22 Clock mode mismatch error H'24 Bit rate selection error H'25 Input frequency error H'26 Multiplication ratio error H'27 Operating frequency error H'29 Block number error H'2A Address error H'2B Data length error H'51 Erasure error H'52 Erasure incomplete error H'53 Programming error H'54 Selection processing error H'80 Command error H'FF Bit-rate-adjustment confirmation error Rev. 1.00, 03/04, page 614 of 730 17.14 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index does not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 256-kbyte on-chip flash memory and 5.0-V programming voltage. Do not select HN28F101 and 3.3-V programming voltage with the programmer parameters. Use only the specified socket adapter. 5. Do not remove the chip from the PROM programmer nor input a reset signal during programming/erasing in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 s. 6. The flash memory is not accessible until FKEY is cleared after programming/erasing starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasing has finished, secure the reset input period (period of RES = 0) of at least 100 s. Transition to the reset state during programming/erasing is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100 s. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 33 MHz, the download for each program takes approximately 50 s at the maximum. 11. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasing of the flash memory in this F-ZTAT H8SX microcomputer. Rev. 1.00, 03/04, page 615 of 730 12 Unlike a conventional F-ZTAT H8 or H8S microcomputers, measures against a program crash are not taken by WDT during programming/erasing. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. The interrupt generation cycle should take into consideration time to download a programming/erasing program and time to program/erase the flash memory. 13 When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 after immediately setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. Rev. 1.00, 03/04, page 616 of 730 Section 18 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (I), peripheral module clock (P), and external clock (B). The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, and divider. Figure 18.1 shows a block diagram of the clock pulse generator. Clock frequencies can be changed by the PLL circuit and divider in the CPG. Changing the system clock control register (SCKCR) setting by software can change the clock frequencies. This LSI supports three types of clocks: a system clock provided to the CPU and bus masters, a peripheral module clock provided to the peripheral modules, and an external clock provided to the external bus. These clocks can be specified independently. Note, however, that the frequencies of the peripheral clock and external clock are lower than that of the system clock. SCKCR ICK2 to ICK0 1/1 1/2 Selector System clock (I) 1/4 (to the CPU and 1/8 bus masters) SCKCR EXTAL Oscillator XTAL PLL circuit EXTAL x 8 Divider (1/1, 1/2, 1/4, and 1/8) PCK2 to PCK0 1/1 1/2 Peripheral module 1/4 Selector clock (P) 1/8 (to peripheral modules) SCKCR BCK2 to BCK0 1/1 1/2 Selector External bus clock (B) 1/4 (to the B pin) 1/8 Figure 18.1 Block Diagram of Clock Pulse Generator CPGSX00A_000020030600 Rev. 1.00, 03/04, page 617 of 730 18.1 Register Description The clock pulse generator has the following register. * System clock control register (SCKCR) 18.1.1 System Clock Control Register (SCKCR) SCKCR controls clock output and frequencies of the system, peripheral module, and external clocks, and selects the clock to be output. Bit Bit Name 15 14 13 12 11 10 9 8 PSTOP1 - POSEL1 - - ICK2 ICK1 ICK0 Initial Value R/W 0 0 0 0 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Bit Name - PCK2 PCK1 PCK0 - BCK2 BCK1 BCK0 Initial Value 0 0 1 0 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W Description 15 PSTOP1 0 R/W Clock Output Enable Controls output on PA7. * Normal operation 0: output 1: Fixed high * Software standby mode X: Fixed high * Hardware standby mode X: Hi-Z 14 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 13 POSEL1 0 R/W Output Select 1 Controls the output on PA7. 0: External clock (B) 1: Setting prohibited Rev. 1.00, 03/04, page 618 of 730 Bit Bit Name Initial Value R/W Description 12, 11 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 10 ICK2 0 R/W System Clock (I) Select 9 ICK1 1 R/W 8 ICK0 0 R/W These bits select the frequency of the system clock provided to the CPU and DMAC. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the peripheral module clock changes to the same frequency as the system clock if the frequency of the system clock is lower than that of the peripheral module clock. 7 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 6 PCK2 0 R/W Peripheral Module Clock (P) Select 5 PCK1 1 R/W 4 PCK0 0 R/W These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the peripheral module clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the peripheral module clock higher than that of the system clock, the clocks will have the same frequency in reality. 3 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00, 03/04, page 619 of 730 Bit Bit Name Initial Value R/W Description 2 BCK2 0 R/W External clock (B) Select 1 BCK1 1 R/W 0 BCK0 0 R/W These bits select the frequency of the external clock. The ratio to the input clock is as follows: 000: x 8 001: x 4 010: x 2 011: x 1 1XX: Setting prohibited The frequency of the external clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the external clock higher than that of the system clock, the clocks will have the same frequency in reality. Note: 18.2 X: Don't care Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 18.2.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping resistance Rd according to table 18.1. An AT-cut parallel-resonance type should be used. When the clock is provided by connecting a crystal resonator, a crystal resonator having a frequency of 4 to 9 MHz should be connected. CL1 EXTAL XTAL Rd CL2 10 pF CL1 = CL2 22 pF Figure 18.2 Connection of Crystal Resonator (Example) Table 18.1 Damping Resistance Value Frequency (MHz) 4 6 8 9 Rd () 500 300 200 100 Rev. 1.00, 03/04, page 620 of 730 Figure 18.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 18.2. CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 18.3 Crystal Resonator Equivalent Circuit Table 18.2 Crystal Resonator Characteristics Frequency (MHz) 4 6 8 9 RS Max. () 120 100 80 80 C0 Max. (pF) 7 7 7 7 18.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. EXTAL XTAL External clock input Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Counter clock input on XTAL pin Figure 18.4 External Clock Input (Examples) For the input conditions of the external clock, refer to table 21.4, Clock Timing, in section 21.3.1, Clock Timing. The input external clock should be from 4 to 9 MHz. Rev. 1.00, 03/04, page 621 of 730 18.3 PLL Circuit The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 8. The frequency multiplication factor is fixed. 18.4 Frequency Divider The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2 to ICK0 and PCK 2 to PCK0 are modified, this LSI operates at the modified frequency. 18.5 Usage Notes 18.5.1 Notes on Clock Pulse Generator 1. The following points should be noted since the frequency of (I: system clock and P: peripheral module clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of electrical characteristics. When the HCAN and SSU are in use, 8 MHz I 40 MHz, and 8 MHz P 20 MHz, the following settings are not permitted: I < 8MHz, I > 40 MHz, P < 8MHz, and P > 20 MHz. When the HCAN and SSU are not in use, 8 MHz I 40 MHz, and 8 MHz P 35 MHz, the following settings are not permitted: I < 8MHz, I > 40 MHz, P < 8MHz, and P > 35 MHz. 2. All the on-chip peripheral modules (except for the DMAC) operate on the P. Therefore, note that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. For details, see section 19.7.3, Setting Oscillation Settling Time after Clearing Software Standby Mode. 3. The relationship between the system clock and peripheral module clock is I P. In addition, the system clock setting has priority. Accordingly, P may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits PCK2 to PCK0. 4. Figure 18.5 shows the clock modification timing. After a value is written to SCKCR, this LSI waits for the current bus cycle to complete. After the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external clock. 5. When I > P is specified by SCKCR, signals from the peripheral modules must be synchronized with the system clock. When CPU instructions are used to clear the interrupt source flag of a peripheral module, the flag must be read after being cleared to 0. Rev. 1.00, 03/04, page 622 of 730 One cycle (worst case) after the bus cycle completion External clock I Bus master CPU CPU Operating clock specified in SCKCR CPU Operating clock changed Figure 18.5 Clock Modification Timing 18.5.2 Notes on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 18.5.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit as shown in figure 18.6 to prevent induction from interfering with correct oscillation. Inhibited Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 18.6 Note on Board Design for Oscillation Circuit Rev. 1.00, 03/04, page 623 of 730 Figure 18.7 shows a connection example of bypass capacitor. Please be sure to insert bypass capacitor (CB) close to the Vcc and Vss pins and its capacitance meets the characteristics of the user system board. This LSI VCL (41) VCC (68) VSS (39) VSS (71) VCC (22) VCC (54) VSS (20) VSS (52) CB*2 C1*1 CB*2 CB*2 Note: Numbers in parenthesis are pin numbers. 1. A 0.1-F capacitor should be used here. 2. CB is a laminated ceramic capacitor. Figure 18.7 Connection Example of Bypass Capacitor 18.5.4 Notes on Input Clock Frequency The frequency of the input clock is multiplied in the PLL circuit by a factor of 8. To reduce noises, a lower frequency ranging of 4 to 9 MHz is recommended. Rev. 1.00, 03/04, page 624 of 730 Section 19 Power-Down Modes This LSI has power consumption reduction functions, such as multi-clock function, module stop function, and transition function to power-down mode. 19.1 Features * Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. * Module stop function The functions for each peripheral modules can be stopped to make a transition to a powerdown mode. * Transition function to power-down mode Transition to a power-down mode is possible to stop the CPU, all the on-chip peripheral modules, and oscillator. * Three power-down modes Sleep mode All-module-clock-stop mode Software standby mode Table 19.1 shows conditions for making a transition to a power-down mode, states of the CPU and peripheral modules, and clearing method for each mode. After the reset state, since this LSI operates in normal program execution state, the modules, other than the DMAC are stopped. Rev. 1.00, 03/04, page 625 of 730 Table 19.1 Operating States Operating State Sleep Mode All-Module-Clock-Stop Mode Software Standby Mode Transition condition Control register + Control register + instruction instruction Cancellation method Interrupt Interrupt*2 External interrupt Oscillator Functions Functions Halted CPU Halted (retained) Halted (retained) Halted (retained) Functions Halted (retained) Watchdog timer Functions 3 Control register + instruction Other peripheral Functions modules Halted* Halted*1 I/O port Retained Retained Functions Notes: "Halted (retained)" in the table means that the internal register values are retained and internal operations are suspended. 1. SCI, HCAN, and SSU enter the reset state, and other peripheral modules retain their states. 2. External interrupt and some internal interrupts (watchdog timer) 3. HCAN enters the reset state, and other peripheral modules retain their states. SSBY = 0 Reset state SLEEP instruction Sleep mode RES pin = high All interrupts SLEEP instruction Program execution state Interrupt*1 SSBY = 0, ACSE = 1 MSTPCR = H'F[0-F]FFFFFF All-module-clockstop mode SLEEP instruction SSBY = 1 External interrupt*2 Software standby mode Program halted state Transition after exception handling Notes: 1. NMI, IRQ0 to IRQ14, and watchdog timer interrupts. 2. NMI and IRQ0 to IRQ14. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1. Figure 19.1 Mode Transitions Rev. 1.00, 03/04, page 626 of 730 19.2 Register Descriptions The registers related to the power-down modes are shown below. For details on the system clock control register (SCKCR), refer to section 18.1.1, System Clock Control Register (SCKCR). * * * * Standby control register (SBYCR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) 19.2.1 Standby Control Register (SBYCR) SBYCR controls software standby mode. Bit 7 Bit Name 5 4 3 2 1 0 SSBY - - STS4 STS3 STS2 STS1 STS0 0 1 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value R/W 6 Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby Specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using external interrupts and shifting to normal operation. For clearing, write 0 to this bit. When the WDT is used as the watchdog timer, the setting of this bit is disabled. In this case, a transition is always made to sleep mode or all-module-clock-stop mode after the SLEEP instruction is executed. 6 1 R/W Reserved This bit is always read as 1. The write value should always be 1. 5 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 1.00, 03/04, page 627 of 730 Bit Bit Name Initial Value R/W Description 4 STS4 0 R/W Standby Timer Select 4 to 0 3 STS3 1 R/W 2 STS2 1 R/W 1 STS1 1 R/W 0 STS0 1 R/W These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an external interrupt. With a crystal resonator, refer to table 19.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. With an external clock, a PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. While oscillation is being settled, the timer is counted on the P clock frequency. Careful consideration is required in multi-clock mode. 00000: Reserved 00001: Reserved 00010: Reserved 00011: Reserved 00100: Reserved 00101: Standby time = 64 states 00110: Standby time = 512 states 00111: Standby time = 1024 states 01000: Standby time = 2048 states 01001: Standby time = 4096 states 01010: Standby time = 16384 states 01011: Standby time = 32768 states 01100: Standby time = 65536 states 01101: Standby time = 131072 states 01110: Standby time = 262144 states 01111: Standby time = 524288 states 10000: Reserved 10001: Reserved 1001X: Reserved 101XX: Reserved 11XXX: Reserved Note: The flash memory settling time must be reserved. Rev. 1.00, 03/04, page 628 of 730 19.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) MSTPCRA and MSTPCRB control module stop mode. Setting a bit to 1 makes the corresponding module enter module stop mode, while clearing the bit to 0 clears module stop mode. * MSTPCRA Bit Bit Name 15 14 13 12 11 10 9 8 ACSE MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA9 MSTPA8 Initial Value R/W 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 MSTPB15 MSTPB14 MSTPB13 MSTPB12 MSTPB11 MSTPB10 MSTPB9 MSTPB8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name Initial Value R/W * MSTPCRB Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 7 6 5 4 3 2 1 0 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Rev. 1.00, 03/04, page 629 of 730 * MSTPCRA Bit Bit Name Initial Value R/W Module 15 ACSE 0 R/W All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop mode for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after module stop mode has been set for all the on-chip peripheral modules controlled by MSTPCR. 0: All-module-clock-stop mode disabled 1: All-module-clock-stop mode enabled 14 MSTPA14 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 13 MSTPA13 0 R/W DMA controller (DMAC) 12 MSTPA12 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 11 MSTPA11 1 R/W Reserved 10 MSTPA10 1 R/W 9 MSTPA9 1 R/W These bits are always read as 1. The write value should always be 1. 8 MSTPA8 1 R/W 7 MSTPA7 1 R/W 6 MSTPA6 1 R/W 5 MSTPA5 1 R/W 4 MSTPA4 1 R/W A/D converter (unit 1) 3 MSTPA3 1 R/W A/D converter (unit 0) 2 MSTPA2 1 R/W Reserved These bits are always read as 1. The write value should always be 1. 1 MSTPA1 1 R/W 16-bit timer pulse unit (TPU channels 11 to 6) 0 MSTPA0 1 R/W 16-bit timer pulse unit (TPU channels 5 to 0)* Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 630 of 730 * MSTPCRB Bit Bit Name 15 Initial Value R/W Module MSTPB15 1 R/W Programmable pulse generator (PPG)* 14 MSTPB14 1 R/W Reserved 13 MSTPB13 1 R/W These bits are always read as 1. The write value should always be 1. 12 MSTPB12 1 R/W Serial communication interface_4 (SCI_4) 11 MSTPB11 1 R/W Serial communication interface_3 (SCI_3) 10 MSTPB10 1 R/W Reserved 9 MSTPB9 1 R/W 8 MSTPB 1 R/W These bits are always read as 1. The write value should always be 1. 7 MSTPB7 1 R/W 6 MSTPB6 1 R/W 5 MSTPB5 1 R/W 4 MSTPB4 1 R/W 3 MSTPB3 1 R/W 2 MSTPB2 1 R/W 1 MSTPB1 1 R/W 0 MSTPB0 1 R/W Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 631 of 730 19.2.3 Module Stop Control Register C (MSTPCRC) When bits MSTPC1 and MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC1 and MSTPC0 bits to 1 while accessing the on-chip RAM. Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 14 13 12 11 10 9 8 MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC8 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Bit Name 15 Initial Value R/W Module MSTPC15 1 R/W Reserved 14 MSTPC14 1 R/W 13 MSTPC13 1 R/W These bits are always read as 1. The write value should always be 1. 12 MSTPC12 1 R/W 11 MSTPC11 1 R/W Controller area network (HCAN) 10 MSTPC10 1 R/W Synchronous serial communication unit 2 (SSU_2) 9 MSTPC9 1 R/W Synchronous serial communication unit 1 (SSU_1) 8 MSTPC8 1 R/W Synchronous serial communication unit 0 (SSU_0) 7 MSTPC7 0 R/W Reserved 6 MSTPC6 0 R/W 5 MSTPC5 0 R/W These bits are always read as 0. The write value should always be 0. 4 MSTPC4 0 R/W 3 MSTPC3 0 R/W 2 MSTPC2 0 R/W 1 MSTPC1 0 R/W On-chip RAM_1 (H'FFF9000 to H'FFF9FFF) 0 MSTPC0 0 R/W On-chip RAM_0 (H'FFFA000 to H'FFFBFFF) Rev. 1.00, 03/04, page 632 of 730 19.3 Multi-Clock Function When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified by bits BCK2 to BCK0. Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral module and external bus clocks. The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0. Multi-clock mode is cleared by clearing all of bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 to 0. A transition is made to normal mode at the end of the bus cycle, and multi-clock mode is cleared. If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, this LSI enters sleep mode. When sleep mode is cleared by an interrupt, multi-clock mode is restored. If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, this LSI enters software standby mode. When software standby mode is cleared by an external interrupt, multiclock mode is restored. When the RES pin is driven low, the reset state is entered and multi-clock mode is cleared. The same applies to a reset caused by watchdog timer overflow. 19.4 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI, HCAN and SSU are retained. After the reset state is cleared, all modules other than the DMAC and on-chip RAM are in module stop mode. The registers of the module for which module stop mode is selected cannot be read from or written to. Rev. 1.00, 03/04, page 633 of 730 19.5 Sleep Mode 19.5.1 Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. 19.5.2 Clearing Sleep Mode Sleep mode is exited by any interrupt, signals on the RES pin, and a reset caused by a watchdog timer overflow. 1. Clearing by interrupt When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. 2. Clearing by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start the reset exception processing. 3. Clearing by reset caused by watchdog timer overflow Sleep mode is exited by an internal reset caused by a watchdog timer overflow. 19.6 All-Module-Clock-Stop Mode When the ACSE bit in MSTPCRA is set to 1 and all modules controlled by MSTPCR are stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the watchdog timer), the bus controller, and the I/O ports to stop operating, and to make a transition to all-module-clock-stop mode at the end of the bus cycle. All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ14 pins), RES pin input, or an internal interrupt (watchdog timer), and the CPU returns to the normal program execution state via the exception handling state. All-module-clock-stop mode is not cleared if interrupts are disabled or interrupts other than NMI are masked on the CPU side. Rev. 1.00, 03/04, page 634 of 730 19.7 Software Standby Mode 19.7.1 Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, HCAN, and SSU, and the states of the I/O ports, are retained. In this mode the oscillator stops, allowing power consumption to be significantly reduced. If the WDT is used as a watchdog timer, it is impossible to make a transition to software standby mode. The WDT should be stopped before the SLEEP instruction execution. 19.7.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ14*), or by means of the RES pin. 1. Clearing by interrupt When an NMI or IRQ0 to IRQ14* interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ14* interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DMAC activation source. Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ14 can be used as a software standby mode clearing source. 2. Clearing by RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling. Rev. 1.00, 03/04, page 635 of 730 19.7.3 Setting Oscillation Settling Time after Clearing Software Standby Mode Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 19.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0. 2. Using an external clock A PLL circuit settling time is necessary. Refer to table 19.2 to set the standby time. Table 19.2 Oscillation Settling Time Settings P* [MHz] Standby STS4 STS3 STS2 STS1 STS0 Time 35 25 20 Unit 0 Reserved s 0 0 1 0 0 1 Reserved 1 0 Reserved 1 Reserved 0 Reserved 1 64 1.8 2.6 3.2 0 512 14.6 20.5 25.6 1 1024 29.3 41.0 51.2 0 0 2048 58.5 81.9 102.4 1 4096 0.12 0.16 0.20 1 0 16384 0.47 0.66 0.82 1 32768 0.94 1.31 1.64 0 65536 1.87 2.62 3.28 1 131072 3.74 5.24 6.55 0 262144 7.49 10.49 13.11 1 524288 14.98 20.97 26.21 0 Reserved 0 1 1 0 1 0 1 1 0 0 0 : Recommended time setting when using a crystal resonator. : Recommended time setting when using an external clock. Note: * P is the output from the peripheral module frequency divider. Rev. 1.00, 03/04, page 636 of 730 ms P* [MHz] Standby STS4 STS3 STS2 STS1 STS0 Time 13 10 8 Unit 0 s 0 0 1 0 Reserved 1 Reserved 1 0 Reserved 1 Reserved 0 0 Reserved 1 64 4.9 6.4 8.0 0 512 39.4 51.2 64.0 1 1024 78.8 102.4 128.0 0 2048 157.5 204.8 256.0 1 4096 0.32 0.41 0.51 1 0 16384 1.26 1.64 2.05 1 32765 2.52 3.28 4.10 0 0 65536 5.04 6.55 8.19 1 131072 10.08 13.11 16.38 0 262144 20.16 26.21 32.77 1 524288 40.33 52.43 65.54 0 Reserved 0 1 1 0 1 0 1 1 0 0 0 ms : Recommended time setting when using a crystal resonator. : Recommended time setting when using an external clock. Note: * is the output from the peripheral module frequency divider. Rev. 1.00, 03/04, page 637 of 730 19.7.4 Software Standby Mode Application Example Figure 19.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2 NMI exception handling SLEEP instruction Figure 19.2 Software Standby Mode Application Example Rev. 1.00, 03/04, page 638 of 730 19.8 B Clock Output Control Output of the B clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for the corresponding PA7 pin. Clearing both bits PSTOP1 and POSEL1 to 0 enables the B clock output on the PA7 pin. When bit PSTOP1 is set to 1, the B clock output stops at the end of the bus cycle, and the B clock output goes high. When DDR for the PA7 pin is cleared to 0, the B clock output is disabled and the pin becomes an input port. Disabling B output can reduce electromagnetic interference (EMI). Take it into consideration for design of the user system board. Tables 19.3 shows the states of the B pin in each processing state. Table 19.3 B Pin (PA7) State in Each Processing State Register Setting Value DDR PSTOP1 POSEL1 Normal Operating State All-Module- Software Standby Mode Clock-Stop Sleep Mode Mode OPE = 0 OPE = 1 0 X X Hi-Z Hi-Z Hi-Z 1 0 0 B output B output B output High High 1 0 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 X High High High High High Hi-Z Hi-Z Rev. 1.00, 03/04, page 639 of 730 19.9 Usage Notes 19.9.1 I/O Port Status In software standby mode, the I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 19.9.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period. 19.9.3 DMAC Module Stop Depending on the operating state of the DMAC, bit MSTPA13 may not be set to 1. Setting of the DMAC module stop mode should be carried out only when the DMAC is not activated. For details, refer to section 7, DMA Controller (DMAC). 19.9.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC activation source. Interrupts should therefore be disabled before entering module stop mode. 19.9.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU. Rev. 1.00, 03/04, page 640 of 730 Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * 2. * * * * 3. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified according to functional modules. Undefined and reserved addresses cannot be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. Register bits Bit configurations of the registers are listed in the same order as the register addresses. Reserved bits are indicated by in the bit name column. Space in the bit name field indicates that the entire register is allocated to either the counter or data. For the registers of 16 or 32 bits, the MSB is listed first. Byte configuration description order is subject to big endian. Register states in each operating mode Register states are listed in the same order as the register addresses. For the initialized state of each bit, refer to the register description in the corresponding section. The register states shown here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. Rev. 1.00, 03/04, page 641 of 730 20.1 Register Addresses (Address Order) Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Master control register MCR 8 H'FEA00 HCAN 16 4P/4P General status register GSR 8 H'FEA01 HCAN 16 4P/4P Bit configuration register BCR 16 H'FEA02 HCAN 16 4P/4P Mailbox configuration register MBCR 16 H'FEA04 HCAN 16 4P/4P Transmit wait register TXPR 16 H'FEA06 HCAN 16 4P/4P Transmit wait cancel register TXCR 16 H'FEA08 HCAN 16 4P/4P Transmit acknowledge register TXACK 16 H'FEA0A HCAN 16 4P/4P Abort acknowledge register ABACK 16 H'FEA0C HCAN 16 4P/4P Receive complete register RXPR 16 H'FEA0E HCAN 16 4P/4P Remote request register RFPR 16 H'FEA10 HCAN 16 4P/4P Interrupt register IRR 16 H'FEA12 HCAN 16 4P/4P Mailbox interrupt mask register MBIMR 16 H'FEA14 HCAN 16 4P/4P Interrupt mask register IMR 16 H'FEA16 HCAN 16 4P/4P Receive error counter REC 8 H'FEA18 HCAN 16 4P/4P Transmit error counter TEC 8 H'FEA19 HCAN 16 4P/4P Unread message status register UMSR 16 H'FEA1A HCAN 16 4P/4P Local acceptance filter mask L LAFML 16 H'FEA1C HCAN 16 4P/4P Local acceptance filter mask H LAFMH 16 H'FEA1E HCAN 16 4P/4P Message control 0 [1] MC0[1] 8 H'FEA20 HCAN 16 4P/4P Message control 0 [2] MC0[2] 8 H'FEA21 HCAN 16 4P/4P Message control 0 [3] MC0[3] 8 H'FEA22 HCAN 16 4P/4P Message control 0 [4] MC0[4] 8 H'FEA23 HCAN 16 4P/4P Message control 0 [5] MC0[5] 8 H'FEA24 HCAN 16 4P/4P Message control 0 [6] MC0[6] 8 H'FEA25 HCAN 16 4P/4P Message control 0 [7] MC0[7] 8 H'FEA26 HCAN 16 4P/4P Message control 0 [8] MC0[8] 8 H'FEA27 HCAN 16 4P/4P Message control 1 [1] MC1[1] 8 H'FEA28 HCAN 16 4P/4P Message control 1 [2] MC1[2] 8 H'FEA29 HCAN 16 4P/4P Message control 1 [3] MC1[3] 8 H'FEA2A HCAN 16 4P/4P Rev. 1.00, 03/04, page 642 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message control 1 [4] MC1[4] 8 H'FEA2B HCAN 16 4P/4P Message control 1 [5] MC1[5] 8 H'FEA2C HCAN 16 4P/4P Message control 1 [6] MC1[6] 8 H'FEA2D HCAN 16 4P/4P Message control 1 [7] MC1[7] 8 H'FEA2E HCAN 16 4P/4P Message control 1 [8] MC1[8] 8 H'FEA2F HCAN 16 4P/4P Message control 2 [1] MC2[1] 8 H'FEA30 HCAN 16 4P/4P Message control 2 [2] MC2[2] 8 H'FEA31 HCAN 16 4P/4P Message control 2 [3] MC2[3] 8 H'FEA32 HCAN 16 4P/4P Message control 2 [4] MC2[4] 8 H'FEA33 HCAN 16 4P/4P Message control 2 [5] MC2[5] 8 H'FEA34 HCAN 16 4P/4P Message control 2 [6] MC2[6] 8 H'FEA35 HCAN 16 4P/4P Message control 2 [7] MC2[7] 8 H'FEA36 HCAN 16 4P/4P Message control 2 [8] MC2[8] 8 H'FEA37 HCAN 16 4P/4P Message control 3 [1] MC3[1] 8 H'FEA38 HCAN 16 4P/4P Message control 3 [2] MC3[2] 8 H'FEA39 HCAN 16 4P/4P Message control 3 [3] MC3[3] 8 H'FEA3A HCAN 16 4P/4P Message control 3 [4] MC3[4] 8 H'FEA3B HCAN 16 4P/4P Message control 3 [5] MC3[5] 8 H'FEA3C HCAN 16 4P/4P Message control 3 [6] MC3[6] 8 H'FEA3D HCAN 16 4P/4P Message control 3 [7] MC3[7] 8 H'FEA3E HCAN 16 4P/4P Message control 3 [8] MC3[8] 8 H'FEA3F HCAN 16 4P/4P Message control 4 [1] MC4[1] 8 H'FEA40 HCAN 16 4P/4P Message control 4 [2] MC4[2] 8 H'FEA41 HCAN 16 4P/4P Message control 4 [3] MC4[3] 8 H'FEA42 HCAN 16 4P/4P Message control 4 [4] MC4[4] 8 H'FEA43 HCAN 16 4P/4P Message control 4 [5] MC4[5] 8 H'FEA44 HCAN 16 4P/4P Message control 4 [6] MC4[6] 8 H'FEA45 HCAN 16 4P/4P Message control 4 [7] MC4[7] 8 H'FEA46 HCAN 16 4P/4P Message control 4 [8] MC4[8] 8 H'FEA47 HCAN 16 4P/4P Message control 5 [1] MC5[1] 8 H'FEA48 HCAN 16 4P/4P Message control 5 [2] MC5[2] 8 H'FEA49 HCAN 16 4P/4P Message control 5 [3] MC5[3] 8 H'FEA4A HCAN 16 4P/4P Rev. 1.00, 03/04, page 643 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message control 5 [4] MC5[4] 8 H'FEA4B HCAN 16 4P/4P Message control 5 [5] MC5[5] 8 H'FEA4C HCAN 16 4P/4P Message control 5 [6] MC5[6] 8 H'FEA4D HCAN 16 4P/4P Message control 5 [7] MC5[7] 8 H'FEA4E HCAN 16 4P/4P Message control 5 [8] MC5[8] 8 H'FEA4F HCAN 16 4P/4P Message control 6 [1] MC6[1] 8 H'FEA50 HCAN 16 4P/4P Message control 6 [2] MC6[2] 8 H'FEA51 HCAN 16 4P/4P Message control 6 [3] MC6[3] 8 H'FEA52 HCAN 16 4P/4P Message control 6 [4] MC6[4] 8 H'FEA53 HCAN 16 4P/4P Message control 6 [5] MC6[5] 8 H'FEA54 HCAN 16 4P/4P Message control 6 [6] MC6[6] 8 H'FEA55 HCAN 16 4P/4P Message control 6 [7] MC6[7] 8 H'FEA56 HCAN 16 4P/4P Message control 6 [8] MC6[8] 8 H'FEA57 HCAN 16 4P/4P Message control 7 [1] MC7[1] 8 H'FEA58 HCAN 16 4P/4P Message control 7 [2] MC7[2] 8 H'FEA59 HCAN 16 4P/4P Message control 7 [3] MC7[3] 8 H'FEA5A HCAN 16 4P/4P Message control 7 [4] MC7[4] 8 H'FEA5B HCAN 16 4P/4P Message control 7 [5] MC7[5] 8 H'FEA5C HCAN 16 4P/4P Message control 7 [6] MC7[6] 8 H'FEA5D HCAN 16 4P/4P Message control 7 [7] MC7[7] 8 H'FEA5E HCAN 16 4P/4P Message control 7 [8] MC7[8] 8 H'FEA5F HCAN 16 4P/4P Message control 8 [1] MC8[1] 8 H'FEA60 HCAN 16 4P/4P Message control 8 [2] MC8[2] 8 H'FEA61 HCAN 16 4P/4P Message control 8 [3] MC8[3] 8 H'FEA62 HCAN 16 4P/4P Message control 8 [4] MC8[4] 8 H'FEA63 HCAN 16 4P/4P Message control 8 [5] MC8[5] 8 H'FEA64 HCAN 16 4P/4P Message control 8 [6] MC8[6] 8 H'FEA65 HCAN 16 4P/4P Message control 8 [7] MC8[7] 8 H'FEA66 HCAN 16 4P/4P Message control 8 [8] MC8[8] 8 H'FEA67 HCAN 16 4P/4P Message control 9 [1] MC9[1] 8 H'FEA68 HCAN 16 4P/4P Message control 9 [2] MC9[2] 8 H'FEA69 HCAN 16 4P/4P Message control 9 [3] MC9[3] 8 H'FEA6A HCAN 16 4P/4P Rev. 1.00, 03/04, page 644 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message control 9 [4] MC9[4] 8 H'FEA6B HCAN 16 4P/4P Message control 9 [5] MC9[5] 8 H'FEA6C HCAN 16 4P/4P Message control 9 [6] MC9[6] 8 H'FEA6D HCAN 16 4P/4P Message control 9 [7] MC9[7] 8 H'FEA6E HCAN 16 4P/4P Message control 9 [8] MC9[8] 8 H'FEA6F HCAN 16 4P/4P Message control 10 [1] MC10[1] 8 H'FEA70 HCAN 16 4P/4P Message control 10 [2] MC10[2] 8 H'FEA71 HCAN 16 4P/4P Message control 10 [3] MC10[3] 8 H'FEA72 HCAN 16 4P/4P Message control 10 [4] MC10[4] 8 H'FEA73 HCAN 16 4P/4P Message control 10 [5] MC10[5] 8 H'FEA74 HCAN 16 4P/4P Message control 10 [6] MC10[6] 8 H'FEA75 HCAN 16 4P/4P Message control 10 [7] MC10[7] 8 H'FEA76 HCAN 16 4P/4P Message control 10 [8] MC10[8] 8 H'FEA77 HCAN 16 4P/4P Message control 11 [1] MC11[1] 8 H'FEA78 HCAN 16 4P/4P Message control 11 [2] MC11[2] 8 H'FEA79 HCAN 16 4P/4P Message control 11 [3] MC11[3] 8 H'FEA7A HCAN 16 4P/4P Message control 11 [4] MC11[4] 8 H'FEA7B HCAN 16 4P/4P Message control 11 [5] MC11[5] 8 H'FEA7C HCAN 16 4P/4P Message control 11 [6] MC11[6] 8 H'FEA7D HCAN 16 4P/4P Message control 11 [7] MC11[7] 8 H'FEA7E HCAN 16 4P/4P Message control 11 [8] MC11[8] 8 H'FEA7F HCAN 16 4P/4P Message control 12 [1] MC12[1] 8 H'FEA80 HCAN 16 4P/4P Message control 12 [2] MC12[2] 8 H'FEA81 HCAN 16 4P/4P Message control 12 [3] MC12[3] 8 H'FEA82 HCAN 16 4P/4P Message control 12 [4] MC12[4] 8 H'FEA83 HCAN 16 4P/4P Message control 12 [5] MC12[5] 8 H'FEA84 HCAN 16 4P/4P Message control 12 [6] MC12[6] 8 H'FEA85 HCAN 16 4P/4P Message control 12 [7] MC12[7] 8 H'FEA86 HCAN 16 4P/4P Message control 12 [8] MC12[8] 8 H'FEA87 HCAN 16 4P/4P Message control 13 [1] MC13[1] 8 H'FEA88 HCAN 16 4P/4P Message control 13 [2] MC13[2] 8 H'FEA89 HCAN 16 4P/4P Message control 13 [3] MC13[3] 8 H'FEA8A HCAN 16 4P/4P Rev. 1.00, 03/04, page 645 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message control 13 [4] MC13[4] 8 H'FEA8B HCAN 16 4P/4P Message control 13 [5] MC13[5] 8 H'FEA8C HCAN 16 4P/4P Message control 13 [6] MC13[6] 8 H'FEA8D HCAN 16 4P/4P Message control 13 [7] MC13[7] 8 H'FEA8E HCAN 16 4P/4P Message control 13 [8] MC13[8] 8 H'FEA8F HCAN 16 4P/4P Message control 14 [1] MC14[1] 8 H'FEA90 HCAN 16 4P/4P Message control 14 [2] MC14[2] 8 H'FEA91 HCAN 16 4P/4P Message control 14 [3] MC14[3] 8 H'FEA92 HCAN 16 4P/4P Message control 14 [4] MC14[4] 8 H'FEA93 HCAN 16 4P/4P Message control 14 [5] MC14[5] 8 H'FEA94 HCAN 16 4P/4P Message control 14 [6] MC14[6] 8 H'FEA95 HCAN 16 4P/4P Message control 14 [7] MC14[7] 8 H'FEA96 HCAN 16 4P/4P Message control 14 [8] MC14[8] 8 H'FEA97 HCAN 16 4P/4P Message control 15 [1] MC15[1] 8 H'FEA98 HCAN 16 4P/4P Message control 15 [2] MC15[2] 8 H'FEA99 HCAN 16 4P/4P Message control 15 [3] MC15[3] 8 H'FEA9A HCAN 16 4P/4P Message control 15 [4] MC15[4] 8 H'FEA9B HCAN 16 4P/4P Message control 15 [5] MC15[5] 8 H'FEA9C HCAN 16 4P/4P Message control 15 [6] MC15[6] 8 H'FEA9D HCAN 16 4P/4P Message control 15 [7] MC15[7] 8 H'FEA9E HCAN 16 4P/4P Message control 15 [8] MC15[8] 8 H'FEA9F HCAN 16 4P/4P Message data 0 [1] MD0[1] 8 H'FEAB0 HCAN 16 4P/4P Message data 0 [2] MD0[2] 8 H'FEAB1 HCAN 16 4P/4P Message data 0 [3] MD0[3] 8 H'FEAB2 HCAN 16 4P/4P Message data 0 [4] MD0[4] 8 H'FEAB3 HCAN 16 4P/4P Message data 0 [5] MD0[5] 8 H'FEAB4 HCAN 16 4P/4P Message data 0 [6] MD0[6] 8 H'FEAB5 HCAN 16 4P/4P Message data 0 [7] MD0[7] 8 H'FEAB6 HCAN 16 4P/4P Message data 0 [8] MD0[8] 8 H'FEAB7 HCAN 16 4P/4P Message data 1 [1] MD1[1] 8 H'FEAB8 HCAN 16 4P/4P Message data 1 [2] MD1[2] 8 H'FEAB9 HCAN 16 4P/4P Message data 1 [3] MD1[3] 8 H'FEABA HCAN 16 4P/4P Rev. 1.00, 03/04, page 646 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message data 1 [4] MD1[4] 8 H'FEABB HCAN 16 4P/4P Message data 1 [5] MD1[5] 8 H'FEABC HCAN 16 4P/4P Message data 1 [6] MD1[6] 8 H'FEABD HCAN 16 4P/4P Message data 1 [7] MD1[7] 8 H'FEABE HCAN 16 4P/4P Message data 1 [8] MD1[8] 8 H'FEABF HCAN 16 4P/4P Message data 2 [1] MD2[1] 8 H'FEAC0 HCAN 16 4P/4P Message data 2 [2] MD2[2] 8 H'FEAC1 HCAN 16 4P/4P Message data 2 [3] MD2[3] 8 H'FEAC2 HCAN 16 4P/4P Message data 2 [4] MD2[4] 8 H'FEAC3 HCAN 16 4P/4P Message data 2 [5] MD2[5] 8 H'FEAC4 HCAN 16 4P/4P Message data 2 [6] MD2[6] 8 H'FEAC5 HCAN 16 4P/4P Message data 2 [7] MD2[7] 8 H'FEAC6 HCAN 16 4P/4P Message data 2 [8] MD2[8] 8 H'FEAC7 HCAN 16 4P/4P Message data 3 [1] MD3[1] 8 H'FEAC8 HCAN 16 4P/4P Message data 3 [2] MD3[2] 8 H'FEAC9 HCAN 16 4P/4P Message data 3 [3] MD3[3] 8 H'FEACA HCAN 16 4P/4P Message data 3 [4] MD3[4] 8 H'FEACB HCAN 16 4P/4P Message data 3 [5] MD3[5] 8 H'FEACC HCAN 16 4P/4P Message data 3 [6] MD3[6] 8 H'FEACD HCAN 16 4P/4P Message data 3 [7] MD3[7] 8 H'FEACE HCAN 16 4P/4P Message data 3 [8] MD3[8] 8 H'FEACF HCAN 16 4P/4P Message data 4 [1] MD4[1] 8 H'FEAD0 HCAN 16 4P/4P Message data 4 [2] MD4[2] 8 H'FEAD1 HCAN 16 4P/4P Message data 4 [3] MD4[3] 8 H'FEAD2 HCAN 16 4P/4P Message data 4 [4] MD4[4] 8 H'FEAD3 HCAN 16 4P/4P Message data 4 [5] MD4[5] 8 H'FEAD4 HCAN 16 4P/4P Message data 4 [6] MD4[6] 8 H'FEAD5 HCAN 16 4P/4P Message data 4 [7] MD4[7] 8 H'FEAD6 HCAN 16 4P/4P Message data 4 [8] MD4[8] 8 H'FEAD7 HCAN 16 4P/4P Message data 5 [1] MD5[1] 8 H'FEAD8 HCAN 16 4P/4P Message data 5 [2] MD5[2] 8 H'FEAD9 HCAN 16 4P/4P Message data 5 [3] MD5[3] 8 H'FEADA HCAN 16 4P/4P Rev. 1.00, 03/04, page 647 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message data 5 [4] MD5[4] 8 H'FEADB HCAN 16 4P/4P Message data 5 [5] MD5[5] 8 H'FEADC HCAN 16 4P/4P Message data 5 [6] MD5[6] 8 H'FEADD HCAN 16 4P/4P Message data 5 [7] MD5[7] 8 H'FEADE HCAN 16 4P/4P Message data 5 [8] MD5[8] 8 H'FEADF HCAN 16 4P/4P Message data 6 [1] MD6[1] 8 H'FEAE0 HCAN 16 4P/4P Message data 6 [2] MD6[2] 8 H'FEAE1 HCAN 16 4P/4P Message data 6 [3] MD6[3] 8 H'FEAE2 HCAN 16 4P/4P Message data 6 [4] MD6[4] 8 H'FEAE3 HCAN 16 4P/4P Message data 6 [5] MD6[5] 8 H'FEAE4 HCAN 16 4P/4P Message data 6 [6] MD6[6] 8 H'FEAE5 HCAN 16 4P/4P Message data 6 [7] MD6[7] 8 H'FEAE6 HCAN 16 4P/4P Message data 6 [8] MD6[8] 8 H'FEAE7 HCAN 16 4P/4P Message data 7 [1] MD7[1] 8 H'FEAE8 HCAN 16 4P/4P Message data 7 [2] MD7[2] 8 H'FEAE9 HCAN 16 4P/4P Message data 7 [3] MD7[3] 8 H'FEAEA HCAN 16 4P/4P Message data 7 [4] MD7[4] 8 H'FEAEB HCAN 16 4P/4P Message data 7 [5] MD7[5] 8 H'FEAEC HCAN 16 4P/4P Message data 7 [6] MD7[6] 8 H'FEAED HCAN 16 4P/4P Message data 7 [7] MD7[7] 8 H'FEAEE HCAN 16 4P/4P Message data 7 [8] MD7[8] 8 H'FEAEF HCAN 16 4P/4P Message data 8 [1] MD8[1] 8 H'FEAF0 HCAN 16 4P/4P Message data 8 [2] MD8[2] 8 H'FEAF1 HCAN 16 4P/4P Message data 8 [3] MD8[3] 8 H'FEAF2 HCAN 16 4P/4P Message data 8 [4] MD8[4] 8 H'FEAF3 HCAN 16 4P/4P Message data 8 [5] MD8[5] 8 H'FEAF4 HCAN 16 4P/4P Message data 8 [6] MD8[6] 8 H'FEAF5 HCAN 16 4P/4P Message data 8 [7] MD8[7] 8 H'FEAF6 HCAN 16 4P/4P Message data 8 [8] MD8[8] 8 H'FEAF7 HCAN 16 4P/4P Message data 9 [1] MD9[1] 8 H'FEAF8 HCAN 16 4P/4P Message data 9 [2] MD9[2] 8 H'FEAF9 HCAN 16 4P/4P Message data 9 [3] MD9[3] 8 H'FEAFA HCAN 16 4P/4P Rev. 1.00, 03/04, page 648 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message data 9 [4] MD9[4] 8 H'FEAFB HCAN 16 4P/4P Message data 9 [5] MD9[5] 8 H'FEAFC HCAN 16 4P/4P Message data 9 [6] MD9[6] 8 H'FEAFD HCAN 16 4P/4P Message data 9 [7] MD9[7] 8 H'FEAFE HCAN 16 4P/4P Message data 9 [8] MD9[8] 8 H'FEAFF HCAN 16 4P/4P Message data 10 [1] MD10[1] 8 H'FEB00 HCAN 16 4P/4P Message data 10 [2] MD10[2] 8 H'FEB01 HCAN 16 4P/4P Message data 10 [3] MD10[3] 8 H'FEB02 HCAN 16 4P/4P Message data 10 [4] MD10[4] 8 H'FEB03 HCAN 16 4P/4P Message data 10 [5] MD10[5] 8 H'FEB04 HCAN 16 4P/4P Message data 10 [6] MD10[6] 8 H'FEB05 HCAN 16 4P/4P Message data 10 [7] MD10[7] 8 H'FEB06 HCAN 16 4P/4P Message data 10 [8] MD10[8] 8 H'FEB07 HCAN 16 4P/4P Message data 11 [1] MD11[1] 8 H'FEB08 HCAN 16 4P/4P Message data 11 [2] MD11[2] 8 H'FEB09 HCAN 16 4P/4P Message data 11 [3] MD11[3] 8 H'FEB0A HCAN 16 4P/4P Message data 11 [4] MD11[4] 8 H'FEB0B HCAN 16 4P/4P Message data 11 [5] MD11[5] 8 H'FEB0C HCAN 16 4P/4P Message data 11 [6] MD11[6] 8 H'FEB0D HCAN 16 4P/4P Message data 11 [7] MD11[7] 8 H'FEB0E HCAN 16 4P/4P Message data 11 [8] MD11[8] 8 H'FEB0F HCAN 16 4P/4P Message data 12 [1] MD12[1] 8 H'FEB10 HCAN 16 4P/4P Message data 12 [2] MD12[2] 8 H'FEB11 HCAN 16 4P/4P Message data 12 [3] MD12[3] 8 H'FEB12 HCAN 16 4P/4P Message data 12 [4] MD12[4] 8 H'FEB13 HCAN 16 4P/4P Message data 12 [5] MD12[5] 8 H'FEB14 HCAN 16 4P/4P Message data 12 [6] MD12[6] 8 H'FEB15 HCAN 16 4P/4P Message data 12 [7] MD12[7] 8 H'FEB16 HCAN 16 4P/4P Message data 12 [8] MD12[8] 8 H'FEB17 HCAN 16 4P/4P Message data 13 [1] MD13[1] 8 H'FEB18 HCAN 16 4P/4P Message data 13 [2] MD13[2] 8 H'FEB19 HCAN 16 4P/4P Message data 13 [3] MD13[3] 8 H'FEB1A HCAN 16 4P/4P Rev. 1.00, 03/04, page 649 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Message data 13 [4] MD13[4] 8 H'FEB1B HCAN 16 4P/4P Message data 13 [5] MD13[5] 8 H'FEB1C HCAN 16 4P/4P Message data 13 [6] MD13[6] 8 H'FEB1D HCAN 16 4P/4P Message data 13 [7] MD13[7] 8 H'FEB1E HCAN 16 4P/4P Message data 13 [8] MD13[8] 8 H'FEB1F HCAN 16 4P/4P Message data 14 [1] MD14[1] 8 H'FEB20 HCAN 16 4P/4P Message data 14 [2] MD14[2] 8 H'FEB21 HCAN 16 4P/4P Message data 14 [3] MD14[3] 8 H'FEB22 HCAN 16 4P/4P Message data 14 [4] MD14[4] 8 H'FEB23 HCAN 16 4P/4P Message data 14 [5] MD14[5] 8 H'FEB24 HCAN 16 4P/4P Message data 14 [6] MD14[6] 8 H'FEB25 HCAN 16 4P/4P Message data 14 [7] MD14[7] 8 H'FEB26 HCAN 16 4P/4P Message data 14 [8] MD14[8] 8 H'FEB27 HCAN 16 4P/4P Message data 15 [1] MD15[1] 8 H'FEB28 HCAN 16 4P/4P Message data 15 [2] MD15[2] 8 H'FEB29 HCAN 16 4P/4P Message data 15 [3] MD15[3] 8 H'FEB2A HCAN 16 4P/4P Message data 15 [4] MD15[4] 8 H'FEB2B HCAN 16 4P/4P Message data 15 [5] MD15[5] 8 H'FEB2C HCAN 16 4P/4P Message data 15 [6] MD15[6] 8 H'FEB2D HCAN 16 4P/4P Message data 15 [7] MD15[7] 8 H'FEB2E HCAN 16 4P/4P Message data 15 [8] MD15[8] 8 H'FEB2F HCAN 16 4P/4P HCAN monitor register HCANMON 8 H'FEB40 HCAN 16 4P/4P SS control register H_0 SSCRH_0 8 H'FF200 SSU_0 16 3P/3P SS control register L_0 SSCRL_0 8 H'FF201 SSU_0 16 3P/3P SS mode register_0 SSMR_0 8 H'FF202 SSU_0 16 3P/3P SS enable register_0 SSER_0 8 H'FF203 SSU_0 16 3P/3P SS status register_0 SSSR_0 8 H'FF204 SSU_0 16 3P/3P SS control register 2_0 SSCR2_0 8 H'FF205 SSU_0 16 3P/3P SS transmit data register 0_0 SSTDR0_0 8 H'FF206 SSU_0 16 3P/3P SS transmit data register 1_0 SSTDR1_0 8 H'FF207 SSU_0 16 3P/3P SS transmit data register 2_0 SSTDR2_0 8 H'FF208 SSU_0 16 3P/3P SS transmit data register 3_0 SSTDR3_0 8 H'FF209 SSU_0 16 3P/3P Rev. 1.00, 03/04, page 650 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address SS receive data register 0_0 SSRDR0_0 8 H'FF20A SSU_0 16 3P/3P SS receive data register 1_0 SSRDR1_0 8 H'FF20B SSU_0 16 3P/3P SS receive data register 2_0 SSRDR2_0 8 H'FF20C SSU_0 16 3P/3P SS receive data register 3_0 SSRDR3_0 8 H'FF20D SSU_0 16 3P/3P SS control register H_1 SSCRH_1 8 H'FF210 SSU_1 16 3P/3P SS control register L_1 SSCRL_1 8 H'FF211 SSU_1 16 3P/3P SS mode register_1 SSMR_1 8 H'FF212 SSU_1 16 3P/3P SS enable register_1 SSER_1 8 H'FF213 SSU_1 16 3P/3P SS status register_1 SSSR_1 8 H'FF214 SSU_1 16 3P/3P SS control register2_1 SSCR2_1 8 H'FF215 SSU_1 16 3P/3P SS transmit data register0_1 SSTDR0_1 8 H'FF216 SSU_1 16 3P/3P SS transmit data register1_1 SSTDR1_1 8 H'FF217 SSU_1 16 3P/3P SS transmit data register2_1 SSTDR2_1 8 H'FF218 SSU_1 16 3P/3P SS transmit data register3_1 SSTDR3_1 8 H'FF219 SSU_1 16 3P/3P SS receive data register0_1 SSRDR0_1 8 H'FF21A SSU_1 16 3P/3P SS receive data register1_1 SSRDR1_1 8 H'FF21B SSU_1 16 3P/3P SS receive data register2_1 SSRDR2_1 8 H'FF21C SSU_1 16 3P/3P SS receive data register3_1 SSRDR3_1 8 H'FF21D SSU_1 16 3P/3P SS control register H_2 SSCRH_2 8 H'FF220 SSU_2 16 3P/3P SS control register L_2 SSCRL_2 8 H'FF221 SSU_2 16 3P/3P SS mode register_2 SSMR_2 8 H'FF222 SSU_2 16 3P/3P SS enable register_2 SSER_2 8 H'FF223 SSU_2 16 3P/3P SS status register_2 SSSR_2 8 H'FF224 SSU_2 16 3P/3P SS control register2_2 SSCR2_2 8 H'FF225 SSU_2 16 3P/3P SS transmit data register0_2 SSTDR0_2 8 H'FF226 SSU_2 16 3P/3P SS transmit data register1_2 SSTDR1_2 8 H'FF227 SSU_2 16 3P/3P SS transmit data register2_2 SSTDR2_2 8 H'FF228 SSU_2 16 3P/3P SS transmit data register3_2 SSTDR3_2 8 H'FF229 SSU_2 16 3P/3P SS receive data register0_2 SSRDR0_2 8 H'FF22A SSU_2 16 3P/3P SS receive data register1_2 SSRDR1_2 8 H'FF22B SSU_2 16 3P/3P SS receive data register2_2 SSRDR2_2 8 H'FF22C SSU_2 16 3P/3P SS receive data register3_2 SSRDR3_2 8 H'FF22D SSU_2 16 3P/3P Rev. 1.00, 03/04, page 651 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Port H realtime input data register PHRTIDR 8 H'FF240 PORT 16 3P/3P A/D data register A_1 ADDRA_1 16 H'FFA90 A/D_1 16 2P/2P A/D data register B_1 ADDRB_1 16 H'FFA92 A/D_1 16 2P/2P A/D data register C_1 ADDRC_1 16 H'FFA94 A/D_1 16 2P/2P A/D data register D_1 ADDRD_1 16 H'FFA96 A/D_1 16 2P/2P A/D data register E_1 ADDRE_1 16 H'FFA98 A/D_1 16 2P/2P A/D data register F_1 ADDRF_1 16 H'FFA9A A/D_1 16 2P/2P A/D data register G_1 ADDRG_1 16 H'FFA9C A/D_1 16 2P/2P A/D data register H_1 ADDRH_1 16 H'FFA9E A/D_1 16 2P/2P A/D control/status register_1 ADCSR_1 8 H'FFAA0 A/D_1 16 2P/2P A/D control register_1 ADCR_1 8 H'FFAA1 A/D_1 16 2P/2P Timer start register TSTRB 8 H'FFB00 TPU 16 2P/2P Timer synchronous register TSYRB 8 H'FFB01 TPU 16 2P/2P Timer control register_6 TCR_6 8 H'FFB10 TPU_6 16 2P/2P Timer mode register_6 TMDR_6 8 H'FFB11 TPU_6 16 2P/2P Timer I/O control register H_6 TIORH_6 8 H'FFB12 TPU_6 16 2P/2P Timer I/O control register L_6 TIORL_6 8 H'FFB13 TPU_6 16 2P/2P Timer interrupt enable register_6 TIER_6 8 H'FFB14 TPU_6 16 2P/2P Timer status register_6 TSR_6 8 H'FFB15 TPU_6 16 2P/2P Timer counter _6 TCNT_6 16 H'FFB16 TPU_6 16 2P/2P Timer general register A_6 TGRA_6 16 H'FFB18 TPU_6 16 2P/2P Timer general register B_6 TGRB_6 16 H'FFB1A TPU_6 16 2P/2P Timer general register C_6 TGRC_6 16 H'FFB1C TPU_6 16 2P/2P Timer general register D_6 TGRD_6 16 H'FFB1E TPU_6 16 2P/2P Timer control register_7 TCR_7 8 H'FFB20 TPU_7 16 2P/2P Timer mode register_7 TMDR_7 8 H'FFB21 TPU_7 16 2P/2P Timer I/O control register_7 TIOR_7 8 H'FFB22 TPU_7 16 2P/2P Timer interrupt enable register_7 TIER_7 8 H'FFB24 TPU_7 16 2P/2P Timer status register_7 TSR_7 8 H'FFB25 TPU_7 16 2P/2P Rev. 1.00, 03/04, page 652 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Timer counter _7 TCNT_7 16 H'FFB26 TPU_7 16 2P/2P Timer general registerA_7 TGRA_7 16 H'FFB28 TPU_7 16 2P/2P Timer general registerB_7 TGRB_7 16 H'FFB2A TPU_7 16 2P/2P Timer control register_8 TCR_8 8 H'FFB30 TPU_8 16 2P/2P Timer mode register_8 TMDR_8 8 H'FFB31 TPU_8 16 2P/2P Timer I/O control register_8 TIOR_8 8 H'FFB32 TPU_8 16 2P/2P Timer interrupt enable register_8 TIER_8 8 H'FFB34 TPU_8 16 2P/2P Timer status register_8 TSR_8 8 H'FFB35 TPU_8 16 2P/2P Timer counter _8 TCNT_8 16 H'FFB36 TPU_8 16 2P/2P Timer general registerA_8 TGRA_8 16 H'FFB38 TPU_8 16 2P/2P Timer general registerB_8 TGRB_8 16 H'FFB3A TPU_8 16 2P/2P Timer control register_9 TCR_9 8 H'FFB40 TPU_9 16 2P/2P Timer mode register_9 TMDR_9 8 H'FFB41 TPU_9 16 2P/2P Timer I/O control register H_9 TIORH_9 8 H'FFB42 TPU_9 16 2P/2P Timer I/O control register L_9 TIORL_9 8 H'FFB43 TPU_9 16 2P/2P Timer interrupt enable register_9 TIER_9 8 H'FFB44 TPU_9 16 2P/2P Timer status register_9 TSR_9 8 H'FFB45 TPU_9 16 2P/2P Timer counter _9 TCNT_9 16 H'FFB46 TPU_9 16 2P/2P Timer general registerA_9 TGRA_9 16 H'FFB48 TPU_9 16 2P/2P Timer general registerB_9 TGRB_9 16 H'FFB4A TPU_9 16 2P/2P Timer general registerC_9 TGRC_9 16 H'FFB4C TPU_9 16 2P/2P Timer general registerD_9 TGRD_9 16 H'FFB4E TPU_9 16 2P/2P Timer control register_10 TCR_10 8 H'FFB50 TPU_10 16 2P/2P Timer mode register_10 TMDR_10 8 H'FFB51 TPU_10 16 2P/2P Timer I/O control register_10 TIOR_10 8 H'FFB52 TPU_10 16 2P/2P Timer interrupt enable register_10 TIER_10 8 H'FFB54 TPU_10 16 2P/2P Timer status register_10 TSR_10 8 H'FFB55 TPU_10 16 2P/2P Timer counter _10 TCNT_10 16 H'FFB56 TPU_10 16 2P/2P Timer general registerA_10 TGRA_10 16 H'FFB58 TPU_10 16 2P/2P Timer general registerB_10 TGRB_10 16 H'FFB5A TPU_10 16 2P/2P Rev. 1.00, 03/04, page 653 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Timer control register_11 TCR_11 8 H'FFB60 TPU_11 16 2P/2P Timer mode register_11 TMDR_11 8 H'FFB61 TPU_11 16 2P/2P Timer I/O control register_11 TIOR_11 8 H'FFB62 TPU_11 16 2P/2P Timer interrupt enable register_11 TIER_11 8 H'FFB64 TPU_11 16 2P/2P Timer status register_11 TSR_11 8 H'FFB65 TPU_11 16 2P/2P Timer counter _11 TCNT_11 16 H'FFB66 TPU_11 16 2P/2P Timer general registerA_11 TGRA_11 16 H'FFB68 TPU_11 16 2P/2P Timer general registerB_11 TGRB_11 16 H'FFB6A TPU_11 16 2P/2P Port 1 data direction register P1DDR 8 H'FFB80 I/O port 8 2P/2P Port 2 data direction register P2DDR 8 H'FFB81 I/O port 8 2P/2P Port 3 data direction register P3DDR 8 H'FFB82 I/O port 8 2P/2P Port 6 data direction register P6DDR 8 H'FFB85 I/O port 8 2P/2P Port A data direction register PADDR 8 H'FFB89 I/O port 8 2P/2P Port D data direction register PDDDR 8 H'FFB8C I/O port 8 2P/2P Port 1 input buffer control register P1ICR 8 H'FFB90 I/O port 8 2P/2P Port 2 input buffer control register P2ICR 8 H'FFB91 I/O port 8 2P/2P Port 3 input buffer control register P3ICR 8 H'FFB92 I/O port 8 2P/2P Port 4 input buffer control register P4ICR 8 H'FFB93 I/O port 8 2P/2P Port 5 input buffer control register P5ICR 8 H'FFB94 I/O port 8 2P/2P Port 6 input buffer control register P6ICR 8 H'FFB95 I/O port 8 2P/2P Port A input buffer control register PAICR 8 H'FFB99 I/O port 8 2P/2P Port D input buffer control register PDICR 8 H'FFB9C I/O port 8 2P/2P Port g register PORTH 8 H'FFBA0 I/O port 8 2P/2P Port J register PORTJ 8 H'FFBA2 I/O port 8 2P/2P Port K register PORTK 8 H'FFBA3 I/O port 8 2P/2P Port g data register PHDR 8 H'FFBA4 I/O port 8 2P/2P Rev. 1.00, 03/04, page 654 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Port J data register PJDR 8 H'FFBA6 I/O port 8 2P/2P Port K data register PKDR 8 H'FFBA7 I/O port 8 2P/2P Port H data direction register PHDDR 8 H'FFBA8 I/O port 8 2P/2P Port J data direction register PJDDR 8 H'FFBAA I/O port 8 2P/2P Port K data direction register PKDDR 8 H'FFBAB I/O port 8 2P/2P Port H input buffer control register PHICR 8 H'FFBAC I/O port 8 2P/2P Port J input buffer control register PJICR 8 H'FFBAE I/O port 8 2P/2P Port K input buffer control register PKICR 8 H'FFBAF I/O port 8 2P/2P Port D pull-up MOS control register PDPCR 8 H'FFBB4 I/O port 8 2P/2P Port H pull-up MOS control register PHPCR 8 H'FFBB8 I/O port 8 2P/2P Port J pull-up MOS control register PJPCR 8 H'FFBBA I/O port 8 2P/2P Port K pull-up MOS control register PKPCR 8 H'FFBBB I/O port 8 2P/2P Port 2 open drain control register P2ODR 8 H'FFBBC I/O port 8 2P/2P Port function control register 9 PFCR9 8 H'FFBC9 I/O port 8 2P/3P Port function control register A PFCRA 8 H'FFBCA I/O port 8 2P/3P Port function control register B PFCRB 8 H'FFBCB I/O port 8 2P/3P Software standby release IRQ SSIER enable register 16 H'FFBCE INTC 8 2P/3P DMA source address register_0 DSAR_0 32 H'FFC00 DMAC_0 16 2I/2I DMA destination address register_0 DDAR_0 32 H'FFC04 DMAC_0 16 2I/2I DMA offset register_0 DOFR_0 32 H'FFC08 DMAC_0 16 2I/2I DMA transfer count register_0 DTCR_0 32 H'FFC0C DMAC_0 16 2I/2I DMA block size register_0 DBSR_0 32 H'FFC10 DMAC_0 16 2I/2I DMA mode control register_0 DMDR_0 32 H'FFC14 DMAC_0 16 2I/2I DMA address control register_0 DACR_0 32 H'FFC18 DMAC_0 16 2I/2I Rev. 1.00, 03/04, page 655 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address DMA source address register_1 DSAR_1 32 H'FFC20 DMAC_1 16 2I/2I DMA destination address register_1 DDAR_1 32 H'FFC24 DMAC_1 16 2I/2I DMA offset register_1 DOFR_1 32 H'FFC28 DMAC_1 16 2I/2I DMA transfer count register_1 DTCR_1 32 H'FFC2C DMAC_1 16 2I/2I DMA block size register_1 DBSR_1 32 H'FFC30 DMAC_1 16 2I/2I DMA mode control register_1 DMDR_1 32 H'FFC34 DMAC_1 16 2I/2I DMA address control register_1 DACR_1 32 H'FFC38 DMAC_1 16 2I/2I DMA source address register_2 DSAR_2 32 H'FFC40 DMAC_2 16 2I/2I DMA destination address register_2 DDAR_2 32 H'FFC44 DMAC_2 16 2I/2I DMA offset register_2 DOFR_2 32 H'FFC48 DMAC_2 16 2I/2I DMA transfer count register_2 DTCR_2 32 H'FFC4C DMAC_2 16 2I/2I DMA block size register_2 DBSR_2 32 H'FFC50 DMAC_2 16 2I/2I DMA mode control register_2 DMDR_2 32 H'FFC54 DMAC_2 16 2I/2I DMA address control register_2 DACR_2 32 H'FFC58 DMAC_2 16 2I/2I DMA source address register_3 DSAR_3 32 H'FFC60 DMAC_3 16 2I/2I DMA destination address register_3 DDAR_3 32 H'FFC64 DMAC_3 16 2I/2I DMA offset register_3 DOFR_3 32 H'FFC68 DMAC_3 16 2I/2I DMA transfer count register_3 DTCR_3 32 H'FFC6C DMAC_3 16 2I/2I DMA block size register_3 DBSR_3 32 H'FFC70 DMAC_3 16 2I/2I DMA mode control register_3 DMDR_3 32 H'FFC74 DMAC_3 16 2I/2I DMA address control register_3 DACR_3 32 H'FFC78 DMAC_3 16 2I/2I DMA module request select register_0 DMRSR_0 8 H'FFD20 DMAC_0 16 2I/2I DMA module request select register_1 DMRSR_1 8 H'FFD21 DMAC_1 16 2I/2I DMA module request select register_2 DMRSR_2 8 H'FFD22 DMAC_2 16 2I/2I Rev. 1.00, 03/04, page 656 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address DMA module request select register_3 DMRSR_3 8 H'FFD23 DMAC_3 16 2I/2I Interrupt priority register A IPRA 16 H'FFD40 INTC 16 2I/3I Interrupt priority register B IPRB 16 H'FFD42 INTC 16 2I/3I Interrupt priority register C IPRC 16 H'FFD44 INTC 16 2I/3I Interrupt priority register D IPRD 16 H'FFD46 INTC 16 2I/3I Interrupt priority register E IPRE 16 H'FFD48 INTC 16 2I/3I Interrupt priority register F IPRF 16 H'FFD4A INTC 16 2I/3I Interrupt priority register G IPRG 16 H'FFD4C INTC 16 2I/3I Interrupt priority register I IPRI 16 H'FFD50 INTC 16 2I/3I Interrupt priority register K IPRK 16 H'FFD54 INTC 16 2I/3I Interrupt priority register L IPRL 16 H'FFD56 INTC 16 2I/3I Interrupt priority register M IPRM 16 H'FFD58 INTC 16 2I/3I Interrupt priority register N IPRN 16 H'FFD5A INTC 16 2I/3I Interrupt priority register O IPRO 16 H'FFD5C INTC 16 2I/3I Interrupt priority register Q IPRQ 16 H'FFD60 INTC 16 2I/3I Interrupt priority register R IPRR 16 H'FFD62 INTC 16 2I/3I IRQ sense control register H ISCRH 16 H'FFD68 INTC 16 2I/3I IRQ sense control register L ISCRL 16 H'FFD6A INTC 16 2I/3I Bus control register 2 BCR2 8 H'FFD94 BSC 16 2I/3I RAM emulation register RAMER 8 H'FFD9E BSC 16 2I/3I Mode control register MDCR 16 H'FFDC0 SYSTEM 16 2I/3I System control register SYSCR 16 H'FFDC2 SYSTEM 16 2I/3I System clock control register SCKCR 16 H'FFDC4 SYSTEM 16 2I/3I Standby control register SBYCR 8 H'FFDC6 SYSTEM 16 2I/3I Module stop control register A MSTPCRA 16 H'FFDC8 SYSTEM 16 2I/3I Module stop control register B MSTPCRB 16 H'FFDCA SYSTEM 16 2I/3I Module stop control register C MSTPCRC 16 H'FFDCC SYSTEM 16 2I/3I Serial mode register_3 SMR_3 8 H'FFE88 SCI_3 8 2P/2P Bit rate register_3 BRR_3 8 H'FFE89 SCI_3 8 2P/2P Serial control register_3 SCR_3 8 H'FFE8A SCI_3 8 2P/2P Transmit data register_3 TDR_3 8 H'FFE8B SCI_3 8 2P/2P Serial status register_3 SSR_3 8 H'FFE8C SCI_3 8 2P/2P Rev. 1.00, 03/04, page 657 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address Receive data register_3 RDR_3 8 H'FFE8D SCI_3 8 2P/2P Smart card mode register_3 SCMR_3 8 H'FFE8E SCI_3 8 2P/2P Serial mode register_4 SMR_4 8 H'FFE90 SCI_4 8 2P/2P Bit rate register_4 BRR_4 8 H'FFE91 SCI_4 8 2P/2P Serial control register_4 SCR_4 8 H'FFE92 SCI_4 8 2P/2P Transmit data register_4 TDR_4 8 H'FFE93 SCI_4 8 2P/2P Serial status register_4 SSR_4 8 H'FFE94 SCI_4 8 2P/2P Receive data register_4 RDR_4 8 H'FFE95 SCI_4 8 2P/2P Smart card mode register_4 SCMR_4 8 H'FFE96 SCI_4 8 2P/2P Flash code control/status register FCCS 8 H'FFEA8 FLASH 8 2P/2P Flash program code select register FPCS 8 H'FFEA9 FLASH 8 2P/2P Flash erase code select register FECS 8 H'FFEAA FLASH 8 2P/2P Flash key code register FKEY 8 H'FFEAC FLASH 8 2P/2P Flash MAT select register FMATS 8 H'FFEAD FLASH 8 2P/2P Flash transfer destination address register FTDAR 8 H'FFEAE FLASH 8 2P/2P Timer control register_4 TCR_4 8 H'FFEE0 TPU_4* 2 16 2P/2P Timer mode register_4 TMDR_4 8 H'FFEE1 TPU_4* 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P Timer I/O control register_4 TIOR_4 8 H'FFEE2 TPU_4* Timer interrupt enable register_4 TIER_4 8 H'FFEE4 TPU_4* Timer status register_4 TSR_4 8 H'FFEE5 TPU_4* Timer counter_4 TCNT_4 16 H'FFEE6 TPU_4* Timer general registerA_4 TGRA_4 16 H'FFEE8 TPU_4* Timer general registerB_4 TGRB_4 16 H'FFEEA TPU_4* Timer control register_5 Timer mode register_5 Timer I/O control register_5 TCR_5 TMDR_5 TIOR_5 8 8 8 H'FFEF0 H'FFEF1 H'FFEF2 TPU_5* TPU_5* TPU_5* Timer interrupt enable register_5 TIER_5 8 H'FFEF4 TPU_5* Timer status register_5 TSR_5 8 H'FFEF5 TPU_5* Rev. 1.00, 03/04, page 658 of 730 Register Name Abbr. Number of Bits Address Timer counter_5 TCNT_5 16 Timer general registerA_5 TGRA_5 16 H'FFEF6 H'FFEF8 Data Width Access Cycles (Read/Write) 2 16 2P/2P 2 16 2P/2P 2 Module TPU_5* TPU_5* Timer general registerB_5 TGRB_5 16 H'FFEFA TPU_5* 16 2P/2P Interrupt control register INTCR 8 H'FFF32 INTC 16 2I/3I CPU priority control register CPUPCR 8 H'FFF33 INTC 16 2I/3I IRQ enable register IER 16 H'FFF34 INTC 16 2I/3I IRQ status register ISR 16 H'FFF36 INTC 16 2I/3I Port 1 register PORT1 8 H'FFF40 I/O port 8 2P/- Port 2 register PORT2 8 H'FFF41 I/O port 8 2P/- Port 3 register PORT3 8 H'FFF42 I/O port 8 2P/- Port 4 register PORT4 8 H'FFF43 I/O port 8 2P/- Port 5 register PORT5 8 H'FFF44 I/O port 8 2P/- Port 6 register PORT6 8 H'FFF45 I/O port 8 2P/- Port A register PORTA 8 H'FFF49 I/O port 8 2P/- Port D register PORTD 8 H'FFF4C I/O port 8 2P/- Port 1 data register P1DR 8 H'FFF50 I/O port 8 2P/2P Port 2 data register P2DR 8 H'FFF51 I/O port 8 2P/2P Port 3 data register P3DR 8 H'FFF52 I/O port 8 2P/2P Port 6 data register P6DR 8 H'FFF55 I/O port 8 2P/2P Port A data register PADR 8 H'FFF59 I/O port 8 2P/2P Port D data register PDDR 8 H'FFF5C I/O port PPG output control register PPG output mode register PCR PMR 8 8 H'FFF76 H'FFF77 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P 2 8 2P/2P PPG* PPG* Next data enable register H NDERH 8 H'FFF78 PPG* Next data enable register L NDERL 8 H'FFF79 PPG* Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L PODRH PODRL NDRH NDRL NDRH NDRL 8 8 8 8 8 8 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F PPG* PPG* PPG* PPG* PPG* PPG* Rev. 1.00, 03/04, page 659 of 730 Module Data Width Access Cycles (Read/Write) Register Name Abbr. Number of Bits Address A/D data registerA_0 ADDRA_0 16 H'FFF90 A/D _0 16 2P/2P A/D data registerB_0 ADDRB_0 16 H'FFF92 A/D _0 16 2P/2P A/D data registerC_0 ADDRC_0 16 H'FFF94 A/D _0 16 2P/2P A/D data registerD_0 ADDRD_0 16 H'FFF96 A/D _0 16 2P/2P A/D data registerE_0 ADDRE_0 16 H'FFF98 A/D _0 16 2P/2P A/D data registerF_0 ADDRF_0 16 H'FFF9A A/D _0 16 2P/2P A/D data registerG_0 ADDRG_0 16 H'FFF9C A/D _0 16 2P/2P A/D data register H_0 ADDRH_0 16 H'FFF9E A/D _0 16 2P/2P A/D control/status register_0 ADCSR_0 8 H'FFFA0 A/D _0 16 2P/2P A/D control register_0 ADCR_0 8 H'FFFA1 A/D _0 16 2P/2P Timer control/status register TCSR 8 H'FFFA4 WDT 2P/3P Timer counter TCNT 8 H'FFFA5 WDT 2P/3P Reset control/status register RSTCSR 8 H'FFFA7 WDT Timer start register Timer synchronous register TSTR TSYR 8 8 H'FFFBC H'FFFBD 2P/3P 2 TPU* 2 TPU* 16 2P/2P 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P TCR_0 8 H'FFFC0 TPU_0* Timer mode register_0 TMDR_0 8 H'FFFC1 TPU_0* Timer I/O control register L_0 TIORL_0 8 8 H'FFFC2 H'FFFC3 TPU_0* TPU_0* Timer interrupt enable register_0 TIER_0 8 H'FFFC4 TPU_0* Timer status register_0 TSR_0 8 H'FFFC5 TPU_0* Timer counter_0 TCNT_0 16 H'FFFC6 TPU_0* Timer general register A_0 TGRA_0 16 H'FFFC8 TPU_0* Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/control register_1 Timer interrupt enable register_1 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 Rev. 1.00, 03/04, page 660 of 730 16 16 16 8 8 8 8 H'FFFCA H'FFFCC H'FFFCE H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD4 2P/2P 2 Timer control register_0 Timer I/O control register H_0 TIORH_0 16 TPU_0* TPU_0* TPU_0* TPU_1* TPU_1* TPU_1* TPU_1* Register Name Abbr. Number of Bits Address Timer status register_1 TSR_1 8 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 16 16 16 8 8 8 H'FFFD5 H'FFFD6 H'FFFD8 H'FFFDA H'FFFE0 H'FFFE1 H'FFFE2 Data Width Access Cycles (Read/Write) 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P 2 16 2P/2P Module TPU_1* TPU_1* TPU_1* TPU_1* TPU_2* TPU_2* TPU_2* Timer interrupt enable register_2 TIER_2 8 H'FFFE4 TPU_2* Timer status register_2 TSR_2 8 H'FFFE5 TPU_2* Timer counter_2 Timer general registerA_2 Timer general registerB_2 Timer control register_3 Timer mode register_3 TCNT_2 TGRA_2 TGRB_2 TCR_3 16 16 16 8 H'FFFE6 H'FFFE8 H'FFFEA H'FFFF0 TPU_2* TPU_2* TPU_2* TPU_3* TMDR_3 8 H'FFFF1 TPU_3* Timer I/O control register H_3 TIORH_3 8 H'FFFF2 TPU_3* Timer I/O control register L_3 TIORL_3 8 H'FFFF3 TPU_3* Timer interrupt enable register_3 TIER_3 8 H'FFFF4 TPU_3* Timer status register_3 TSR_3 8 H'FFFF5 TPU_3* Timer counter_3 TCNT_3 16 H'FFFF6 TPU_3* Timer general register A_3 TGRA_3 16 H'FFFF8 TPU_3* Timer general register B_3 TGRB_3 16 H'FFFFA TPU_3* Timer general register C_3 Timer general register D_3 TGRC_3 TGRD_3 16 16 H'FFFFC H'FFFFE TPU_3* TPU_3* Notes: 1. The lower 20 bits are indicated. 2. Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 661 of 730 20.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MCR MCR7 MCR5 MCR2 GSR GSR3 BCR BCR7 BCR6 BCR5 BCR4 BCR3 MBCR TXPR TXCR TXACK ABACK RXPR RFPR IRR MBIMR IMR Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module MCR1 MCR0 HCAN GSR2 GSR1 GSR0 BCR2 BCR1 BCR0 BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 IRR12 IRR9 IRR8 MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR12 IMR9 IMR8 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 REC TEC UMSR Rev. 1.00, 03/04, page 662 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module LAFML LAFML7 LAFML0 HCAN LAFML6 Bit LAFML5 Bit LAFML4 Bit LAFML3 Bit Bit LAFML2 LAFML1 Bit LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8 LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 MC0[1] DLC3 DLC2 DLC1 DLC0 MC0[2] MC0[3] MC0[4] MC0[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC0[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC0[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC0[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC1[1] DLC3 DLC2 DLC1 DLC0 MC1[2] MC1[3] MC1[4] MC1[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC1[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC1[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC1[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC2[1] DLC3 DLC2 DLC1 DLC0 MC2[2] MC2[3] MC2[4] MC2[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC2[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC2[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC2[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC3[1] DLC3 DLC2 DLC1 DLC0 MC3[2] MC3[3] MC3[4] MC3[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 LAFMH Rev. 1.00, 03/04, page 663 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module MC3[6] ID-28 HCAN ID-27 Bit ID-26 Bit Bit Bit Bit Bit ID-25 ID-24 ID-23 ID-22 ID-21 MC3[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC3[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC4[1] DLC3 DLC2 DLC1 DLC0 MC4[2] MC4[3] MC4[4] MC4[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC4[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC4[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC4[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC5[1] DLC3 DLC2 DLC1 DLC0 MC5[2] MC5[3] MC5[4] MC5[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC5[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC5[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC5[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC6[1] DLC3 DLC2 DLC1 DLC0 MC6[2] MC6[3] MC6[4] MC6[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC6[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC6[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC7[1] DLC3 DLC2 DLC1 DLC0 MC7[2] MC7[3] MC7[4] MC7[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC7[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 Rev. 1.00, 03/04, page 664 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module MC7[7] ID-7 ID-0 HCAN ID-6 Bit ID-5 Bit ID-4 Bit ID-3 Bit Bit ID-2 ID-1 Bit MC7[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC8[1] DLC3 DLC2 DLC1 DLC0 MC8[2] MC8[3] MC8[4] MC8[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC8[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC8[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC8[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC9[1] DLC3 DLC2 DLC1 DLC0 MC9[2] MC9[3] MC9[4] MC9[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC9[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC9[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC9[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC10[1] DLC3 DLC2 DLC1 DLC0 MC10[2] MC10[3] MC10[4] MC10[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC10[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC10[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC10[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC11[1] DLC3 DLC2 DLC1 DLC0 MC11[2] MC11[3] MC11[4] MC11[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC11[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC11[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 Rev. 1.00, 03/04, page 665 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit 24/16/8/0 Module MC11[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-8 HCAN MC12[1] DLC3 DLC2 DLC1 DLC0 MC12[2] MC12[3] MC12[4] MC12[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC12[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC12[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC12[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC13[1] DLC3 DLC2 DLC1 DLC0 MC13[2] MC13[3] MC13[4] MC13[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC13[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC13[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC14[1] DLC3 DLC2 DLC1 DLC0 MC14[2] MC14[3] MC14[4] MC14[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC14[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC14[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC14[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 MC15[1] DLC3 DLC2 DLC1 DLC0 MC15[2] MC15[3] MC15[4] MC15[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16 MC15[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21 MC15[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0 MC15[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 Rev. 1.00, 03/04, page 666 of 730 Bit Bit Bit ID-10 Bit ID-9 Bit Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MD0[1] Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module HCAN MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] MD2[2] MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] Rev. 1.00, 03/04, page 667 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] MD6[3] MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] Rev. 1.00, 03/04, page 668 of 730 Bit Bit Bit Bit Bit 24/16/8/0 Module HCAN Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MD8[3] Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module HCAN MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] MD10[4] MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] Rev. 1.00, 03/04, page 669 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 MD12[4] Module HCAN MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] MD14[5] MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON TxSTP HCANE TxD RxD SSCRH_0 MSS BIDE SOL SOLP SCKS CSS1 CSS0 SSCRL_0 SSUMS SRES DATS1 DATS0 SSMR_0 MLS CPOS CPHS CKS2 CKS1 CKS0 Rev. 1.00, 03/04, page 670 of 730 SSU_0 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit SSER_0 TE RE SSSR_0 ORER SSCR2_0 SDOS SSCKOS SSCRH_1 MSS SSCRL_1 Bit 24/16/8/0 Module CEIE SSU_0 TEIE TIE RIE TEND TDRE RDRF CE SCSOS TENDSTS SCSATS SSODTS BIDE SOL SOLP SCKS CSS1 CSS0 SSUMS SRES DATS1 DATS0 SSMR_1 MLS CPOS CPHS CKS2 CKS1 CKS0 SSER_1 TE RE TEIE TIE RIE CEIE SSSR_1 ORER TEND TDRE RDRF CE SSCR2_1 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS SSTDR0_0 SSTDR1_0 SSTDR2_0 SSTDR3_0 SSRDR0_0 SSRDR1_0 SSRDR2_0 SSRDR3_0 SSU_1 SSTDR0_1 SSTDR1_1 SSTDR2_1 SSTDR3_1 SSRDR0_1 SSRDR1_1 SSRDR2_1 SSRDR3_1 SSCRH_2 MSS BIDE SOL SOLP SCKS CSS1 CSS0 SSCRL_2 SSUMS SRES DATS1 DATS0 SSMR_2 MLS CPOS CPHS CKS2 CKS1 CKS0 SSER_2 TE RE TEIE TIE RIE CEIE SSSR_2 ORER TEND TDRE RDRF CE SSCR2_2 SDOS SSCKOS SCSOS TENDSTS SCSATS SSODTS SSU_2 SSTDR0_2 SSTDR1_2 Rev. 1.00, 03/04, page 671 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 SSTDR2_2 Module SSU_2 SSTDR3_2 SSRDR0_2 SSRDR1_2 SSRDR2_2 SSRDR3_2 PHRTIDR PHRTIDR7 PHRTIDR6 PHRTIDR5 PHRTIDR4 PHRTIDR3 PHRTIDR2 PHRTIDR1 PHRTIDR0 I/O port ADDRA_1 A/D_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADF ADIE ADST CH3 CH2 CH1 CH0 ADCR_1 TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 TSTRB CST5 CST4 CST3 CST2 CST1 CST0 TSYRB SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_6 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_6 BFB BFA MD3 MD2 MD1 MD0 TIORH_6 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_6 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_6 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA TSR_6 TCFV TGFD TGFC TGFB TGFA Rev. 1.00, 03/04, page 672 of 730 TPU TPU_6 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 TCNT_6 Module TPU_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_7 MD2 MD1 MD0 TIOR_7 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_7 TCIEU TCIEV TGIEB TGIEA TSR_7 TCFD TCFU TCFV TGFB TGFA TCR_8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_8 MD2 MD1 MD0 TIOR_8 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_8 TCIEU TCIEV TGIEB TGIEA TSR_8 TCFD TCFU TCFV TGFB TGFA TPU_7 TCNT_7 TGRA_7 TGRB_7 TPU_8 TCNT_8 TGRA_8 TGRB_8 Rev. 1.00, 03/04, page 673 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit 24/16/8/0 Module TCR_9 CCLR2 CCLR1 CCLR0 TPSC0 TPU_9 TMDR_9 BFB BFA MD2 MD1 MD0 TIORH_9 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_9 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_9 TCIEV TGIED TGIEC TGIEB TGIEA TSR_9 TCFV TGFD TGFC TGFB TGFA TCR_10 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_10 MD2 MD1 MD0 TIOR_10 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_10 TCIEU TCIEV TGIEB TGIEA TSR_10 TCFD TCFU TCFV TGFB TGFA TCR_11 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_11 MD2 MD1 MD0 TIOR_11 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_11 TCIEU TCIEV TGIEB TGIEA TSR_11 TCFD TCFU TCFV TGFB TGFA CKEG1 Bit CKEG0 Bit TPSC2 Bit TPSC1 Bit TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TPU_10 TCNT_10 TGRA_10 TGRB_10 TCNT_11 Rev. 1.00, 03/04, page 674 of 730 TPU_11 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 TGRA_11 Module TPU_11 TGRB_11 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P2DDR P23DDR P22DDR P21DDR P20DDR P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P6DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PDDDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR P1ICR P17ICR P16ICR P15ICR P14ICR P13ICR P12ICR P11ICR P10ICR P2ICR P23ICR P22ICR P21ICR P20ICR P3ICR P37ICR P36ICR P35ICR P34ICR P33ICR P32ICR P31ICR P30ICR P4ICR P47ICR P46ICR P45ICR P44ICR P43ICR P42ICR P41ICR P40ICR P5ICR P57ICR P56ICR P55ICR P54ICR P53ICR P52ICR P51ICR P50ICR P6ICR P66ICR P65ICR P64ICR P63ICR P62ICR P61ICR P60ICR PAICR PA7ICR PA6ICR PA5ICR PA4ICR PA3ICR PA2ICR PA1ICR PDICR PD7ICR PD6ICR PD5ICR PD4ICR PD3ICR PD2ICR PD1ICR PD0ICR PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PORTK PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR PKDR PK7DR PK6DR PK5DR PK4DR PK3DR PK2DR PK1DR PK0DR PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR PKDDR PK7DDR PK6DDR PK5DDR PK4DDR PK3DDR PK2DDR PK1DDR PK0DDR PHICR PH7ICR PH6ICR PH5ICR PH4ICR PH3ICR PH2ICR PH1ICR PH0ICR PJICR PJ7ICR PJ6ICR PJ5ICR PJ4ICR PJ3ICR PJ2ICR PJ1ICR PJ0ICR PKICR PK7ICR PK6ICR PK5ICR PK4ICR PK3ICR PK2ICR PK1ICR PK0ICR PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PHPCR PH7PCR PH6PCR PH5PCR PH4PCR PH3PCR PH2PCR PH1PCR PH0PCR PJPCR PJ7PCR PJ6PCR PJ5PCR PJ4PCR PJ3PCR PJ2PCR PJ1PCR PJ0PCR I/O port Rev. 1.00, 03/04, page 675 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module PKPCR PK7PCR PK6PCR PK5PCR PK4PCR PK3PCR PK2PCR PK1PCR PK0PCR I/O port P2ODR P23ODR P22ODR P21ODR P20ODR PFCR9 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B PFCRA TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B PFCRB ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 SSIER SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 DSAR_0 DMAC_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 DMDR_0 INTC BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DTE DACKE TENDE DREQS NRD ACT ERRF ESIF DTIF DTSZ1 DTSZ0 MDS1 MDS0 TSEIE ESIE DTIE DTF1 DTF0 DTA DMAP2 DMAP1 DMAP0 Rev. 1.00, 03/04, page 676 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit DACR_0 AMS DIRS SAT1 SAT0 DAT1 DAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Bit Bit Bit RPTIE ARS1 Bit 24/16/8/0 Module ARS0 DMAC_0 DSAR_1 DMAC_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 DMDR_1 DACR_1 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DTE DACKE TENDE DREQS NRD ACT ESIF DTIF DTSZ1 DTSZ0 MDS1 MDS0 TSEIE ESIE DTIE DTF1 DTF0 DTA DMAP2 DMAP1 DMAP0 AMS DIRS RPTIE ARS1 ARS0 SAT1 SAT0 DAT1 DAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Rev. 1.00, 03/04, page 677 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 DSAR_2 Module DMAC_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 DMDR_2 DACR_2 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DTE DACKE TENDE DREQS NRD ACT ESIF DTIF DTSZ1 DTSZ0 MDS1 MDS0 TSEIE ESIE DTIE DTF1 DTF0 DTA DMAP2 DMAP1 DMAP0 AMS DIRS RPTIE ARS1 ARS0 SAT1 SAT0 DAT1 DAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 DSAR_3 Rev. 1.00, 03/04, page 678 of 730 DMAC_3 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 DDAR_3 Module DMAC_3 DOFR_3 DTCR_3 DBSR_3 BKSZH31 BKSZH30 BKSZH29 BKSZH28 BKSZH27 BKSZH26 BKSZH25 BKSZH24 BKSZH23 BKSZH22 BKSZH21 BKSZH20 BKSZH19 BKSZH18 BKSZH17 BKSZH16 DMDR_3 DACR_3 BKSZ15 BKSZ14 BKSZ13 BKSZ12 BKSZ11 BKSZ10 BKSZ9 BKSZ8 BKSZ7 BKSZ6 BKSZ5 BKSZ4 BKSZ3 BKSZ2 BKSZ1 BKSZ0 DTE DACKE TENDE DREQS NRD ACT ESIF DTIF DTSZ1 DTSZ0 MDS1 MDS0 TSEIE ESIE DTIE DTF1 DTF0 DTA DMAP2 DMAP1 DMAP0 AMS DIRS RPTIE ARS1 ARS0 SAT1 SAT0 DAT1 DAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 DMRSR_0 DMAC_0 DMRSR_1 DMAC_1 DMRSR_2 DMAC_2 DMRSR_3 DMAC_3 IPRA IPRB IPRA14 IPRA13 IPRA12 IPRA10 IPRA9 IPRA8 IPRA6 IPRA5 IPRA4 IPRA2 IPRA1 IPRA0 IPRB14 IPRB13 IPRB12 IPRB10 IPRB9 IPRB8 IPRB6 IPRB5 IPRB4 IPRB2 IPRB1 IPRB0 INTC Rev. 1.00, 03/04, page 679 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module IPRC IPRC14 IPRC8 INTC IPRC6 IPRD14 IPRD6 IPRC12 IPRC10 IPRC5 IPRC4 IPRC2 IPRC1 IPRC0 IPRD13 IPRD12 IPRD10 IPRD9 IPRD8 IPRD5 IPRD4 IPRE10 IPRE9 IPRE8 IPRF10 IPRF9 IPRF8 IPRF6 IPRF5 IPRF4 IPRF2 IPRF1 IPRF0 IPRG14 IPRG13 IPRG12 IPRG10 IPRG9 IPRG8 IPRG6 IPRG5 IPRG4 IPRG2 IPRG1 IPRG0 IPRI14 IPRI13 IPRI12 IPRI10 IPRI9 IPRI8 IPRI6 IPRI5 IPRI4 IPRI2 IPRI1 IPRI0 IPRK14 IPRK13 IPRK12 IPRL10 IPRL9 IPRL8 IPRL6 IPRL5 IPRL4 IPRL2 IPRL1 IPRL0 IPRM14 IPRM13 IPRM12 IPRM10 IPRM9 IPRM8 IPRM6 IPRM5 IPRM4 IPRM2 IPRM1 IPRM0 IPRN14 IPRN13 IPRN12 IPRN10 IPRN9 IPRN8 IPRN6 IPRN5 IPRN4 IPRN2 IPRN1 IPRN0 IPRO14 IPRO13 IPRO12 IPRO10 IPRO9 IPRO8 IPRO6 IPRO5 IPRO4 IPRQ2 IPRQ1 IPRQ0 IPRR14 IPRR13 IPRR12 IPRR10 IPRR9 IPRR8 IPRR6 IPRR5 IPRR4 IPRR2 IPRR1 IPRR0 IRQ14SR IRQ14SF IRQ13SR IRQ13SF IRQ12SR IRQ12SF IRQ11SR IRQ11SF IRQ10SR IRQ10SF IRQ9SR IRQ9SF IRQ8SR IRQ8SF IRQ7SR IRQ7SF IRQ6SR IRQ6SF IRQ5SR IRQ5SF IRQ4SR IRQ4SF IRQ3SR IRQ3SF IRQ2SR IRQ2SF IRQ1SR IRQ1SF IRQ0SR IRQ0SF BCR2 IBCCS PWDBE RAMER RAMS RAM2 RAM1 RAM0 IPRD IPRE IPRF IPRG IPRI IPRK IPRL IPRM IPRN IPRO IPRQ IPRR ISCRH ISCRL IPRC13 Rev. 1.00, 03/04, page 680 of 730 IPRC9 INTC BSC Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module MDCR SYSTEM MDS3 MDS2 MDS1 MDS0 MACS FETCHMD RAME FLSHE PSTOP1 POSEL1 ICK2 ICK1 ICK0 PCK2 PCK1 PCK0 BCK2 BCK1 BCK0 SBYCR SSBY STS4 STS3 STS2 STS1 STS0 MSTPCRA ACSE MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA9 MSTPA8 MSTPA7 MSTPA6 MSTPA0 SYSCR SCKCR MSTPCRB MSTPCRC 1 SMR_3* MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPB15 MSTPB14 MSTPB13 MSTPB12 MSTPB11 MSTPB10 MSTPB9 MSTPB8 MSTPB7 MSTPB1 MSTPB0 MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC8 MSTPC7 MSTPC6 C/A (GM) CHR (BLK) PE MSTPB6 MSTPB5 MSTPC5 MSTPB4 MSTPB3 MSTPB2 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 O/E STOP MP CKS1 CKS0 (BCP1) (BCP0) MPIE TEIE CKE1 CKE0 SCI_3 BRR_3 SCR_3*1 TIE RIE TE RE TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT SDIR SINV SMIF C/A (GM) CHR (BLK) PE O/E STOP MP CKS1 CKS0 (BCP1) (BCP0) MPIE TEIE CKE1 CKE0 TDR_3 SSR_3*1 RDR_3 SCMR_3 1 SMR_4* SCI_4 BRR_4 SCR_4*1 TIE RIE TE RE TDRE RDRF ORER FER (ERS) PER TEND MPB MPBT SCMR_4 SDIR SINV SMIF FCCS FLER SCO FPCS PPVS FECS EPVB FKEY K7 K6 K5 K4 K3 K2 K1 K0 TDR_4 SSR_4*1 RDR_4 FLASH Rev. 1.00, 03/04, page 681 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module FMATS MS7 MS1 MS0 FLASH MS6 Bit Bit Bit MS5 MS4 MS3 Bit MS2 Bit Bit FTDAR TDER TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 TCR_4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_4 MD2 MD1 MD0 TIOR_4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_4 TTGE TCIEU TCIEV TGIEB TGIEA TSR_4 TCFD TCFU TCFV TGFB TGFA TCR_5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_5 MD2 MD1 MD0 TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_5 TTGE TCIEU TCIEV TGIEB TGIEA TSR_5 TCFD TCFU TCFV TGFB TGFA INTM1 INTM0 NMIEG CPUPCR CPUPCE IPSETE CPUP2 CPUP1 CPUP0 IER IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT2 P23 P22 P21 P20 PORT3 P37 P36 P35 P34 P33 P32 P31 P30 TPU_4*2 TCNT_4 TGRA_4 TGRB_4 TPU_5*2 TCNT_5 TGRA_5 TGRB_5 INTCR ISR Rev. 1.00, 03/04, page 682 of 730 INTC I/O port Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit 24/16/8/0 Module PORT4 P47 P40 I/O port P46 Bit P45 Bit P44 Bit P43 Bit Bit P42 P41 Bit PORT5 P57 P56 P55 P54 P53 P52 P51 P50 PORT6 P66 P65 P64 P63 P62 P61 P60 PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR P23DR P22DR P21DR P20DR P3DR P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR P6DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 PMR G3INV G2INV G3NOV G2NOV NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 NDRL NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 ADDRA_0 PPG*2 A/D_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 Rev. 1.00, 03/04, page 683 of 730 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 ADDRH_0 Module A/D_0 ADCSR_0 ADF ADIE ADST CH3 CH2 CH1 CH0 ADCR_0 TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 TCSR OVF WT/IT TME CKS2 CKS1 CKS0 RSTCSR WOVF RSTE TSTR CST5 CST4 CST3 CST2 CST1 CST0 TSYR SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 BFB BFA MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV TGFB TGFA WDT TCNT TPU*2 TPU_0*2 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCNT_1 Rev. 1.00, 03/04, page 684 of 730 TPU_1*2 Register Bit Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 Module TPU_1*2 TGRA_1 TGRB_1 TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_3 BFB BFA MD2 MD1 MD0 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_3 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_3 TCFV TGFD TGFC TGFB TGFA TPU_2*2 TCNT_2 TGRA_2 TGRB_2 TPU_3*2 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 Notes: 1. Parts of the bit functions differ in normal mode and the smart card interface mode. 2. Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 685 of 730 20.3 Register States in Each Operating Mode Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MCR Initialized Initialized Initialized Initialized HCAN GSR Initialized Initialized Initialized Initialized BCR Initialized Initialized Initialized Initialized MBCR Initialized Initialized Initialized Initialized TXPR Initialized Initialized Initialized Initialized TXCR Initialized Initialized Initialized Initialized TXACK Initialized Initialized Initialized Initialized ABACK Initialized Initialized Initialized Initialized RXPR Initialized Initialized Initialized Initialized RFPR Initialized Initialized Initialized Initialized IRR Initialized Initialized Initialized Initialized MBIMR Initialized Initialized Initialized Initialized IMR Initialized Initialized Initialized Initialized REC Initialized Initialized Initialized Initialized TEC Initialized Initialized Initialized Initialized UMSR Initialized Initialized Initialized Initialized LAFML Initialized Initialized Initialized Initialized LAFMH Initialized Initialized Initialized Initialized MC0[1] MC0[2] MC0[3] MC0[4] MC0[5] MC0[6] MC0[7] MC0[8] MC1[1] MC1[2] MC1[3] MC1[4] MC1[5] Rev. 1.00, 03/04, page 686 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MC1[6] HCAN MC1[7] MC1[8] MC2[1] MC2[2] MC2[3] MC2[4] MC2[5] MC2[6] MC2[7] MC2[8] MC3[1] MC3[2] MC3[3] MC3[4] MC3[5] MC3[6] MC3[7] MC3[8] MC4[1] MC4[2] MC4[3] MC4[4] MC4[5] MC4[6] MC4[7] MC4[8] MC5[1] MC5[2] MC5[3] MC5[4] MC5[5] MC5[6] Rev. 1.00, 03/04, page 687 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MC5[7] HCAN MC5[8] MC6[1] MC6[2] MC6[3] MC6[4] MC6[5] MC6[6] MC6[7] MC6[8] MC7[1] MC7[2] MC7[3] MC7[4] MC7[5] MC7[6] MC7[7] MC7[8] MC8[1] MC8[2] MC8[3] MC8[4] MC8[5] MC8[6] MC8[7] MC8[8] MC9[1] MC9[2] MC9[3] MC9[4] MC9[5] MC9[6] MC9[7] Rev. 1.00, 03/04, page 688 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MC9[8] HCAN MC10[1] MC10[2] MC10[3] MC10[4] MC10[5] MC10[6] MC10[7] MC10[8] MC11[1] MC11[2] MC11[3] MC11[4] MC11[5] MC11[6] MC11[7] MC11[8] MC12[1] MC12[2] MC12[3] MC12[4] MC12[5] MC12[6] MC12[7] MC12[8] MC13[1] MC13[2] MC13[3] MC13[4] MC13[5] MC13[6] MC13[7] MC13[8] Rev. 1.00, 03/04, page 689 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MC14[1] HCAN MC14[2] MC14[3] MC14[4] MC14[5] MC14[6] MC14[7] MC14[8] MC15[1] MC15[2] MC15[3] MC15[4] MC15[5] MC15[6] MC15[7] MC15[8] MD0[1] MD0[2] MD0[3] MD0[4] MD0[5] MD0[6] MD0[7] MD0[8] MD1[1] MD1[2] MD1[3] MD1[4] MD1[5] MD1[6] MD1[7] MD1[8] MD2[1] Rev. 1.00, 03/04, page 690 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MD2[2] HCAN MD2[3] MD2[4] MD2[5] MD2[6] MD2[7] MD2[8] MD3[1] MD3[2] MD3[3] MD3[4] MD3[5] MD3[6] MD3[7] MD3[8] MD4[1] MD4[2] MD4[3] MD4[4] MD4[5] MD4[6] MD4[7] MD4[8] MD5[1] MD5[2] MD5[3] MD5[4] MD5[5] MD5[6] MD5[7] MD5[8] MD6[1] MD6[2] Rev. 1.00, 03/04, page 691 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MD6[3] HCAN MD6[4] MD6[5] MD6[6] MD6[7] MD6[8] MD7[1] MD7[2] MD7[3] MD7[4] MD7[5] MD7[6] MD7[7] MD7[8] MD8[1] MD8[2] MD8[3] MD8[4] MD8[5] MD8[6] MD8[7] MD8[8] MD9[1] MD9[2] MD9[3] MD9[4] MD9[5] MD9[6] MD9[7] MD9[8] MD10[1] MD10[2] MD10[3] Rev. 1.00, 03/04, page 692 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MD10[4] HCAN MD10[5] MD10[6] MD10[7] MD10[8] MD11[1] MD11[2] MD11[3] MD11[4] MD11[5] MD11[6] MD11[7] MD11[8] MD12[1] MD12[2] MD12[3] MD12[4] MD12[5] MD12[6] MD12[7] MD12[8] MD13[1] MD13[2] MD13[3] MD13[4] MD13[5] MD13[6] MD13[7] MD13[8] MD14[1] MD14[2] MD14[3] MD14[4] Rev. 1.00, 03/04, page 693 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby MD14[5] HCAN MD14[6] MD14[7] MD14[8] MD15[1] MD15[2] MD15[3] MD15[4] MD15[5] MD15[6] MD15[7] MD15[8] HCANMON Initialized Initialized Initialized Initialized SSCRH_0 Initialized Initialized Initialized Initialized SSCRL_0 Initialized Initialized Initialized Initialized SSMR_0 Initialized Initialized Initialized Initialized SSER_0 Initialized Initialized Initialized Initialized SSSR_0 Initialized Initialized Initialized Initialized SSCR2_0 Initialized Initialized Initialized Initialized SSTDR0_0 Initialized Initialized Initialized Initialized SSTDR1_0 Initialized Initialized Initialized Initialized SSTDR2_0 Initialized Initialized Initialized Initialized SSTDR3_0 Initialized Initialized Initialized Initialized SSRDR0_0 Initialized Initialized Initialized Initialized SSRDR1_0 Initialized Initialized Initialized Initialized SSRDR2_0 Initialized Initialized Initialized Initialized SSRDR3_0 Initialized Initialized Initialized Initialized SSCRH_1 Initialized Initialized Initialized Initialized SSCRL_1 Initialized Initialized Initialized Initialized SSMR_1 Initialized Initialized Initialized Initialized SSER_1 Initialized Initialized Initialized Initialized SSSR_1 Initialized Initialized Initialized Initialized SSCR2_1 Initialized Initialized Initialized Initialized Rev. 1.00, 03/04, page 694 of 730 SSU_0 SSU_1 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby SSTDR0_1 Initialized Initialized Initialized Initialized SSU_1 SSTDR1_1 Initialized Initialized Initialized Initialized SSTDR2_1 Initialized Initialized Initialized Initialized SSTDR3_1 Initialized Initialized Initialized Initialized SSRDR0_1 Initialized Initialized Initialized Initialized SSRDR1_1 Initialized Initialized Initialized Initialized SSRDR2_1 Initialized Initialized Initialized Initialized SSRDR3_1 Initialized Initialized Initialized Initialized SSCRH_2 Initialized Initialized Initialized Initialized SSCRL_2 Initialized Initialized Initialized Initialized SSMR_2 Initialized Initialized Initialized Initialized SSER_2 Initialized Initialized Initialized Initialized SSSR_2 Initialized Initialized Initialized Initialized SSCR2_2 Initialized Initialized Initialized Initialized SSTDR0_2 Initialized Initialized Initialized Initialized SSTDR1_2 Initialized Initialized Initialized Initialized SSTDR2_2 Initialized Initialized Initialized Initialized SSTDR3_2 Initialized Initialized Initialized Initialized SSRDR0_2 Initialized Initialized Initialized Initialized SSRDR1_2 Initialized Initialized Initialized Initialized SSRDR2_2 Initialized Initialized Initialized Initialized SSRDR3_2 Initialized Initialized Initialized Initialized PHRTIDR Initialized I/O port ADDRA_1 Initialized A/D_1 ADDRB_1 Initialized ADDRC_1 Initialized ADDRD_1 Initialized ADDRE_1 Initialized ADDRF_1 Initialized ADDRG_1 Initialized ADDRH_1 Initialized ADCSR_1 Initialized ADCR_1 Initialized SSU_2 SSU_2 Rev. 1.00, 03/04, page 695 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TSTRB Initialized TPU TSYRB Initialized TCR_6 Initialized TMDR_6 Initialized TIORH_6 Initialized TIORL_6 Initialized TIER_6 Initialized TSR_6 Initialized TCNT_6 Initialized TGRA_6 Initialized TGRB_6 Initialized TGRC_6 Initialized TGRD_6 Initialized TCR_7 Initialized TMDR_7 Initialized TIOR_7 Initialized TIER_7 Initialized TSR_7 Initialized TCNT_7 Initialized TGRA_7 Initialized TGRB_7 Initialized TPU_7 TCR_8 Initialized TPU_8 TMDR_8 Initialized TIOR_8 Initialized TIER_8 Initialized TSR_8 Initialized TCNT_8 Initialized TGRA_8 Initialized TGRB_8 Initialized TCR_9 Initialized TMDR_9 Initialized TIORH_9 Initialized TIORL_9 Initialized Rev. 1.00, 03/04, page 696 of 730 TPU_6 TPU_7 TPU_9 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TIER_9 Initialized TPU_9 TSR_9 Initialized TCNT_9 Initialized TGRA_9 Initialized TGRB_9 Initialized TGRC_9 Initialized TGRD_9 Initialized TCR_10 Initialized TMDR_10 Initialized TIOR_10 Initialized TIER_10 Initialized TSR_10 Initialized TCNT_10 Initialized TGRA_10 Initialized TGRB_10 Initialized TCR_11 Initialized TMDR_11 Initialized TIOR_11 Initialized TIER_11 Initialized TSR_11 Initialized TCNT_11 Initialized TGRA_11 Initialized TGRB_11 Initialized P1DDR Initialized P2DDR Initialized P3DDR Initialized P6DDR Initialized PADDR Initialized PDDDR Initialized P1ICR Initialized P2ICR Initialized P3ICR Initialized P4ICR Initialized TPU_10 TPU_11 I/O port Rev. 1.00, 03/04, page 697 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby P5ICR Initialized I/O port P6ICR Initialized PAICR Initialized PDICR Initialized PORTH PORTJ PORTK PHDR Initialized PJDR Initialized PKDR Initialized PHDDR Initialized PJDDR Initialized PKDDR Initialized PHICR Initialized PJICR Initialized PKICR Initialized PDPCR Initialized PHPCR Initialized PJPCR Initialized PKPCR Initialized P2ODR Initialized PFCR9 Initialized PFCRA Initialized PFCRB Initialized SSIER Initialized INTC DSAR_0 Initialized DMAC_0 DDAR_0 Initialized DOFR_0 Initialized DTCR_0 Initialized DBSR_0 Initialized DMDR_0 Initialized DACR_0 Initialized Rev. 1.00, 03/04, page 698 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby DSAR_1 Initialized DMAC_1 DDAR_1 Initialized DOFR_1 Initialized DTCR_1 Initialized DBSR_1 Initialized DMDR_1 Initialized DACR_1 Initialized DSAR_2 Initialized DDAR_2 Initialized DOFR_2 Initialized DTCR_2 Initialized DBSR_2 Initialized DMDR_2 Initialized DACR_2 Initialized DSAR_3 Initialized DDAR_3 Initialized DOFR_3 Initialized DTCR_3 Initialized DBSR_3 Initialized DMDR_3 Initialized DACR_3 Initialized DMRSR_0 Initialized DMAC_0 DMRSR_1 Initialized DMAC_1 DMRSR_2 Initialized DMAC_2 DMRSR_3 Initialized DMAC_3 IPRA Initialized INTC IPRB Initialized IPRC Initialized IPRD Initialized IPRE Initialized IPRF Initialized IPRG Initialized IPRI Initialized IPRK Initialized DMAC_2 DMAC_3 Rev. 1.00, 03/04, page 699 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby IPRL Initialized INTC IPRM Initialized IPRN Initialized IPRO Initialized IPRQ Initialized IPRR Initialized ISCRH Initialized ISCRL Initialized BCR2 Initialized RAMER Initialized MDCR Initialized SYSCR Initialized SCKCR Initialized SBYCR Initialized MSTPCRA Initialized MSTPCRB Initialized MSTPCRC Initialized SMR_3 Initialized BRR_3 Initialized SCR_3 Initialized TDR_3 Initialized Initialized Initialized Initialized SSR_3 Initialized Initialized Initialized Initialized RDR_3 Initialized Initialized Initialized Initialized SCMR_3 Initialized SMR_4 Initialized BRR_4 Initialized SCR_4 Initialized TDR_4 Initialized Initialized Initialized Initialized SSR_4 Initialized Initialized Initialized Initialized RDR_4 Initialized Initialized Initialized Initialized SCMR_4 Initialized Rev. 1.00, 03/04, page 700 of 730 BSC SYSTEM SCI_3 SCI_4 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby FCCS Initialized FLASH FPCS Initialized FECS Initialized FKEY Initialized FMATS Initialized FTDAR Initialized TCR_4 Initialized TMDR_4 Initialized TIOR_4 Initialized TIER_4 Initialized TSR_4 Initialized TCNT_4 Initialized TGRA_4 Initialized TGRB_4 Initialized TCR_5 Initialized TMDR_5 Initialized TIOR_5 Initialized TIER_5 Initialized TSR_5 Initialized TCNT_5 Initialized TGRA_5 Initialized TGRB_5 Initialized INTCR Initialized CPUPCR Initialized IER Initialized ISR Initialized PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA PORTD TPU_4* TPU_5* INTC I/O port Rev. 1.00, 03/04, page 701 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby P1DR Initialized I/O port P2DR Initialized P3DR Initialized P6DR Initialized PADR Initialized PDDR Initialized PCR Initialized PMR Initialized NDERH Initialized NDERL Initialized PODRH Initialized PODRL Initialized NDRH Initialized NDRL Initialized ADDRA_0 Initialized ADDRB_0 Initialized ADDRC_0 Initialized ADDRD_0 Initialized ADDRE_0 Initialized ADDRF_0 Initialized ADDRG_0 Initialized ADDRH_0 Initialized ADCSR_0 Initialized ADCR_0 Initialized TCSR Initialized TCNT Initialized RSTCSR Initialized TSTR Initialized TSYR Initialized TCR_0 Initialized TMDR_0 Initialized TIORH_0 Initialized TIORL_0 Initialized Rev. 1.00, 03/04, page 702 of 730 PPG* A/D_0 WDT TPU* TPU_0* Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TIER_0 Initialized TPU_0* TSR_0 Initialized TCNT_0 Initialized TGRA_0 Initialized TGRB_0 Initialized TGRC_0 Initialized TGRD_0 Initialized TCR_1 Initialized TMDR_1 Initialized TIOR_1 Initialized TIER_1 Initialized TSR_1 Initialized TCNT_1 Initialized TGRA_1 Initialized TGRB_1 Initialized TCR_2 Initialized TMDR_2 Initialized TIOR_2 Initialized TIER_2 Initialized TSR_2 Initialized TCNT_2 Initialized TGRA_2 Initialized TGRB_2 Initialized TCR_3 Initialized TMDR_3 Initialized TIORH_3 Initialized TIORL_3 Initialized TIER_3 Initialized TSR_3 Initialized TCNT_3 Initialized TGRA_3 Initialized TGRB_3 Initialized TPU_1* TPU_2* TPU_3* Rev. 1.00, 03/04, page 703 of 730 Register Abbreviation Reset Sleep Module Stop All-ModuleClock-Stop Software Standby Hardware Standby TGRC_3 Initialized TPU_3* Initialized TGRD_3 Note: * Supported only by the H8SX/1527. Rev. 1.00, 03/04, page 704 of 730 Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC -0.3 to +7.0 V Input voltage (except ports 4 and 5) Vin -0.3 to VCC + 0.3 V Input voltage (port 4) Vin -0.3 to AVCC1 + 0.3 V Input voltage (port 5) Vin -0.3 to AVCC0 + 0.3 V Analog power supply voltage AVCC0 -0.3 to +7.0 V AVCC1 -0.3 to +7.0 V VAN -0.3 to AVCC1 + 0.3 V Analog input voltage (port 4) Analog input voltage (port 5) VAN -0.3 to AVCC0 + 0.3 V Operating temperature Topr Regular specifications: -20 to +75* C Wide-range specifications: -40 to +85* Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * The operating temperature when programming/erasing the flash memory ranges from 0C to +75C for regular specification products and from 0C to +85C for wide-range specification products. Rev. 1.00, 03/04, page 705 of 730 21.2 DC Characteristics Table 21.2 DC Characteristics (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt IRQ input pin, trigger input TPU input pin, voltage ports 2, 3, J, K Symbol VT - VT + + VT - VT Input high voltage (except Schmitt trigger input pin) Input low voltage (except Schmitt trigger input pin) MD, RES, NMI - Min. Typ. Max. Test Unit Conditions VCC x 0.2 V VCC x 0.7 VCC x 0.05 VCC - 0.7 VCC + 0.3 EXTAL VCC x 0.7 VCC + 0.3 Other input pins VCC x 0.7 VCC + 0.3 Port 4 AVCC1 x 0.7 AVCC1 + 0.3 Port 5 AVCC0 x 0.7 AVCC0 + 0.3 RES, MD, NMI VIH -0.3 VCC x 0.1 EXTAL -0.3 VCC x 0.2 Other pins -0.3 VCC x 0.2 VIL Port 4 -0.3 AVCC1 x 0.2 Port 5 -0.3 AVCC0 x 0.2 VCC - 0.5 VCC - 1.0 V V VOH Output low voltage All output pins VOL 0.4 V IOL = 1.6 mA Input leakage current RES, NMI, MD |Iin| 1.0 A Vin = 0.5 to VCC - 0.5 V Port 4 1.0 Vin = 0.5 to AVCC1 - 0.5 V Port 5 1.0 Vin = 0.5 to AVCC0 - 0.5 V Rev. 1.00, 03/04, page 706 of 730 V IOH = -200 A Output high All output pins voltage IOH = -1 mA Table 21.2 DC Characteristics (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Tri-state leakage current (off state) Symbol Ports 1 to 3, 6, A, | ITSI | D, H, J, K Min. Typ. Max. Test Unit Conditions 1.0 A Vin = 0.5 to VCC - 0.5 V Input pull-up Ports D, H, J, K MOS current -Ip 50 300 A Vin = 0 V Input All input pins capacitance Cin 15 pF Vin = 0 V f = 1 MHz Ta = 25C 48 78 mA f = 40 MHz 40 70 1 2 Ta 50C 3 50C < Ta 35 45 3.5 5 10 100 A 3.5 5 mA 10 100 A 3.0 V 4 Current Normal operation ICC* consumption Sleep mode 2 * 3 Standby mode* All-module-clockstop mode*5 Analog power During A/D conversion supply current Standby for A/D conversion During A/D conversion AICC0 AICC1 Standby for A/D conversion RAM standby voltage VRAM AVCC0 = 5.0 V AVCC1 = 5.0 V Notes: 1. When the A/D converter is not used, the AVCC0, AVCC1, and AVSS pins should not be open. Connect the AVCC and AVCC1 pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIH = AVCC0 (port 5), AVCC1 (port 4), VCC (others) and VIL = 0 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 4.5 V, VIHmin. = VCC - 0.1 V, and VILmax. = 0.1 V. 4. ICC depends on VCC and f as follows: ICCmax = 12 (mA) + 0.3 (mA/(MHz x V)) x VCC x f (normal operation) ICCmax = 12 (mA) + 0.26 (mA/(MHz x V)) x VCC x f (sleep mode) 5. The values are for reference. Rev. 1.00, 03/04, page 707 of 730 Table 21.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Typ. Max. Unit Permissible output low current (per pin) All output pins IOL 10 mA Permissible output low current (total) Total of all output pins IOL 100 mA Permissible output high current (per pin) All output pins -IOH 2.0 mA Permissible output high current (total) Total of all output pins -IOH 30 mA Caution: Note: * 21.3 To protect the LSI's reliability, do not exceed the output current values in table 21.3. When the A/D converter is not used, the AVCC0, AVCC1, and AVSS pins should not be open. Connect the AVCC0 and AVCC1 pins to VCC, and the AVSS pin to VSS. AC Characteristics 5V RL C = 30 pF (all ports) RL = 2.4 k RH = 12 k Input/output timing measurement level: low at 0.8 V and high at 2.0 V LSI output pin C RH Figure 21.1 Output Load Circuit Rev. 1.00, 03/04, page 708 of 730 21.3.1 Clock Timing Table 21.4 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 40 MHz, P = 8 to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit. Test Conditions Clock cycle time tcyc 25 125 ns Figure 21.2 Clock high pulse width tCH 5 ns Clock low pulse width tCL 5 ns Clock rising time tCr 5 ns Clock falling time tCf 5 ns Oscillation settling time after reset (crystal) tOSC1 20 ms Figure 21.4 Oscillation settling time after leaving software standby mode (crystal) tOSC2 10 ms Figure 21.3 External clock output delay settling time tDEXT 2 ms Figure 21.4 External clock input low pulse width TEXL 45 ns Figure 21.5 External clock input high pulse width TEXH 45 ns External clock input frequency = 4 to 9 MHz External clock rising time TEXr 5 ns External clock falling time TEXf 5 ns tcyc tCH tCf I tCL tCr Figure 21.2 System Bus Clock Timing Rev. 1.00, 03/04, page 709 of 730 Oscillator I NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2 SLEEP instruction Figure 21.3 Oscillation Settling Timing after Software Standby Mode EXTAL tDEXT VCC tOSC1 RES I Figure 21.4 Oscillation Settling Timing tEXH tEXL EXTAL Vcc x 0.5 tEXr tEXf Figure 21.5 External Input Clock Timing Rev. 1.00, 03/04, page 710 of 730 21.3.2 Control Signal Timing Table 21.5 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 40 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ns Figure 21.6 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns NMI hold time tNMIH 10 ns NMI pulse width (after leaving software standby mode) tNMIW 200 ns IRQ setup time tIRQS 150 ns IRQ hold time tIRQH 10 ns IRQ pulse width (after leaving software standby mode) tIRQW 200 ns Figure 21.7 I tRESS tRESS RES tRESW Figure 21.6 Reset Input Timing Rev. 1.00, 03/04, page 711 of 730 I tNMIS tNMIH NMI tNMIW tIRQW IRQi* (i = 0 to 14) tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * SSIER must be set to cancel software standby mode. Figure 21.7 Interrupt Input Timing 21.3.3 Timing of On-Chip Peripheral Modules Table 21.6 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Min. Max. Unit Test Conditions Figure 21.8 tPWD 40 ns Input data setup time tPRS 25 ns Input data hold time tPRH 25 ns Realtime input port data hold time tRTIPH 4 tcyc Figure 21.9 Timer output delay time tTOCD 40 ns Figure 21.10 Timer input setup time tTICS 25 ns Timer clock input setup time tTCKS 25 ns Timer clock pulse width Single-edge setting tTCKWH 1.5 tcyc Both-edge setting tTCKWL 2.5 tcyc I/O ports Output data delay time TPU Symbol Rev. 1.00, 03/04, page 712 of 730 Figure 21.11 Item Symbol Min. Max. Unit Test Conditions PPG Pulse output delay time tPOD 40 ns Figure 21.12 SCI Input clock cycle tScyc 4 tcyc Figure 21.13 6 Asynchronous Clocked synchronous Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr 20 ns Figure 21.13 Input clock fall time tSCKf 20 ns Measurement voltages: VCC x 0.3 V to VCC x 0.7 V 30 4 tSCKW 0.4 0.6 tScyc Output clock rise time tSCKr 20 ns Figure 21.13 Output clock fall time tSCKf 20 ns Measurement Output clock Asynchronous cycle Clocked synchronous tScyc Output clock pulse width tcyc Figure 21.13 voltages: VCC x 0.3 V to VCC x 0.7 V Transmit data delay time tTXD 40 ns Receive data setup time (clocked synchronous) tRXS 40 ns Receive data hold time (clocked synchronous) tRXH 40 ns tTRGS 30 ns A/D Trigger input setup time converter Figure 21.14 Figure 21.15 Rev. 1.00, 03/04, page 713 of 730 Table 21.6 Timing of On-Chip Peripheral Modules (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 20 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item HCAN* SSU Symbol Min. Max. Figure 21.16 Transmit data delay time tHTXD 100 ns tHRXS 100 ns Receive data hold time tHRXH 100 ns tcyc Clock cycle time Clock high pulse width Master tSUcyc Master tHI Slave Clock low pulse width Master tLO 4 256 4 256 80 80 80 ns ns 80 20 ns Clock falling time tFALL 20 ns ns Master 25 30 10 10 tLEAD 2.5 2.5 tLAG 2.5 2.5 tSU Slave Data input hold time Master tH Slave SCS setup time Master SCS hold time Master Slave Slave Data output delay time Master tOD Slave Data output hold time Master tOH Slave Consecutive transmit delay time Master tTD Slave 40 40 30 30 2.5 2.5 Figure 21.19 Figure 21.20 tRISE Data input setup time Figure 21.17 Figure 21.18 Clock rising time Slave * Test Conditions Receive data setup time Slave Note: Unit ns tcyc tcyc ns ns tcyc Slave access time tSA 1 tcyc Figure 21.19 Slave out release time tREL 1 tcyc Figure 21.20 Although the HCAN input signals are asynchronous signals, they are received as the signals in synchronization with every other rising edge of the P clock (see figure 21.16). The HCAN output signals are also asynchronous signals, however, change their levels based on every other rising edge of the P clock. Rev. 1.00, 03/04, page 714 of 730 T1 T2 P tPRS tPRH Ports 1 to 6, A, D, H, J, K (read) tPWD Ports 1 to 3, 6, A, D, H, J, K (write) Figure 21.8 I/O Port Input/Output Timing P IRQ14 tRTIPH Port H input Figure 21.9 Data Input Timing for Realtime Input Port P tTOCD Output compare output*1 tTICS Input capture input*1 Notes: 1. TIOCA0 to TIOCA3*2, TIOCB0 to TIOCB3*2, TIOCC0*2, TIOCC3*2, TIOCD0*2, TIOCD3*2, TIOCA6 to TIOCA11, TIOCB6 to TIOCB11, TIOCC6, TIOCC9, TIOCD6, and TIOCD9 2. Supported only by the H8SX/1527. Figure 21.10 TPU Input/Output Timing P tTCKS tTCKS TCLKA to TCLKD* TCLKE to TCLKH tTCKWL Note: * tTCKWH Supported only by the H8SX/1527. Figure 21.11 TPU Clock Input Timing Rev. 1.00, 03/04, page 715 of 730 P tPOD PO15 to PO8 Figure 21.12 PPG Output Timing tSCKW tSCKr tSCKf SCK3, SCK4 tScyc Figure 21.13 SCK Clock Input/Output Timing SCK3, SCK4 tTXD TxD3, TxD4 (transmit data) tRXS tRXH RxD3, RxD4 (receive data) Figure 21.14 SCI Input/Output Timing: Clocked Synchronous Mode P tTRGS ADTRG0, ADTRG1 Figure 21.15 A/D Converter External Trigger Input Timing P tHTXD HTxD (transmit data) tHRXS tHRXH HRxD (receive data) Figure 21.16 HCAN Input/Output Timing Rev. 1.00, 03/04, page 716 of 730 SCS (output) tTD tLEAD tFALL tHI tRISE tLAG SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tSUcyc tLO SSO (output) tOH tOD SSI (input) tSU tH Figure 21.17 SSU Timing (Master, CPHS = 1) SCS (output) tTD tLEAD tFALL tHI tRISE tLAG SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUcyc SSO (output) tOH tOD SSI (input) tSU tH Figure 21.18 SSU Timing (Master, CPHS = 0) Rev. 1.00, 03/04, page 717 of 730 SCS (input) tFALL tHI tLEAD tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUcyc tLO SSO (input) tSU tH tREL SSI (output) tOH tSA tOD Figure 21.19 SSU Timing (Slave, CPHS = 1) SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUcyc tLO SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 21.20 SSU Timing (Slave, CPHS = 0) Rev. 1.00, 03/04, page 718 of 730 21.3.4 A/D Conversion Characteristics Table 21.7 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, P = 8 to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 7.4 200 s Analog input capacitance 20 pF Permissible signal source impedance 5 k Nonlinearity error 3.5 LSB Offset error 3.5 LSB Full-scale error 3.5 LSB Quantization error 0.5 LSB Absolute accuracy 4.0 LSB Rev. 1.00, 03/04, page 719 of 730 21.3.5 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC0 = 4.5 V to 5.5 V, AVCC1 = 4.5 V to 5.5 V, VSS = AVSS = 0 V, I = 8 to 40 MHz, P = 8 to 35 MHz, Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications) Item Programming time*1*2*4 1 2 4 Erase time* * * Symbol Min. Typ. Max. Unit tP 3 30 ms/128 bytes tE 80 800 ms/4-kbyte block 500 5000 ms/32-kbyte block 1000 10000 ms/64-kbyte block Test Condition Programming time (total) *1*2*4 tP 5 15 s/256 kbytes Ta = 25C, memory filled with 0. Erase time (total) *1*2*4 tE 5 15 s/256 kbytes Ta = 25C Programming/erase time (total) *1*2*4 tPE 10 30 s/256 kbytes Ta = 25C Number of programming NWEC 100*3 Times tDRP 10 Year 4 Data retention time* Notes: 1. Programming time and erase time depend on data in the flash memory. 2. Programming time and erase time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value Rev. 1.00, 03/04, page 720 of 730 Appendix A. Port States in Each Pin State Table A.1 Port States in Each Pin State Port Name MCU Operating Mode Reset Software Standby Mode Port 1 All Hi-Z Keep Port 2 All Hi-Z Keep Port 3 All Hi-Z Keep Port 4 All Hi-Z Hi-Z Port 5 All Hi-Z Hi-Z Port 6 All Hi-Z Keep Port A All Hi-Z Keep Port D All Hi-Z Keep Port H All Hi-Z Keep Port J All Hi-Z Keep Port K All Hi-Z Keep Rev. 1.00, 03/04, page 721 of 730 B. Product Lineup Product Classification Product Model Marking Package (Package Code) H8SX/1527 R5F61527 R5F61527 QFP-100 (FP-100M) H8SX/1525 R5F61525 R5F61525 Rev. 1.00, 03/04, page 722 of 730 C. Package Dimensions For the package dimensions, data in the Renesas IC Package General Catalog has priority. Unit: mm 16.0 0.2 14 75 51 50 100 26 0.10 *Dimension including the plating thickness Base material dimension 0.15 0.04 *0.17 0.05 0.08 M 1.0 0.12 +0.13 -0.12 0.20 0.04 2.70 25 1 *0.22 0.05 3.05 Max 0.5 16.0 0.2 76 1.0 0 - 8 0.5 0.1 Package Code JEDEC JEITA Mass (reference value) FP-100M -- Conforms 1.2 g Figure C.1 Package Dimensions (FP-100M) Rev. 1.00, 03/04, page 723 of 730 Rev. 1.00, 03/04, page 724 of 730 Index 0-output/1-output .................................... 283 11 consecutive recessive bits .................. 449 16-bit timer pulse unit (TPU) ................. 235 A/D conversion accuracy........................ 521 A/D converter ......................................... 507 Absolute accuracy................................... 521 Absolute maximum ratings..................... 705 AC characteristics................................... 708 Address error ............................................ 73 Address error exception handling ............. 74 Address map ............................................. 66 All-module-clock-stop mode .......... 626, 634 Arbitration field .............................. 456, 459 Asynchronous mode ............................... 378 AT-cut parallel-resonance type............... 620 Available output signal and settings in each port ............................................. 225 B clock output control .......................... 639 Bit rate ............................................ 371, 452 Block diagram............................................. 2 Block structure........................................ 534 Boot mode ...................................... 531, 558 Buffer operation...................................... 288 Buffer segment ....................................... 452 Bus arbitration ........................................ 125 Bus configuration ................................... 121 Bus controller (BSC) .............................. 119 Bus-released state ..................................... 60 CAN bus interface .................................. 465 Cascaded operation................................. 291 Clock....................................................... 381 Clock pulse generator ............................. 617 Clock synchronous communication mode ....................................................... 498 Clocked synchronous mode .................... 393 Communications protocol....................... 590 Configuration mode ................................ 449 Control field............................................ 456 Controller area network (HCAN)............ 417 Counter operation.................................... 281 CPU priority control function over DMAC .................................................... 114 Crystal resonator ..................................... 620 Data direction register............................. 202 Data field................................................. 456 Data frame reception............................... 459 Data register............................................ 202 DC characteristics ................................... 706 Direct convention.................................... 401 DMA controller (DMAC) ....................... 127 Double-buffered structure ....................... 378 Download pass/fail result parameter....... 547 DTC interface ......................................... 464 Electrical characteristics ......................... 705 Error protection....................................... 582 Error signal ............................................. 400 Exception handling ................................... 67 Exception handling by general illegal instruction ................................................. 78 Exception handling vector table................ 68 Exception-handling state........................... 60 External access bus ................................. 121 External bus clock (B) .................. 122, 617 External clock ......................................... 621 External interrupts..................................... 97 External trigger input .............................. 520 Flash erase block select parameter.......... 556 Flash memory ......................................... 529 Flash multipurpose address area parameter ................................................ 554 Flash multipurpose data destination parameter ................................................ 555 Flash pass and fail parameter .................. 548 Rev. 1.00, 03/04, page 725 of 730 Flash program/erase frequency parameter ................................................ 553 Free-running count operation ................. 282 Frequency divider ........................... 617, 622 Full-scale error........................................ 521 Hardware protection ............................... 581 HCAN halt mode .................................... 462 HCAN sleep mode.................................. 461 HCAN transmission setting .................... 468 I/O ports.................................................. 195 ID code ................................................... 387 Illegal instruction...................................... 77 Input buffer control register.................... 203 Input capture function............................. 284 Internal bus ............................................. 123 Internal interrupts ..................................... 98 Internal peripheral bus ............................ 121 Internal system bus 1 .............................. 121 Interrupt .................................................... 75 Interrupt control mode 0 ......................... 106 Interrupt control mode 2 ......................... 108 Interrupt controller.................................... 81 Interrupt exception handling..................... 76 Interrupt exception handling sequence ... 110 Interrupt exception handling vector table . 99 Interrupt response times.......................... 111 Interrupt sources ....................................... 97 Interrupt sources and vector address offsets ....................................................... 99 Interval timer mode ................................ 346 Inverse convention.................................. 401 IRQn interrupts......................................... 97 List of registers ....................................... 641 Mailbox .................................................. 443 Mark state ....................................... 378, 412 MCU operating modes.............................. 61 Memory MAT configuration .................. 533 Message control (MC0 to MC15)........... 443 Message data (MD0 to MD15) ............... 446 Rev. 1.00, 03/04, page 726 of 730 Message transmission cancellation ......... 457 Message transmission method ................ 454 Mode 1 ...................................................... 65 Mode 2 ...................................................... 65 Mode 3 ...................................................... 65 Mode pin................................................... 61 Module stop mode .................................. 633 Multi-clock function ....................... 122, 633 Multiprocessor bit ................................... 387 Multiprocessor communication function 387 NMI interrupt............................................ 97 Nonlinearity error ................................... 521 Non-overlapping pulse output................. 333 Offset error.............................................. 521 On-board programming .......................... 558 On-board programming mode................. 529 On-chip baud rate generator.................... 381 Open-drain control register ..................... 205 Oscillator................................................. 620 Output buffer control .............................. 206 Output trigger.......................................... 332 Overflow ................................................. 345 Package ....................................................... 1 Package dimensions................................ 723 Parity bit.................................................. 378 Periodic count operation ......................... 282 Peripheral module clock (P).......... 122, 617 Phase counting mode .............................. 298 Pin assignments........................................... 4 Pin configuration in each operating mode ........................................................... 6 Pin functions ............................................. 10 PLL circuit ...................................... 617, 622 Port function controller ........................... 229 Port H realtime input data register .......... 205 Port register............................................. 203 Port states in each pin state ..................... 721 Power-down modes................................. 625 Procedure program.................................. 576 Processing states ....................................... 60 Product lineup......................................... 722 Program execution state............................ 60 Program stop state .................................... 60 Programmable pulse generator (PPG) .... 321 Programmer mode .................................. 588 Programming/erasing interface............... 535 Programming/erasing interface parameters............................................... 545 Programming/erasing interface register.. 538 Protection................................................ 581 Pull-up MOS control register.................. 204 PWM modes ........................................... 293 Quantization error................................... 521 RAM ....................................................... 527 Register addresses................................... 642 Register bits ............................................ 662 Register configuration in each port......... 200 Register states in each operating mode... 686 Registers ABACK ...................... 429, 642, 662, 686 ADCR ......................... 515, 660, 684, 702 ADCSR....................... 513, 660, 684, 702 ADDR......................... 512, 660, 683, 702 BCR .................................................... 642 BCR .................................... 423, 662, 686 BCR2 .......................... 120, 657, 680, 700 BRR ............................ 371, 658, 681, 700 CPUPCR....................... 84, 659, 682, 701 DACR ................................... 655, 677, 698 DBSR .................................... 655, 676, 698 DDAR......................... 131, 655, 676, 698 DDR............................ 202, 654, 675, 697 DMDR................................... 655, 676, 698 DMRSR ................................. 656, 679, 699 DOFR ......................... 132, 655, 676, 698 DPFR .................................................. 547 DR ........................................ 659, 683, 702 DSAR.................................... 655, 676, 698 DTCR.................................... 655, 676, 698 FCCS .................................... 658, 681, 701 FEBS................................................... 556 FECS........................... 541, 658, 681, 701 FKEY .......................... 542, 658, 681, 701 FMATS ....................... 543, 658, 682, 701 FMPAR............................................... 554 FMPDR............................................... 555 FPCS ........................... 541, 658, 681, 701 FPEFEQ .............................................. 553 FPFR ................................................... 548 FTDAR ....................... 544, 658, 682, 701 GSR............................. 421, 642, 662, 686 HCANMON................ 448, 650, 670, 694 ICR.............................. 203, 654, 675, 697 IER................................ 88, 659, 682, 701 IMR............................. 436, 642, 662, 686 INTCR .......................... 84, 659, 682, 701 IPR ................................ 86, 657, 679, 699 IRR.............................. 432, 642, 662, 686 ISCRH........................... 90, 657, 680, 700 ISCRL ........................... 90, 657, 680, 700 ISR ................................ 95, 659, 682, 701 LAFMH ...................... 440, 642, 663, 686 LAFML....................... 440, 642, 663, 686 MAR ........................................... 130, 133 MBCR......................... 425, 642, 662, 686 MBIMR....................... 435, 642, 662, 686 MC .............................. 443, 642, 663, 686 MCR............................ 420, 642, 662, 686 MD .............................. 446, 646, 667, 690 MDCR........................... 62, 657, 681, 700 MSTPCRA.................. 629, 657, 681, 700 MSTPCRB .................. 629, 657, 681, 700 MSTPCRC .................. 632, 657, 681, 700 NDERH....................... 322, 659, 683, 702 NDERL ....................... 322, 659, 683, 702 NDRH ......................... 325, 659, 683, 702 NDRL.......................... 325, 659, 683, 702 ODR............................ 205, 655, 676, 698 PCR..................... 204, 328, 659, 683, 702 PFCR9......................... 229, 655, 676, 698 PFCRA........................ 231, 655, 676, 698 PFCRB ........................ 232, 655, 676, 698 PHRTIDR ................... 205, 652, 672, 695 PMR ............................ 328, 659, 683, 702 Rev. 1.00, 03/04, page 727 of 730 PODRH .......................324, 659, 683, 702 PODRL ........................324, 659, 683, 702 PORT...........................203, 659, 682, 701 RAMER ................................. 657, 680, 700 RDR.............................355, 658, 681, 700 REC .............................438, 642, 662, 686 RFPR ...........................431, 642, 662, 686 RSR .................................................... 355 RSTCSR ......................344, 660, 684, 702 RXPR...........................430, 642, 662, 686 SBYCR........................627, 657, 681, 700 SCKCR........................618, 657, 681, 700 SCMR..........................370, 658, 681, 700 SCR .............................359, 657, 681, 700 SIER ...................................................... 676 SMR.....................356, 657, 658, 681, 700 SSCR2 .........................481, 650, 671, 694 SSCRH ........................474, 650, 670, 694 SSCRL.........................476, 650, 670, 694 SSER ...........................478, 650, 671, 694 SSIER ................................... 96, 655, 698 SSMR ..........................477, 650, 670, 694 SSR..............................363, 657, 681, 700 SSRDR ........................484, 651, 671, 694 SSSR............................479, 650, 671, 694 SSTDR.........................483, 650, 671, 694 SSTRSR.............................................. 484 SYSCR ..........................63, 657, 681, 700 TCNT...........278, 342, 660, 684, 702, 703 TCR .............................249, 660, 684, 702 TCSR ...........................342, 660, 684, 702 TDR .............................355, 658, 681, 700 TEC .............................438, 642, 662, 686 TGR .............................278, 660, 684, 703 TIER ............................273, 660, 684, 703 TIOR............................255, 660, 684, 702 TMDR .........................254, 660, 684, 702 TSR......................275, 355, 660, 684, 703 TSTR ...........................279, 660, 684, 702 TSYR...........................280, 660, 684, 702 TXACK .......................428, 642, 662, 686 TXCR ..........................427, 642, 662, 686 TXPR...........................426, 642, 662, 686 Rev. 1.00, 03/04, page 728 of 730 UMSR ......................... 439, 642, 662, 686 Remote frame reception.......................... 460 Reset ......................................................... 70 Reset exception handling .......................... 70 Reset state ................................................. 60 Resolution ............................................... 521 Sample-and-hold circuit.......................... 519 Scan mode............................................... 517 Serial communication interface (SCI)..... 351 Single mode ............................................ 516 Sleep mode...................................... 626, 634 Slot illegal instruction ............................... 78 Smart card interface ................................ 400 Software protection................................. 582 Software standby mode................... 626, 635 Space state .............................................. 378 SSU mode ............................................... 489 Stack status after exception handling........ 79 Standard serial communication interface specifications for boot mode................... 588 Start bit.................................................... 378 State transitions......................................... 60 Stop bit.................................................... 378 Synchronous clearing.............................. 286 Synchronous operation............................ 286 Synchronous presetting........................... 286 Synchronous serial communication unit (SSU) ...................................................... 469 System clock (I) ............................ 122, 617 Time quanta (tq)...................................... 452 Time quanta (TQ) ................................... 453 Toggle output.......................................... 284 Trace exception handling.......................... 72 Transfer clock ......................................... 485 Transmit/receive data.............................. 378 Trap instruction exception handling ......... 77 Unread message overwrite...................... 460 user boot MAT........................................ 587 User boot MAT....................................... 529 User boot mode....................................... 572 user MAT................................................ 587 User MAT............................................... 529 User program mode ................................ 562 Vector table address.................................. 68 Vector table address offset........................ 68 Watchdog timer (WDT) .......................... 341 Watchdog timer mode............................. 345 Waveform output by compare match...... 283 Write data buffer function....................... 124 Write data buffer function for external data bus ................................................... 124 Rev. 1.00, 03/04, page 729 of 730 Rev. 1.00, 03/04, page 730 of 730 Renesas 32-Bit CISC Microcomputer Hardware Manual H8SX/1520 Group Publication Date: Rev.1.00, Mar 15, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Colophon 1.0 H8SX/1520 Group Hardware Manual