DS2505 DALLAS SEMICONDUCTOR DS2505 16K bit AddOnly Memory FEATURES 16384 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground Unique, factorylasered and tested 64-bit registra- tion number (8-bit family code + 48-bit serial number + &-bit CRC tester) assures absolute traceability because no two parts are alike Builtjn multidrop controller ensures compatibility with other MicroLAN products @ EPROM partitioned into sixty-four 256-bit pages for randomly accessing packetized data records * Each memory page can be pennanently write-pro- tected to prevent tampering Device is an add only memory where additional data can be programmed into EPROM without disturbing existing data Architecture allows software to patch data by super- seding an old page in favor of a newly programmed page @ Reduces control, address, data, power, and program- ming signals to a single data pin * Directly connects toa single port pin of amicroproces- sor and communicates at up to 16.3k bits per second * 8-bit family code specifies DS2505 communications requirements to reader @ Presence detector acknowledges when the reader first applies voltage Low cost TO-92 or 6-pin TSOC surface mount package @ Reads over a wide voltage range of 2.8V to 6.0V from 40C to +85C; programs at 11.5V to 12.0V from 40C to +85C PIN ASSIGNMENT TO_92 ya TSOC PACKAGE PEEL + GNDq/1 6 /7NC DATA (2 5/0 NC NCq|3 4/nNC he o/ TOP VIEW 3.7X4.0X% 1.5mm Cd SIDE VIEW See Mech. Drawings Section BOTTOM VIEW See Mech. Drawings Section ORDERING INFORMATION DS2505 TO-92 Package DS2505P 6-pin TSOC Package DS2505T Tape & Reel version of DS2505 DS2505V Tape & Reel version of DS2505P SILICON LABEL DESCRIPTION The DS2505 16k bits AddOnly Memory identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. The DS2505 con- sists of a factorylasered registration number that Copyright 1995 by Dallas Semiconductor Corporation All Rights Reserved For important information regarding atents and other intellectual property rights please refer to allas Semiconductor data books 691597 1/23DS2505 includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (OBH) plus 16k bits of user programmable EPROM. The power to program and read the D$2505 is derived entirely from the 1-Wire communication line. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The entire device can be pro- grammed and then writeprotected if desired. Alterna- tively, the part may be programmed multiple times with new data being appended to, but not overwriting, exist- ing data with each subsequent programming of the device. Note: Individual bits can be changed only froma logical 1 to alogical 0, never from a logical 0 to a logical 1. A provision is also included for indicating that a cer- tain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. This page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. The 48-bit serial number that is factory lasered into each DS2505 provides a guaranteed unique identity which allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking, product revision status and access codes. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2505. The DS2505 has three main data compo- nents: 1) 64-bit lasered ROM, 2) 16384-bits EPROM Data Memory, and 3) 704-bits EPROM Status Memory. The device derives its power for read operations entirely from the 1-Wire communication line by storing energy onan internal capacitor during periods of time when the signal line is high and continues to operate off of this parasite power source during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply. During programming, 1Wire com- munication occurs at normal voltage levels and thenis pulsed momentarily to the programming voltage to cause the selected EPROM bits tobe programmed. The 1-Wire line must be able to provide 12 volts and 10 mil- liamperes to adequately program the EPROM portions of the part. Whenever programming voltages are pres- ent on the 1Wire line a special high voltage detect cir- cuit within the DS2505 generates aninternal logic signal to indicate this condition. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus mas- ter must first provide one of the four ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on the 64-bit lasered ROM portion of each device and can sin- gulate a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The proto- col required for these ROM Function Commands is described in Figure 8. Aftera ROM Function Command is successfully executed, the memory functions that operate on the EPROM portions of the DS2505 become accessible and the bus master may issue any one of the five Memory Function Commands specific to the DS2505 to read or program the various data fields. The protocol for these Memory Function Commands is described in Figure 5. All datais read and written least significant bit first. 64-BIT LASERED ROM Each D$2505 contains a unique ROM code thatis 64 bits long. The first eight bits are a 1Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3.) The 64-bit ROM and ROM Function Control section allow the DS2505 to operate as a 1Wire device and fol- low the 1Wire protocol detailed in the section 1-Wire Bus System. The memory functions required to read and program the EPROM sections of the D82505 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM func- tions flow chart (Figure 8). The 1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been suc- cessfully executed, the bus master may then provide any one of the memory function commands specific to the DS2505 (Figure 5). The 1-Wire CRC of the lasered ROMis generated using the polynomial X + X84 X44 1. Additional information about the Dallas Semiconductor 1Wire Cyclic Redun- dancy Check is available in the Book of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant bit of the family code, one bitatatimeis shifted in. After the eighth bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shiftingin the eight bits of CRC should return the shift register to all zeroes. 091597 2/23DS2505 DS2505 BLOCK DIAGRAM Figure 1 1-WIRE BUS aoe DATA Vv PARASITE POWER +o 1-WIRE FUNCTION CONTROL << 64-BIT LASERED ROM PROGRAM VOLTAGE DETECT MEMORY FUNCTION CONTROL 16-BIT CRC GENERATOR 16K BIT EPROM (64 PAGES OF 32 BYTES} 3-BIT SCRATCHPAD a 88 EPROM STATUS BYTES - ' 091597 3/23DS2505 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER 1-WIRE BUS y OTHER DEVICES DS2505 COMMAND 4 AVAILABLE DATA FIELD LEVEL: COMMANDS: AFFECTED: READ ROM 64-BIT ROM 1-WIRE ROM FUNCTION MATCH ROM 64-BIT ROM COMMANDS (SEE FIGURE 9} SEARCH ROM 64-BIT ROM SKIP ROM NWA A y WRITE MEMORY 16K BIT EPROM DS?505-SPECIFIC WRITE STATUS EPROM STATUS BYTES AE a MARS READ MEMORY 16K BIT EPROM (SEE FIGURE 6) READ STATUS EPROM STATUS BYTES EXTENDED READ DATA 16K BIT EPROM 64-BIT LASERED ROM Figure 3 8-Bit CRC Code 48-Bit Serial Number | 8Bit Family Code (OBH) MSB LSB MSB LSB MSB LSB 091597 4/23DS2505 16384-BITS EPROM The memory map in Figure 4 shows the 16384bit EPROM section of the D32505 which is configured as sixty-four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when pro- gramming the memory. Data is first written to the scratchpad and then verified by reading an 16-bit CRC from the DS2505 that confirms proper receipt of the data and address. If the buffer contents are correct, a pro- gramming voltage should be applied and the byte of data will be written into the selected address in memory. This process insures data integrity when programming the memory. The details for reading and programming the 16384bit EPROM portion of the DS2505 are given in the Memory Function Gommands section. EPROM STATUS BYTES In addition to the 16384 bits of data memory the DS2505 provides 704 bits of Status Memory accessible with separate commands. The EPROM Status Bytes can be read or programmed to indicate various conditions to the software interrogat- ing the DS2505. The first eight bytes of the EPROM Sta- tus Memory (addresses 000 to 007H) contain the Write Protect Page bits which inhibit programming of the cor- responding page in the 16384bit main memory area if the appropriate write protection bit is programmed. Once a bit has been programmed in the Write Protect Page section of the Status Memory, the entire 32 byte page that corresponds to that bit can no longer be altered but may still be read. The next eight bytes of the EPROM Status Memory (addresses 020 to 027H) contain the Write Protect bits which inhibit altering the Page Address Redirection Byte corresponding to each page in the 16384bit main memory area. The following eight bytes within the EPROM Status Memory (addresses 040 to 047H) are reserved for use by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in use. Originally, all of these bits are unprogrammed, indicat- ing that the device does not store any data. As soon as datais written to any page of the device under control of TMEX, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this page as used. These bits are application flags only and have no impact on the internal logic of the DS2505. The next sixtyfour bytes of the EPROM Status Memory {addresses 100H to 13FH) contain the Page Address Redirection Bytes which indicate if one or more of the pages of data in the 16384-bit EPROM section have beeninvalidated by software and redirected to the page address contained in the appropriate redirection byte. The hardware of the D$2505 makes no decisions based onthe contents of the Page Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an entire page to ancther page address, indicating that the data in the original page is no longer considered relevant or valid. With EPROM technology, bits within a page can be changed from a logical 1 toa logical 0 by programming, but cannot be changed back. Therefore, itis not possible to simply rewrite a page ifthe data requires changing or updating, but with space per- mitting, an entire page of data can be redirected to another page within the D82505 by writing the one's complement of the new page address into the Page Address Redirection Byte that corresponds to the origi- nal (replaced) page. This architecture allows the user's software to make a data patch to the EPROM by indicating thata particu- lar page or pages should be replaced with those indi- cated in the Page Address Redirection Bytes. To leave an authentic audit trail of data patches, it is recom- mended to also program the write protect bit of the Page Address Redirection Byte, after the page redirection is programmed. Without this protection, itis still possible to modify the Page Address Redirection Byte, making it point to a different memory page than the true one. Ifa Page Address Redirection Byte has a FFH value, the datain the main memory that corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the ones complement of the page address indicated by the hex value stored in the associated Page Address Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. The details for reading and programming the EPROM status memory portion of the DS2505 are givenin the Memory Function Gommands section. The Status Memory address range of the DS2505 extends from 000 to 13FH. The memory locations 008H to 01FH, 028H to O3FH, 048H to GFFH and 140H to 091597 5/23DS2505 7FFH are physically not implemented. Reading these locations will usually result in FFH bytes. Attempts to write to these locations will be ignored. If the bus master sends a starting address higher than 7FFH, the five most significant address bits are set to zeros by the DS2505 MEMORY MAP Figure 4 STARTI NG ADDRESS 0000 0020) 16K BIT. EPROM | 0040 Oo7EO internal circuitry of the chip. This will result in a mis- match between the CRC calculated by the DS2505 and ated by the bus master, indicating an the CRG calcul error condition. SCRATCHPAD S-BIT H 32-BYTE FINAL STORAGE EPROM H 32-BYTE FINAL STORAGE EPROM H H 32-BYTE FINAL STORAGE EPROM REDIRECTION BYTES BIT MAP OF USED PAGES WRITE-PROTECT BITS REDIRECTION BYTES WRITE-PROTECT BITS DATA MEMORY STATUS MEMORY MAP 11 PAGES OF 8 BYTES EAI CH i? 8BYTES ____ 00H WRITE-PROTECT BITS DATA MEMORY 007H RESERVED 008H O1FH 020H WRITE-PROTECT BITS OF REDIRECTION BYTES o27H RESERVED oz 03FH o40H BIT MAP OF USED PAGES 47H o48H RESERVED FOR FUTURE EXTENSIONS OFFH 100H * REDIRECTION : BYTES , 13FH PAGE 0 PAGE 1 PAGE 63 83 BYTES STATUS MEMORY BIT 0 OF ADDRESS QOOH=WRITE-PROTECT OF PAGE 0. ETC. ADDRESS 100H=PAGE ADDRESS REDIRECTION BYTE FOR PAGE 0, ETC. 091597 6/23DS2505 MEMORY FUNCTION COMMANDS The Memory Function Flow Chart (Figure 5) describes the protocols necessary for accessing the various data fields within the DS2505. The Memory Function Control section, 8-bit scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. A three-byte protocol is issued by the bus master. Itis comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. The command byte indicates if the device is to be read or written. Writing data involves not only issuing the correct command sequence but also providinga 12 volt programming voltage at the appropri- ate times. To execute a write sequence, a byte of datais first loaded into the scratchpad and then programmed into the selected address. Write sequences always occur a byte at a time. To execute a read sequence, the starting address is issued by the bus master and datais read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS2505 and received back by the bus master are sent least significant bit first. READ MEMORY [FOH] The Read Memory command is used to read data from the 16384bits EPROM data field. The bus master fol- lows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subse- quent read data time slot the bus master receives data from the DS2505 starting at the initial address and con- tinuing until the end of the 16384bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus mas- ter may issue sixteen additional read time slots and the DS2505 will respond with a 16-bit CRC of the com- mand, address bytes and all data bytes read from the initial starting byte through the last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to the last byte of the EPROM data memory. Atter the CRC is received by the bus master, any subsequentread time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to deter- mine if the received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recom- mended file structure to be used with the 1Wire envi- ronment.) lf CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command. READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subse- quent read data time slot the bus master receives data from the D$2505 starting at the supplied address and continuing until the end of an eight-byte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS2505 and read back by the bus master to check if the command word, starting address and data were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a 16-bit CRC thatis the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field. This feature is provided since the EPROM Status information may change over time making itimpossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Sta- tus command supplies a 16-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. 091597 7/23DS2505 MEMORY FUNCTION FLOW CHART Figure 5 MASTER Tx MEMORY FUNCTION COMMAND BUS MASTER Tx TAT (T7 TO} BUS MASTER Tx TA2 (T15 TB} : DS2505 SETS MEMORY ADDRESS = (T18 TO} = BUS MASTER Ry DATA FROM DATA MEMORY BUS MASTER Tx RESET DS2505 INCREMENTS ADDRESS COUNTER BUS MASTER Ty RESET BUS MASTER Ry GRG1E OF COMMAND ADDRESS DATA BUS MASTER Ty RESET BUS MASTER Ry 1S AAN READ STATUS BUS MASTER Tx TAI (T7 To} BUS MASTER Tx TA2 (T15 TB} ! DS2805 SETS STATUS ADDRESS = (715 To} - BUS MASTER Ry DATA FROM STATUS MEMORY BUS MASTER Ty RESET 052505 INCREMENTS ADDRESS COUNTER BUS MASTER Ry GRC16 OF COMMAND ADDRESS DATA (1ST PASS) CRC16 OF DATA (SUBSEQUENT PASSES) | BUS MASTER Ty RESET CRG GORREGCT 7 DS2505 T: PRESENCE pts E DS2608 CLEARS CRG GENERATOR BUS MASTER Ty RESET BUS MASTER Ry 1'5 091597 8/23DS2505 MEMORY FUNCTION FLOW CHART (cont'd) Figure 5 TO WRITE COMMANDS BUS MASTER Ty TAI (17 TO} BUS MASTER Tx TA2 (T15 T8} DS2s05 SETS MEMORY ADDRESS = (T1570) or BUS MASTER Ry REDIR BYTE LEGEND: BUS MASTER Ry CRO1E OF COMMAND ADDRESS REDIR BYTE (18ST PASS) GRO1E OF REDIR BYTE DECISION MADE (SUBSEQUENT PASSES} BY THEMASIER | BUS MASTER <> conser Ty RESET DECISION MADE BY DS2505 Bus. MASTER Rx DATA MEMORY BUS MASTER Ty RESET DS2605 INCREMENTS ADDRESS COLNTER END OF PAGE BUS MASTER Ry GRO1E OF PRECEDING PAGE OF DATA BUS MASTER Tx RESET Ds2505 INCREMENTS ADDRESS COUNTER BUS MASTER DS2505 Ty Ty RESET PRESENCE PULSE BUS MASTER Ry 1'S 091597 9/23DS2505 MEMORY FUNCTION FLOW CHART (cont'd) Figure 5 BUS MASTER Ty TAI (17 TO} BUS MASTER Tx TA2 (15 TB} ~ BUS MASTER Tx DATA BYTE (D7? Do} t BUS MASTER Ry CRC16 OF COMMAND ADDRESS DATA (187 PASS) CRC16 OF ADDRESS DATA {SUBSEQUENT PASSES} N CRG CORRECT BUS MASTER T PROGRAM PULSE y DS2506 COPIES SCRATCHPAD TO DATA EPROM Y BUS MASTER Rx BYTE FROM EPROM EPROM BYTE = DATA BYTE DS2505 INCREMENTS: ADDRESS COUNTER Ds2805 LOADS NEW MASTER Ty RESET ADDRESS INTO CRG GENERATOR Ld BUS MASTER Ty TAI (17 TO} Y BUS MASTER Ty Ta? (T15 Ta) + BUS MASTER Tx DATA BYTE (D7 Do} Y BUS MASTER Ry CRC16 OF COMMAND ADDRESS DATA (181 PASS} BUS MASTER Ty RESET CRGIE OF ADDRESS DATA (SUBSEQUENT PASSES} GRC CORRECT BUS MASTER Ty PROGRAM PULSE Y DS2505 COPIES SCRATCHPAD TO STATUS EPROM ' BUS MASTER Rx BYTE FROM EPROM EPROM BYTE = DATA BYTE END OF STATUS MEMORY DS2505 INCREMENTS ADDRESS COUNTER ! MASTER Ty RESET 0528085 LOADS NEW ADDRESS INTO CRC GENERATOR t Ld DS2506 PRES ENCE T p x ULSE 091597 10/23DS2505 After the 16-bit CRC of the last EPROM Status data pageis read, the bus master will receive logical 1s from the DS2505 until a Reset Pulseis issued. The Read Sta- tus command sequence can be ended at any point by issuing a Reset Pulse. EXTENDED READ MEMORY [ASH] The Extended Read Memory command supports page redirection when reading data from the 16384bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirec- tion Byte first before investing time in reading data from the addressed memory Iccation. This allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to termi- nate and restart the reading process at the redirected page address. A non-redirected page is identified bya Redirection Byte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is differ- ent than this, the master has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in the new address the master has to send to the DS2505 to read the updated data replacing the old data. There is nological limitation in the number of redirections of any page. The only limit is the number of available memory pages within the DS2505. In addition to page redirection, the Extended Read Memory command also supports bit-oriented applica- tions where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may change over time within a page bound- ary making it impossible to include an accompanying GRC that will always be valid. Therefore, the Extended Read Memory command concludes each page with the D82505 generating and supplying a 16-bit CRC that is based on and therefore always consistent with the cur- rent data stored in each page of the 16384-bit EPROM data field. After having sent the command code of the Extended Read Memory command, the bus master follows the command byte with a two byte address (TA1=(T7:TO), TA2=(T15:T8)) that indicates a starting byte location within the data field. By sending eight read data time slots, the master receives the Redirection Byte associated with the page given by the starting address. With the next sixteen read data time slots, the bus mas- ter receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the DS2505 and read back by the bus master to check if the command word, starting address and Redirection Byte were received correctly. lf the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is cor- rect, the bus master issues read time slots and receives data from the DS2505 starting at the initial address and continuing until the end of a32-byte page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. With the next 24 read data time slots the master will receive the Redirection Byte of the next page followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 16384bit EPROM data field starting at the beginning of the new page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page. The CRC received by the bus master directly following the Redirection Byte, is calculated in two different ways. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2505 until a Reset Pulse is issued. The Extended Read Memory command sequence can be exited at any point by issu- ing a Reset Pulse. 091597 11/23DS2505 WRITE MEMORY [OFH]/SPEED WRITE MEMORY [F3] The Write Memory command is used to program the 163284bit EPROM data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:TO), TA2=(T15:T8)) and a byte of data (D7:DO). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2505 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. The highest starting address within the DS2505 is O7FFH. If the bus master sends a starting address higher than this, the five most significant address bits are set to zero by the internal circuitry of the chip. This will resultina mismatch between the CRC calculated by the DS2505 and the CRC calculated by the bus master, indicating an error condition. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is cor- rect, a programming pulse (12 volts on the 1-Wire bus for 480 jus) is issued by the bus master. Prior to program- ming, the entire unprogrammed 16384bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to alog- ical 0, the corresponding bitin the selected byte of the 16384-bit EPROM will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 Ls programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2505 responds with the data from the selected EPROM address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS2505 EPROM data byte contains Os in the same bit positions as the data byte, the programming was successful and the DS2505 will automatically increment its address counter to select the next byte in the 16384bit EPROM data field. The new twobyte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC genera- tor that has been preloaded with the current address and the resultis a 16-bit GRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value thatis the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2505 automatically increment- ing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new (increm- ented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made entirely by the bus master, since the D82505 will not be able to determine if the 16-bit CRC calculated by the bus mas- ter agrees with the 16-bit CRC calculated by the DS2505. lf an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect program- ming could occur within the DS2505. Also note that the DS2505 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master contin- ues with the Write Memory command, incorrect pro- gramming could occur within the DS2505. The Write Memory command sequence can be ended at any point by issuing a Reset Pulse. To save time when writing more than one consecutive byte of the DS2505's data memory itis possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 pts for every byte to be programmed. This speedprogramming mode is accessed with the command code F3H instead of OFH. It follows basically the same flow chart as the 091597 12/23DS2505 Write Memory command, but skips sending the CRC immediately preceding the program pulse. This com- mand should only be used if the electrical contact between bus master and the DS2505 is firm since a peor contact may result in corrupted data inside the EPROM memcry. WRITE STATUS [55H]/SPEED WRITE STATUS [FS] The Write Status command is used to program the EPROM Status data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data (D7:DO). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2505 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. lf the CRC read by the bus masteris incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is cor- rect, a programming pulse (12 volts on the 1-Wire bus for 480 1s) is issued by the bus master. Prior to program- ming, the EPROM Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 ts programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2505 responds with the data from the selected EPROM Status address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained Os, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS2505 EPROM Status byte contains Os in the same bit posi- tions as the data byte, the programming was successful and the DS2505 will automatically incrementits address counter to select the next byte in the EPROM Status datafield. The new twobyte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC genera- tor that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to the DS2505 automatically incrementing its address counter will generate a 16-bit CRC thatis the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made entirely by the bus master, since the D$2505 will not be able to determine if the 16-bit CRC calculated by the bus mas- ter agrees with the 16-bit CRC calculated by the DS2505. lf anincorrect CRC is ignored and a program pulse is applied by the bus master, incorrect program- ming could occur within the DS2505. Also note that the DS2505 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master contin- ues with the Write Status command, incorrect program- ming could occur within the DS2505. The Write Status command sequence can be ended at any point by issu- ing a Reset Pulse. To save time when writing more than one consecutive byte of the DS2505's status memory itis possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 jis for every byte to be programmed. This speedprogramming 091597 13/23DS2505 mode is accessed with the command code FSH instead of 55H. It follows basically the same flow chart as the Write Status command, but skips sending the CRC immediately preceding the program pulse. This com- mand should only be used if the electrical contact between bus master and the DS2505 is firm since a poor contact may result in corrupted data inside the EPROM status memory. 1-WIRE BUS SYSTEM The 1Wire bus is a system which has a single bus mas- ter and oneormore slaves. Inallinstances, the DS2505 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken down into three topics: hardware configuration, transac- tion sequence, and 1Wire signalling (signal type and timing). A 1Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For amore detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. Hardware Configuration The 1Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3state outputs. The DS2505 is an open drain part with an internal circuit equivalent to that shown in Figure 6. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pull-up resistor atthe master end of the bus, with the bus master circuit equivalent to the one shown in Figures 7a and 7b. The value of the pull-up resistor should be approximately 5kQ for short line lengths. A multidrop bus consists of a 1Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. If the bus master is also required to perform programming of the EPROM por- tions of the DS2505, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 ps is required. The idle state for the 1Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 ws, one or more of the devices on the bus may be reset. Transaction Sequence The sequence for accessing the DS2505 via the 1-Wire port is as follows: Initialization @ ROM Function Command Memory Function Command *# Read/Write Memory/Status INITIALIZATION All transactions on the 1Wire bus begin with an initial- ization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2505 is on the bus andis ready to operate. For more details, see the 1Wire Signalling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 8): Read ROM [33H] This command allows the bus master to read the D82505's 8-bit family code, unique 48-bit serial num- ber, and 8-bit CRC. This command can be used only if there is a single DS2505 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). 091597 14/23DS2505 EQUIVALENT CIRCUIT Figure 6 DS2505 Rx DATA 5A Ty TYP. 1000 q MOSFET V GROUND BUS MASTER CIRCUIT Figure 7 A) OPEN DRAIN 124 Yoo Yop BUS MASTER 10kO DSS000 OR 8051 EQUIVALENT > VPo300L 10k0. s OR 5ko | VP0106N3 D OR OPEN DRAIN BSS110 PORT PIN B $s D t pe TODATA CONNECTION 2N7000 OF DS2505 T 470 pF PGM CAPACITOR ADDED TO REDUCE COUPLING ON DATA LINE DUE TO 4 2N7000 PROGRAMMING SIGNAL SWITCHING B) STANDARD TTL Voo BUS MASTER iy Yoo = 0mAmin.) TTL-EQUIVALENT| ska PORT PINS PROGRAMMING PULSE og | | w TO DATACONNECTION Bx ps OF DS2505 [5 5ko y 091597 15/23DS2505 ROM FUNCTIONS FLOW CHART Figure 8 MASTER Tx A RESET PULSE DS2505 Tx PRESENCE PULSE ' MASTER Tx ROM FUNCTION COMMAND 33h READ ROM COMMAND 55h MATCH ROM COMMAND FOr SEARCH ROM COMMAND cth SKIP ROM COMMAND DS2505 Ty BIT 0 8 ME MY MASTER Ty BIT 0 DS2505 Tx BIT O 1 BYTE MASTER Ty BIT O BIT oO N N BITO MATCH? MATCH? DS2505 Ty BIT 1 DS2505 Tx SERIAL NUMBER MASTER Tx BIT 1 DS2505 Tx BIT 1 6 BYTES MASTER T BIT 1 N N DS2505 Ty CRC BYTE Y x DS2505 Ty BIT 63 MASTER Tx BIT 63 DS?2505 Ty BIT 63 MASTER Ty BIT 63 N N BIT 63 BIT 63 MATCH? MATCH? s y MASTER Tx MEMORY FUNCTION COMMAND (SEE FIGURE 5} 091597 16/23DS2505 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2505 on a multidrop bus. Only the DS2505 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used witha single or multiple devices on the bus. Skip ROM [CCH] This command can save time ina single drop bus sys- tern by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wiredAND result). Search ROM [FOH] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM com- mand allows the bus master to use a process of elimina- tion to identify the 64bit ROM codes of all slave devices onthe bus. The ROM search process is the repetition of asimple 3-step routine: read abit, read the complement of the bit, then write the desired value of thatbit. The bus master perfonns this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master Knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Bock of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual exam- ple. 1-Wire Signalling The DS2505 requires strict protocols to insure data integrity. The protocol consists of five types of signalling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data and Pro- gram Pulse. All these signals except presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2505 is shown in Figure 9. A reset pulse followed by a pres- ence pulse indicates the DS2505 is ready to accept a ROM command. The bus master transmits (TX) a reset pulse (tas7_, minimum 480 ps). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resis- tor. After detecting the rising edge on the data pin, the DS2505 waits (tppy, 15-60 ws) and then transmits the presence pulse (tpp_, 60-240 us). Read/Write Time Slots Thedefinitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS52505 to the master by triggering a delay circuitin the D52505. During write time slots, the delay circuit determines when the DS2505 will sample the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the DS2505 will hold the data line low overriding the 1 gen- erated by the master. If the data bit is a 1, the device will leave the read data time slot unchanged. PROGRAM PULSE To copy data from the 8-bit scratchpad to the EPROM Data or Status Memory, a program pulse of 12 volts is applied to the data line after the bus master has con- firmed that the GRC for the current byteis correct. Dur- ing programming, the bus master controls the transition from a state where the data line is idling high via the pull-up resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 mA of current to the DS2505. This pro- gramming voltage (Figure 11) should be applied for 480 us, afterwhich the bus master returs the data line to an idle high state controlled by the pull-up resistor. Note that due to the high voltage programming requirements for any 1-Wire EPROM device, itis not possible to mul- ti-drop nonEPROM based 1Wire devices with the DS$2505 during programming. An internal diode within the nonEPROM based 1Wire devices will atternpt to clamp the data line at approximately 8 volts and could potentially damage these devices. 091597 17/23DS2505 INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES Figure 9 | MASTER Tx RESET PULSE I i ' MASTER Ry PRESENCE PULSE y A VeULLUP VPULLUP MIN ViH MIN VIL MAX ov TRSTL RESISTOR 480 Us <tasr, <co* MASTER 480 us < tasty < co (includes recovery time) svowwoev Ds2505 15 us < Ippy < 60 Us 60 us <tpp < 240 Us *In order not to mask interrupt signalling by other devices on the 1Wire bus, trsq_ + ta should always be less than 960 Ls. READ/WRITE TIMING DIAGRAM Figure 10 Writeone Time Slot TREC VPULLUP 2 VPULLUP MIN Vid MIN DS2505 VIL MAX SAMPLING WINDOW ov 60 Hs 60 us <tslo7 < 120 Us RESISTOR 1 Us <tlowi < 15 us MASTER Tus <thec < se seen DS2505. 091597 18/23DS2505 READ/WRITE TIMING DIAGRAM (cont'd) Figure 10 Writezero Time Slot VeuLLUP VPULLUP MIN Vi MIN VIL MAX ov DS2505 SAMPLING WINDOW tLlowo 60 Us =tlowo <= tsLor < 120 us 1 us < treo < co Read-Data Time Slot TREC ___- Is_oT lee tREC pe VeuLLUP ie PULLUP MIN \ f ws ui VIH MIN MASTER SAMPLING L Vit MAX WINDOW \ ov SU _ RELEASE tlowR fe j_Q taovw 60 us <ts_o7 < 120 Us RESISTOR 4 us <tlowa < 15s MASTER 0 <treLease < 45 us tus<t <0 ana DS2505 HS <IREC < <2 tapv = 15 us tsy <1 us PROGRAM PULSE TIMING DIAGRAM Figure 11 VPULLUP NORMAL 1Wire NORMAL 1Wire COMMUNICATION RESUMES COMMUNICATION ENDS = LINE TYPE LEGEND: _ep ap Bus master active high (12V @ 10 mA} Resistor pull-up 091597 19/23DS2505 CRC GENERATION With the DS2505 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is a 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compareit to the value stored within the DS2505 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRCis: X + X54X4441. This @-bit CRCis received in the true (non inverted) form when reading the ROM of the DS2505. It is computed once at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized GRC16polynomial function X18 4 x15 + X24 1. This CRC is used to safeguard user-defined EPROM data when reading data memory or status memory. It is the same type of CRC as is used with NV RAM based iButtons to safeguard data packets of the iButton File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returnedin the complemented (inverted) form. A GRCgenerator inside the DS2505 chip (Figure 12) will calculate a new 16-bit CRC atevery situation shown in the command flow chart of Figure 5. The DS2505 provides this CRCvalue to the bus mas- ter to validate the transfer of command, address, and data to and from the bus master. When reading the data memory of the DS2505 with the Read Memory com- mand, the 16-bit CRC is only transmitted as the end of the memoryis reached. This CRC is generated by clear- ing the GRC generator, shifting in the command, low address, high address and every data byte starting at the firstaddressed memory location and continuing until the end of the implemented data memory is reached. When reading the status memory with the Read Status command, the 16-bit CRC is transmitted when the end of each 8-byte page of the status memory is reached. At the initial pass through the Read Status flow chart the 16-bit CRC will be generated by clearing the CRC gen- erator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed EPROM Status data page is reached. Subsequent passes through the Read Status flow chart will generate a 16-bit CRC thatis the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field and continuing until the last byte of the page is reached. When reading the data memory of the DS2505 with the Extended Read Memory command, there are two situa- tions where a 16-bit CRC is transmitted. One 16-bit CRC follows each Redirection Byte, another 16-bit CRC is received after the last byte of a memory data page is read. The GRC at the end of the memory pageis always the result of clearing the CRC generator and shifting in the data bytes beginning atthe first addressed memory location of the EPROM data page until the last byte of this page. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will gen- erate a 16-bit CRC thatis the result of clearing the CRC generator and then shifting in the Redirection Byte only. When writing to the DS2505 (either data memory or sta- tus memory), the bus master receives a 16-bit CRC to verify the correctness of the data transfer before apply- ing the programming pulse. With theinitial pass through the Write Memory/Status flow chart the 16-bit CRC will be generated by clearing the CRCgenerator, shiftingin the command, address low, address high and the data byte. Subsequent passes through the Write Memory/ Status flow chart due to the DS2505 automatically incre- menting its address counter will generate an 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. The comparison of CRC values and decision to con- tinue with an operation are determined entirely by the bus master. Thereis nocircuitry on the DS2505 thatpre- vents a command sequence from proceeding if the CRC stored in or calculated by the DS2505 does not match the value generated by the bus master. For more details on generating CRC values including example imple- mentations in both hardware and software, see the Bock of DS19xx iButton Standards. 091597 20/23DS2505 CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 12 Polynomial = X19 4 X15 4.x? 41 1sT 2ND 3AD 4TH STH 6TH 7TH 8TH STAGE |""] STAGE ) >> STAGE [""] STAGE|*"| STAGE J) STAGE |*") STAGE |") STAGE xo x! xe x8 xt x6 x6 x? x8 9TH 10TH 11TH 12TH 13TH 14TH 15TH 16TH STAGE [) STAGE [") STAGE [") STAGE|| STAGE |*"| sTAGE/) STAGE Dr STAGE] xg x10 x1 yl2 X13 yi4 xis y16 CRC OUTPUT INPUT DATA 091597 21/23DS2505 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature 0.5V to 412.0V 40C to +85C 55C to 4125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is notimplied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (Vey p=2.8V to 6.0V; 40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Vin 2.2 Vv 1,6 Logic 0 Vit -0.3 +0.8 Vv 1,10 Output Logic Low @ 4 mA VoL 0.4 Vv 1 Output Logic High Vou Vpup 6.0 Vv 1,2 Input Load Current I 5 pA 3 Operating Charge Qop 30 nc 7,8 Programming Voltage @ 10 mA Vpp 11.5 12.0 Vv CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data (1Wire) CinvouTt 800 pF 9 AC ELECTRICAL CHARACTERISTICS (Vpyp=2.8V to 6.0V; 40C to +85C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Time Slot te_ot 60 120 ps Write 1 Low Time tLow1 1 15 us Write 0 Low Time tLowo 60 120 ps Read Data Valid trapy exactly 15 us Release Time tRELEASE 0 15 45 us Read Data Setup tsu 1 Us 5 Recovery Time tREc 1 ps Reset Time High trsTH 480 us 4 Reset Time Low tRstL 480 us Presence Detect High tppHIGH 15 60 ps Presence Detect Low tppLow 60 240 ps Delay to Program top 5 us Delay to Verify toy 5 us Program Pulse Width tpp 480 ps Program Voltage Rise Time trp 0.5 5.0 us Program Voltage Fall Time trp 0.5 5.0 us 091597 22/23DS2505 NOTES: 1. 2. o oN 10. All voltages are referenced to ground. Vpyp = external pull-up voltage. If Vpyp is lower than 3.0V the first byte read (any read command) may not repro- duce the correct memory contents. Therefore, under low voltage conditions, itis recommended to set either the most significant bit or all five most significant bits of TA2 to 1. Internal circuitry of the chip will force these five bits back to zero before they are shifted in the address counter and CRC generator. Input load is to ground. An additional reset or communication sequence cannot begin until the reset high time has expired. Read data setup time refers to the time the host must pull the 1-Wire bus low to read abit. Data is guaranteed to be valid within 1 1s of this falling edge and will remain valid for 14 ws minimum. (15 ps total from falling edge on 1Wire bus.) Vin is a function of the external pull-up resistor and Vpyp. 30 nanocoulombs per 72 time slots @ 5.0V. At Vec=5.0V with a 5k pullup to Vee and a maximum time slot of 120 us. Capacitance on the data pin could be 800 pF when poweris first applied. If a 5k resistor is used to pull up the data line to Veg, 5 ws after power has been applied the parasite capacitance will not affect normal communica- tions. Under certain low voltage conditions Vijay may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 091597 23/23