CPC7584 Line Card Access Switch Features sary functions to replace two 2-Form-C electromechanical relays on analog line cards found in Central Office, Access, and PBX equipment. The device contains solid state switches for tip and ring line break, ring injection/ring return and test access. The CPC7584 requires only a +5V supply and offers "break-before-make" or "make-before-break" switch operation using simple logic-level input control. ar The CPC7584xC differs from the CPC7584xA/B with the addition of a logic state. See "Functional Description" on page 10 for more information. The CPC7584xC also has a higher hold current for the protection SCR. in Applications Ordering Information Part Number el im Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Description CPC7584BA CPC7584BB CPC7584BC CPC7584MA CPC7584MB CPC7584MC Pr * * * * * * * * y * Small 16-pin surface-mount SOIC package and very small micro-leadframe package (MLP) available * Monolithic IC reliability * Low matched RDSON * Eliminates the need for zero cross switching * Flexible switch timing to transition from ringing mode to idle/talk mode. * Clean, bounce free switching * Tertiary protection consisting of integrated current limiting, thermal shutdown, and SLIC protection * 5 V operation with power consumption less than 10 mW * Intelligent battery monitor * Latched logic level inputs, no drive circuitry CPC7584xx-TR The CPC7584 is a monolithic solid state switch in a 16-pin surface-mount package. It provides the neces- Description SOIC 6-pole LCAS with protection SCR SOIC 6-pole LCAS without protection SCR SOIC 6-pole LCAS with protection SCR and added logic state MLP 6-pole LCAS with protection SCR MLP 6-pole LCAS without protection SCR MLP 6-pole LCAS with protection SCR and added logic state Add -TR to the part number when ordering tape and reel packaging Figure 1. CPC7584 Block Diagram TRING (4) TIP TLINE R1 TTEST-IN (5) SW3 Ringing Return (3) SW5 Test-In TBAT(2) SW1 Break Secondary Protection Ring VBAT Reference (16) SCR and Trip Circuit SLIC R2 RLINE (14) SW4 Ringing Access SW2 Break SW6 Test-In CPC7584 RBAT (15) Ring Generator RRING (13) DS-CPC7584-R0.A www.clare.com + RTest-In (12) Battery 1 CPC7584 2 2 2 2 2 3 4 4 5 6 6 6 7 7 7 ar y 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Ring Return Switch, SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Ringing Access Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Test-In Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 CPC7584xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 CPC7584xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 el im in 3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pr 4 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 www.clare.com 12 12 12 12 13 13 13 13 13 13 13 14 14 R0.A CPC7584 1. Specifications 1.1 Absolute Maximum Ratings (at 25 C) Parameter Minimum Maximum Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. Unit Operating temperature -40 +110 C Storage temperature -40 +150 C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +260 C +5 V power supply - 7 V Battery Supply - -85 V Logic input voltage - 7 V VDD +4.5 +5.0 +5.5 V Logic input to switch output isolation - 330 V VBAT1 -19 - -72 V Switch isolation (SW1, SW2, SW3, SW5, SW6) - 330 V Switch Isolation (SW4) - 480 V Minimum Typical Maximum ar Supply y 1.2.1 Power Supply Specifications Unit im in 1V BAT is used only as a reference for internal protection circuitry. If VBAT rises above -10 V, the device will enter the all-off state and will remain in the all-off state until the battery drops below -15 V. ESD Rating (Human Body Model) 1.2 Electrical Characteristics, TA = -40 C to +85 C Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. Pr el 1000 V 1.2.2 Break Switches, SW1 and SW2 Parameter Conditions Symbol Minimum Typical Maximum Unit Off-state leakage current +25 C VSW (differential) = -320 V to GND VSW (differential) = -60 V to +260 V ISW - 0.1 1 A +85 C VSW (differential) = -330 V to GND VSW (differential) = -60 V to +270 V ISW - 0.3 1 A -40 C VSW (differential) = -310 V to GND VSW (differential) = -60 V to +250 V ISW - 0.1 1 A +25 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 14.5 - +85 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 20.5 28 -40 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 10.5 - RDSON match Per on-resistance test condition of SW1, SW2RON SW1-RONSW2 Magnitude - 0.15 0.8 RDSON DC current limit +25 C VSW (on) = 10 V ISW - 300 - mA +85 C VSW (on) = 10 V ISW 80 160 - mA -40 C VSW (on) = 10 V ISW - 400 425 mA Rev. 0.A www.clare.com 2 CPC7584 Parameter Conditions Dynamic current limit (t = <0.5 s) Symbol Minimum Typical Maximum Unit ISW - 2.5 - A Break switches in on state, ringing access switches off, apply 1 kV at 10/1000 ms pulse, with appropriate secondary protection in place. Logic input to switch output isolation VSW (TLINE, RLINE) = 320 V, logic inputs = gnd ISW - 0.1 1 A +85 C VSW (TLINE, RLINE) = 330 V, logic inputs = gnd ISW - 0.3 1 A -40 C VSW (TLINE, RLINE) = 310 V, logic inputs = gnd ISW - 1 A dv/dt sensitivity Applied voltage = 100 V p-p square wave at 100 Hz - ar 200 - V/s Minimum Typical Maximum Unit ISW - 0.1 1 A in Conditions Symbol VSW (differential) = -320 V to GND VSW (differential) = -60 V to +260 V +85 C VSW (differential) = -330 V to GND VSW (differential) = -60 V to +270 V ISW - 0.3 1 A -40 C VSW (differential) = -310 V to GND VSW (differential) = -60 V to +250 V ISW - 0.1 1 A ISW (on) = 0 mA, 10 mA V - 60 - ISW (on) = 0 mA, 10 mA V - 85 100 ISW (on) = 0 mA, 10 mA V - 45 - +25 C VSW (on) = 10 V ISW - 135 - mA +85 C VSW (on) = 10 V ISW - 85 - mA -40 C VSW (on) = 10 V ISW - 210 - mA Dynamic current limit (t = <0.5 s) Break switches in on state, ringing access switches off, apply 1 kV at 10/1000 ms pulse, with appropriate secondary protection in place. ISW - 2.5 - A el im +25 C Pr Off-state leakage current 0.1 - 1.2.3 Ring Return Switch, SW3 Parameter y +25 C RDSON +25 C +85 C -40 C DC current limit Logic input to switch output isolation +25 C VSW (TRING, TLINE) = 320 V, logic inputs = gnd ISW - 0.1 1 A +85 C VSW (TRING, TLINE) = 330 V, logic inputs = gnd ISW - 0.3 1 A -40 C VSW (TRING, TLINE) = 310 V, logic inputs = gnd ISW - 0.1 1 A 3 www.clare.com Rev. 0.A CPC7584 1.2.4 Ringing Access Switch, SW4 Parameter Conditions Symbol Minimum Typical Maximum Unit Off-state leakage current VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V ISW - 0.05 1 A +85 C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V ISW - 0.1 1 A -40 C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V ISW - 0.05 1 A On Voltage ISW (on) = 1 mA - - 1.5 3 V Ring generator current during ring VCC = 5 V, INaccess = 0 IR - 0.1 0.25 mA Surge current - - - - 2 A Release current - - - 300 - A RDSON ISW (on) = 70 mA, 80 mA - 8.5 12 ISW - 0.05 1 A Logic input to switch output isolation ar in V y +25 C VSW (RRING, RLINE) = 320 V, logic inputs = gnd +85 C VSW (RRING, RLINE) = 330 V, logic inputs = gnd ISW - 0.1 1 A -40 C VSW (RRING, RLINE) = 310 V, logic inputs = gnd ISW - 0.05 1 A Symbol Minimum Typical Maximum Unit VSW (differential) = -320 V to GND VSW (differential) = -60 V to +260 V ISW - 0.1 1 A +85 C VSW (differential) = -330 V to GND VSW (differential) = -60 V to +270 V ISW - 0.3 1 A -40 C VSW (differential) = -310 V to GND VSW (differential) = -60 V to +250 V ISW - 0.1 1 A +25 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 38 - +85 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 46 70 -40 C TLINE = 10 mA, 40 mA, TBAT = -2 V V - 28 - +25 C VSW (on) = 10 V ISW - 175 - mA +85 C VSW (on) = 10 V ISW 80 110 - mA -40 C VSW (on) = 10 V ISW - 210 250 mA Dynamic current limit (t = <0.5 s) Break switches in on state, ringing access switches off, apply 1 kV at 10/1000 ms pulse, with appropriate secondary protection in place. ISW - 2.5 - A el im +25 C 1.2.5 Test-In Switches, SW5 and SW6 Conditions Pr Parameter Off-state leakage current +25 C RDSON DC current limit Rev. 0.A www.clare.com 4 CPC7584 Parameter Conditions Symbol Minimum Typical Maximum Unit Logic input to switch output isolation VSW (TACCESS, TLINE) = 320 V, logic inputs = gnd ISW - 0.1 1 A +85 C VSW (TACCESS, TLINE) = 330 V, logic inputs = gnd ISW - 0.3 1 A -40 C VSW (TACCESS, TLINE) = 310 V, logic inputs = gnd ISW - 0.1 1 A Symbol Minimum Typical Maximum Unit - - 1.5 3.5 - - Ilog - 0.1 1 Ilog - 0.1 1 IDD, IBAT - 5.5 10 y +25 C Parameter Conditions Digital input characteristics - - Input high voltage - - Input leakage current (high) VDD = 5.5 V, VBAT = -75 V, Vlog = 5 V Input leakage current (low) VDD = 5.5 V, VBAT = -75 V, Vlog = 0 V im in Input low voltage VDD = 5 V, VBAT = -48 V Power dissipation in ringing and access states VSW (on) = 10 V IDD IDD el Power dissipation in idle/talk and all-off states Pr Power requirements VDD current in idle/talk and all off states VDD current in ringing and access states VBAT current in idle/talk and all off states VBAT current in ringing and access states ar 1.3 Additional Electrical Characteristics V A mW - 6.5 10 1.1 2.0 VDD = 5 V mA IDD - 1.3 2.0 IBAT - 0.1 10 IBAT - 0.1 10 A VBAT = -48 V Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature - - 110 125 150 C Shutdown circuit hysteresis - 10 - 25 C 5 www.clare.com Rev. 0.A CPC7584 1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) Break Ring Switches Return 1 and 2 Switch 3 Line Ring Access Access Switches Switch 4 5 and 6 Test-In Input TSD State Timing 0V 5V Floating Ringing - Open Closed Closed Open Closed Open Closed Open Closed Open Open 0V Floating Makebeforebreak 0V 0V Floating Idle/Talk Zero-cross current has occurred Input TSD State 0V 5V Floating Ringing 5V 5V Floating 5V 5V Floating 0V 0V Floating All-off ar Open Break Ring Switches Return 1 and 2 Switch 3 Line Ring Access Access Switches Switch 4 5 and 6 - Open Closed Closed Open Hold this state for at least 25 ms. SW4 waiting for zero current to turn off. Open Open Closed Open SW4 has opened. Open Open Open Open Release Break Switches Closed Open Open Open el Idle/Talk Timing im Test-In in 1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) y 0V SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of ringing. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Pr 1.4 Alternate Break-Before-Make Operation Break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of "BreakBefore-Make Operation (Ringing to Idle/Talk Transition)" on page 6, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for 25 ms. During this 25 ms all-off state, toggle the inputs from the ringing state (Ring = 5 V, Test-In = 0 V) to the idle/talk state (Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to return switch control to the input pins which will set the idle talk state. When using the CPC7584 in this mode, forcing TSD to ground overrides the input pins and force an all off state. Setting TSD to +5 V allows switch control via the logic input pins. However, setting TSD to +5 V also disables the thermal shutdown mechanism. This is not recommended. Therefore, to allow switch control via the logic input pins, allow TSD to float. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This may require use of an open-collector buffer. Rev. 0.A www.clare.com 6 CPC7584 1.5 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum Unit Voltage drop at continu- Apply dc current limit of break ous current (50/60 Hz) switches Forward Voltage - 2.1 3 Voltage drop at surge current Forward Voltage - 5 - - - - * A Trigger current (+25 C) - ITRIG - 60 - mA Hold current (+25 C) - IHOLD - 100 - mA Trigger current (+85 C) - ITRIG - 35 - mA Hold current (+85 C) - IHOLD 60 70 - mA Gate trigger voltage Trigger current VBAT -4 - VBAT -2 V Reverse leakage current VBAT Parameters Related to the Diodes in the Diode Bridge Apply dynamic current limit of break switches V - 2.0 A, t = 0.5 ms - - - 1.0 A VON - -3 - V - - -5 - V im 0.5 A, t = 0.5 ms On-state voltage ar - in Surge current y Parameters Related to the Protection SCR *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. Ring Test-In TSD1 Pr State el 1.6 CPC7584xA/B Truth Table Tip Break Switch Ring Break Switch Ringing Return Switch Ring Switch Tip Test-In Switch Ring TestIn Switch On On Off Off Off Off Off Off On On Off Off Idle/Talk 0V 0V Power Ringing 5V 0V Test-In 0V 5V Off Off Off Off On On All Off 5V 5V Off Off Off Off Off Off All off Don't care Don't care Off Off Off Off Off Off 5 V/Floating 0V 1If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled. 1.7 CPC7584xC Truth Table State Tip Break Switch Ring Break Switch Ringing Return Switch Ring Switch Tip Test-In Switch Ring TestIn Switch On On Off Off Off Off Off Off On On Off Off 5V On On Off Off On On 5V 5V Off Off Off Off Off Off Don't care Don't care Off Off Off Off Off Off Ring Test-In Idle/Talk 0V 0V Power Ringing 5V 0V Test Monitor 0V All Off All off 1 TSD 5 V/Floating 0V 1 If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled. 7 www.clare.com Rev. 0.A CPC7584 2. Package Pinout 2.1 Pinout Pin 1 TTEST-IN RTEST-IN 16 1 Name TTEST-IN Tip lead test input 2 FGND VBAT 15 2 FGND Fault ground 3 TBAT RBAT 14 3 TBAT Connect to tip lead on SLIC side 4 TLINE RLINE 13 4 TLINE Connect to tip lead on the line side 5 TRING RRING 12 5 TRING Connect to ring generator return 6 VDD LATCH 11 6 VDD 7 TSD INRING 10 TSD Temperature shutdown pin. Can be used as a logic-level input or output. See "MakeBefore-Break Operation (Ringing to Idle/ Talk Transition)" on page 6, "BreakBefore-Make Operation (Ringing to Idle/ Talk Transition)" on page 6, and "CPC7584xA/B Truth Table" on page 7 for details. As an output, TSD will read +5 V when the device is in the operational mode and 0 V in the thermal shutdown mode. To disable thermal shutdown, tie this pin to +5 V (not recommended) DGND Digital ground y INTEST-IN +5 V supply 9 ar 8 DGND Pr el im in 7 8 9 INTEST-IN Logic-level switch control input 10 INRING Logic-level switch control input 11 LATCH Data latch control, active high, transparent low 12 RACCESS Test access 13 RRING Connect to ring generator 14 RLINE Connect to ring lead on the line side 15 RBAT Connect to ring lead on the SLIC side 16 Rev. 0.A Description www.clare.com VTEST-IN Test-in access on ring 8 CPC7584 3. Functional Description y The CPC7584 operates from a +5 V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CPC7584 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7584 enters the all-off state. in * Idle/Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 open. * Ringing. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 closed, and test-in switches SW5 and SW6 open. * Test-In. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed. * All off. Line break switches SW1 and SW2 open, ringing switches SW3 and SW4 open, and loop test switches SW5 and SW6 open. mum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582BC will meet all relevant ITU, LSSGR, FCC and UL protection requirements. ar 3.1 Introduction The CPC7584xA/B has four states: im In the CPC7584xC, the test-in state is replaced with the test monitor state, defined as: line break switches SW1 and SW2 closed, Ringing switches SW3 and SW4 open, and test-in switches SW5 and SW6 closed. Pr el The CPC7584 offers break-before-make and makebefore-break switching with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDSON and excellent matching characteristics. The ringing access switch SW4 has a breakdown voltage rating of greater than 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ring generator). Integrated into the CPC7584 is a diode bridge/SCR clamping circuit, current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes and the integrated SCR. Power-cross transients are also reduced by the current limiting and thermal shutdown circuits. Note that only the CPC7584xA and CPC7584xC parts include the integrated protection SCR. To protect the CPC7584 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the maxi9 3.2 Switch Timing The CPC7584 provides, when switching from the ringing state to the idle/talk state, the ability to control the release timing of the ringing access switches SW3 and SW4 relative to the state of the line break switches SW1 and SW2 using simple logic-level input. This is referred to a make-before-break or breakbefore-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing access switch contacts (SW3 and SW4) are opened (or broken), this is referred to makebefore-break operation. Break-before-make operation occurs when the ringing access contacts (SW3 and SW4) are opened (broken) before the line break switch contacts (SW1 and SW2) are closed (made). With the CPC7584, the make-before-break and breakbefore-make operations can easily be selected by applying logic-level inputs to pins 9 and 10 (INRING and INTEST-IN) of the device. The logic sequences for either mode of operation are given in "Make-Before-Break Operation (Ringing to Idle/Talk Transition)" on page 6 and "Break-BeforeMake Operation (Ringing to Idle/Talk Transition)" on page 6. Logic states and explanations are given in "CPC7584xA/B Truth Table" on page 7. Break-before-make operation can also be achieved using pin 7 (TSD) as an input. In "Break-Before-Make Operation (Ringing to Idle/Talk Transition)" on page 6 lines 2 and 3, it is possible to induce the switches to the all-off state by grounding pin 7 (TSD) instead of apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the all-off state. Hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state www.clare.com Rev. 0.A CPC7584 3.6.1 Diode Bridge/SCR The CPC7584 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground. Voltage is clamped to the diode drop above ground. During a negative transient of 2 to 4 V more negative than the battery, the SCR conducts and faults are shunted to ground via the SCR and diode bridge. Pr el im in 3.3 Ring Access Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. For proper operation, pin 12 (RRING) should be connected using proper impedance to a ring generator or other AC source. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 in series with the ring generator is recommended. 3.6 Protection y Setting TSD to +5 V allows switch control using the logic pins 9 and 10. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins 9 and 10, pin 7 (TSD) should be allowed to float. As a result, the two recommended states when using pin 7 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to pins 9 and 10 to remain active. This may require the use of an open-collector buffer. restored. The device also enters the all-off state if the battery voltage rises above -10 V and remains in the all-off state until the battery voltage drops below -15 V. This battery monitor feature draws a small current from the battery (less than 1 mA typical) and will add slightly to the device's overall power dissipation. ar (10) to the idle/talk state (00). After the 25 ms, release pin 7 (TSD) to return the switch control to the input pins 9 and 10 and reset the device to the idle/talk state. 3.4 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7584. CPC7584 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7584 exhibits extremely low power dissipation during both active and idle states. In order for the SCR to crowbar or foldback, the on voltage (see "Protection Circuitry Electrical Specifications" on page 7) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative the SCR on voltage, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. 3.6.2 Current Limiting function The battery voltage is not used for switch control but rather as a reference for the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 3 (TBAT) or pin 14 (RBAT) drops 2 to 4 V below the battery. This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10/1000 pulse (LSSGR lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 ms. 3.5 Battery Voltage Monitor The CPC7584 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7582BC immediately enters the all-off state. It remains in this state until the battery voltage is If a power-cross fault occurs with the device in the talk/ idle state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA Rev. 0.A www.clare.com 10 CPC7584 Pr el im in If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the all-off state. At this point the current measured at pin 3 (TBAT) and pin 14 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. 3.9 Data Latch The CPC7584 has an integrated data latch. The latch operation is controlled by logic-level input pin 11 (LATCH). The data input of the latch is pin 10 (INRING) and pin 9 (INTEST-IN) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control via pin 10 (INRING) and pin 9 (INTEST-IN) and the LATCH. y 3.7 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 7 (TSD) will read 0 V. Normal output of TSD is +VDD. to the specifications of external secondary protectors, fused resistors and PTCs. ar and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 2 (TBAT) and pin 15 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the all-off state. The thermal shutdown mechanism of the CPC7584 can be disable by applying +VDD to pin 7 (TSD). 3.8 External Protection Elements The CPC7584 requires only one overvoltage secondary protector on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7584. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related 11 www.clare.com Rev. 0.A CPC7584 4. Manufacturing Information 4.1 Mechanical Dimensions 4.1.1 SOIC 16 Pin SOIC (JEDEC Package) 10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX) 1.27 (.050) 0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) ar 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX) y 2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) in 0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX) 4.1.2 MLP im 7 el INDEX AREA 6 Pr TOP VIEW 0.2 0.80 (0.10) SEATING PLANE SIDE VIEW 0.23 0.55 0.02 (+0.05, -0) 1 0.33 (+0.07, -0.05) 2 EXPOSED PAD 0.55 4.0 (0.05) 0.55 (0.1) 16 6.0 (0.05) 0.80 Terminal Tip BOTTOM VIEW Dimensions in mm Rev. 0.A www.clare.com 12 CPC7584 4.2 Printed-Circuit Board Layout 4.2.2 MLP 5.75 4.2.1 SOIC 0.75 on center 0.65 PC Board Pattern (Top View) 0.38 1.270 (.050) 5.35 on center 6.1 Detail A 9.728 .051 (.383 .002) y 1.193 (.047) 6.13 Detail A ar .787 (.031) 0.66 All dimensions in mm Not drawn to scale 0.47 0.65 in 0.38 im 4.3 Tape and Reel Packaging 4.3.1 SOIC A0 3.00 el 6.50 2.00 B0 6.80 1.30 Pr R = .50 K1 16.00 K0 2.30 2.70 7.50 12.00 4.00 2.00 1.50 A0 = 6.5 mm B0 = 10.3 mm 2.3 mm 2.7 mm K0 = K1 = NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. 4.4 Soldering 4.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, 13 in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may www.clare.com Rev. 0.A lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-020A per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 2 for the MLP package. 4.4.2 Reflow Profile ar y The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC/JEDEC standard J-STD-020A, which were used to determine the moisture sensitivity level of this component. Pr el im in 4.5 Washing Clare does not recommend ultrasonic cleaning of LCAS parts. For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7584-R0.A (c) Copyright 2002, Clare, Inc. All rights reserved. Printed in USA. 5/6/2002