SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
FEATURES
DSimultaneous Sampling of Two Single-Ended
Signals or One Differential Signal
DIntegrated 16-Word FIFO
DSignal-to-Noise and Distortion Ratio: 59 dB at
fI = 2 MHz
DDifferential Nonlinearity Error: ±1 LSB
DIntegral Nonlinearity Error: ±1 LSB
DAuto-Scan Mode for Two Inputs
D3-V or 5-V Digital Interface Compatible
DLow Power: 216 mW Max
D5-V Analog Single Supply Operation
DInternal Voltage References ...50 PPM/°C
and ±5% Accuracy
DParallel µC/DSP Interface
APPLICATIONS
DRadar Applications
DCommunications
DControl Applications
DHigh-Speed DSP Front-End
DAutomotive Applications
DESCRIPTION
The THS10082 is a CMOS, low-power, 10-bit, 8 MSPS
analog-to-digital converter (ADC). The speed, resolution,
bandwidth, and single-supply operation are suited for
applications in radar, imaging, high-speed acquisition, and
communications. A multistage pipelined architecture with
output error correction logic provides for no missing codes
over the full operating temperature range. Internal control
registers allow for programming the ADC into the desired
mode. The THS10082 consists of two analog inputs,
which are sampled simultaneously. These inputs can be
selected individually and configured to single-ended or
differential inputs. An integrated 16 word deep FIFO
allows the storage of data in order to take the load off
of the processor connected to the ADC. Internal
reference voltages for the ADC (1.5 V and 3.5 V) are
provided.
An external reference can also be chosen to suit the dc
accuracy and temperature drift requirements of the
application. Two different conversion modes can be
selected. In the single conversion mode, a single and
simultaneous conversion can be initiated by using the
single conversion start signal (CONVST). The conversion
clock in the single conversion mode is generated internally
using a clock oscillator circuit. In the continuous
conversion mode, an external clock signal is applied to the
CONV_CLK input of the THS10082. The internal clock
oscillator is switched off in the continuous conversion
mode.
The THS10082C is characterized for operation from 0°C
to 70°C, and the THS10082I is characterized for operation
from −40°C to 85°C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
RA0
RA1
CONV_CLK (CONVST)
DATA_AV
OV_FL
RESET
AINP
AINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W
)
RD
DVDD
DGND
DA PACKAGE
(TOP VIEW)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2002, Texas Instruments Incorporated
SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
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2
ORDERING INFORMATION
PACKAGED DEVICE
TATSSOP
(DA)
0°C to 70°C THS10082CDA
−40°C to 85°C THS10082IDA
These devices have limited built-in ESD protection. The
leads should be shorted together or the device placed in
conductive foam during storage or handling to prevent
electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
THS10082
DGND to DVDD −0.3 V to 6.5 V
Supply voltage range BGND to BVDD −0.3 V to 6.5 V
Supply voltage range
AGND to AVDD −0.3 V to 6.5 V
Analog input voltage range AGND −0.3 V to AVDD + 1.5 V
Reference input voltage −0.3 V + AGND to AVDD + 0.3 V
Digital input voltage range −0.3 V to BVDD/DVDD + 0.3 V
Operating virtual junction temperature range, TJ−40°C to 150°C
Operating free-air temperature range, TA
THS10082C 0°C to 70°C
Operating free-air temperature range, T
ATHS10082I −40°C to 85°C
Storage temperature range, Tstg −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY MIN NOM MAX UNIT
AVDD 4.75 5 5.25
Supply voltage DVDD 3 3.3 5.25 V
Supply voltage
BVDD 3 3.3 5.25
V
ANALOG AND REFERENCE INPUTS MIN NOM MAX UNIT
Analog input voltage in single-ended configuration VREFM VREFP V
Common-mode input voltage VCM in differential configuration 1 2.5 4 V
External reference voltage,VREFP (optional) 3.5 AVDD−1.2 V
External reference voltage, VREFM (optional) 1.4 1.5 V
Input voltage difference, REFP − REFM 2 V
DIGITAL INPUTS MIN NOM MAX UNIT
High-level input voltage, VIH
BVDD = 3 V 2 V
High-level input voltage, V
IH BVDD = 5.25 V 2.6 V
Low-level input voltage, VIL
BVDD = 3 V 0.6 V
Low-level input voltage, V
IL BVDD = 5.25 V 0.6 V
Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 8 MHz
CONV_CLK pulse duration, clock high, tw(CONV_CLKH) DVDD = 3 V to 5.25 V 62 83 5000 ns
CONV_CLK pulse duration, clock low, tw(CONV_CLKL) DVDD = 3 V to 5.25 V 62 83 5000 ns
Operating free-air temperature, TA
THS10082CDA 0 70
°C
Operating free-air temperature, T
ATHS10082IDA −40 85 °
C
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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3
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, DVDD = 3.3 V, AVDD = 5 V, VREF = internal (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Digital inputs
IIH High-level input current DVDD = digital inputs −50 50 µA
IIL Low-level input current Digital input = 0 V −50 50 µA
CiInput capacitance 5 pF
Digital outputs
VOH High-level output voltage IOH = −50 µA, BVDD = 3.3 V, 5 V BVDD−0.5 V
VOL Low-level output voltage IOL = −50 µA, BVDD = 3.3 V, 5 V 0.4 V
IOZ High-impedance-state output current CS1 = DGND, CS0 = DVDD −10 10 µA
COOutput capacitance 5 pF
CLLoad capacitance at databus D0 −D9 30 pF
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, A VDD = 5 V, DVDD = BVDD = 3.3 V, fs = 8 MSPS, VREF = internal (unless otherwise noted)
DC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 Bits
Accuracy
Integral nonlinearity, INL ±1 LSB
Differential nonlinearity, DNL ±1 LSB
Offset error
After calibration in single-ended mode ±5 LSB
Offset error
After calibration in differential mode −10 10 LSB
Gain error −10 10 LSB
Analog input
Input capacitance 15 pF
Input leakage current VAIN = VREFM to VREFP ±10 µA
Internal voltage reference
VREFP Accuracy 3.3 3.5 3.7 V
VREFM Accuracy 1.4 1.5 1.6 V
Temperature coefficient 50 PPM/°C
Reference noise 100 µV
Accuracy, REFOUT 2.475 2.5 2.525 V
Power supply
IDDA Analog supply current AVDD = 5 V, BVDD = DVDD = 3.3 V 36 40 mA
IDDD Digital supply current AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA
IDDB Buffer supply current AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA
IDD_AP Analog supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 8 mA
PDPower dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW
Power dissipation in powerdown AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MHz, fI = 2 MHz at −1 dB (unless otherwise noted)
AC SPECIFICATIONS, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SINAD
Signal-to-noise ratio + distortion
Differential mode 56 59 dB
SINAD
Signal-to-noise ratio + distortion
Single-ended mode(1) 55 58 dB
SNR
Signal-to-noise ratio
Differential mode 59 61 dB
SNR
Signal-to-noise ratio
Single-ended mode(1) 60 dB
THD
Total harmonic distortion
Differential mode −67 −61 dB
THD
Total harmonic distortion
Single-ended mode −63 dB
ENOB
Effective number of bits
Differential mode 9 9.5 Bits
ENOB
Effective number of bits
Single-ended mode(1) 9.35 Bits
SFDR
Spurious free dynamic range
Differential mode 61 65 dB
SFDR
Spurious free dynamic range
Single-ended mode 64 dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
dif ferential configuration. Full-scale sinewave, −3 dB 96 MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration. Full-scale sinewave, −3 dB 54 MHz
Small-signal bandwidth with a source impedance of 150 Ω in
dif ferential configuration. 100-mVpp sinewave, −3 dB 96 MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration. 100-mVpp sinewave, −3 dB 54 MHz
(1) The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the sampling
clock.
TIMING REQUIREMENTS(1)
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(DATA_AV) Delay time 5 ns
td(o) Delay time 5 ns
tpipe Latency 5 CONV
CLK
(1) See Figure 27.
TIMING SPECIFICATION OF THE SINGLE CONVERSION MODE(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tcClock cycle of the internal clock oscillator 117 125 133 ns
tw1
Pulse duration, CONVST
One analog input 1.5×tc
ns
t
w1
Pulse duration, CONVST
Two analog inputs 2.5×tc
ns
td(A) Aperture time 1 ns
t2
Delay time between consecutive start of
One analog input 2×tc
ns
t
2
Delay time between consecutive start of
single conversion Two analog inputs 3×tc
ns
One analog input, TL = 1 6.5×tc+15
ns
Two analog inputs, TL = 2 7.5×tc+15
ns
One analog input, TL = 4 3×t2 +6.5×tc+15
ns
td(DATA_AV)
Delay time, DATA_AV becomes active for the
Two analog inputs, TL = 4 t2 +7.5×tc+15
ns
t
d(DATA_AV)
Delay time, DATA_AV becomes active for the
trigger level condition: TRIG0 = 1, TRIG1 = 1 One analog input, TL = 8 7×t2 +6.5×tc+15
ns
trigger level condition: TRIG0 = 1, TRIG1 = 1
Two analog inputs, TL = 8 3×t2 +7.5×tc+15
ns
One analog input, TL = 14 13×t2 +6.5×tc+15
ns
Two analog inputs, TL = 12 13×t2 +6.5×tc+15
ns
(1) See Figure 26.
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
AINP 30 I Analog input, single-ended or positive input of differential channel A
AINM 29 I Analog input, single-ended or negative input of differential channel A
AVDD 23 I Analog supply voltage
AGND 24 I Analog ground
BVDD 7 I Digital supply voltage for buffer
BGND 8 I Digital ground for buffer
CONV_CLK
(CONVST) 15 I Digital input. This input is used to apply an external conversion clock in the continuous conversion mode. In
the single conversion mode, this input functions as the conversion start (CONVST) input. A high-to-low
transition on this input holds simultaneously the selected analog input channels and initiates a single
conversion of all selected analog inputs.
CS0 22 I Chip select input (active low)
CS1 21 I Chip select input (active high)
DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level information
of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static
level or pulse output. See Table 14.
DGND 17 I Digital ground. Ground reference for digital circuitry.
DVDD 18 I Digital supply voltage
D0–D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB
RA0 13 I Digital input. RA0 is used as an address line (RA0) for the control register. This is required for writing to
control register 0 and control register 1. See Table 8.
RA1 14 I Digital input. RA1 is used as an address line (RA1) for the control register. This is required for writing to
control register 0 and control register 1. See Table 8.
OV_FL 32 O Overflow o u tput. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if an
overflow occurs. It is set back to low level with a reset of the THS10082 or a reset of the FIFO.
REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be
connected to the reference output REFOUT.
REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
voltage. A n e x t ernal reference voltage at this input can be applied. This option can be programmed through
control register 0. See Table 9.
REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference
voltage. A n e x t ernal reference voltage at this input can be applied. This option can be programmed through
control register 0. See Table 9.
RESET 31 I Hardware reset of the THS10082. Sets the control register to default values.
REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output
requires a capacitor of 10 µF to AGND for filtering and stability.
RD(1) 19 I The R D input is used only if the WR input is configured as a write only input. In this case, it is a digital input,
active low as a data read select from the processor. See timing section.
WR (R/W)(1) 20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a
write-only input (WR), which is active low and used as data write select from the processor . In this case, the
RD input is used as a read input from the processor. See timing section.
(1) The start conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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6
FUNCTIONAL BLOCK DIAGRAM
Logic
and
Control
Control
Register
S/H
S/H
Single-Ended
and/or
Differential
MUX
10-Bit
Pipeline
ADC
REFP REFM
1.225 V
REF
2.5 V
FIFO
16 × 10
10 10
Buffers
REFOUT
DATA_AV
OV_FL
BVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
RA0
RA1
BGND
AGND DGND
3.5 V
1.5 V
AV
DD
DV
DD
REFP
REFM
AINP
AINM
CONV_CLK (CONVST)
CS0
CS1
RD
WR (R/W)
RESET
REFIN
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
7
TYPICAL CHARACTERISTICS
Figure 1
40
45
50
55
60
65
70
75
80
0123456789
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
fs − Sampling Frequency − MHz
THD − Total Harmonic Distortion − dB
Figure 2
40
45
50
55
60
65
0123456789
SIGNAL-TO-NOISE AND DIST ORTION
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs − Sampling Frequency − MHz
SINAD − Signal-to-Noise and Distortion − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
Figure 3
40
45
50
55
60
65
70
75
80
85
90
0123456789
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs − Sampling Frequency − MHz
SFDR − Spurious Free Dynamic Range − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
Figure 4
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
fs − Sampling Frequency − MHz
SNR − Signal-to-Noise − dB
40
45
50
55
60
65
0123456789
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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8
TYPICAL CHARACTERISTICS
Figure 5
40
45
50
55
60
65
70
75
80
85
0123456789
TOTAL HARMONIC DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
fs − Sampling Frequency − MHz
THD − Total Harmonic Distortion − dB
Figure 6
40
45
50
55
60
65
0123456789
SIGNAL-TO-NOISE AND DIST ORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs − Sampling Frequency − MHz
SINAD − Signal-to-Noise and Distortion − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
Figure 7
40
45
50
55
60
65
70
75
80
85
90
0123456789
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs − Sampling Frequency − MHz
SFDR − Spurious Free Dynamic Range − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
Figure 8
SIGNAL-TO-NOISE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
fs − Sampling Frequency − MHz
SNR − Signal-to-Noise − dB
40
45
50
55
60
65
0123456789
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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9
TYPICAL CHARACTERISTICS
Figure 9
40
45
50
55
60
65
70
75
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
THD − Total Harmonic Distortion −dB
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 800 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz Figure 10
40
45
50
55
60
65
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SINAD − Signal-to-Noise and Distortion − dB
SIGNAL-TO-NOISE AND DIST ORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz
Figure 11
40
45
50
55
60
65
70
75
80
85
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SFDR − Spurious Free Dynamic Range − dB
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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10
TYPICAL CHARACTERISTICS
Figure 12
40
45
50
55
60
65
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SNR − Signal-to-Noise − dB
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz Figure 13
40
45
50
55
60
65
70
75
80
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
fi − Input Frequency − MHz
THD − Total Harmonic Distortion − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
Figure 14
40
45
50
55
60
65
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SIGNAL-TO-NOISE AND DIST ORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs= 8 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz
SINAD − Signal-to-Noise and Distortion − dB
Figure 15
40
45
50
55
60
65
70
75
80
85
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
fi − Input Frequency − MHz
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
SFDR − Spurious Free Dynamic Range − dB
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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11
TYPICAL CHARACTERISTICS
Figure 16
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
fi − Input Frequency − MHz
SNR − Signal-to-Noise − dB
40
45
50
55
60
65
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
Figure 17
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
0123456789
ENOB − Effective Number of Bits − Bits
EFFECTIVE NUMBER OF BITS
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
fs − Sampling Frequency − MHz
Figure 18
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
0123456789
EFFECTIVE NUMBER OF BITS
vs
SAMPLING RATE (DIFFERENTIAL)
fs − Sampling Frequency − MHz
ENOB − Effective Number of Bits − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fIN = 500 kHz, AIN = −1 dB FS
Figure 19
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
fi − Input Frequency − MHz
ENOB − Effective Number of Bits − dB
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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12
TYPICAL CHARACTERISTICS
Figure 20
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (DIFFERENTIAL)
fi − Input Frequency − MHz
ENOB − Effective Number of Bits − dB
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
Figure 21
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
fi − Input Frequency − MHz
G − Gain − dB
−30
−25
−20
−15
−10
−5
0
5
0 20406080100120
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MSPS, AIN = −1 dB FS
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
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13
TYPICAL CHARACTERISTICS
−1.0
−0.8
−0.6
−0.4
−0.2
−0.0
0.2
0.4
0.6
0.8
1.0
0 256 512 768 1024
Figure 22
DNL − Differential Nonlinearity − LSB
Code
DIFFERENTIAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V,
DVDD = BVDD = 3 V,
fs = 8 MSPS
Figure 23
−1.0
−0.8
−0.6
−0.4
−0.2
−0.0
0.2
0.4
0.6
0.8
1.0
0 256 512 768 1024
INL − Integral Nonlinearity − LSB
Code
INTEGRAL NONLINEARITY
vs
ADC CODE
AVDD = 5 V,
DVDD = BVDD = 3 V,
fs = 8 MSPS
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14
TYPICAL CHARACTERISTICS
Figure 24
−140
−120
−100
−80
−60
−40
−20
0
0 500000 1000000 1500000 2000000 2500000 3000000 3500000 4000000
Magnitude − dB
f − Frequency − Hz
FAST FOURIER TRANSFORM
vs
FREQUENCY
(4096 POINTS) (SINGLE-ENDED MODE)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MHz, AIN = −1 dB FS, fIN = 1.25 MHz
Figure 25
−140
−120
−100
−80
−60
−40
−20
0
0 500000 1000000 1500000 2000000 2500000 3000000 3500000 4000000
Magnitude − dB
f − Frequency − Hz
FAST FOURIER TRANSFORM
vs
FREQUENCY
(4096 POINTS) (DIFFERENTIAL MODE)
AVDD = 5 V, DVDD = BVDD = 3 V,
fs = 8 MHz, AIN = −0.5 dB FS, fIN = 1.25 MHz
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15
DETAILED DESCRIPTION
Reference Voltage
The THS10082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and
VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the
reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits
of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS10082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually
and configured as single-ended or differential inputs. The desired analog input channel can be programmed.
Analog-to-Digital Converter
The THS10082 uses a 10-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit stages, which
achieves a high sample rate with low power consumption. The THS10082 distributes the conversion over several smaller
ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage
to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while
the second through the eighth stages operate on the seven preceding samples.
DATA_AV
In continuous conversion mode, the first DATA_A V signal is delayed by (7+TL) cycles of the CONV_CLK after a FIFO reset.
This is due to the latency of the pipeline architecture of the THS10082.
Conversion Modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is
initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion
mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling
edge of the applied clock signal.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows
the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION NUMBER OF
CHANNELS MAXIMUM CONVERSION
RATE PER CHANNEL
One single-ended channel 18 MSPS
Two single-ended channels 24 MSPS
One differential channel 18 MSPS
The maximum conversion rate in the continuous conversion mode per channel, is given by:
fc +8 MSPS
# channels
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode(1)
CHANNEL CONFIGURATION NUMBER OF
CHANNELS MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel 14 MSPS
2 single-ended channels 22.67 MSPS
1 differential channel 14 MSPS
(1) The maximum conversion rate with respect to the typical internal oscillator speed [i.e., 8 MHz × (tc/t2)].
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SINGLE CONVERSION MODE
In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion
mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages
of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels
is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV
(data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written
into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.
Figure 26 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be selected
to be sampled simultaneously (see Table 2).
CONVST
AIN
Sample N
t1t1
td(A)
t2
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 26. Timing of Single Conversion Mode
The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input
channels. Th e t i m e t DATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n ×tc. This equation is valid for
a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer
to the timing specifications of single conversion mode.
CONTINUOUS CONVERSION MODE
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In
continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal
CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
Figure 27 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum
throughput rate is 8 MSPS in this mode. The timing of the DATA_A V signal is shown here in the case of a trigger level set
to 1 or 4.
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Sample N
Channel 1 Sample N+1
Channel 1 Sample N+2
Channel 1 Sample N+3
Channel 1 Sample N+4
Channel 1 Sample N+5
Channel 1 Sample N+6
Channel 1 Sample N+7
Channel 1 Sample N+8
Channel 1
Data N−5
Channel 1 Data N−4
Channel 1 Data N−3
Channel 1 Data N−2
Channel 1 Data N−1
Channel 1 Data N
Channel 1 Data N+1
Channel 1 Data N+2
Channel 1 Data N+3
Channel 1
td(A)
tw(CONV_CLKH) tw(CONV_CLKL)
tctd(O)
td(DATA_AV)
td(DATA_AV)
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 1
DATA_AV,
Trigger Level = 4
td(pipe)
50% 50%
Figure 27. Timing of Continuous Conversion Mode (1-channel operation)
Figure 28 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum
throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted
data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4.
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 2
DATA_AV,
Trigger Level = 4
Data N−3
Channel 2 Data N−2
Channel 1 Data N−2
Channel 2 Data N−1
Channel 1 Data N−1
Channel 2 Data N
Channel 1 Data N
Channel 2 Data N+1
Channel 1 Data N+1
Channel 2
td(DATA_AV)
tw(CONV_CLKH) tw(CONV_CLKL)
td(A)
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
tctd(O)
td(Pipe)
td(DATA_AV)
50% 50%
Figure 28. Timing of Continuous Conversion Mode (2-Channel Operation)
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DIGITAL OUTPUT DATA FORMAT
The digital output data format of the THS10082 can either be in binary format or in twos complement format. The following
tables list the digital outputs for the analog input voltages.
Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP 3FFh
AIN = (VREFP + VREFM)/2 200h
AIN = VREFM 000h
Table 4. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
AIN = VREFP 1FFh
AIN = (VREFP + VREFM)/2 000h
AIN = VREFM 200h
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP − AINM
VREF = VREFP − VREFM
Vin = VREF 3FFh
Vin = 0 200h
Vin = −VREF 000h
Table 6. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE
Vin = AINP − AINM
VREF = VREFP − VREFM
Vin = VREF 1FFh
Vin = 0 000h
Vin = −VREF 200h
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FIFO DESCRIPTION
In order to facilitate an ef ficient connection to today’s processors, the THS10082 is supplied with a FIFO. This integrated
FIFO enables a problem-free processing of data with today’ s processors. The FIFO is provided as a flexible circular buffer.
The circular buffer integrated in the THS10082 stores up to 16 conversion values. Therefore, the amount of interrupts to
be served by a processor can be reduced significantly.
8
9
10
11
12
13
14
15 16 12
3
4
5
6
7
Read Pointer
Trigger Pointer
W rite Pointer
Data in FIFO
Free
Figure 29. Circular Buffer
The converted data of the THS10082 is automatically written into the FIFO. To control the writing and reading process, a
write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location which is read next.
The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input
channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way,
the channel information for the reading processor is continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger
level according to Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal
DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal
DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values
as selected for the trigger level are written into the FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the
processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel
according to the autoscan mode, which is shown in Table 10. The channel information is, therefore, always maintained.
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READING DATA FROM THE FIFO
The THS10082 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion
values is ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger
levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger
level of 1 , 4 , 8 , and 14 can be selected. The following figures demonstrate the principle of reading the data (the READ signal
is asynchronous to CONV_CLK).
In Figure 30, a trigger level of 1 is selected. The control signal DATA_A V is set to an active low pulse. This means that the
connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 30. Trigger Level 1 Selected
In Figure 31, a trigger level of 4 is selected. The control signal DATA_A V is set to an active low pulse. This means that the
connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 31. Trigger Level 4 Selected
In Figure 32, a trigger level of 8 is selected. The control signal DATA_A V is set to an active low pulse. This means that the
connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 32. Trigger Level 8 Selected
In Figure 33, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that
the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 33. Trigger Level 14 Selected
As shown in Figure 30 through Figure 33, READ, is the logical combination of CS0, CS1, and RD.
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ADC CONTROL REGISTER
The THS10082 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode.
The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
REG BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
CR0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF
CR1 RESERVED OFFSET BIN/2’s R/W DATA_P DATA_T TRIG1 TRIG0 FRST RESET
Writing to Control Register 0 and Control Register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and
writing the register value to the ADC. The addressing is performed with the upper bits RA0 and RA1. During this write
process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control
register.
Table 8. Control Register Addressing
D0 – D9 RA0 RA1 Addressed Control Register
Desired register value 0 0 Control register 0
Desired register value 1 0 Control register 1
Desired register value 0 1 Reserved for future
Desired register value 1 1 Reserved for future
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INITIALIZATION OF THE THS10082
The initialization of the THS10082 should be done according to the configuration flow shown in Figure 34.
Start
Use Default
Values?
Yes
W rite 0x401 to
THS10082
(Set Reset Bit in CR1)
No
W rite 0x401 to
THS10082
(Set Reset Bit in CR1)
Clear RESET By
W riting 0x400 to
CR1
W rite The User
Configuration to
CR0
W rite The User
Configuration to
CR1 (Can Include
FIFO Reset, Must
Exclude RESET)
Continue
Clear RESET By
W riting 0x400 to
CR1
Figure 34. THS10082 Configuration Flow
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ADC CONTROL REGISTERS
Control Register 0, Write Only (see Table 8)
BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF
Table 9. Control Register 0 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 VREF Vref select:
Bit 0 = 0 → The internal reference is selected
Bit 0 = 1 → The external reference voltage is selected
1 0 MODE Continuous conversion mode/single conversion mode
Bit 1 = 0 → Continuous conversion mode is selected
An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the
CONV_CLK signal a new converted value is written into the FIFO.
Bit 1 = 1 → Single conversion mode is selected
In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the
THS10082 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the
selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected
channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is
satisfied.
2 0 PD Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down. It is also possible to
read out the FIFO.
3, 4 0,0 CHSEL0,
CHSEL1 Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.
5,6 1,0 DIFF0, DIFF1 Number of dif ferential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. See Table 10.
7 0 SCAN Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. See Table 10.
8,9 0,0 TEST0,
TEST1 Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
See Table 11 for selection of the three different test voltages.
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ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS10082 can be selected via bits 3 to 7 of control register 0. One single channel
(single-ended or d i fferential) is selected via bit 3 of control register 0. Bit 5 controls the selection between single-ended and
differential configuration. Bit 6 selects the autoscan mode, if more than one input channel is selected. Table 10 shows the
possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
SCAN BIT 6
DIFF1 BIT 5
DIFF0 BIT 4
CHSEL1 BIT 3
CHSEL0 DESCRIPTION OF THE SELECTED INPUTS
0 0 0 0 0 Analog input AINP (single ended)
0 0 0 0 1 Analog input AINM (single ended)
0 0 0 1 0 Reserved
0 0 0 1 1 Reserved
0 0 1 0 0 Dif ferential channel (AINP−AINM)
0 0 1 0 1 Reserved
1 0 0 0 1 Autoscan two single-ended channels: AINP, AINM, AINP, …
1 0 0 1 0 Reserved
1 0 0 1 1 Reserved
1 0 1 0 1 Reserved
1 0 1 1 0 Reserved
1 1 0 0 1 Reserved
0 0 1 1 0 Reserved
0 0 1 1 1 Reserved
1 0 0 0 0 Reserved
1 0 1 0 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11.
Table 11. Test Mode
BIT 9
TEST1 BIT 8
TEST0 OUTPUT RESULT
0 0 Normal mode
0 1 VREFP
1 0 ((VREFM)+(VREFP))/2
1 1 VREFM
Three d i fferent options can be selected. This feature allows support testing of hardware connections between the ADC and
the processor.
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Control Register 1, Write Only (see Table 8)
BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 1 RESERVED OFFSET BIN/2s R/W DATA_P DATA_T TRIG1 TRIG0 FRST RESET
Table 12. Control Register 1 Bit Functions
BITS RESET
VALUE NAME FUNCTION
0 0 RESET Reset
W riting a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
In addition the FIFO pointer and of fset register is reset. After reset, it takes 5 clock cycles until the first value is
converted and written into the FIFO.
1 0 FRST FRST: FIFO reset
By writing a 1 into this bit, the FIFO is reset.
2, 3 0,0 TRIG0,
TRIG1 FIFO trigger level
Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the
signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This
indicates to the processor that the ADC values can be read. Refer to Table 13.
4 1 DATA_T DATA_AV type
Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g., for edge or level
sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a
pulse. See Table 14.
5 1 DATA_P DATA_AV polarity
Bit 5 of control register 1 controls the polarity of DATA_AV. I f i t is set to 1, DAT A_AV is active high. If it is set to 0,
DATA_AV is active low. Refer to Table 14.
6 0 R/W R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7 0 BIN/2s Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6.
8 0 OFFSET Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-
sion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the of fset error.
9 0 RESERVED Always write 0.
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FIFO TRIGGER LEVEL
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger
level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to
indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be
selected, is dependent on the number of input channels. One channel is considered as two inputs in differential
configuration, or one single-ended input. The processor, therefore, always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1 BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
0 0 01 02
0 1 04 04
1 0 08 08
1 1 14 12
TIMING AND SIGNAL DESCRIPTION OF THE THS10082
The reading from the THS10082 and writing to the THS10082 is performed by using the chip select inputs (CS0, CS1),
the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is
desired in cases where the connected processor consists of a combined read/write output signal (R/W ). The two chip select
inputs can be used to interface easily to a processor.
Reading from the THS10082 takes place by an internal RDint signal, which is generated from the logical combination of
the external signals CS0, CS1, and RD (see Figure 35). This signal is then used to strobe the words out of the FIFO and
to enable the output buf fers. The last external signal (either CS0, CS1, or RD) to become valid makes RDint active while
the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates RDint.
Writing to the THS10082 takes place by an internal WRint signal, which is generated from the logical combination of the
external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and
1. The last external signal (either CS0, CS1, or WR) to become valid makes WRint active while the read input (RD) is
inactive. The first of those external signals going to its inactive state then deactivates WRint.
Read Enable
W rite Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 35. Logical Combination of CS0, CS1, RD, and WR
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DATA_AV Type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_A V. Bit 4 of control register 1
determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of
DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P BIT 4
DATA_T DATA_AV TYPE
0 0 Active low level
0 1 Active low pulse
1 0 Active high level
1 1 Active high pulse
The signal DATA_A V is set to active when the trigger condition is satisfied. It is set back inactive dependent of the DATA_T
selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of
READ). The trigger condition is checked again after TL reads. For single conversion mode, the DATA_AV type should be
programmed to active level mode.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous
conversion mode.
Read Timing (Using R/W, CS0-Controlled)
Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W which becomes valid.
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÔÔÔ
ÔÔÔ
ÔÔÔ
90%90%
90%
90%
90%
90%
10%
10%
tw(CS)
tsu(R/W)th(R/W)
tath
td(CSDAV)
CS0
CS1
R/W
RD
D(0−9)
DATA_AV
Figure 36. Read Timing Diagram Using R/W (CS0-controlled)
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Read Timing Parameter (CS0-Controlled)(1)
PARAMETER MIN TYP MAX UNIT
tsu(R/W)Setup time, R/W high to last CS valid 0 ns
taAccess time, last CS valid to data valid 0 10 ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive 12 ns
thHold time, first CS invalid to data invalid 0 5 ns
th(R/W)Hold time, first external CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
(1) CS = CS0
Write Timing (Using R/W, CS0-Controlled)
Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W .
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W which becomes valid.
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
90%
90% 90%
10%
t
w(CS)
tsu(R/W)th(R/W)
CS0
CS1
WR
RD
D(0−9)
DATA_AV
10%
tsu th
Figure 37. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-Controlled)(1)
PARAMETER MIN TYP MAX UNIT
tsu(R/W)Setup time, R/W stable to last CS valid 0 ns
tsu Setup time, data valid to first CS invalid 5 ns
thHold time, first CS invalid to data invalid 2 ns
th(R/W)Hold time, first CS invalid to R/W change 5 ns
tw(CS) Pulse duration, CS active 10 ns
(1) CS = CS0
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29
INTERFACING THE THS10082 TO THE TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS10082 to the TMS320C30/31/33 DSPs. The read and write
timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/W
DATA_AV
CONV_CLK
DATA
RD
DVDD THS10082 TMS320C30/31/33
STRB
A23
R/W
INTX
TOUT
DATA
INTERFACING THE THS10082 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS10082 to the TMS320C54x. The read and write timings (using
R/W, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/W
DATA_AV
CONV_CLK
DATA
RD
DVDD THS10082 TMS320C54x
I/O STRB
A15
R/W
INTX
BCLK
DATA
Read Timing (Using RD, RD-Controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts
as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0,
CS1, and RD which becomes valid.
ÓÓÓÓ
ÓÓÓÓ
ÔÔÔ
ÔÔÔ
90%90%
90%
10%
tw(RD)
tsu(CS) th(CS)
tath
td(CSDAV)
CS0
CS1
WR
RD
D(0−9)
DATA_AV
10%
Figure 38. Read Timing Diagram Using RD (RD-controlled)
TMS320C30 is a trademark of Texas Instruments.
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
30
Read Timing Parameter (RD-Controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CS) Setup time, RD low to last CS valid 0 ns
taAccess time, last CS valid to data valid 0 10 ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive 12 ns
thHold time, first CS invalid to data invalid 0 5 ns
th(CS) Hold time, RD change to first CS invalid 5 ns
tw(RD)Pulse duration, RD active 10 ns
Write Timing (using WR, WR-Controlled)
Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input
RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal
of CS0, CS1, and WR which becomes valid.
90%90%
10%
tsu th
D(0−9)
DATA_AV
10%
ÓÓÓÓÓ
ÓÓÓÓÓ
ÓÓÓÓÓ
ÔÔÔÔ
ÔÔÔÔ
ÔÔÔÔ
tw(WR)
tsu(CS) th(CS)
CS0
CS1
WR
RD
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 39. Write Timing Diagram Using WR (WR-controlled)
Write Timing Parameter Using WR (WR-Controlled)
PARAMETER MIN TYP MAX UNIT
tsu(CS) Setup time, CS stable to last WR valid 0 ns
tsu Setup time, data valid to first WR invalid 5 ns
thHold time, WR invalid to data invalid 2 ns
th(CS) Hold time, WR invalid to CS change 5 ns
tw(WR)Pulse duration, WR active 10 ns
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
31
INTERFACING THE THS10082 TO THE TMS320C6201 DSP
The following application circuit shows an interface of the THS10082 to the TMS320C6201. The read (using RD,
RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
THS10082−1
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
THS10082−2
TMS320C6201
CE1
EA20
ARE
AWE
EXT_INT6
DATA
TOUT1
TOUT2
EA21
EXT_INT7
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS10082 features two analog input channels. These can be configured for either single-ended or differential
operation. Best performance is achieved in differential mode. Figure 40 shows a simplified model, where a single-ended
configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal
or external reference voltage). The analog input voltage range goes from VREFM to VREFP. This means that VREFM defines
the minimum voltage, which can be applied to the ADC. VREFP defines the maximum voltage, which can be applied to the
ADC. The internal reference source provides the voltage VREFM of 1.5 V and the voltage VREFP of 3.5 V. The resulting
analog input voltage swing of 2 V can be expressed by:
VREFM vAINP vVREFP
10-Bit
ADC
VREFP
VREFM
AINP
Figure 40. Single-Ended Input Stage
A differential operation is desired for many applications. Figure 41 shows a simplified model for the analog inputs AINM
and AINP, which are configured for differential operation. This configuration has a few advantages, which are discussed
in the following paragraphs.
(1)
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
32
10-Bit
ADC
VREFP
VREFM
AINP
ΣVADC
AINM
+
−
Figure 41. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage (VADC) which is applied at the input of the
ADC is the difference between the input AINP and AINM. This means that VREFM defines the minimum voltage (AINM)
which can be applied to the ADC. VREFP defines the maximum voltage (AINP) which can be applied to the ADC. The voltage
VADC can be calculated as follows:
VADC +ABS(AINP–AINM)
An advantage to single-ended operation is that the common-mode voltage
VCM +AINM )AINP
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND vAINM, AINP vAVDD
1VvVCM v4V
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which is common
to both analog inputs. See Figure 43.
SINGLE-ENDED MODE OF OPERATION
The THS10082 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the
THS10082 must be driven from an operational amplifier that does not degrade the ADC performance. Because the
THS10082 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its
input requirements. This can be achieved with dc and ac coupling. An application example is shown for dc-coupled level
shifting in the following section, dc coupling.
(2)
(3)
(4)
(5)
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
33
DC COUPLING
An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the
THS10082. The analog input voltage range of the THS10082 goes from 1.5 V to 3.5 V. An op-amp specified for 5-V single
supply can be used as shown in Figure 42.
Figure 42 shows an application example where the analog input signal in the range from −1 V up to 1 V is shifted by an
op-amp to the analog input range of the THS10082 (1.5 V to 3.5 V). The op-amp is configured as an inverting amplifier with
a gain of −1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT
of the THS10082 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio
matched, thin-film resistor networks minimizes gain and offset errors.
_
+
5 V
R
RRS
3.5 V
2.5 V
1.5 V THS10082
AINP
REFOUT
R
R
1.25 V
1 V
0 V
−1 V
REFIN
Figure 42. Level-Shift for DC-Coupled Input
DIFFERENTIAL MODE OF OPERATION
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential
signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in
differential mode.
THS10082
AINP
AINM
REFOUT
C
C
R
R
200 Ω
49.9 Ω
Mini Circuits
T4−1
Figure 43. Transformer Coupled Input
SLAS254B − M AY 2002 − REVISED NOVEMBER 2002
www.ti.com
34
MECHANICAL DATA
DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
38 PINS SHOWN
4040066/D 11/98
0,25
0,75
0,50
0,15 NOM
Gage Plane
6,20
NOM 8,40
7,80
32
11,1011,10
30
Seating Plane
10,9010,90
20
0,19
19
A
0,30
38
1
PINS **
A MAX
A MIN
DIM
1,20 MAX
9,60
9,80
28
M
0,13
0°−ā8°
0,10
0,65
38
12,60
12,40
0,15
0,05
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
THS10082IDA ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
THS10082IDAG4 ACTIVE TSSOP DA 32 46 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Aug-2009
Addendum-Page 1
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