© Semiconductor Components Industries, LLC, 2015
December, 2015 Rev. 5
1Publication Order Number:
KAI08051/D
KAI-08051
3296 (H) x 2472 (V)
Interline CCD Image Sensor
Description
The KAI08051 Image Sensor is an 8megapixel CCD in a 4/3”
optical format that provides increased QE, reduced read noise, and
improved color accuracy compared to earlier generation devices in the
TRUESENSE 5.5 micron Interline Transfer CCD family. The sensor
features broad dynamic range, excellent imaging performance, and a
flexible readout architecture that enables use of 1, 2, or 4 outputs. Full
resolution readout is supported at up to 16 frames per second, a Region
of Interest (ROI) mode supports partial readout of the sensor at even
higher frame rates.
The sensor is available with the TRUESENSE Sparse Color Filter
Pattern, which provides a 2x improvement in light sensitivity
compared to a standard color Bayer part.
The sensor shares common pinout and electrical configurations
with other devices based on the TRUESENSE 5.5 micron Interline
Transfer Platform, allowing a single camera design to support multiple
members of this family.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CCD; Progressive Scan
Total Number of Pixels 3364 (H) x 2520 (V)
Number of Effective Pixels 3320 (H) x 2496 (V)
Number of Active Pixels 3296 (H) x 2472 (V)
Pixel Size 5.5 mm (H) x 5.5 mm (V)
Active Image Size 18.13 mm (H) x 13.60 mm (V)
22.66 mm (diag), 4/3” optical format
Aspect Ratio 4:3
Number of Outputs 1, 2, or 4
Charge Capacity 20,000 electrons
Output Sensitivity 39 mV/e
Quantum Efficiency
RGB (FXAJD, FXAJP (no glass), QXPJD)
RGB (FBAJD, FBAJP (no glass))
Mono, PAN (AAAJP)
Mono (AXAJD, AXAJP (no glass))
Mono (ABAJD, ABAJP (no glass))
33%, 41%, 42%
30%, 37%, 39%
4.0%, 4.4%
51%
52%
Read Noise (f = 40 MHz) 10 e
Dark Current
Photodiode
VCCD
7 electrons/s
100 electrons/s
Dark Current Doubling Temp.
Photodiode
VCCD
7°C
9°C
Dynamic Range 66 dB
Charge Transfer Efficiency 0.999999
Blooming Suppression > 300 X
Smear 100 dB
Image Lag < 10 electrons
Maximum Pixel Clock Speed 40 MHz
Maximum Frame Rates
Quad Output
Dual Output
Single Output
16 fps
8 fps
4 fps
Package 68 pin PGA
Cover Glass AR coated, 2 Sides or Clear Glass
NOTE: All parameters are specified at T = 40°C unless otherwise noted.
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Figure 1. KAI08051 CCD Image Sensor
Features
Increased QE, Reduced Read Noise, and
and Improved Color Accuracy
Bayer Color Pattern, TRUESENSE Sparse
Color Filter Pattern, and Monochrome
Configurations
Progressive Scan Readout
Flexible Readout Architecture
High Frame Rate
High Sensitivity
Low Noise Architecture
Excellent Smear Performance
Package Pin Reserved for Device
Identification
Applications
Industrial Imaging
Medical Imaging
Security
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
KAI08051
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ORDERING INFORMATION
Table 2. ORDERING INFORMATION KAI08051 IMAGE SENSOR
Part Number Description Marking Code
KAI08051AAAJPBA Monochrome, No Microlens, PGA Package, Taped Clear Cover
Glass, no coatings, Standard Grade KAI08051AAA
Serial Number
KAI08051AAAJPAE Monochrome, No Microlens, PGA Package, Taped Clear Cover
Glass, no coatings, Engineering Grade
KAI08051AXAJDBA Monochrome, Special Microlens, PGA Package, Sealed Clear Cover
Glass with AR coatings (both sides), Standard Grade KAI08051AXA
Serial Number
KAI08051AXAJDAE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover
Glass with AR coatings (both sides), Engineering Grade
KAI08051AXAJPBA Monochrome, Special Microlens, PGA Package, Taped Clear Cover
Glass, no coatings, Standard Grade KAI08051AXA
Serial Number
KAI08051AXAJPAE Monochrome, Special Microlens, PGA Package, Taped Clear Cover
Glass, no coatings, Engineering Grade
KAI08051FXAJDBA Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed
Clear Cover Glass with AR coatings (both sides), Standard Grade KAI08051FXA
Serial Number
KAI08051FXAJDAE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed
Clear Cover Glass with AR coatings (both sides), Engineering Grade
KAI08051FXAJBB2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed
Clear Cover Glass, no coatings, Grade 2 KAI08051FXA
Serial Number
KAI08051FXAJBAE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed
Clear Cover Glass, no coatings, Engineering Grade
KAI08051QXAJDBA Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed
Clear Cover Glass with AR coatings (both sides), Standard Grade KAI08051QXA
Serial Number
KAI08051QXAJDAE Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed
Clear Cover Glass with AR coatings (both sides), Engineering Grade
KAI08051ABAJDBA * Monochrome, Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR coatings (both sides), Standard Grade KAI08051ABA
Serial Number
KAI08051ABAJDAE * Monochrome, Telecentric Microlens, PGA Package, Sealed Clear
Cover Glass with AR coatings (both sides), Engineering Grade
KAI08051ABAJPBA * Monochrome, Telecentric Microlens, PGA Package, Taped Clear
Cover Glass, no coatings, Standard Grade KAI08051ABA
Serial Number
KAI08051ABAJPAE * Monochrome, Telecentric Microlens, PGA Package, Taped Clear
Cover Glass, no coatings, Engineering Grade
KAI08051FBAJDBA * Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coatings (both sides), Standard
Grade KAI08051FBA
Serial Number
KAI08051FBAJDAE * Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coatings (both sides), Engineering
Grade
KAI08051FBAJBB2 * Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass, no coatings, Grade 2 KAI08051FBA
Serial Number
KAI08051FBAJBAE * Gen2 Color (Bayer RGB), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass, no coatings, Engineering Grade
KAI08051QBAJDBA * Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coatings (both sides), Standard
Grade KAI08051FBA
Serial Number
KAI08051QBAJDAE * Gen2 Color (Sparse CFA), Telecentric Microlens, PGA Package,
Sealed Clear Cover Glass with AR coatings (both sides), Engineering
Grade
*Not recommended for new designs.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI08051
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram (Monochrome No Filter Pattern)
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
12 Dark
12
V1B
12 Buffer
12
12
22
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112822101 12
822101 12 8 2212
22 12
DevID
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
HLOD
10 1
Dark Reference Pixels
There are 12 dark reference rows at the top and 12 dark
rows at the bottom of the image sensor. The dark rows are not
entirely dark and so should not be used for a dark reference
level. Use the 22 dark columns on the left or right side of the
image sensor as a dark reference.
Under normal circumstances use only the center 20
columns of the 22 column dark reference due to potential
light leakage.
Dummy Pixels
Within each horizontal shift register there are 11 leading
additional shift phases. These pixels are designated as
dummy pixels and should not be used to determine a dark
reference level.
In addition, there is one dummy row of pixels at the top
and bottom of the image.
Active Buffer Pixels
12 unshielded pixels adjacent to any leading or trailing
dark reference regions are classified as active buffer pixels.
Eight of the active buffer pixels that are adjacent to the dark
reference region have a lower response than the rest of the
4 active buffer pixels that are directly adjacent to the active
pixels. These pixels are light sensitive but are not tested for
defects and nonuniformities.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electronhole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
KAI08051
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and exposure time and nonlinearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
ESD Protection
Adherence to the powerup and powerdown sequence is
critical. Failure to follow the proper powerup and
powerdown sequences may cause damage to the sensor.
See PowerUp and PowerDown Sequence section.
Bayer Color Filter Pattern
Figure 3. Bayer Color Filter Pattern
HLOD
12 Dark
12
V1B
12 Buffer
12
12
B G
GR
22
1 Dummy
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112822101 12
822101 12 8 22 10 112
22 12
DevID
HLOD
B G
GR
B G
GR
B G
GR
TRUESENSE Sparse Color Filter Pattern
Figure 4. TRUESENSE Sparse Color Filter Pattern
HLOD
12 Dark
12
V1B
12 Buffer
12
12
22
1 Dummy
1 Dummy
3296H x 2472V
5.5 mm x 5.5 mm Pixels
1648 1648
1648 1648
(Last VCCD Phase = V1 H1S)
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sa
H1Ba
H2Sa
H2Ba
RDa
Ra
VDDa
VOUTa
GND
H1Sb
H1Bb
H2Sb
H2Bb
RDc
Rc
VDDc
VOUTc
GND
RDd
Rd
VDDd
VOUTd
GND
RDb
Rb
VDDb
VOUTb
GND
V1B
V2B
V3B
V4B
V1T
V2T
V3T
V4T
H1Sd
H1Bd
H2Sd
H2Bd
H1Sc
H1Bc
H2Sc
H2Bc
H2SLa
OGa
H2SLc
OGc
H2SLd
OGd
H2SLb
OGb
ESD ESD
SUBSUB
822 10 112
822101 12
822101 12 8 22 10 112
22 12
DevID
HLOD
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
P B G
R
P
B P
P
G
G
G
P
P
P R P
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PHYSICAL DESCRIPTION
Pin Description and Device Orientation
Figure 5. Package Pin Designations Top View
Pixel
(1,1)
1 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V3B V1B
V4B
VDDa
V2B
GND
VOUTa
Ra
RDa
H2SLa
OGa
H1Bb
H2Bb
H2Sb
H1Sb
N/C
SUB
H2Sa
H1Sa
H1Ba
H2Ba
23
24
H2SLb
OGb
25
26
27
28
29
30
31
32
V1B
V4B
VDDb
V2B
GND
VOUTb
Rb
RDb
33
34
V3B
ESD
68 66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
ESD V4T
V1T
V2T
VDDc
VOUTc
GND
RDc
Rc
OGc
H2SLc
H2Bd
H1Bd
H1Sd
H2Sd
SUB
N/C
H1Sc
H2Sc
H2Bc
H1Bc
46
45
OGd
H2SLd
44
43
42
41
40
39
38
37
V4T
V1T
V2T
VDDd
VOUTd
GND
RDd
Rd
36
35
DevID
V3T
67
V3T
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Table 3. PIN DESCRIPTION
Pin Name Description
1 V3B Vertical CCD Clock, Phase 3, Bottom
3 V1B Vertical CCD Clock, Phase 1, Bottom
4 V4B Vertical CCD Clock, Phase 4, Bottom
5 VDDa Output Amplifier Supply, Quadrant a
6 V2B Vertical CCD Clock, Phase 2, Bottom
7 GND Ground
8 VOUTa Video Output, Quadrant a
9 Ra Reset Gate, Quadrant a
10 RDa Reset Drain, Quadrant a
11 H2SLa Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant a
12 OGa Output Gate, Quadrant a
13 H1Ba Horizontal CCD Clock, Phase 1, Barrier,
Quadrant a
14 H2Ba Horizontal CCD Clock, Phase 2, Barrier,
Quadrant a
15 H2Sa Horizontal CCD Clock, Phase 2,
Storage, Quadrant a
16 H1Sa Horizontal CCD Clock, Phase 1,
Storage, Quadrant a
17 N/C No Connect
18 SUB Substrate
19 H2Sb Horizontal CCD Clock, Phase 2,
Storage, Quadrant b
20 H1Sb Horizontal CCD Clock, Phase 1,
Storage, Quadrant b
21 H1Bb Horizontal CCD Clock, Phase 1, Barrier,
Quadrant b
22 H2Bb Horizontal CCD Clock, Phase 2, Barrier,
Quadrant b
23 H2SLb Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant b
24 OGb Output Gate, Quadrant b
25 Rb Reset Gate, Quadrant b
26 RDb Reset Drain, Quadrant b
27 GND Ground
28 VOUTb Video Output, Quadrant b
29 VDDb Output Amplifier Supply, Quadrant b
30 V2B Vertical CCD Clock, Phase 2, Bottom
31 V1B Vertical CCD Clock, Phase 1, Bottom
32 V4B Vertical CCD Clock, Phase 4, Bottom
33 V3B Vertical CCD Clock, Phase 3, Bottom
34 ESD ESD Protection Disable
Pin Name Description
68 ESD ESD Protection Disable
67 V3T Vertical CCD Clock, Phase 3, Top
66 V4T Vertical CCD Clock, Phase 4, Top
65 V1T Vertical CCD Clock, Phase 1, Top
64 V2T Vertical CCD Clock, Phase 2, Top
63 VDDc Output Amplifier Supply, Quadrant c
62 VOUTc Video Output, Quadrant c
61 GND Ground
60 RDc Reset Drain, Quadrant c
59 Rc Reset Gate, Quadrant c
58 OGc Output Gate, Quadrant c
57 H2SLc Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant c
56 H2Bc Horizontal CCD Clock, Phase 2, Barrier,
Quadrant c
55 H1Bc Horizontal CCD Clock, Phase 1, Barrier,
Quadrant c
54 H1Sc Horizontal CCD Clock, Phase 1,
Storage, Quadrant c
53 H2Sc Horizontal CCD Clock, Phase 2,
Storage, Quadrant c
52 SUB Substrate
51 N/C No Connect
50 H1Sd Horizontal CCD Clock, Phase 1,
Storage, Quadrant d
49 H2Sd Horizontal CCD Clock, Phase 2,
Storage, Quadrant d
48 H2Bd Horizontal CCD Clock, Phase 2, Barrier,
Quadrant d
47 H1Bd Horizontal CCD Clock, Phase 1, Barrier,
Quadrant d
46 OGd Output Gate, Quadrant d
45 H2SLd Horizontal CCD Clock, Phase 2,
Storage, Last Phase, Quadrant d
44 RDd Reset Drain, Quadrant d
43 Rd Reset Gate, Quadrant d
42 VOUTd Video Output, Quadrant d
41 GND Ground
40 V2T Vertical CCD Clock, Phase 2, Top
39 VDDd Output Amplifier Supply, Quadrant d
38 V4T Vertical CCD Clock, Phase 4, Top
37 V1T Vertical CCD Clock, Phase 1, Top
36 DevID Device Identification
35 V3T Vertical CCD Clock, Phase 3, Top
1. Liked named pins are internally connected and should have a
common drive signal.
2. N/C pins (17, 51) should be left floating.
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IMAGING PERFORMANCE
Table 4. TYPICAL OPERATION CONDITIONS
Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.
Description Condition Notes
Light Source Continuous red, green and blue LED illumination For monochrome sensor, only
green LED used.
Operation Nominal operating voltages and timing
Table 5. SPECIFICATIONS
All Configurations
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Dark Field Global NonUniformity DSNU 2.0 mVpp Die 27, 40
Bright Field Global NonUniformity 2.0 5.0 %rms Die 27, 40 1
Maximum Gain Difference Between
Outputs
DG10 % Design 2
Maximum Signal Error due to
Nonlinearity Differences
DNL 1% Design 2
Horizontal CCD Charge Capacity HNe 55 keDesign
Vertical CCD Charge Capacity VNe 40 keDesign
Photodiode Charge Capacity PNe 20 keDie 27, 40 3
Horizontal CCD Charge Transfer
Efficiency
HCTE 0.999995 0.999999 Die
Vertical CCD Charge Transfer
Efficiency
VCTE 0.999995 0.999999 Die
Photodiode Dark Current Ipd 1 70 e/p/s Die 40
Vertical CCD Dark Current Ivd 100 300 e/p/s Die 40
Image Lag Lag 10 eDesign
Antiblooming Factor Xab 300 Design
Vertical Smear Smr 100 dB Design
Read Noise neT10 erms Design 4
Dynamic Range DR 66 dB Design 4, 5
Output Amplifier DC Offset Vodc 8.9 V Die 27, 40
Output Amplifier Bandwidth f3db 250 MHz Die 6
Output Amplifier Impedance ROUT 127 WDie 27, 40
Output Amplifier Sensitivity DV/DN39 mV/eDesign
Bright Field Global NonUniformity
(FXA, QXA)
2.2 5 %rms Die 27, 40 1
Bright Field Global Peak to Peak
NonUniformity (FXA, QXA)
PRNU 9.5 20 %pp Die 27, 40 1
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set
such that the photodiode charge capacity is 780 mV.
4. At 40 MHz
5. Uses 20LOG (PNe/ neT)
6. Assumes 5 pF load.
7. Monochrome or PAN pixels
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Table 5. SPECIFICATIONS
All Configurations
Description Notes
Temperature
Tested At
(5C)
Sampling
Plan
UnitsMax.Nom.Min.Symbol
Bright Field Center NonUniformity
(FXA, QXA)
1.3 2.5 % Die 27, 40 1
Bright Field Global NonUniformity
(AXA, QXA)
1.5 2 %rms Die 27, 40 7
Bright Field Global Peak to Peak
NonUniformity (AXA, QXA)
PRNU 5 12 %pp Die 27, 40 7
Bright Field Center NonUniformity
(AXA, QXA)
0.9 1.5 % Die 27, 40 7
Bright Field Global NonUniformity
(FBA, QBA)
2 5 %rms Die 27, 40 1
Bright Field Global Peak to Peak
NonUniformity (FBA, QBA)
PRNU 5 15 %pp Die 27, 40 1
Bright Field Center NonUniformity
(FBA, QBA)
1 2 % Die 27, 40 1
Bright Field Global NonUniformity
(ABA, QBA)
2 5 %rms Die 27, 40 7
Bright Field Global Peak to Peak
NonUniformity (ABA, QBA)
PRNU 5 15 %pp Die 27, 40 7
Bright Field Center NonUniformity
(ABA, QBA)
1 2 % Die 27, 40 7
1. Per color
2. Value is over the range of 10% to 90% of photodiode saturation.
3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set
such that the photodiode charge capacity is 780 mV.
4. At 40 MHz
5. Uses 20LOG (PNe/ neT)
6. Assumes 5 pF load.
7. Monochrome or PAN pixels
Table 6. MONO (OR PAN) PIXEL QUANTUM EFFICIENCY FOR KAI08051AXA, KAI08051ABA (1),
KAI08051QBA, AND KAI08051PBA (1) CONFIGURATIONS WITH AR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Mono
or
Pan
QEmax 51 % Design 30
Peak Quantum Efficiency Mono
or
Pan
lQE 460 nm Design 30
1. Configuration KAI08051ABA and KAI08051PBA are not recommended for new designs.
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Table 7. QUANTUM EFFICIENCY FOR KAI08051FXA, KAI08051FBA (1), KAI08051QXA AND
KAI08051QBA (1) CONFIGURATIONS WITH AR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Blue
Green
Red
QEmax 42
41
34
% Design 30
Peak Quantum Efficiency Blue
Green
Red
lQE 460
540
600
nm Design 30
1. Configuration KAI08051FBA and KAI08051QBA are not recommended for new designs.
Table 8. QUANTUM EFFICIENCY FOR KAI08051FXA, KAI08051FBA (1), KAI08051QXA AND
KAI08051QBA (1) CONFIGURATIONS WITH CLEAR GLASS
Description Symbol Min. Nom. Max. Units
Sampling
Plan
Temperature
Tested At
(5C) Notes
Peak Quantum Efficiency Blue
Green
Red
QEmax 38
38
31
% Design 30
Peak Quantum Efficiency
Wavelength
Blue
Green
Red
lQE 460
540
600
nm Design 30
1. Configuration KAI08051FBA and KAI08051QBA are not recommended for new designs.
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TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
Figure 6. Quantum Efficiency: Monochrome with Microlens. Configuration with AR Glass and with No Glass.
Monochrome without Microlens
Figure 7. Monochrome without Microlens (No Cover Glass) Quantum Efficiency
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KAI08051 Color (Bayer RGB) with Microlens MAR Glass (compared to KAI08050)
Figure 8. Quantum Efficiency: Color Bayer with Microlens and AR Glass Configuration.
KAI08051 compared to KAI08050.
KAI08051 Color (Bayer RGB) with Microlens (compared MAR vs. Clear Glass)
Figure 9. Quantum Efficiency: KAI08051 Color Bayer with Microlens (AR vs. Clear Glass Configuration)
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KAI08051 Color (TRUESENSE Sparse CFA) with Microlens (MAR Glass)
Figure 10. KAI08051 Color (TRUESENSE Sparse CFA) with Microlens (MAR Glass) Quantum Efficiency
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Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light
angle is varied in a plane parallel to the HCCD.
For the curves marked “Vertical”, the incident light angle
is varied in a plane parallel to the VCCD.
Monochrome with Microlens
Figure 11. KAI08051ABA Monochrome with Microlens Angular Quantum Efficiency
(not recommended for new designs)
Figure 12. KAI08051AXA Monochrome with Special Microlens Angular Quantum Efficiency
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Dark Current versus Temperature
Figure 13. Dark Current versus Temperature
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Power Estimated
Figure 14. Power
HCCD Frequency (MHz)
Power (W)
Single Dual Quad
0.0
0.2
0.4
0.6
0.8
1.0
1.2
10 15 20 25 30 35 40
Frame Rates
Figure 15. Frame Rates
0
2
4
6
8
10
12
14
16
18
20
10 15 20 25 30 35 40
HCCD Frequency (MHz)
Frame Rate (fps)
0
2
4
6
8
10
12
14
16
18
20
Single Dual (Left/Right) Quad
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DEFECT DEFINITIONS
Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C
Description Condition Notes
Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency 10 MHz
Pixels Per Line 3520 1
Lines Per Frame 1360 2
Line Time 354.9 msec
Frame Time 482.7 msec
Photodiode Integration Time Mode A: PD_Tint = Frame Time = 482.7 msec, no electronic shutter used
Mode B: PD_Tint = 33 msec, electronic shutter used
VCCD Integration Time 447.2 msec 3
Temperature 40°C
Light Source Continuous red, green and blue LED illumination 4
Operation Nominal operating voltages and timing
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
4. For monochrome sensor, only the green LED is used.
Table 10. DEFECT DEFINITIONS FOR TESTING AT 405C
Description Definition Standard Grade Grade 2 Notes
Major dark field defective bright pixel PD_Tint = Mode A Defect 191 mV
or
PD_Tint = Mode B Defect 13.8 mV
80 80 1
Major bright field defective dark pixel Defect 12%
Minor dark field defective bright pixel PD_Tint = Mode A Defect 99 mV
or
PD_Tint = Mode B Defect 7 mV
800 800
Cluster defect A group of 2 to 10 contiguous major defective
pixels, but no more than 3 adjacent defects
horizontally.
15 n/a 2
Cluster defect (grade 2) A group of 2 to 10 contiguous major defective
pixels
n/a 15 2
Column defect A group of more than 10 contiguous major
defective pixels along a single column
0 0 2
1. For the color device (KAI08051FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
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Table 11. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C
Description Condition Notes
Operational Mode Two outputs, using VOUTa and VOUTc, continuous readout
HCCD Clock Frequency 20 MHz
Pixels Per Line 3520 1
Lines Per Frame 1360 2
Line Time 177.8 msec
Frame Time 241.8 msec
Photodiode Integration Time
(PD_Tint)
Mode A: PD_Tint = Frame Time = 241.8 msec, no electronic shutter used
Mode B: PD_Tint = 33 msec, electronic shutter used
VCCD Integration Time 224.0 msec 3
Temperature 27°C
Light Source Continuous red, green and blue LED illumination 4
Operation Nominal operating voltages and timing
1. Horizontal overclocking used.
2. Vertical overclocking used.
3. VCCD Integration Time = 1260 lines x Line Time, which is the total time a pixel will spend in the VCCD registers.
4. For monochrome sensor, only the green LED is used.
Table 12. DEFECT DEFINITIONS FOR TESTING AT 275C
Description Definition Standard Grade Grade 2 Notes
Major dark field defective bright pixel PD_Tint = Mode A Defect 30 mV
or
PD_Tint = Mode B Defect 4.6 mV
80 80 1
Major bright field defective dark pixel Defect 12%
Cluster defect A group of 2 to 10 contiguous major defective
pixels, but no more than 3 adjacent defects
horizontally.
15 n/a 2
Cluster defect (grade 2) A group of 2 to 10 contiguous major defective
pixels
n/a 15 2
Column defect A group of more than 10 contiguous major
defective pixels along a single column
0 0 2
1. For the color device (KAI08051FBA), a bright field defective pixel deviates by 12% with respect to pixels of the same color.
2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (27°C) temperature. Minor point
defects are not included in the defect map. All defective
pixels are reference to pixel 1, 1 in the defect maps. See
Figure 16: Regions of interest for the location of pixel 1,1.
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TEST DEFINITIONS
Test Regions of Interest
Image Area ROI: Pixel (1, 1) to Pixel (3320, 2496)
Active Area ROI: Pixel (13, 13) to Pixel (3308, 2484)
Center ROI: Pixel (1611, 1199) to Pixel (1710, 1298)
Only the Active Area ROI pixels are used for performance and defect tests.
Overclocking
The test system timing is configured such that the sensor
is overclocked in both the vertical and horizontal directions.
See Figure 16 for a pictorial representation of the regions of
interest.
Figure 16. Regions of Interest
Horizontal Overclock
12 buffer rows
12 buffer rows
12 buffer columns
12 buffer columns
22 dark columns
22 dark columns
12 dark rows
VOUTa
12 dark rows
3296 x 2472
Active Pixels
1, 1
13,
13
Pixel
Pixel
VOUTc
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Tests
Dark Field Global NonUniformity
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. The average signal level
of each of the 768 sub regions of interest is calculated. The
signal level of each of the sub regions of interest is calculated
using the following formula:
Signal of ROI[i] = (ROI Average in counts Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
are found. The dark field global uniformity is then calculated
as the maximum signal found minus the minimum signal
level found.
Units: mVpp (millivolts peak to peak)
Global NonUniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 546 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 780 mV. Global nonuniformity is
defined as
GlobalNonUniformity +100 ǒActiveAreaStandardDeviation
ActiveAreaSignal Ǔ
Units: %rms.
Active Area Signal = Active Area Average Dark Column
Average
Global Peak to Peak NonUniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 546 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 780 mV. The sensor is partitioned
into 768 sub regions of interest, each of which is 103 by 103
pixels in size. The average signal level of each of the 768 sub
regions of interest (ROI) is calculated. The signal level of
each of the sub regions of interest is calculated using the
following formula:
Signal of ROI[i] = (ROI Average in counts Horizontal
overclock average in counts) * mV per count
Where i = 1 to 768. During this calculation on the 768 sub
regions of interest, the maximum and minimum signal levels
are found. The global peak to peak uniformity is then
calculated as:
GlobalUniformity +100 MaximumSignal *MinimumSignal
ActiveAreaSignal
Units: %pp
Center NonUniformity
This test is performed with the imager illuminated to a
level such that the output is at 70% of saturation
(approximately 560 mV). Prior to this test being performed
the substrate voltage has been set such that the charge
capacity of the sensor is 780 mV. Defects are excluded for
the calculation of this test. This test is performed on the
center 100 by 100 pixels of the sensor. Center uniformity is
defined as:
Center ROI Uniformity +100 ǒCenter ROI Standard Deviation
Center ROI Signal Ǔ
Units: %rms.
Center ROI Signal = Center ROI Average Dark Column
Average
Dark Field Defect Test
This test is performed under dark field conditions. The
sensor is partitioned into 768 sub regions of interest, each of
which is 103 by 103 pixels in size. In each region of interest,
the median value of all pixels is found. For each region of
interest, a pixel is marked defective if it is greater than or
equal to the median value of that region of interest plus the
defect threshold specified in the “Defect Definitions”
section.
Bright Field Defect Test
This test is performed with the imager illuminated to a
level such that the output is at approximately 546 mV. Prior
to this test being performed the substrate voltage has been set
such that the charge capacity of the sensor is 780 mV. The
average signal level of all active pixels is found. The bright
and dark thresholds are set as:
Dark defect threshold = Active Area Signal * threshold
Bright defect threshold = Active Area Signal * threshold
The sensor is then partitioned into 768 sub regions of
interest, each of which is 103 by 103 pixels in size. In each
region of interest, the average value of all pixels is found.
For each region of interest, a pixel is marked defective if it
is greater than or equal to the median value of that region of
interest plus the bright threshold specified or if it is less than
or equal to the median value of that region of interest minus
the dark threshold specified.
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Example for major bright field defective pixels:
Average value of all active pixels is found to be
546 mV
Dark defect threshold: 546 mV * 12 % = 66 mV
Bright defect threshold: 546 mV * 12 % = 66 mV
Region of interest #1 selected. This region of interest is
pixels 13, 13 to pixels 115, 115.
Median of this region of interest is found to be
546 mV.
Any pixel in this region of interest that
is (546 + 66 mV) 612 mV in intensity will be
marked defective.
Any pixel in this region of interest that
is (546 66 mV) 480 mV in intensity will be
marked defective.
All remaining 768 sub regions of interest are analyzed
for defective pixels in the same manner.
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OPERATION
Table 13. ABSOLUTE MAXIMUM RATINGS
Description Symbol Minimum Maximum Units Notes
Operating Temperature TOP 50 +70 °C 1
Humidity RH +5 +90 % 2
Output Bias Current Iout 60 mA 3
Offchip Load CL 10 pF
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is 15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 14. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Description Minimum Maximum Units Notes
VDDa, VOUTa0.4 15.5 V 1
RDa0.4 15.5 V 1
V1B, V1T ESD 0.4 ESD + 24.0 V
V2B, V2T, V3B, V3T, V4B, V4T ESD 0.4 ESD + 14.0 V
H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra, OGaESD 0.4 ESD + 14.0 V 1
ESD 10.0 0.0 V
SUB 0.4 40.0 V 2
1. a denotes a, b, c or d
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
PowerUp and PowerDown Sequence
Adherence to the powerup and powerdown sequence is critical. Failure to follow the proper powerup and powerdown
sequences may cause damage to the sensor.
Figure 17. PowerUp and PowerDown Sequence
VDD
SUB
ESD VCCD
Low
HCCD
Low
time
V+
V
Activate all other biases when
ESD is stable and sub is above 3V
Do not pulse the electronic shutter
until ESD is stable
Notes:
1. Activate all other biases when ESD is stable and
SUB is above 3 V
2. Do not pulse the electronic shutter until ESD is
stable
3. VDD cannot be +15 V when SUB is 0 V
4. The image sensor can be protected from an
accidental improper ESD voltage by current
limiting the SUB current to less than 10 mA. SUB
and VDD must always be greater than GND. ESD
must always be less than GND. Placing diodes
between SUB, VDD, ESD and ground will protect
the sensor from accidental overshoots of SUB,
VDD and ESD during power on and power off.
See the figure below.