5-360
FAST AND LS TTL DATA
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The SN54/74LS194A is a High Speed 4-Bit Bidirectional Universal Shift
Register. As a high speed multifunctional sequential building block, it is useful
in a wide variety of applications. It may be used in serial-serial, shift left, shift
right, serial-parallel, parallel-serial, and parallel-parallel data register trans-
fers. The LS194A is similar in operation to the LS195A Universal Shift
Register, with added features of shift left without external connections and
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped
process to achieve high speeds and is fully compatible with all Motorola TTL
families.
•Typical Shift Frequency of 36 MHz
•Asynchronous Master Reset
•Hold (Do Nothing) Mode
•Fully Synchronous Serial or Parallel Data Transfers
•Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1234567
16 15
8
VCC
MR
Q0Q1Q2Q3S1
CP S0
DSR P0P1P2P3DSL GND
PIN NAMES LOADING (Note a)
HIGH LOW
S0, S1Mode Control Inputs 0.5 U.L. 0.25 U.L.
P0–P3Parallel Data Inputs 0.5 U.L. 0.25 U.L.
DSR Serial (Shift Right) Data Input 0.5 U.L. 0.25 U.L.
DSL Serial (Shift Left) Data Input 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.
Q0–Q3Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS194A
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
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5-361
FAST AND LS TTL DATA
SN54/74LS194A
LOGIC DIAGRAM
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS194A 4-Bit Bidirectional Shift Regis-
ter. The LS194A is similar in operation to the Motorola LS195A
Universal Shift Register when used in serial or parallel data
register transfers. Some of the common features of the two
devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations taking
place in less than 15 ns (typical) making the device especially
useful for implementing very high speed CPUs, or the memory
buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing on
P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
Q3 outputs respectively following the next LOW to HIGH
transition of the clock.
The asynchronous Master Reset (MR), when LOW, over-
rides all other input conditions and forces the Q outputs LOW .
Special logic features of the LS194A design which increase
the range of application are described below:
Two mode control inputs (S0, S1) determine the synchro-
nous operation of the device. As shown in the Mode Selection
Table, data can be entered and shifted from left to right (shift
right, Q0 º Q1, etc.) or right to left (shift left, Q3 º Q2, etc.), or
parallel data can be entered loading all four bits of the register
simultaneously. When both S0 and S1,are LOW, the existing
data is retained in a “do nothing” mode without restricting the
HIGH to LOW clock transition.
D-type serial data inputs (DSR, DSL) are provided on both
the first and last stages to allow multistage shift right or shift left
data transfers without interfering with parallel load operation.
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
OPERATING MODE
MR S1S0DSR DSL PnQ0Q1Q2Q3
Reset L X X X X X L L L L
Hold H I I X X X q0q1q2q3
Shift Left H h I X I X q1q2q3L
H h I X h X q1q2q3H
Shift Right H I h I X X L q0q1q2
H I h h X X H q0q1q2
Parallel Load H h h X X PnP0P1P2P3
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
5-362
FAST AND LS TTL DATA
SN54/74LS194A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 23 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
fMAX Maximum Clock Frequency 25 36 MHz
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL Propagation Delay,
Clock to Output 14
17 22
26 ns
VCC = 5.0 V
CL = 15 pF
tPHL Propagation Delay,
MR to Output 19 30 ns
CL = 15 pF
5-363
FAST AND LS TTL DATA
SN54/74LS194A
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tWClock or MR Pulse Width 20 ns
VCC = 5.0 V
tsMode Control Setup Time 30 ns
VCC = 5.0 V
tsData Setup Time 20 ns
VCC = 5.0 V
thHold time, Any Input 0 ns
CC = 5.0 V
trec Recovery Time 25 ns
DEFINITIONS OF TERMS
SETUP TIME(ts) —is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level must
be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and transfer
HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width and fmax
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time Figure 4. Setup (ts) and Hold (th) Time for S Input
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5-364
FAST AND LS TTL DATA
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FAST AND LS TTL DATA
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