General Description
The MAX5204–MAX5207 serial input, voltage-output 16-
bit digital-to-analog converters (DACs) provide monotonic
16-bit output over temperature without any adjustments.
The MAX5204/MAX5205 operate from a +5V single
power supply and use an external reference ranging
from +4V to VDD, while the MAX5206/MAX5207 operate
from a +3V or +3.3V single power supply and use an
external reference ranging from +2V to VDD. The
MAX5204–MAX5207 DAC output range is typically from
0 to VDD.
The MAX5204–MAX5207 feature a hardware reset input
(CLR) that when pulled low clears the output to zero
code 0000 hex (MAX5205/MAX5207) or resets the out-
put to midscale code 8000 hex (MAX5204/MAX5206).
The 3-wire serial interface is compatible with
SPI™/QSPI™/MICROWIRE™. All devices have a low-
power shutdown mode that reduces the supply current
consumption to 1µA.
The MAX5204–MAX5207 are available in a space-sav-
ing 10-pin µMAX package and are guaranteed over the
extended temperature range (-40°C to +105°C). Refer
to the MAX5200–MAX5203 data sheet for internal refer-
ence versions.
Applications
Low-Cost VCO/VCXO Frequency Control
Industrial Process Control
High-Resolution Offset Adjustment
Features
♦Guaranteed 16-Bit Monotonic
♦10-Pin 5mm ✕3mm µMAX Package
♦Rail-to-Rail®Output Amplifier
♦Single-Supply Operation
+5V (MAX5204/MAX5205)
+3V, +3.3V (MAX5206/MAX5207)
♦Low Power Consumption: 0.5mA
♦Shutdown Mode Reduces Supply Current to 1µA
♦SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface
♦Power-On-Reset Sets Output to
Midscale (MAX5204/MAX5206)
Zero-Scale (MAX5205/MAX5207)
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
________________________________________________________________ Maxim Integrated Products 1
1
2
3
4
5
10
9
8
7
6
DGND
SCLK
DIN
LDACVDD
AGND
REF
CLR
MAX5204–
MAX5207
µMAX
TOP VIEW
CSOUT
Pin Configuration
Ordering Information
19-2658; Rev 0; 10/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5204AEUB -40°C to +105°C 10 µMAX
MAX5204BEUB -40°C to +105°C 10 µMAX
MAX5204ACUB 0°C to +105°C 10 µMAX
MAX5205AEUB -40°C to +105°C 10 µMAX
MAX5205BEUB -40°C to +105°C 10 µMAX
MAX5205ACUB 0°C to +105°C 10 µMAX
MAX5206AEUB -40°C to +105°C 10 µMAX
MAX5206BEUB -40°C to +105°C 10 µMAX
MAX5206ACUB 0°C to +105°C 10 µMAX
MAX5207AEUB -40°C to +105°C 10 µMAX
MAX5207BEUB -40°C to +105°C 10 µMAX
MAX5207ACUB 0°C to +105°C 10 µMAX
Selector Guide appears at end of data sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Rail-to-Rail is a registered trademark of Motorola Nippon, Ltd.
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND...............................................-0.3V to +6V
AGND to DGND.........................................……….-0.3V to +0.3V
REF, OUT to AGND.................................…-0.3V to (VDD + 0.3V)
CLR, LDAC, SCLK, DIN, CS to DGND .......-0.3V to (VDD + 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C) .........444.4mW
Operating Temperature Ranges
MAX520_CUB ....................................................0°C to +105°C
MAX520_EUB .........................................…….-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS—MAX5204/MAX5205
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), VREF = 4.096V, output load = 10kΩin parallel with 250pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE (Note 1)
Resolution N 16 Bits
MAX520_AEUB ±10 ±20
MAX520_ACUB ±10 ±20Integral Nonlinearity (Note 2) INL
MAX520_BEUB ±20 ±40
LSB
MAX520_A_UB (Note 3) ±1
MAX520_BEUB (0°C to +105°C) (Note 3) ±1
Differential Nonlinearity
(Note 2) DNL
MAX520_BEUB (-40°C to 0°C) ±2
LSB
Offset Error Inferred from measurement at 1C00 hex
and FFFF hex ±3 ±25 mV
Gain Error GE Within DAC output range (Note 4) ±0.01 ±1 %FSR
Offset Temperature Coefficient 1.5 µV/°C
Gain Temperature Coefficient 3ppm of
FSR/°C
Power-Supply Rejection PSR VDD = 5V ±5%, midscale input ±0.06 ±0.5 mV/V
DYNAMIC PERFORMANCE
DAC Output Range (Note 2) 0 to
VDD V
Output-Voltage Slew Rate SR 0.6 V/µs
Output Settling Time To ±1LSB of FS,
VSTEP = 0.25 × VREF to 0.75 × VREF 25 µs
Output Noise DAC code = 8400 hex, 10kHz 120 nV/√Hz
DAC Glitch Impulse Major carry transition (code 7FFF hex to
code 8000 hex) 10 nV⋅s
Digital Feedthrough Code = 0000 hex; CS = VDD;
LDAC = 0; SCLK, DIN = 0 or VDD 10 nV⋅s
Wake-Up Time From software shutdown to 90% of output
code = FFFF hex 50 µs
Power-Up Time From power applied to 90% of output
code = FFFF hex 10 ms
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—MAX5204/MAX5205 (continued)
(VDD = +4.75V to +5.25V, fSCLK = 10MHz (50% duty cycle), VREF = 4.096V, output load = 10kΩin parallel with 250pF, TA= TMIN to
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUT
VREF Input Range 4.0 VDD V
VREF Input Current 40 µA
VREF Input Resistance 100 kΩ
Input Capacitance 18 pF
DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Hysteresis VHYST 200 mV
Input Leakage IIN Digital inputs = 0 or VDD ±1 µA
Input Capacitance CIN 15 pF
POWER REQUIREMENTS
Positive Power Supply VDD 4.75 5.25 V
Positive Supply Current IDD All digital inputs at 0 or VDD (Note 5) 0.8 1.5 mA
Shutdown Supply Current ISHDN All digital inputs at 0 or VDD 110µA
TIMING CHARACTERISTICS
SCLK Frequency fSCLK 10 MHz
SCLK Clock Period tCP 100 ns
SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
DIN Setup Time tDS 40 ns
DIN Hold Time tDH 0ns
CS Fall to SCLK Rise Setup Time tCSS 40 ns
SCLK Rise to CS Rise Hold Time tCSH 0ns
SCLK Rise to CS Fall Ignore tCS0 10 ns
CS Rise to SCLK Rise Ignore tCS1 40 ns
LDAC Pulse Width tLDAC 40 ns
CS Rise to LDAC Low Setup tLDACS 40 ns
SCLK Fall to CS Fall Ignore tCSOL 10 ns
CS Pulse Width Low for Shutdown tCSWL 40 ns
CS Pulse Width High tCSWH 100 ns
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE (Note 1)
Resolution N 16 Bits
MAX520_AEUB ±10 ±20
MAX520_ACUB ±10 ±20
Integral Nonlinearity (Note 2) INL
MAX520_BEUB ±20 ±40
LSB
MAX520_A_UB (Note 3) ±1
MAX520_BEUB (0°C to +105°C) (Note 3) ±1Differential Nonlinearity (Note 2) DNL
MAX520_BEUB (-40°C to 0°C) ±2
LSB
Offset Error Inferred from measurement at 3800 hex and
FFFF hex ±3 ±25 mV
Gain Error GE Within DAC output range (Note 4) ±0.01 ±1.0 %FSR
Offset Temperature Coefficient 1.5 µV/°C
Gain Temperature Coefficient 3ppm of
FSR/°C
Power-Supply Rejection PSR VDD = 3V ±10%, midscale input ±0.06 ±0.5 mV/V
DYNAMIC PERFORMANCE
DAC Output Range (Note 2) 0 to
VDD V
Voltage-Output Slew Rate SR 0.6 V/µs
Output Settling Time To ±1LSB of FS,
VSTEP = 0.25 ✕ VREF to 0.75 ✕ VREF 25 µs
Output Noise Code = 8400 hex, 10kHz 120 nV/√Hz
DAC Glitch Impulse Major carry transition (code 7FFF hex to
code 8000 hex) 10 nV⋅s
Digital Feedthrough Code = 0000 hex; CS = VDD;
LDAC = 0; SCLK, DIN = 0 or VDD 10 nV⋅s
Wake-Up Time From software shutdown to 90% of output
code = FFFF hex 50 µs
Power-Up Time From power boosting to 90% of output
code = FFFF hex 10 ms
REFERENCE INPUT
VREF Input Range 2.0 VDD V
VREF Input Current 20 µA
VREF Input Resistance 100 kΩ
Input Capacitance 18 pF
ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), VREF = 2.048V, output load = 10kΩin parallel with 250pF, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (DIN, SCLK, CS, CLR, LDAC)
Input High Voltage VIH 2.1 V
Input Low Voltage VIL 0.6 V
Input Hysteresis VHYST 200 mV
Input Leakage IIN Digital inputs = 0 or VDD ±1 µA
Input Capacitance CIN 15 pF
POWER REQUIREMENTS
Positive Power Supply VDD 2.7 3.6 V
Positive Supply Current IDD All digital inputs at 0 or VDD (Note 5) 0.5 1.5 mA
Shutdown Supply Current ISHDN All digital inputs at 0 or VDD 110µA
TIMING CHARACTERISTICS
SCLK Frequency fSCLK 10 MHz
SCLK Clock Period tCP 100 ns
SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
DIN Setup Time tDS 40 ns
DIN Hold Time tDH 0ns
CS Fall to SCLK Rise Setup Time tCSS 40 ns
SCLK Rise to CS Rise Hold Time tCSH 0ns
SCLK Rise to CS Fall Ignore tCS0 10 ns
CS Rise to SCLK Rise Ignore tCS1 40 ns
LDAC Pulse Width tLDAC 40 ns
CS Rise to LDAC Low Setup tLDACS 40 ns
SCLK Fall to CS Fall Ignore tCSOL 10 ns
CS Pulse Width Low for Shutdown tCSWL 40 ns
CS Pulse Width High tCSWH 100 ns
Note 1: Static performance tested at VDD = +5.0V (MAX5204/MAX5205) and at VDD = +3.0V (MAX5206/MAX5207).
Note 2: INL and DNL are guaranteed for outputs between 0.5V to (VDD - 0.5V).
Note 3: Guaranteed monotonic.
Note 4: VREF = 4.096V (MAX5204/MAX5205) and VREF = 2.048V (MAX5206/MAX5207).
Note 5: RL= ∞, digital inputs are at VDD or DGND.
ELECTRICAL CHARACTERISTICS—MAX5206/MAX5207 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 10MHz (50% duty cycle), VREF = 2.048V, output load = 10kΩin parallel with 250pF, TA= TMIN to TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
GAIN ERROR
vs. TEMPERATURE
MAX5204 toc04
TEMPERATURE (°C)
GAIN ERROR (%FSR)
8040 60200-20
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
-0.10
-40
OFFSET ERROR
vs. TEMPERATURE
MAX5204 toc05
TEMPERATURE (°C)
OFFSET ERROR (mV)
6040-20 0 20
-0.30
-0.20
-0.10
0
0.10
0.20
0.30
0.40
-0.40
-40 80
100 10,000 100,000
OUTPUT NOISE DENSITY
vs. FREQUENCY
MAX5204 toc08
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
1000
700
0
100
200
300
400
600
500
DAC CODE = 8400 HEX
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
SUPPLY CURRENT vs. TEMPERATURE
MAX5204 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
7550250-40 -25
0.6
0.7
0.8
0.9
1.0
0.5
85
INTEGRAL NONLINEARITY
vs. CODE (A GRADE)
MAX5204 toc02
DAC CODE
INL (LSB)
600005000010000 20000 30000 40000
-12
-8
-4
0
4
8
12
16
-16
0 70000
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX5204 toc03
DAC CODE
DNL (LSB)
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0600005000010000 20000 30000 40000 70000
HALF-SCALE OUTPUT SETTLING TIME
(CODE FROM 4000H TO C000H)
MAX5204 toc06
4µs/div
OUT
1V/div
OUT
1mV/div
LARGE SIGNAL
(1V/div)
SMALL SIGNAL
(1mV/div)
RLOAD = 10kΩ
CLOAD = 250pF
HALF-SCALE OUTPUT SETTLING TIME
(CODE FROM C000H TO 4000H)
MAX5204 toc07
4µs/div
OUT
1V/div
OUT
1mV/div
LARGE SIGNAL
(1V/div)
SMALL SIGNAL
(1mV/div)
RLOAD = 10kΩ
CLOAD = 250pF
Typical Operating Characteristics
(VDD = +5V, VREF = 4.096V, TA= +25°C, unless otherwise noted.)
6 _______________________________________________________________________________________
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX5204 toc13
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
60-20 0 20 40
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
-40 80
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
SOURCE-CURRENT CAPABILITY
MAX5204 toc09
SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
302010
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
040
CODE = FFFF HEX
CODE = C000 HEX
CODE = 8000 HEX
SINK-CURRENT CAPABILITY
MAX5204 toc10
SINK CURRENT (mA)
OUTPUT VOLTAGE (V)
12963
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
015
CODE = 0000 HEX
CODE = 4000 HEX
MAJOR-CARRY OUTPUT GLITCH
(CODE FROM 8000H TO 7FFFH)
MAX5204 toc11
1µs/div
OUT
(AC-COUPLED,
5mV/div)
MAJOR-CARRY OUTPUT GLITCH
(CODE FROM 7FFFH TO 8000H)
MAX5204 toc12
1µs/div
OUT
(AC-COUPLED,
5mV/div)
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = 4.096V, TA= +25°C, unless otherwise noted.)
_______________________________________________________________________________________ 7
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
8 _______________________________________________________________________________________
Detailed Description
The MAX5204–MAX5207 serial 16-bit, voltage-output
DACs are easily configured with a 3-wire serial interface.
These devices offer full 16-bit performance with less than
±20LSB integral linearity error and less than ±1LSB dif-
ferential linearity error, thus ensuring monotonic perfor-
mance. Serial data transfer minimizes the number of
package pins required. The MAX5204–MAX5207 include
control-logic circuitry, a 16-bit data-in shift register, and
a DAC register. The MAX5204–MAX5207 output is
buffered and the full-scale output voltage is VREF (typ).
The MAX5204–MAX5207 feature a hardware reset input
(CLR) that when pulled low clears the DAC output to
zero code 0000 hex (MAX5205/MAX5207) or resets the
DAC output to midscale code 8000 hex (MAX5204/
MAX5206). For normal operation, connect CLR to VDD.
Reference Input
The MAX5204/MAX5205 (+5V supply) use an external
reference between 4V to VDD, while the MAX5206/
MAX5207 (+3V supply) use an external reference from
2V to VDD. The DAC output range is from 0 to VREF.
Digital Interface
The MAX5204–MAX5207 digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE and most DSP interfaces. All of the digital
input pins (CS, SCLK, DIN, CLR, and LDAC) are TTL
compatible. SCLK can accept clock frequencies as
high as 10MHz for a +5V supply and 10MHz for a +3V
or +3.3V supply.
One of two methods can be used when interfacing and
updating the MAX5204–MAX5207. The first requires
Pin Description
PIN NAME FUNCTION
1CLR
Reset DAC Active-Low Input. Pull CLR low to reset the DAC output to midscale output (8000 hex) for
MAX5204/MAX5206 and to zero-scale output (0000 hex) for MAX5205/MAX5207. For normal operation,
connect CLR to VDD.
2 REF External Reference Voltage Input
3 AGND Analog Ground
4V
DD Positive Supply Voltage. Bypass VDD to AGND with a 10µF capacitor in parallel with a 0.1µF capacitor.
5 OUT DAC Output Voltage
6CS Active-Low Chip-Select Input
7LDAC Load DAC Input
8 DIN Serial Data Input
9 SCLK Serial Clock Input. Duty cycle must be 40% to 60%.
10 DGND Digital Ground
CLR
AGND
REF
16-BIT DAC
16-BIT DATA LATCH
DIN
SCLK
CS
CONTROL
LOGIC
LDAC
OUT
DGND
VDD
MAX5204–
MAX5207
SERIAL INPUT REGISTER
BUFFER
Figure 1. MAX5204–MAX5207 Simplified Functional Diagram
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
_______________________________________________________________________________________ 9
three digital inputs: CS, DIN, and SCLK (Figure 2). The
active-low chip-select input (CS) enables the serial
data loading at the data input (DIN). Pull CS low and
clock in each bit of the 16-bit digital word on the rising
edge of the serial clock (SCLK). Two eight-bit bytes
can be used, and do not require any additional time
between them. Pulling CS high after loading the 16-bit
word transfers that code into the DAC register and then
updates the output. If CS is not kept low during the
entire loading of the 16-bit word, data will be corrupted.
In this case, a new 16-bit word must be loaded. LDAC
must be kept low at all times for the above instructions.
An alternate method of interfacing and updating the
MAX5204–MAX5207 can be done with a fourth digital
input, the active-low load DAC (LDAC). LDAC allows
the output to update asynchronously after CS goes
high. It is useful when updating multiple MAX5204–
MAX5207s synchronously when sharing a single LDAC
and CS line. LDAC must be kept high at all times dur-
ing the data loading sequence and must only be
asserted when CS is high. Asserting LDAC when CS is
low can cause corrupted data. To operate the
MAX5204–MAX5207 using LDAC, pull LDAC high, pull
CS low, load the 16-bit word as described in the previ-
ous paragraph, and pull CS high again. Following these
commands, the DAC output only updates when LDAC
is asserted low (Figure 3).
Shutdown Mode
The low-power shutdown mode reduces supply current
to typically 1µA and a maximum of 10µA. Shutdown
mode is not activated through command words, as is
common among D/A converters. These devices require
careful manipulation of CS and SCLK (Figure 4).
Shutting Down
To shut down the MAX5204–MAX5207, change the
state of SCLK (either a high to low or low to high transi-
tion can be used) and pulse two falling CS edges. In
order to keep the device in shutdown mode, SCLK
must not change state. SCLK must remain in the state
it is in after the two CS pulses.
Waking Up
There are two methods to wake up the MAX5204–
MAX5207. Pulse one falling CS edge or transition SCLK.
It takes 50µs typically from the CS falling edge or SCLK
transition for the DAC to return to normal operation.
Power-On Reset
The MAX5204–MAX5207 have a power-on reset circuit
to set the DAC’s output to a known state when VDD is
first applied. The MAX5204/MAX5206 reset to midscale
(code 8000 hex) upon power-up. The MAX5205/
MAX5207 reset to zero-scale (code 0000 hex) upon
power-up. This ensures that unwanted output voltages
do not occur immediately following a system power-up,
such as a loss of power. It is required to apply VDD first
before any other input (DIN, SCLK, CLR, LDAC, CS,
and REF).
tCL
tCH
tCSS
D14D15
tDS
tDH
D0
tCSH
tCS1
tCS0
SCLK
CS
DIN
tCP
tCSWH
NOTE: LDAC IS LOGIC LOW.
Figure 2. 3-Wire Interface Timing Diagram
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
10 ______________________________________________________________________________________
Applications Information
Power Supply and Bypassing
Considerations
Bypass the power supply with a 10µF capacitor in par-
allel with a 0.1µF capacitor to AGND. Minimize lead
lengths to reduce lead inductance. If noise becomes
an issue, use shielding and/or ferrite beads to increase
isolation.
Output Buffer
The MAX5204–MAX5207 include low-offset, low-noise
buffers enabling the output to source 15mA or sink
5mA. The output buffer operates at a slew rate of
0.6V/µs. With a 1/4 FS to 3/4 FS output transition, the
buffer output typically settles to 1LSB in about 25µs.
The MAX5204–MAX5207 output buffers provide a low
0.2Ωtypical output impedance. The MAX5204–
MAX5207 buffer amplifiers typically produce
120nV/√Hz noise at 10kHz.
tCS0L
tCSWL tCSWH
SHUTDOWN WAKE-UP
tCS0L
tCSWL tCSWH
SHUTDOWN WAKE-UP
SCLK
CS
A. WAKING UP USING A THIRD FALLING EDGE ON CS.
B. WAKING UP USING A TRANSITION ON SCLK.
SCLK
CS
Figure 4. Shutdown Timing
tCL
tCH
tCSS
D14D15
tDS
tDH
D0
tCSH
tCS1
tCS0
SCLK
CS
DIN
LDAC
tCP
tCSWH
tLDACS tLDAC
Figure 3. 4-Wire Interface Timing Diagram
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
______________________________________________________________________________________ 11
Bipolar Configuration
The MAX5204–MAX5207 are designed for unipolar opera-
tion, but can be used in bipolar applications with an exter-
nal amplifier and resistors. Figure 5 shows the
MAX5204–MAX5207 configured for bipolar operation. The
op amp is set for unity gain. Table 1 lists the offset binary
code for this circuit. Output voltage range is ±VREF.
Layout Considerations
Digital and AC transient signals coupling to AGND can
create noise at the output. Connect AGND to the high-
est quality ground available. Use proper grounding
techniques, such as a multilayer board with a low-
inductance ground plane. Wire-wrapped boards and
sockets are not recommended. For optimum system
performance, use printed circuit (PC) boards with sep-
arate analog and digital ground planes. Connect the
two ground planes together at the low-impedance
power-supply source. Connect DGND and AGND pins
together at the IC. The best ground connection is
achieved by connecting the DAC’s DGND and AGND
together, and then connecting that point to the system
analog ground plane. If the DAC’s DGND is connected
to the system digital ground, digital noise can get
through the DAC’s analog portion.
Chip Information
TRANSISTOR COUNT: 8764
PROCESS: BiCMOS
CLR
AGND
VDD
REF
DIN
SCLK
CS
DGND
BIPOLAR OUT
(±VREF)
LDAC
OUT
MC68XXXX
10µF
0.1µF
0.1µF
10µF
PCS0
MOSI
SCLK
+5V
RR
MAX5204–
MAX5207
MAX400
Figure 5. MAX5204–MAX5207 Typical Operating Circuit—Bipolar Output
DAC LATCH CONTENTS
MSB LSB ANALOG OUTPUT, VOUT
1111 1111 1111 1111 +VREF × (32,767 / 32,768)
1000 0000 0000 0001 +VREF × (1 / 32,768)
1000 0000 0000 0000 0V
0111 1111 1111 1111 -VREF × (1 / 32,768)
0000 0000 0000 0000 -VREF × (32,768 / 32,768)
Table 1. Bipolar Code Table
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
12 ______________________________________________________________________________________
Selector Guide
PART INTEGRAL NONLINEARITY
(LSB MAX)
SUPPLY VOLTAGE
RANGE (V)
REFERENCE INPUT
RANGE (V)
POWER-ON-RESET
VALUE
MAX5204AEUB 20 4.75 to 5.25 4 to VDD Midscale
MAX5204ACUB 20 4.75 to 5.25 4 to VDD Midscale
MAX5204BEUB 40 4.75 to 5.25 4 to VDD Midscale
MAX5205AEUB 20 4.75 to 5.25 4 to VDD Zero
MAX5205ACUB 20 4.75 to 5.25 4 to VDD Zero
MAX5205BEUB 40 4.75 to 5.25 4 to VDD Zero
MAX5206AEUB 20 2.7 to 3.6 2 to VDD Midscale
MAX5206ACUB 20 2.7 to 3.6 2 to VDD Midscale
MAX5206BEUB 40 2.7 to 3.6 2 to VDD Midscale
MAX5207AEUB 20 2.7 to 3.6 2 to VDD Zero
MAX5207ACUB 20 2.7 to 3.6 2 to VDD Zero
MAX5207BEUB 40 2.7 to 3.6 2 to VDD Zero
MAX5204–MAX5207
Low-Cost, Voltage-Output, 16-Bit DACs in µMAX
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
10LUMAX.EPS
PACKAGE OUTLINE, 10L uMAX/uSOP
1
1
21-0061 I
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
1
0.498 REF
0.0196 REF
S
6∞
SIDE VIEW
α
BOTTOM VIEW
0∞0∞6∞
0.037 REF
0.0078
MAX
0.006
0.043
0.118
0.120
0.199
0.0275
0.118
0.0106
0.120
0.0197 BSC
INCHES
1
10
L1
0.0035
0.007
e
c
b
0.187
0.0157
0.114
H
L
E2
DIM
0.116
0.114
0.116
0.002
D2
E1
A1
D1
MIN
-A
0.940 REF
0.500 BSC
0.090
0.177
4.75
2.89
0.40
0.200
0.270
5.05
0.70
3.00
MILLIMETERS
0.05
2.89
2.95
2.95
-
MIN
3.00
3.05
0.15
3.05
MAX
1.10
10
0.6±0.1
0.6±0.1
ÿ 0.50±0.1
H
4X S
e
D2
D1
b
A2 A
E2
E1 L
L1
c
α
GAGE PLANE
A2 0.030 0.037 0.75 0.95
A1
