© Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.
Freescale Semiconductor
Technical Data
The MPC7410 is a PowerPC™ reduced instruct ion set computing
(RISC) m icroprocessor. This document describes pertinent
electrical and physical characteristics of the MPC7410. For
functional characteri stics of the processor, ref er to the MPC7410
RISC Microprocessor User’s Manual.
To locate any publi she d errata or update s f or th is document , r efer
to the web site at http://www.freescale.com.
1Overview
The MPC7410 is the second implementation of the fourth
generation (G4) micr oprocessors from Freescale . The MPC7410
implements the full PowerPC 32-bit architecture and is targeted at
both computing and embedded systems applicat ions.
Some comments on the MPC7410 with respect to the MPC750:
• The MPC7410 adds an implementation of the new
AltiVec™ technology instruction set.
• The MPC7410 includes significant improve ments in
memory subsystem (MSS) ba ndwidth and offers an
optional, high-bandwidth MPX bus interface.
• The MPC7410 adds full ha rdware-base d multipr ocessing
capability, including a five-state cache coherency protocol
(four ME S I stat es plus a fifth stat e fo r sha red
intervention).
MPC7410EC
Rev. 6.1, 11/2007
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Electrical and Thermal Characteristics . . . . . . . . . . . . 7
5. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29
8. System Design Information . . . . . . . . . . . . . . . . . . . 34
9. Document Revision History . . . . . . . . . . . . . . . . . . . 48
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53
MPC7410 RISC Microprocessor
Hardware Specifications
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
2Freescale Semiconductor
Features
• The MPC7410 is implemented in a next generat ion process technology for core fr equenc y improvement.
• The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision
operations involving multiplication.
• The completion queue has been extended to eight slots.
• There are no othe r significant ch anges to scalar pipelines, decode/dispatch/ completi on mechanisms, or the
branch unit. The MPC750 four-st age pipe line model is unchan ged (fetch, decode /dispatch, execute,
complete/writeback).
Some comments on the MPC7410 with respect to the MPC7400:
• The MPC7410 adds configurabl e direct-mapped SRAM capability to the L2 cache inte rface.
• The MPC7410 adds 32-bit inte rface support to the L2 cache interface. The MPC7410 implements a 19th L2
address pin (L2ASPARE on the MPC7400) in order to suppor t additional address range.
• The MPC7410 removes support for 3.3-V I/O on the L2 cache inter face.
Figure 1 shows a block diagra m of the MPC7410.
2Features
This section sum marizes fe atures of the MPC7410 implemen tation of the PowerPC architecture . M ajor feat ures of
the MPC7410 are as follows:
• Branch processi ng unit
— Four instructions fetched per clock
— One branch processed per cycle (plus resol ving two speculat ions)
— Up to one speculative stream in execution, one additiona l speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay
slots
• Dispatch unit
— Full hardware detec tion of dependencie s (re solved in the execut ion units)
— Dispatch two instr uctions to eight independent units (system, br anch, load/stor e, fixed-point uni t 1,
fixed-poin t unit 2, f loating-point, AltiVec permute, AltiVec ALU)
— Serializ ation control (predispatch, postdispatch, execution serialization)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 3
Features
Figure 1. MPC7410 Block Diagram
SRs
(Original)
Additional Features
•Time Base
• Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
+
+
Fetcher Branch Processing
BTIC
(64-Entry)
+ x ÷
FPSCR
VSCR FPSCR
L2CR
CTRLR
PA
EA
+ x ÷
Instruction Unit
Unit
Instruction Queue
(6-Word)
2 Instructions
Reservation
Integer System
Dispatch Unit
64-Bit (2 Instructions)
128-Bit
(4 Instructions)
32-Bit
Floating-
Point Unit
32-Bit
64-Bit
Reservation
Load/Store Unit
(EA Calculation)
Finished
32-Bit
Completion Unit
Completion Queue
(8-Entry)
Ta g s 32-Kbyte
D Cache
Memory Subsystem
Instruction
Data Reload
L2 Controller Bus Interface Unit
L2 Castout
32-Bit Address Bus
64-Bit Data Bus
19-Bit L2 Address Bus
64- or 32-Bit L2 Data Bus
Integer
Station
Reservation
Station
Reservation
Station
Register UnitUnit 1 Unit 2
Reservation
Station FPR File
6 Rename
Buffers
Station (2-Entry)
GPR File
6 Rename
Buffers
VCIU
Vector Vector ALU
Reservation
Station
Reservation
Station
Permute
VR File
6 Rename
Buffers
Unit
64-Bit
Reload Table
VSIU VFPU
128-Bit128-Bit
Ability to Complete Up
Completed
Instruction MMU
SRs
(Shadow)
128-Entry
IBAT
Array
ITLB
BHT
(512-Entry)
L2 Miss Data
Tra n s a ct i on Table
Tag s 32-Kbyte
I Cache
Data Reload
Buffer
Instruction
Reload Buffer
to Two Instructions Per Clock
Data MMU
128-Entry
DBAT
Array
DTLB
Load Fold
L1
Stores
Stores
Operations
L2 Data
Transaction
Vector
To u c h
Queue
L2PMCR
Queue
Queue Queue
L2 Tags
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
4Freescale Semiconductor
Features
• Decode
— Re g ister fi le acce ss
— Forwarding control
— Partial instruction decode
• Completion
— Eight-entry completion buffer
— Instruction tracking and peak completion of two instructions per cycle
— Completion of instr uctions in progr am order while support ing out- of-or der instruction execution,
completion serialization, and all instruction flow changes
• Fixed point units (FXUs) that shar e 32 GPRs for integer operan ds
— Fixed point unit 1 (FXU1)—multiply, divide , shif t, rotat e, arithmetic , logical
— Fixed point unit 2 (FXU2)—shift, r otate, arithmeti c, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-c yc le)
— Early out multiply
• Three-sta ge floating-point unit and a 32- entry FPR file
— Support for IEEE Std 754™ singl e- and double-pre cision floating-point arithmetic
— Three-cycle latency, one-cycle throughput (single- or double-precision)
— Hardware support for divide
— Hardware support for de norma lized numbers
— Time determinist ic non-IEEE mode
• System unit
— Executes CR logical ins tructions and miscellane ous system instru ctions
— Special register transfer instructions
• AltiVec unit
— Full 128-bit data paths
— Two dispatchabl e units: vector pe rmute unit and vector ALU unit.
— Contains its own 32-entry, 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector
complex integer unit ( VCIU) , and the vector floating-point unit (VFPU).
— Fully pipelined
• Load/store unit
— One-cycle load or store cach e access (byte, half wor d, wor d, double word)
— Two-cycle loa d latency with 1-cycle thr oughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycl e unaligned access within double-word bounda ry
— Alignment, zero padding, sign extend fo r integer register file
— Floating-point interna l format conversion (alignment, normalizat ion)
— Sequencing for load/store multiples and string operations
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 5
Features
— Store gathe ring
— Executes the cache and TLB instructions
— Big- and little- endian byte addressing supporte d
— Misaligned lit tle-endi an supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all four archite ct ure AltiVec DST str eams
• Lev el 1 (L1) cache stru ct ure
— 32 Kbyte, 32-byte line, eight-way set-associative instruction cache (iL1)
— 32 Kbyte, 32-byte line, eight-way set- as sociative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transie nt instructions algorithm
— Copy-back or write-through data cache (on a page-per-page basis)
— Supports all PowerPC memory coher ency modes
— Nonblocking inst ruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruct ion cache except for ICBI instruction
• Lev el 2 (L2) cache int erfa ce
— Int ern al L 2 ca che co n troll er and ta gs; ex te rnal da ta SRA M s
— 512-Kbyte, 1-Mbyte, and 2-Mbyte two-way set-associat ive L2 cache support
— Copy-back or write-thr ough data cache (on a page basis, or for all L2)
— 32-byte (512-Kbyte ), 64-byte (1-Mbyte), o r 128-byte (2-Mbyte) sectored line size
— Supports pipelined (register- register) synchronous BurstRAMs and pipelined (register-register) la te
write synchronous BurstRAMs
— Supports dir ec t-mapped mode for 256 Kbyte s, 512 Kbytes, 1 Mbyte, or 2 Mbytes of SRAM (eit her all,
half, or none of L2 SRAM must be configured as direct-mapped)
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64-bit data bus which also supports 32-bit bus mode
— Selectable interface voltages of 1.8 and 2.5 V
• Memory management unit
— 128-entry, two-way set-associative instruction TLB
— 128-entry, two-way set-associative data TLB
— Hard w a re rel oad fo r TLB s
— Four instruction BATs and four data BATs
— Virtua l memory support for up to 4 h exabytes (252) of virtual memory
— Real memory support for up to 4 gigabytes (232) of physical memory
— Snooped a nd invalidated for TLBI instructions
• Efficient data flow
— All data buses be tween VRF, loa d/store unit, dL1, iL1, L2, and the bus are 128 bits wide
— dL1 is fully pipe lined to provide 128 bits/cycle to/from the VRF
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
6Freescale Semiconductor
Features
— L2 is fully pipe lined to provide 128 bits per L2 clock cycle to the L1s.
— Up to e ight outstanding, out-of-order, cache misses between dL1 and L2/bus
— Up to seven outstanding, out-of-order transactions on the bus
— Load folding to fold new dL1 misses into olde r, outstanding load and store misses to the same line
— Store miss mer ging for multiple store misse s to the same line. Only coherenc y action taken (that is,
address only) for stor e misses merged to all 32 bytes of a cache line (no data tenure needed).
— Two -entry finishe d store queue and four-entry completed stor e queue between load/store unit and dL1
— Separa te addi tional queues for ef fici ent buf fering of outbound data ( casto uts, write thro ughs, and so on)
from dL1 and L2
• Bus interface
— MPX bus extension to 60x processor inte r face
— Mode-compatible with 60x processor interface
— 32-bit address bus
— 64-bit data bus
— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3. 5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x
supported
— Se le ctab l e interf ace v o ltages of 1.8, 2.5, an d 3. 3 V
• Power management
— Low-power design with thermal requirements very similar to MPC740 and MPC750
— Low-voltage proc essor core
— Selectable interface voltages can reduce power in output buffers
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management
• Testability
— LSSD scan design
— IEEE Std 1149.1™ JTAG interface
— Array built-in se lf test (ABIST)—factory test only
— Redundancy on L1 data arrays and L2 tag arrays
• Reliability and serviceability
— Parity checking on 60x and L2 cache buses
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 7
General Parameters
3 General Parameters
The following list provides a summary of the general pa ramete rs of the MPC7410:
Technology 0.18 µm CMOS, six-layer metal
Die size 6.32 mm × 8.26 mm (52 mm2)
Transistor co unt 10.5 million
Logic design Fully static
Packages Surface mount 360 ceramic ball gri d array ( CBGA)
Surface mount 360 high coefficient of thermal expansion ceramic ball grid array
(HCTE_CBGA)
Surface mount 360 high coeffic ient of thermal e xpa nsion cerami c ball grid array with
lead free C5 sp heres (H CTE _ C BGA L ead Free C5 Sph ere s)
Surface mount 360 high coefficient of thermal expansion ceramic land grid array
(HCTE_LGA)
Core power supply 1.8 V ± 100 mV DC (nominal; see Table 3 for recommended operat ing conditio ns)
I/O power supply 1.8 V ± 100 mV DC or
2.5 V ± 100 mV
3.3 V ± 165 mV (system bus only)
(input thresholds are configuration pin se lectable)
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical spec ificat ions and thermal characteris tics for the MPC7410.
4.1 DC Electrical Characteristics
The tables in this sect ion describe the MPC7410 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic Symbol Maximum Value Unit Notes
Core supply voltage VDD –0.3 to 2.1 V 4
PLL supply voltage AVDD –0.3 to 2.1 V 4
L2 DLL supply voltage L2AVDD –0.3 to 2.1 V 4
Processor bus supply voltage OVDD –0.3 to 3.6 V 3, 6
L2 bus supply voltage L2OVDD –0.3 to 2.8 V 3
Input voltage Processor bus Vin –0.3 to OVDD + 0.2 V V 2, 5
L2 bus Vin –0.3 to L2OVDD + 0.2 V V 2, 5
JTAG signals Vin –0.3 to OVDD + 0.2 V V —
Storage temperature range Tstg –55 to 150 °C —
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
8Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 2 shows the allowa ble undershoo t and overs hoot voltage for the MPC7410.
Figure 2. Overshoot/Undershoot Voltage
The MPC7410 provides several I/ O voltages to support both compatibil ity with existing systems and migration to
future systems. The MPC7410 core voltage must always be provided at nominal volt age (see Table 3 for actual
recommended cor e volt age) . Voltage t o the L2 I/Os and process or int erface I/Os are provi ded through separate sets
of supply pins and may be provided at the volt ages shown in Table 2. Voltage must be provided to the L2OVDD
power pins even if the interface is not used. The input voltage thr eshold for each bus is selected by sampling the
state of the voltage se lect pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must
remain stable dur ing part operation and cannot cha nge. The output volt age will swing from GND t o the maximum
voltage applied to the OVDD or L2OVDD power pins.
Rework temperature Trwk 260 °C —
Notes:
1. Functional and tested operating conditions are given in Ta bl e 3 . Absolute maximum ratings are stress ratings only,
and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.2 V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V at any time including during
power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down
sequences.
5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
6. M
xx
7410
xxnnn
LE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a maximum
value OVDD of –0.3 to 2.8 V.
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic Symbol Maximum Value Unit Notes
VIH
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
(L2)OVDD + 20%
VIL
(L2)OVDD
(L2)OVDD + 5%
of tSYSCLK (OVDD)
or tL2CLK (L2OVDD)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 9
Electrical and Thermal Characteristics
Table 3 provides the recommended operating conditions for the MPC7410.
Table 2. Input Threshold Voltage Setting
BVSEL Signal 3 Processor Bus Input
Threshold is Relative to: L2VSEL Signal 3 L2 Bus Input Threshold is
Relative to: Notes
0 1.8 V 0 1.8 V 1
HRESET 2.5 V HRESET 2.5 V 1, 2
1 3.3 V 1 2.5 V 1, 4, 5
¬HRESET 3.3 V ¬HRESET Not Supported 6
Notes:
1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied.
2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals
change state together. This is the preferred method for selecting this mode of operation.
3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used.
4. Default voltage setting if left unconnected (internal pulled-up). MPC7410RX
nnn
LE (Rev 1.4) and later only.
Previous revisions do not support 3.3 V OVDD; the default voltage setting if left unconnected is 2.5 V.
5. M
xx
7410
xxnnn
LE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD; having BVSEL = 1 selects
the 2.5-V threshold.
6. M
xx
7410
xxnnn
LE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. (¬HRESET is
the inverse of HRESET
.)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
10 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 4 provides the package thermal characteristics for the M PC7410.
Table 3. Recommended Operating Conditions 1
Characteristic Symbol Recommended
Value Unit Notes
Core supply voltage VDD 1.8 V ± 100 mV V —
PLL supply voltage AVDD 1.8 V ± 100 mV V —
L2 DLL supply voltage L2AVDD 1.8 V ± 100 mV V —
Processor bus supply
voltage
BVSEL = 0 OVDD 1.8 V ± 100 mV V —
BVSEL = HRESET OVDD 2.5 V ± 100 mV V —
BVSEL = ¬HRESET or
BVSEL = 1
OVDD 3.3 V ± 165 mV V 2, 3
L2 bus supply voltage L2VSEL = 0 L2OVDD 1.8 V ± 100 mV V —
L2VSEL = HRESET or
L2VSEL = 1
L2OVDD 2.5 V ± 100 mV V —
Input voltage Processor bus and
JTAG signals
Vin GND to OVDD V—
L2 bus Vin GND to L2OVDD V—
Die-junction temperature Tj0 to 105 °C —
Notes:
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
2. M
xx
7410
xxnnn
LE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OVDD and have a
recommended OVDD value of 2.5 V ± 100 mV for BVSEL = 1.
3. M
xx
7410
xxnnn
LE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET.
Table 4. Package Thermal Characteristics
Characteristic Symbol
Value
Unit Notes
MPC7410
CBGA
MPC7410
HCTE
Junction-to-ambient thermal resistance, natural convection,
four-layer (2s2p) board
RθJMA 18 20 °C/W 1, 2
Junction-to-ambient thermal resistance, 1m/sec airflow,
four-layer (2s2p) board
RθJMA 14 16 °C/W 1, 2
Junction-to-ambient thermal resistance, 2m/sec airflow,
four-layer (2s2p) board
RθJMA 13 15 °C/W 1, 2
Junction-to-board thermal resistance RθJB 911°C/W3
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 11
Electrical and Thermal Characteristics
Table 5 provides the DC electrical characteristics for the MPC7410.
Junction-to-case thermal resistance RθJC < 0.1 < 0.1 °C/W 4
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4. Thermal resistance between the active portion of the die and the calculated case temperature at the top of the die.
The actual value of R JC is less than 0.1 °C/W.
Note: Refer to Section 8.8, “Thermal Management Information,” for details on thermal management.
Table 5. DC Electrical Specifications
At recommended operating conditions (see Ta bl e 3 )
Characteristic
Nominal
Bus
Vo lt ag e 1
Symbol Min Max Unit Notes
Input high voltage (all inputs except
SYSCLK)
1.8 VIH 0.65 × (L2)OVDD (L2)OVDD + 0.2 V 2, 3, 8
2.5 VIH 1.7 (L2)OVDD + 0.2
3.3 VIH 2.0 OVDD + 0.3
Input low voltage (all inputs except
SYSCLK)
1.8 VIL –0.3 0.35 × (L2)OVDD V8
2.5 VIL –0.3 0.2 × (L2)OVDD
3.3 VIL –0.3 0.8
SYSCLK input high voltage 1.8 CVIH 1.5 OVDD + 0.2 V 2, 8
2.5 CVIH 2.0 OVDD + 0.2
3.3 CVIH 2.4 OVDD + 0.3
SYSCLK input low voltage 1.8 CVIL –0.3 0.2 V 8
2.5 CVIL –0.3 0.4
3.3 CVIL –0.3 0.4
Input leakage current,
Vin = L2OVDD/OVDD
1.8 Iin —20µA2, 3,
6, 7
2.5 Iin —35
3.3 Iin —70
Table 4. Package Thermal Characteristics (continued)
Characteristic Symbol
Value
Unit Notes
MPC7410
CBGA
MPC7410
HCTE
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
12 Freescale Semiconductor
Electrical and Thermal Characteristics
High-Z (off-state) leakage current,
Vin = L2OVDD/OVDD
1.8 ITSI —20µA2, 3,
5, 7
2.5 ITSI —35
3.3 ITSI —70
Output high voltage, IOH = –5 mA 1.8 VOH (L2)OVDD – 0.45 — V 8
2.5 VOH 1.7 —
3.3 VOH 2.4 —
Output low voltage, IOL = 5 mA 1.8 VOL —0.45V8
2.5 VOL —0.4
3.3 VOL —0.4
Capacitance, Vin = 0 V, f = 1 MHz Cin — 6.0 pF 3, 4, 7
Notes:
1. Nominal voltages; see Table 3 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
3. Excludes factory test signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same
direction (for example, both OVDD and L2OVDD vary by either +5% or –5%).
6. Measured at max OVDD/L2OVDD.
7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.
8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of
1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by
the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR
or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,
there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a
SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET
.
Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST
or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.
Table 5. DC Electrical Specifications (continued)
At recommended operating conditions (see Ta bl e 3 )
Characteristic
Nominal
Bus
Vo lt ag e 1
Symbol Min Max Unit Notes
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 13
Electrical and Thermal Characteristics
Table 6 provides the power consumption for the MPC7410.
4.2 AC Electrical Characteristics
This section provides the AC electrica l char acteristics for the MPC7410. After fabrica tion, funct ional parts are
sorted by maximum processor core fre quency, see Section 4.2.1, “Clock AC Specifications,” and te sted for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core
frequency; see Section 10, “Orde ring Information.”
Table 6. Power Consumption for MPC7410
Processor (CPU) Frequency
Unit Notes
400 MHz 450 MHz 500 MHz
Full-On Mode
Typical 4.2 4.7 5.3 W 1, 3
Maximum 9.5 10.7 11.9 W 1, 2
Doze Mode
Maximum 4.3 4.8 5.3 W 1
Nap Mode
Maximum 1.35 1.5 1.65 W 1
Sleep Mode
Maximum 1.3 1.45 1.6 W 1
Sleep Mode—PLL and DLL Disabled
Typical 600 600 600 mW 1
Maximum 1.1 1.1 1.1 W 1
Notes:
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD
and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but
is typically <5% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD =15 mW.
2. Maximum power is measured at 105°C and VDD = 1.8 V while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, including AltiVec, maximally busy.
3. Typical power is an average value measured at 65°C and VDD = 1.8 V in a system while running typical benchmarks.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
14 Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.1 Clock AC Specifications
Table 7 provides the clock AC timing specifications as defined in Figure 3.
Figure 3 provides the SYSCLK input timing diagra m.
Figure 3. SYSCLK Input Timing Diagram
Table 7. Clock AC Timing Specifications
At recommended operating conditions (see Ta bl e 3 )
Characteristic Symbol
Maximum Processor Core Frequency
Unit Notes400 MHz 450 MHz 500 MHz
Min Max Min Max Min Max
Processor frequency fcore 350 400 350 450 350 500 MHz 1
VCO frequency fVCO 700 800 700 900 700 1000 MHz 1
SYSCLK frequency fSYSCLK 33 133 33 133 33 133 MHz 1
SYSCLK cycle time tSYSCLK 7.5 30 7.5 30 7.5 30 ns —
SYSCLK rise and fall time tKR and tKF — 0.5 — 0.5 — 0.5 ns/V 2
SYSCLK duty cycle
measured at OVDD/2
tKHKL/tSYSCLK 40 60 40 60 40 60 % 3
SYSCLK jitter — — ±150 — ±150 — ±150 ps 4
Internal PLL-relock time — — 100 — 100 — 100 μs5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, “PLL Configuration,” for valid PLL_CFG[0:3]
settings.
2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a result, the
0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-V bus interface.
Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from 0.2 to 1.2 V) in 0.5 ns for the
1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change (from 0.4 to 2.4 V) in 1 ns.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL
lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when
the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
SYSCLK VMVMVM CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
t
KR
tKF
tKHKL
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 15
Electrical and Thermal Characteristics
4.2.2 Processor Bus AC Specifications
Table 8 provides the proc essor bus AC timing specifi cations for the M PC7410 as def ine d in Figure 4 and Figure 5.
Timing specifi cations for the L2 bus are provide d in Section 4.2.3, “L2 Clock AC Specifications.”
Table 8. Processor Bus AC Timing Specifications 1
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol 2
400, 450, 500 MHz
Unit Notes
Min Max
Input setup tIVKH 1.0 — ns 4
Input hold tIXKH 0—ns4
Output valid times:
TS
ARTRY
, SHD0, SHD1
All other outputs
tKHTSV
tKHARV
tKHOV
—
—
—
3.0
2.3
3.0
ns 5, 6
Output hold times:
TS
ARTRY
, SHD0, SHD1
All other outputs
tKHTSX
tKHARX
tKHOX
0.5
0.5
0.5
—
—
—
ns 5
SYSCLK to output enable tKHOE 0.5 — ns 9
SYSCLK to output high impedance (all except ABB/AMON(0),
ARTRY/SHD, DBB/DMON(0), SHD0, SHD1)
tKHOZ —3.5ns
SYSCLK to ABB/AMON(0), DBB/DMON(0) high impedance after
precharge
tKHABPZ —1t
SYSCLK 3, 7, 9
Maximum delay to ARTRY
, SHD0, SHD1 precharge tKHARP —1t
SYSCLK 3, 8, 9
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
16 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 4 provides the AC te st load for the MPC7410.
Figure 4. AC Test Load
SYSCLK to ARTRY, SHD0, SHD1 high impedance after precharge tKHARPZ —2t
SYSCLK 3, 8, 9
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V)
relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from
SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that
the input signal (I) went invalid (X) with respect to the rising clock edge (KH)— note the position of the reference and its state
for inputs—and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period
of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. Includes mode select signals: BVSEL, EMODE, L2VSEL. See Figure 5 for mode select timing with respect to HRESET
.
5. All other output signals are composed of the following— A[0:31], AP[0:3], TT[0:4], TS, TBST, TSIZ[0:2], GBL, WT, CI,
DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.
6. Output valid time is measured from 2.4 to 0.8 V which may be longer than the time required to discharge from VDD to 0.8 V.
7. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low
then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for ABB or DBB is 0.5
× tSYSCLK, that is, less than the minimum tSYSCLK period, to ensure that another master asserting ABB, or DBB on the
following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted.
Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.
8. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting
it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle
after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high-Z as shown in
Figure 6 before the first opportunity for another master to assert ARTRY
. Output valid and output hold timing are tested for
the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.
9. Guaranteed by design and not tested.
Table 8. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol 2
400, 450, 500 MHz
Unit Notes
Min Max
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 17
Electrical and Thermal Characteristics
Figure 5 provides the mode select input ti ming diagr am for the MPC7410. The mode s elect input s are sampl ed
twice, once before and once a fter HRESET negation.
Figure 5. Mode Input Timing Diagram
Figure 6 provides the input/output timing diagra m for the MPC7410.
Figure 6. Input/Output Timing Diagram
HRESET
Mode Signals
VM = Midpoint Voltage (OVDD/2)
SYSCLK
First sample Second sample
VM VM
SYSCLK
All Inputs
VM
VM = Midpoint Voltage (OVDD/2)
All Outputs
tKHOX
VM
(Except TS, ABB,
ARTRY
, DBB)
All Outputs
TS,
ARTRY
,
ABB/AMON(0),
(Except TS, ABB,
ARTRY
, DBB)
DBB/DMON(0)
VM
tkhoe
tKHOZ
tKHABPZ
tKHARPZ
tKHARP
SHD1
SHD0,
tKHOV
tIXKH
tKHTSX
tKHTSV
tKHTSV
tKHARV
tKHARX
tKHARV
tIVKH
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
18 Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.3 L2 Clock AC Specifications
The L2CLK frequ ency is programmed b y the L2 Configuration Register (L2CR[4:6] ) core-t o-L2 div isor ratio. See
Table 14 for example core and L2 frequencies at various divisors. Table 9 provides the potential range of L2C LK
output AC timing specifi cations as defined in Figure 7.
The L2SYNC_OUT signal is int ended to be r outed halfway out to t he SRAMs and then returne d to the L2SYNC_IN
input of the MPC7410 to synchronize L2CLK_OUT at the SRAM with the processor’s internal clock. L2CLK_OUT
at the SRAM can be o ff set for ward or back ward in ti me by shorte ning or lengthe nin g the rout ing of L2SYNC_OUT
to L2SYNC_IN. See Freescale Application Note AN1794, Backside L2 Timing Analy sis for the PCB Des ign
Engineer.
The minimum L2CLK frequency in Table 9 is specified by the maximum delay of the internal DLL. The variable-tap
DLL intro duces up to a fu ll clock period delay in th e L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT signals
so tha t the retur ning L2SYNC_I N signal is phase-a ligned wit h the nex t core cloc k (divide d by the L2 div isor r atio).
Do not c hoose a core-to-L2 divisor that resul ts in an L2 f requency below thi s minimu m, or the L2CLK_OUT signal s
provided for SRAM clocking will not be phase-alig ned with the MPC7410 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 9 is the core f requency divided by one. Very few L2 SRAM
desig ns will be able to ope rate in this mode. Most design s will se lect a grea ter cor e-to-L2 divi sor to provide a longer
L2CLK per iod for read and wr it e access to the L2 SRAMs. The maxi mum L2CLK fr equency for any a pplicati on of
the MPC7410 will be a function of the AC timings of the MPC7410, the AC timings for the SRAM, bus loading,
and printed-ci rcuit board trace length.
Freescale is similarly limited by syste m constraints and cannot pe rform test s of the L2 interface on a sockete d part
on a functional test er at the maximum frequencies in Table 9. Therefore, functional operation and AC timing
information are tested at core-to-L2 divisors of two or greater.
L2 input and output signals are latched or enabled, r espectively, by the inte rnal L2C LK (which is SYSCLK
multiplied up to the core frequency and di vided down to the L2CLK frequency) . In other words, the AC timings in
Table 10 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through
the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output pha se of L2CLK_OUTA and
L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since in a close d loop system
L2S Y N C_ IN is held in phase -a l ig n m ent w ith the i n ter nal L2 CL K , the sig nals in Table 10 are referenced to this
signal rather than the not- externally-visible internal L2CLK. During manufac turing test, these times are actually
measured relative to SYS CLK.
Table 9. L2CLK Output AC Timing Specifications
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol
400 MHz 450 MHz 500 MHz
Unit Notes
Min Max Min Max Min Max
L2CLK frequency fL2CLK 133 400 133 400 133 400 MHz 1, 4
L2CLK cycle time tL2CLK 2.5 7.5 2.5 7.5 2.5 7.5 ns —
L2CLK duty cycle tCHCL/tL2CLK 50 50 50 % 2
Internal DLL-relock time — 640 — 640 — 640 — L2CLK 3
DLL capture window — 0 10 0 10 0 10 ns 5
L2CLK_OUT
output-to-output skew
tL2CSKW —50—50—50ps 6
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 19
Electrical and Thermal Characteristics
The L2CLK_OUT timing diagram is shown in Figure 7.
Figure 7. L2CLK_OUT Output Timing Diagram
L2CLK_OUT output jitter — — ±150 — ±150 — ±150 ps 6
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core
frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their
respective maximum or minimum operating frequencies. The maximum L2CLK frequency will be system
dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL-relock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of
L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. This adds more delay to each tap of
the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward
or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between
L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter
on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already
comprehended in the AC timing and does not have to be considered in the L2 timing analysis.
Table 9. L2CLK Output AC Timing Specifications (continued)
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol
400 MHz 450 MHz 500 MHz
Unit Notes
Min Max Min Max Min Max
VM = Midpoint Voltage (L2OVDD/2)
L2CLK_OUTA
L2CLK_OUTB
L2 Differential Clock Mode
L2 Single-Ended Clock Mode
L2SYNC_OUT
tL2CLK
tCHCL
L2CLK_OUTA VM
tL2CR tL2CF
VM
VMVM
L2CLK_OUTB
VMVM
VM
VM
VM
tL2CLK
tCHCL
L2SYNC_OUT
VM VM VM
VM VM VM
VM
VM
tL2CSKW
VM
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
20 Freescale Semiconductor
Electrical and Thermal Characteristics
4.2.4 L2 Bus AC Specifications
Table 10 provides the L2 bus inter face AC timing specif ications for the MPC7410 as defined in Figure 8 and
Figure 9 for the loading c onditions described in Figure 10.
Table 10. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol
400, 450, 500 MHz
Unit Notes
Min Max
L2SYNC_IN rise and fall time tL2CR and tL2CF —1.0ns1
Setup times: Data and parity tDVL2CH 1.5 — ns 2
Input hold times: Data and parity tDXL2CH —0.0ns2
Valid times:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOV
—
—
—
—
2.5
2.5
2.9
3.5
ns 3, 4
Output hold times
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOX
0.4
0.8
1.2
1.6
—
—
—
—
ns 3
L2SYNC_IN to high impedance:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOZ
—
—
—
—
2.0
2.5
3.0
3.5
ns —
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD
.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-Ω load (see Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs,
L2CR[14–15] = 10 is recommended.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 21
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing dia grams for the MPC7410.
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing dia grams for the MPC7410.
Figure 9. L2 Bus Output Timing Diagrams
Figure 10 provid es the AC test load for L2 interfa ce of the MPC7410.
Figure 10. AC Test Load for the L2 Interface
4.2.5 IEEE 1149.1 AC Timing Specifications
Table 11 provides the IEEE 1149.1 ( JTAG) AC timing specifications as defined in Figure 12 through Figure 15.
Table 11. JTAG AC Timing Specifications (Independent of SYSCLK) 1
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol Min Max Unit Notes
TCK frequency of operation fTCLK 0 33.3 MHz —
TCK cycle time t TCLK 30 — ns —
TCK clock pulse width measured at OVDD/2 tJHJL 15 — ns —
TCK rise and fall times tJR and tJF 02ns—
L2SYNC_IN VM
VM = Midpoint Voltage (L2OVDD/2)
tDVL2CH tDXL2CH
tL2CR tL2CF
L2 Data and
Inputs
Data Parity
Output Z0 = 50 ΩL2OVDD/2
RL = 50 Ω
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
22 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 provides the AC test load for TDO and the boundary- scan outputs of the MPC7410.
Figure 11. Alternate AC Test Load for the JTAG Interface
Figure 12 provid es the JTAG clock input tim ing diagram.
Figure 12. JTAG Clock Input Timing Diagram
TRST assert time tTRST 25 — ns 2
Input setup times:
Boundary-scan data
TMS, TDI
tDVJ H
tIVJH
4
0
—
—
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
tDXJH
tIXJH
20
25
—
—
ns
3
Valid times:
Boundary-scan data
TDO
tJLDV
tJLOV
4
4
20
25
ns
4
TCK to output high impedance:
Boundary-scan data
TDO
tJLDZ
tJLOZ
3
3
19
9
ns
4, 5
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Table 11. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions (see Ta bl e 3 )
Parameter Symbol Min Max Unit Notes
Output Z0 = 50 ΩOVDD/2
RL = 50 Ω
TCLK VMVMVM
VM = Midpoint Voltage (OVDD/2)
tTCLK
tJR tJF
tJHJL
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 23
Electrical and Thermal Characteristics
Figure 13 provid es the TRST timing diagram.
Figure 13. TRST Timing Diagram
Figure 14 provid es the boundary-s can tim ing diagram.
Figure 14. Boundary-Scan Timing Diagram
Figure 15 provid es the test access port timing diagra m.
Figure 15. Test Access Port Timing Diagram
TRST
tTRST
VM = Midpoint Voltage (OVDD/2)
VM VM
VMTCK
Boundary
Boundary
Boundary
Data Outputs
Data Inputs
Data Outputs
VM = Midpoint Voltage (OVDD/2)
tDXJH
tDVJH
tJLDV
tJLDZ
Input
Data Valid
Output Data Valid
Output Data Valid
tJLDX
VM
VM
TCK
TDI, TMS
TDO Output Data Valid
VM = Midpoint Voltage (OVDD/2)
tIXJH
tIVJH
tJLOV
tJLOZ
Input
Data Valid
TDO Output Data Valid
tJLOX
VM
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
24 Freescale Semiconductor
Pin Assignments
5 Pin Assignments
Figure 16, part A shows t he pinout f or the MPC7410, 360 CBGA, 360 HCTE, and 360 HCTE Lead Free C5 Spher es
packages as viewed from the top surface. Figure 16, part B shows t he sid e profile of t he CBGA and HC TE_CBGA
packages to indicate the direction of the top surface view. Figure 16, part C shows the side profile of the
HCTE_LGA package to indicate the direc tion of the top surface view.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Not to Scale
17 18 19
U
V
W
Part A
View
Part B
Die
Substrate Assembly
Encapsulant
BGA Package
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 25
Pinout Listings
Figure 16. Pinout of the MPC7410, 360 CBGA and 360 HCTE Packages
as Viewed from the Top Surface
6 Pinout Listings
Table 12 provides the pin out listing for the MPC7410 360 CBGA, 360 HCTE packages.
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages
Signal Name Pin Number Active I/O I/F Select 1Notes
A[0:31] A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3,
G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3,
J2, J6, K3, K2, L2
High I/O BVSEL
AACK N3 Low Input BVSEL —
ABB L7 Low Output BVSEL 12, 16
AP[0:3] C4, C5, C6, C7 High I/O BVSEL —
ARTRY L6 Low I/O BVSEL —
AVDD A8 — Input VDD —
BG H1 Low Input BVSEL —
BR E7 Low Output BVSEL —
BVSEL W1 High Input N/A 1, 3, 8,
9, 14
CHK K11 Low Input BVSEL 2, 8, 9
CI C2 Low I/O BVSEL —
CKSTP_IN B8 Low Input BVSEL —
CKSTP_OUT D7 Low Output BVSEL —
CLK_OUT E3 High Output BVSEL —
DBB K5 Low Output BVSEL 12, 16
DBG K1 Low Input BVSEL —
DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9,
W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4,
P7, V5, V4, W3, U4, R5
High I/O BVSEL —
View
Part C
Die
Substrate Assembly
Encapsulant
LGA Package
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
26 Freescale Semiconductor
Pinout Listings
DL[0:31] M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12,
P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1,
V1, U1, N1, R2, V3, U3, W2
High I/O BVSEL —
DP[0:7] L1, P2, M2, V2, M1, N2, T3, R1 High I/O BVSEL —
DRDY K9 Low Output BVSEL 6, 8, 13
DBWO
DTI[0]
D1 Low Input BVSEL —
DTI[1:2] H6, G1 High Input BVSEL 5, 10, 13
EMODE A3 Low Input BVSEL 7, 10
GBL B1 Low I/O BVSEL —
GND D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16,
G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10,
K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11,
P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16
—— N/A—
HIT B5 Low Output BVSEL 6, 8
HRESET B6 Low Input BVSEL —
INT C11 Low Input BVSEL —
L1_TSTCLK F8 High Input BVSEL 2
L2ADDR[0:16] L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16,
H18, H17, J14, J13, H19, G18
High Output L2VSEL —
L2ADDR[17:18] K19,W19 High Output L2VSEL 8
L2AVDD L13 — Input VDD —
L2CE P17 Low Output L2VSEL —
L2CLK_OUTA N15 High Output L2VSEL —
L2CLK_OUTB L16 High Output L2VSEL —
L2DATA[0:63] U14, R13, W14, W15, V15, U15, W16, V16, W17, V17,
U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17,
R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18,
H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18,
E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18,
A17, A16, B16, C16, A14, A15, C15, B14, C14, E13
High I/O L2VSEL —
L2DP[0:7] V14, U16, T19, N18, H14, F17, C19, B15 High I/O L2VSEL —
L2OVDD D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16,
T15, F15
—— N/A11
L2SYNC_IN L14 High Input L2VSEL —
L2SYNC_OUT M14 High Output L2VSEL —
L2_TSTCLK F7 High Input BVSEL 2
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 27
Pinout Listings
L2VSEL A19 High Input N/A 1, 3, 8,
9, 14
L2WE N16 Low Output L2VSEL —
L2ZZ G17 High Output L2VSEL —
LSSD_MODE F9 Low Input BVSEL 2
MCP B11 Low Input BVSEL 15
OVDD D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,
R6, R9, R11, T5, T8, T12
—— N/A—
PLL_CFG[0:3] A4, A5, A6, A7 High Input BVSEL 4
QACK B2 Low Input BVSEL —
QREQ J3 Low Output BVSEL —
RSRV D3 Low Output BVSEL —
SHD0 B3 Low I/O BVSEL 8
SHD1 B4 Low I/O BVSEL 5, 8
SMI A12 Low Input BVSEL —
SRESET E10 Low Input BVSEL —
SYSCLK H9 — Input BVSEL —
TA F1 Low Input BVSEL —
TBEN A2 High Input BVSEL —
TBST A11 Low Output BVSEL —
TCK B10 High Input BVSEL —
TDI B7 High Input BVSEL 9
TDO D9 High Output BVSEL —
TEA J1 Low Input BVSEL —
TMS C8 High Input BVSEL 9
TRST A10 Low Input BVSEL 9
TS K7 Low I/O BVSEL —
TSIZ[0:2] A9, B9, C9 High Output BVSEL —
TT[0:4] C10, D11, B12, C12, F11 High I/O BVSEL —
WT C3 Low I/O BVSEL —
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
28 Freescale Semiconductor
Pinout Listings
VDD G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 — — N/A —
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and
L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT)
and the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become
AVDD and L2AVDD
, respectively). These columns serve as a reference for the nominal voltage supported on a given signal
as selected by the BVSEL/L2VSEL pin configurations of Ta bl e 2 and the voltage supplied. For actual recommended value
of Vin or supply voltages, see Table 3.
2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD,
GND, HRESET
, or ¬HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The default selection, if
L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports 3.3-, 2.5-, and 1.8-V options.
The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to Ta b l e 2 for supported BVSEL and L2VSEL
settings.
4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or during sleep
mode and must adhere to the internal PLL-relock time requirement.
5. Ignored input in 60x bus mode.
6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.
7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for MPX bus
mode.
8. Uses one of nine existing no connects in the MPC750 360 BGA package.
9. Internal pull up on die. Pulled-up signals are VDD based.
10.Reuses MPC750 DRTRY
, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).
11.The VOLTDET pin position on the MPC750 360 BGA package is now an L2OVDD pin on the MPC7410 360 package.
12.Output only for MPC7410, was I/O for MPC750.
13.MPX bus mode only.
14.If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down
resistance less than 250 Ω should be used.
15.MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to
guarantee that it is latched by the processor.
16.In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a requirement
of the MPX bus protocol and may not be available on future products.
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name Pin Number Active I/O I/F Select 1Notes
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 29
Package Description
7 Package Description
The following sections provide the package para meters and mechan ical dimensions for the MPC7410, 360 CBGA
and 360 HCTE packa ges.
7.1 Package Parameters for the MPC7410, 360 CBGA and
360 HCTE_CBGA
The package parameters are as provided in the following list. The package types are the 25 ×25 mm, 360-lead
ceramic ball grid array package (CBGA) or the 25 ×25 mm, 360-le ad hig h coef fic ient of th ermal expansi on CBGA
pac kage (HCTE_CBGA).
Pack ag e ou tli ne 25 × 25 mm
Interconnects 360 (19 × 19 ball arr ay – 1)
Pitch 1.27 mm (50 mil)
Minimum modul e height 2.72 mm
Maximum module height 3.20 mm
Ball diameter 0.89 mm (35 mil)
Coeffic ient of thermal expansion 6.8 ppm/°C (CBGA)
12.3ppm /°C (HCTE_CBGA)
7.2 Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead
Free C5 Spheres)
The package parameters are as listed here. The package types are the 25 ×25 mm, 360-lead high coef ficie nt of
thermal expansion CBGA packag e with lead-free C5 spheres (HCTE_CBGA lead-free spheres).
Pack ag e ou tli ne 25 × 25 mm
Interconnects 360 (19 × 19 ball arr ay – 1)
Pitch 1.27 mm (50 mil)
Minimum modul e height 2.32 mm
Maximum module height 2.80 mm
Ball diameter 0.76 mm (30 mil)
Coeffic ient of thermal expansion 12.3ppm/°C
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
30 Freescale Semiconductor
Package Description
7.3 Mechanical Dimensions for the MPC7410, 360 CBGA and
360 HCTE_CBGA
Figure 17 provides t he mechan ical dimensions and bottom surfa ce nomenclature of the M PC7410, 360 CBGA a nd
360 HCTE_CBGA packages.
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,
360 CBGA and 360 HCTE_CBGA Packages
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
BALL MISSING FROM THE ARRAY.
Millimeters
DIM MIN MAX
A 2.72 3.20
A1 0.80 1.00
A2 1.10 1.30
A3 — 0.60
A4 0.82 0.90
b 0.82 0.93
D 25.00 BSC
D2 — 12.50
D4 6.00 9.00
e1.27 BSC
E 25.00 BSC
E2 — 14.30
E4 8.00 11.00
F 22.86 BSC
K1 — 9.75
K2 6.46 —
K3 8.20 8.60
K4 2.75 —
L1 — 9.50
L2 6.94 —
L3 3.10 3.30
L4 3.00 —
A
A1
A2
C
0.15 C
0.25 C
//
0.35 C
//
A3
A4
BC
360X
e
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A0.3
C
0.15
b
171819
U
W
V
F
F
0.2
D
2X
A1 CORNER
EE2
D2
0.2
2X
B
A
E4
D4
K1
K2
L1
L2
K3
L3
Capacitor Region
K4
L4
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 31
Package Description
7.4 Mechanical Dimensions for the MPC7410, 360 HCTE_CBGA
(Lead Free C5 Spheres)
Figure 18 provid es the mechanical dimensions and bottom surface nomenclature of the MPC7410,
360 HCTE_CBGA (le ad-fre e C5 spheres ) package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410
360 HCTE_CBGA (Lead-Free C5 Spheres) Package
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
BALL MISSING FROM THE ARRAY.
Millimeters
DIM MIN MAX
A 2.32 2.80
A1 0.40 0.60
A2 1.10 1.30
A3 — 0.60
A4 0.82 0.90
b 0.60 0.90
D 25.00 BSC
D2 — 12.50
D4 6.00 9.00
e1.27 BSC
E 25.00 BSC
E2 — 14.30
E4 8.00 11.00
F 22.86 BSC
K1 — 9.75
K2 6.46 —
K3 8.20 8.60
K4 2.75 —
L1 — 9.50
L2 6.94 —
L3 3.10 3.30
L4 3.00 —
A
A1
A2
C
0.15 C
0.25 C
//
0.35 C
//
A3
A4
BC
360X
e
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A0.3
C
0.15
b
171819
U
W
V
F
F
0.2
D
2X
A1 CORNER
EE2
D2
0.2
2X
B
A
E4
D4
K1
K2
L1
L2
K3
L3
Capacitor Region
K4
L4
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
32 Freescale Semiconductor
Package Description
7.5 Package Parameters for the MPC7410, 360 HCTE_LGA
The package parameters are as listed here. The package type is the 25 ×25 mm, 360 high coefficie nt of thermal
expansion LGA package (HCTE_LGA).
Pack ag e ou tli ne 25 × 25 mm
Interconnects 360 (19 × 19 land arr ay – 1)
Pitch 1.27 mm (50 mil)
Minimum modul e height 1.92 mm
Maximum module height 2.20 mm
Coeffic ient of thermal expansion 12.3ppm/°C
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 33
Package Description
7.5.1 Mechanical Dimensions for the MPC7410, 360 HCTE_LGA
Figure 19 provides th e mechanical dim ensions and bottom surface nomencla ture of the M PC7410, 360 HCTE_LGA
package.
Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,
360 HCTE_LGA Package
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
METALIZED FEATURE WITH
VARIOUS SHAPES. BOTTOM SIDE A1
CORNER IS DESIGNATED WITH A
PAD MISSING FROM THE ARRAY.
A
A2
C
0.25 C
//
0.35 C
//
A3
A4
0.1
BC
360X
e
12345678910111213141516
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A0.3
C
0.15
b
171819
U
W
V
F
F
0.2
D
2X
A1 CORNER
EE2
D2
0.2
2X
B
A
E4
D4
K1
K2
L1
L2
K3
L3
Capacitor Region
K4
L4
Millimeters
DIM MIN MAX
A1.922.20
A2 1.10 1.30
A3 — 0.60
A4 0.82 0.90
b0.790.99
D 25.00 BSC
D2 — 12.50
D4 6.00 9.00
e 1.27 BSC
E 25.00 BSC
E2 — 14.30
E4 8.00 11.00
F 22.86 BSC
K1 — 9.75
K2 6.46 —
K3 8.20 8.60
K4 2.75 —
L1 — 9.50
L2 6.94 —
L3 3.10 3.30
L4 3.00 —
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
34 Freescale Semiconductor
System Design Information
7.6 Substrate Capacitors for the MPC7410
Figure 20 shows the connectivity of the subs trate capac itor pads for the MPC7410, 360 CBGA and 360 HCTE
packages.
Figure 20. Substrate Bypass Capacitors for the MPC7410
8 System Design Information
This se ction provides electrical and thermal design recommendations for successful a pplication of the MPC7410.
8.1 PLL Configuration
The MPC7410 PLL is configured by the PLL_CFG[0:3] sig nals. For a given SYSCLK (bus) freque ncy, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configur ation for the
MPC7410 is shown in Table 13 for example frequencies. In this example, shaded cells represent settings that, for a
given SYSCLK frequency, re sult in core and/or VCO frequencies that do not comply with the minimum and
maximum core frequencies listed in Table 8.
Table 13. MPC7410 Microprocessor PLL Configuration
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83.3 MHz
Bus
100 MHz
Bus
133 MHz
0100 2x 2x — — — — — — —
0110 2.5x 2x — — — — — — —
1000 3x 2x — — — — — — 400
(800)
1110 3.5x 2x — — — — —350
(700)
465
(930)
1010 4x 2x — — — — —400
(800)
—
Package
Caps
Value
µF
Voltag e
Reference
C1-1
0.01
L2OVDD
C1-2 GND
C2-1
0.01
L2OVDD
C2-2 GND
C3-1
0.01
VDD
C3-2 GND
C4-1
0.01
OVDD
C4-2 GND
C5-1
0.01
OVDD
C5-2 GND
C6-1
0.01
VDD
C6-2 GND
A1 CORNER
C1-1
C1-2
C2-1
C2-2
C3-2
C3-1
C4-2
C4-1
C5-2
C5-1 C6-1
C6-2
L1L2
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 35
System Design Information
The MPC7410 generates the clock fo r the exter nal L2 synchrono us data SRAMs by dividing the core clock
frequency of the MPC7410. The divided-down clock is then phase-adjusted by an on-chip dela y-lock-l oop (DLL)
circuit and should be routed f ro m the MPC7410 to th e external RAMs. A se parat e cloc k output, L2SYNC_OUT is
sent out half the dista nce to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the
risi ng-edg e of the cloc k as see n at the exter nal RAMs can be aligned t o the cl ocking of the i nternal l atches i n the L2
bus interface.
The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register . Generally ,
the divisor must be chosen according to the frequ ency supported by the external RAMs, the frequenc y of the
0111 4.5x 2x — — — — 375
(750)
450
(900)
—
1011 5x 2x — — —375
(750)
416
(833)
500
(1000)
—
1001 5.5x 2x —— 366
(733)
412
(825)
458
(916)
— —
1101 6x 2x —— 400
(800)
450
(900)
500
(1000)
— —
0101 6.5x 2x —— 433
(866)
488
(967)
— — —
0010 7x 2x — 350
(700)
466
(933)
— — — —
0001 7.5x 2x — 375
(750)
500
(1000)
— — — —
1100 8x 2x — 400
(800)
— — — — —
0000 9x 2x — 450
(900)
— — — — —
0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111 PLL off PLL off, no core clocking occurs
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
or VCO frequencies which are not useful, not supported, or not tested for by the MPC7410; see Section 4.2.1,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the
bus mode is set for 1:1 mode operation. This mode is intended for factory use and third-party emulator tool
development only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the MPC7410 regardless of the SYSCLK input.
5. PLL-off mode should not be used during chip power-up sequencing.
Table 13. MPC7410 Microprocessor PLL Configuration (continued)
PLL_CFG
[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83.3 MHz
Bus
100 MHz
Bus
133 MHz
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
36 Freescale Semiconductor
System Design Information
MPC7410 core, and the phase adjustment range that the L2 DLL supports. Table 14 shows various example L2 clock
freq uencies t hat can be obt ained for a given set of cor e freque ncies. The minimum L2 f requency ta r get is 133 MHz.
Sample core-to- L2 frequencies for the MPC7410 is shown in Table 14. In this example, shaded cells represent
settings that, for a given c ore frequency, result in L2 frequencies that do not comply with the minimum and
maximum L2 frequencies listed in Table 10.
8.2 PLL and DLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC7410 to supply power to the PLL and DLL,
respective ly. Both AVDD and L2AVDD can be supplied power from the VDD power plane. Hig h frequenc y noise in
the 500 kHz to 10 MHz re sonant freque ncy range of the PLL on the VDD power plane could affect the stabili ty of
the internal clocks.
On systems that use the MPC7410 HCTE device, the AVDD and L2AVDD input signals sho uld both implement the
circuit shown in Figure 21.
On syste ms that use the MPC7410 CBGA device, the L2AVDD input should implement the circuit shown in
Figure 21.
When s electing which f il ter to use on the AVDD input of the MPC7410 CBGA device speci fically, system designers
should refer to Erratum No. 18 in the MPC7410 RISC Micr opr ocessor Chip Errata (MPC7410C E). Th e AVDD input
of the MPC7410 CBGA device is sensit ive to system nois e on both the VDD power plane, as describe d above, and
the OVDD power plane as de scri bed in the Erra tum No. 18. W ith thes e AVDD se nsit ivitie s to OVDD and VDD noise,
care must be taken when selecting the filter circuit for the AVDD input of the MPC7410 CBGA device. Erratum
No. 18 does not apply to the AVDD input of the MPC7401 HCTE device, nor does it affect the L2AVDD input of
either the HCTE or the CBGA device.
As described in Erratum No. 18, when there is a high amount of noise on the OVDD power plane due to I/O switching
rates, it is possible for the OVDD noise to couple into the PLL supply volt age (AVDD) internal to the MPC7410
CBGA package. I t is the recommendation of Freesc ale, that new designs using the MPC7410 CBGA package
provi de the ability to impl ement either fil ter shown in Figure 21 and Figure 22 at the AVDD input. Existing designs
that imp l em ent ed Figure 21 on AVDD may never experience the error describ ed in Erratum No. 18. Both new and
Table 14. Sample Core-to-L2 Frequencies
Core Frequency
(MHz) ÷1 ÷1.5 ÷2 ÷2.5 ÷3 ÷3.5 ÷4
350 350 233 175 140 ———
366 366 244 183 147 ———
400 400 266 200 160 133 — —
433 — 288 216 173 144 — —
450 — 300 225 180 150 — —
466 — 311 233 186 155 133 —
500 — 333 250 200 166 143 —
Note: The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not tested
for by the MPC7410; see Section 4.2.3, “L2 Clock AC Specifications,” for valid
L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less
than 150 MHz.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 37
System Design Information
existing designs should qualify both AVDD filt er solutions, and the filter providing the most robust mar gin should
be implemented.
Figure 21. PLL Power Supply Filter Circuit No.1
Figure 22. PLL Power Supply Filter Circuit No. 2
The filter circ uit should be placed as close as poss ible to the AVDD pin to minimize noise coupled from nearby
circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route
directly fro m the capacitors to the AVDD pi n, whic h is on the periphery of the 360 BGA footprint, without the
inductance of vias. The L2AVDD pin may be more diffic ult to route, but is propor tionately less critic al.
It is the recommendation of Freescale, that systems that implement the AVDD filter shown in Figure 22 design i n t he
pads for the removed capacitors (shown in Figure 21), to provide for the possibl e rei ntroduction of the filter in
Figure 21. This would be neces sary in case there is a planned transition from the CBGA package to the HCTE
package of the MPC7410.
8.3 Decoupling Recommendations
Due to the MPC7410 dyna mic power management feature, large address and da ta buses, and high operating
frequencies, the MPC7410 can generate transient powe r surges and high frequency noise in its power supply,
espec ially while driv ing larg e capacit ive loads. Thi s noise must be prevente d from reaching ot her components in th e
MPC7410 system, and the MPC7410 itself requ ires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designe r place at least one decoupling capacitor at e ach VDD, OVDD, and L2OVDD
pin of the MPC7410. It is also recommended that these decoupling capacitors receive their power from separate
VDD, ( L 2 )O V DD, and GND power planes in the PCB, utilizing short tra ces to mini mize inductan ce.
These capacitor s should have a value of 0.01 or 0.1 µF. Only cera mic SMT (surface mount technology) capacitors
should be used to minimize lead induc tance, pref erably 0508 or 0603 orienta tions, wher e connections are made
along the length of the part .
In additi on, i t is recom mended that the re be severa l bulk st orage capac itors di stribut ed around the PCB, feeding t he
VDD, L2OVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary . They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).
VDD AVDD (or L2AVDD)
10 Ω
2.2 µF 2.2 µF
GND
Low ESL Surface Mount Capacitors
VDD AVDD
51 Ω
GND
Capacitor
Pad Sites
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
38 Freescale Semiconductor
System Design Information
8.4 Connection Recommendations
To ensure reliable operation , it is highly recommended to conn ect unused inputs to an appropria te signal le vel
throu gh a resistor . Unused active low inputs should be ti ed to OVDD. Unused activ e high input s should be connected
to GND. All NC (no connect) signa ls must remain unconne c ted.
Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the MPC7410.
Note that power must be supplied to L2OVDD even if the L2 interf ace of the MPC7410 will not be used; the
remainder of the L2 interface may be left unterminated.
8.5 Output Buffer DC Impedance
The MPC7410 60x and L2 I/O drivers are characteri zed over process, volt age, and te mperatur e. To mea sure Z0, an
extern al resi s tor is con nect e d from the chi p pad to OV DD or GND. The n, the value of each resistor is varied until
the pad voltage is OVDD/2 (see Figure 23).
The output impe dance i s the a verage of two components, the r esista nces of t he pull- up and pull -down device s. When
data is held low, SW2 is closed (SW1 is ope n), and RN is trimmed until the voltage at the pad equals (L2)OVDD/2.
RN then bec omes the r esistance o f the pul l-down devices. When data is he ld high, SW1 is close d (SW2 is open) , and
RP is trimmed until the voltage at the pad equals (L2)OVDD/2. RP then becomes the resistance of the pull-up devices.
RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
Figure 23 describes the driver impedance measurement circuit described a bove.
Figure 23. Driver Impedance Measurement Circuit
Alterna tely , th e following is another method to determine the output impeda nce of the MPC7410. A volta ge source,
Vforce, is connected to the output of the MPC7410, as in Figure 24. Data is held low, the voltage source is set to a
value that is equal to (L2) OVDD/2, and the current sourced by Vforce is measured. The voltage drop across the
pull-down device, which is equal to (L2)OVDD/2, is divided by the measured current to determine the output
impedance of the pull-down de vice, RN. Simila rly, t he impedanc e of the pull-up devi ce is det ermined by dividing
the voltage d rop of the pu ll-up, (L2 )OVDD/2, by t he current sank by the pull-up when the data is high and Vforce is
equal to (L2)OVDD/2. This method can be employed with either empirical data from a test setup or with dat a from
simulation models, suc h as IBIS.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 39
System Design Information
RP and RN a re d esigned to be close to each other in va lue. Th en, Z0 = ( RP + RN)/2. Figure 24 desc ribes the alte rnate
driver impedance measurement circuit.
Figure 24. Alternate Driver Impedance Measurement Circuit
Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and
105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.
8.6 Pull-Up Resistor Requirements
The MPC7410 requires pull- up resistors (1 kΩ–5 kΩ) on several control pins of the bus interface to maintain the
control signa ls in the negat ed state af ter they have bee n activel y negat ed and rele ased by the MPC7410 or other bus
masters. These pins are: TS, ARTRY, SHDO, SHD1.
Four te st pins also require pull-up resistors ( 100 Ω−1kΩ). T h es e pi ns a r e CHK , L1_TS TCLK, L2_TSTCLK, and
LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD fo r n ormal ma ch ine
operation.
If pull-down resistor s are used to configure BVSEL or L2VSEL, the resistors should be less than 250 Ω (s ee Tabl e
12). Because PLL_CFG[0:3] must remain stable dur ing normal operation, strong pull-up a nd pull-down resistors
(1 kΩ or less) are recommended to configure the se signals in order to protect against erroneous switching due to
ground bounce, power supply noise or noise coupling.
In addition, CKSTP_OUT is an open -drain s tyle outpu t tha t r equire s a pull-up r e sistor (1 kΩ–5 kΩ) if it is used by
the system. The CKSTP_IN signal should likewise be pulled up through a pull- up resistor (1 kΩ–5 kΩ) to prev en t
erroneous assertions of this signal.
During inactive pe riods on the bus, the addres s and transfer att ributes may not be driven by any master and may,
there fore, fl oat in the high-impedance sta te for relative ly long periods of time. Since the MPC7410 must conti nually
monitor these signa ls for snooping, this float condit i on may cause excessive power dr aw by the input rec eivers on
Table 15. Impedance Characteristics
VDD = 1.8 V, OVDD = 2.5 V, Tj = 0° – 105°C
Impedance Processor Bus L2 Bus Symbol Unit
RN41.5–54.3 42.7–54.1 Z0Ω
RP37.3–55.3 39.3–50.0 Z0Ω
(L2)OVDD
BGA
Data
Pin Vforce
OGND
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
40 Freescale Semiconductor
System Design Information
the MPC7410 or by other receivers in the system. These signal s can be pulled up through weak (10-kΩ) pull-up
resistors by the system, address bus drive n mode can be enabled ( see the MPC7410 RISC Microproce ssor Family
Users’ Manual for more inf ormation on this mo de), or the se signals may be otherwise driven by the system dur ing
inactive periods of the bus to avoid this additional power draw. The s noope d address and transf er attribute inputs
are: A[0:31], AP[0:3], TT[0:4], CI, W T, and GBL.
In syst ems where GBL is not connected and other devices m ay be asse rting TS for a snoopa ble transacti on while not
driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on GBL. Note that the
MPC7410 will only snoop transac tions when GBL is asserted.
The data bus input receiver s are normally turned off when no read operation is in progress and, therefore, do not
require pull- up resistors on the bus. Other data bus receivers in the system, however, may require pull- ups, or that
those signals be other wise driven by the system during inactive periods by the system. The data bus signals are:
DH[0:31], DL[0:31], and DP[0:7].
If addre ss or data parity is not used by the system, and the re spective parity checking is disabl ed through HI D0 , the
input receive rs for those pins are disabled, and those pins do not require pull-u p resistors and should be left
unconnec ted by the system. If pa rity c heckin g is disable d through HID0, and par ity generation is not requir ed by the
MPC7410 (note that the MPC7410 always gener ates parity) , then all parit y pins may be left unconnecte d by the
system.
The L2 interface does not normally require pull-up resistor s.
8.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signa ls. The TRST signal is optional in the IEEE
1 149.1 spec ification, but is provi ded on all processors th at implement t he PowerPC archite cture. While it is possible
to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset
performance will be obtained if the TRST signal is asserted during power- on reset. Because the JTAG interface is
also used for accessing the common on-c hip processor ( COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these proces sors allows a remote computer system (typi cally, a PC with dedicated ha rdwar e
and debuggin g soft ware) to access and control the inter nal operati ons of t he processor. The COP interface connects
primarily through the JTAG port of the proce ssor, with some additional status monitor ing signals . The COP port
requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target
system has independent r eset sources, suc h as voltage monitor s, watchdog timers, power supply fai lures, or
push-button switches, then the COP reset signa ls must be merged into these signals with logic.
The arrangement shown in Figure 25 allows the COP port to independently assert HRESET or TRST , while ensuring
that the target can drive HRESET as well . If t he JTAG interface and COP hea der will not be used, TRST should be
tied t o H RESET through a 0-Ω isolatio n resistor so that it is asse rted when the system reset signal (HRESET) is
asserted, ensuring that the JTAG scan chain is initia lized during power-on. While Freesc ale recommends that the
COP header be designed into the system as shown in Figure 25, i f this is not possi ble, the is olation r esistor will allow
future access to TRST in the ca se where a JTAG interfac e may ne ed to be wir ed onto t he syste m in de bug situa tions .
The COP header shown in Figure 25 adds many benefits—breakpoints, watchp oints, register and memory
examination/modificat ion, and other sta ndard debugger feat ures are possible t hrough this interf ace —and can be as
inexpensive as an unpopulated footprint for a header to be added when needed.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 41
System Design Information
Figure 25. COP Connector Diagram
HRESET HRESET 6
From Target
Board Sources
HRESET
13
SRESET
SRESET SRESET
NC
NC
11
VDD_SENSE
6
5 1
15
2 kΩ10 kΩ
10 kΩ
10 kΩ
OVDD
OVDD
OVDD
OVDD
CHKSTP_IN CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
12
(if any)
COP Header
14 2
Key
QACK
OVDD
OVDD
10 kΩ
OVDD
10 kΩOVDD
10 kΩ
10 kΩ
QACK
QACK
CHKSTP_OUT
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 kΩ 4
OVDD
1
2 kΩ 3
0 Ω 5
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7410. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.
6. The COP port and target board should be able to independently assert HRESET and TRST to the pro-
cessor in order to fully control the processor as shown above.
TRST 6
10 kΩ
OVDD
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
42 Freescale Semiconductor
System Design Information
The COP inter face has a standard header for conne ction to the targe t system, based on the 0.025" square -post 0. 100"
centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector
key.
There is no standardiz ed way to number the COP header shown in Figure 25; conseq uently, many dif ferent pin
numbers have been obse rved from emulator vendors. Some a re numbered top-to-bottom then left-to-right, while
others use left- to-right then top- to-bottom, while still others number t he pins counter c l oc kwise f rom pin 1 (as with
an IC). Rega rdless of the numbering, the signal plac ement recommended in Figure 25 is common to all known
emulators.
The QACK signal shown in Figure 25 is usually connected to the PCI bridge chip in a system and is an input to the
MPC7410 i nforming it that it c an go into the quies cent state. Unde r nor mal operatio n this occurs dur ing a low-powe r
mode select ion. In order f or COP t o work, the MPC7410 must se e thi s signal asser te d (pull ed down). While shown
on the COP header, not all emulator products dr ive this signal. If the product does not, a pull-down resistor can be
populated to asser t this signal. Additionally, some emulator produc ts implement ope n-drain type outputs and can
only dr ive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated
when it is not being driven by the tool. Note that the pull-up and pull-down resi stors on the QACK si gnal are
mutually exclusive and it is never necessary to populate both in a system. T o preserve correct power-down operation,
QACK should be merged via logic so tha t it also can be dri ven by the PCI bridge.
8.8 Thermal Management Information
This section provides thermal management information for the MPC7410 for air-cooled applications. Proper
thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal
interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several
methods such as spring clip to holes in the printed circuit board or with screws and springs to the printed circuit
board; se e Figure 26 f or th e BGA pa ck ag e and Figure 27 f or the LGA pac kage. This spri ng force should not exceed
5.5 po unds o f fo rce. No te that car e should be take n t o avoid focused force s being applie d to die cor ners a nd/or edge s
when mounting heat sinks.
Figure 26. BGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option
Thermal Interface Material
Heat Sink BGA Package
Heat Sink
Clip
Printed-Circuit Board
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 43
System Design Information
Figure 27. LGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option
The board designer can choos e betwe en several types of heat sinks to place on the MPC7410. There are sever al
commercially-available heat sinks for the MPC7410 from the following vendors:
Aavid Thermalloy 603-224-9988
70 Commercial Street, Suite 200
Concord, NH 03301
Internet: www.aavidther malloy.com
Alpha Novatech 408-567-8082
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovate ch.com
The Bergquist Company 800-347-4572
18930 We st 78th St.
Chanhassen, MN 5 5317
Internet: www.berg quistcompany.com
Internationa l Electronic Research Corpo ration (IERC) 818-842-72 77
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Wakefie ld Engineer ing 603-635-2800
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield .c om
Ultimately, the final se lection of a n appropr iate he a t sink depends on many f actors , such a s thermal perfor mance at
a given air velocity, spatial volume, m ass, attachment method, assembly, and cost.
Thermal
Heat Sink LGA Package
Heat Sink
Clip
Printed-Circuit Board
Interface Material
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
44 Freescale Semiconductor
System Design Information
8.8.1 Internal Package Conduction Resistance
For the exposed-die packag ing technology, shown in Table 3, the intr insic conduction thermal resistance paths are
as follows:
• The die junction-to-case (or top-of-die for exposed silicon) the rmal resistance
• The die junction-to- ball thermal resistance
Figure 28 depicts t he primar y heat transfer path for a package with an atta ched hea t sink mounted t o a printed-cir cuit
board.
Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach
material (or ther mal inte rface material), and fin ally to the heat sink where it is removed by forced-air convecti on.
Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may
be neglecte d. Thus, the heat sink attach material and t he heat sink con duction/ convective ther mal resis tances are the
dominant terms.
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
8.8.2 Adhesives and Thermal Interface Materials
A thermal interface material is recommended a t the package lid-to-heat sink interface to minimize the thermal
contac t resistance. For thos e applicati ons where the heat sink is attached by spr ing clip mechan ism, Figure 29 s hows
the thermal performance of three thin-sheet thermal-interface materials (silicone , gr aphite/oi l, floroe ther oil), a b are
joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal
interface materials improves with increasing contact pr essure. The use of thermal grease significantly reduces the
interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater
than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 26).
This spring force shou ld not exceed 5.5 pounds of force. Therefore , the synthe tic grease offers the bes t t herm al
performance, considering the low inte rface pres sur e. Of course, the select ion of any thermal inte rfa ce materia l
depends on many factors—thermal performanc e req uirements, manufactur ability, service temperature, dielectric
properties, cost, and so on.
External Resistance
External Resistance
Internal Resistance
Note the internal versus external package resistance.
Radiation Convection
Radiation Convection
Heat Sink
Printed-Circuit Board
Thermal Interface Material
Package/Leads
Die Junction
Die/Package
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 45
System Design Information
Figure 29 describes the thermal performance of selected thermal interface materials.
Figure 29. Thermal Performance of Select Thermal Interface Material
The board designer can choos e betwe en several types of thermal interface . Heat sink adhesive mate rials should be
selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration
requirements. There are several commercially-avail able thermal interface s and adhes ive materials pr ovided by the
following vendor s:
Chomerics, Inc. 781-935-4850
77 Dragon Court
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dow.com
Shin-Etsu M icroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
0
0.5
1
1.5
2
0 1020304050607080
Silicone Sheet (0.006")
Bare Joint
Floroether Oil Sheet (0.007")
Graphite/Oil Sheet (0.005")
Synthetic Grease
Contact Pressure (psi)
Specific Thermal Resistance (K-in.2/W)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
46 Freescale Semiconductor
System Design Information
Thermagon Inc. 888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
8.8.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
Tj = Ta + Tr + (θjc + θint + θsa) × Pd
where:
Tj is the die-junction te mperature
Ta is the inlet cabinet ambient te mperature
Tr is the air temperature rise within the computer cabinet
θjc is the junction-to-case thermal resistance
θint is the adhesive or interfa ce materia l thermal resistance
θsa is the heat sin k ba se -to -am b ie nt the rm al resist an ce
Pd is the power dissipated by the device
During operation the die-junction temperat ures (Tj) should be maintained less than the value specified in Table 3.
The temperatur e of the air cool ing the componen t greatly de pends upon the ambient inle t air temp eratur e and the air
temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30°
to 40°C. The air temperature rise within a cabinet (Tr) may be i n the ra nge of 5° to 10°C. The thermal re sistance of
the thermal interface material (θint) i s typic ally a bout 1°C/W. Assuming a Ta of 30°C, a T r of 5°C, a CBGA pa ckage
θjc = 0.03, and a power consumption (Pd) of 5.0 W, the following expression for Tj is obtained:
Die-junction temperature: Tj = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θsa) × 5.0 W
For a Thermalloy he at sink #2328B, the he at sink- to-ambient thermal resistance (θsa) versus airflow velocity is
shown in Figure 30.
Assuming an air velocity of 0.5 m /s, we have an effective Rsa of 7°C/W, thus
Tj = 30°C + 5°C + (0.03°C/W + 1.0°C/W + 7°C/ W) × 5.0 W,
resulting in a die-junction temper ature of approximately 75°C which is well within the maximum operating
temperat ure o f the co m ponen t.
Other heat sinks offered by Aavid Ther malloy, Alpha Novatech, The Bergquist Company, IERC, and Wakefiel d
Engineering offer different heat sink- to-ambi ent thermal resistances , and may or may not need airflow.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 47
System Design Information
Figure 30. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Though the die juncti on-to-ambient and the heat sink-to-ambi ent thermal re sistances are a common figur e -of-merit
used for comparing the therm al performance of various microel ectr onic packaging technolo gies, one should
exercise caution when only using this metric in determining th ermal m anagement because no single para meter can
adequately describe three-dimensional heat flow . The final die-junction operating temperature, is not only a function
of the component-level the rmal resistance, but the system-level design and its operating conditions. In addition to
the component's power consumption, a number of factors affe ct the final operating die-junction
temperature —airflow, board population (l ocal heat flux of adjacent components) , heat sink ef ficie ncy, heat sink
attach, heat sink placement, next -level int erc onnect technology, system air temperatu re ri se, altitude, and so on.
Due to the complexity and the many variations of system- level boundary co nditions for today's microel ectroni c
equip ment, the combi ned eff ects of the heat transfe r mechanisms (ra diatio n, conve ction, and c onduction) may va ry
widely. For these reaso ns, we recommend using conjugate heat transfer models for the board, as well as ,
system-lev el des ign s.
1
3
5
7
8
00.511.522.533.5
Thermalloy #2328B Pin-Fin Heat Sink
Approach Air Velocity (m/s)
Heat Sink Thermal Resistance (ºC/W)
(25 × 28 × 15 mm)
2
4
6
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
48 Freescale Semiconductor
Document Revision History
9 Document Revision History
Table 16 provides a revis ion history for this hardware spec ification.
Table 16. Document Revision History
Revision Date Substantive Change(s)
6.1 11/16/2007 Updated Ta b le 1 7 and Table 19 to show the VU package is available as an MC prefix device compared
to an MPC prefix for the other package types; this was done to match the specification documents
with the device ordering and part marking information.
Updated title of Ta b l e 1 9 to reflect correct name of referenced document and updated respective
document order information below table.
Updated notes in Ta bl e 1 –Tab le 3 replacing references to MPC7410RX
nnn
LE with M
xx
7410
xxnnn
LE
since notes to apply to all the available packages types.
6 8/14/2007 Updated Ta bl e 4 thermal information:
• Deleted rows on single-layer (1s) boards.
• CBGA package RθJMA for natural convection for four layer boards changed from 17 to 18 °C/W.
• HCTE package RθJMA for natural convection for four layer boards changed from 22 to 20 °C/W.
• HCTE package RθJMA for 200 ft./min airflow for four layer boards changed from 19 to 16 °C/W with
airflow rate specification changed from 200 ft./min to 1 m/sec.
• HCTE package RθJMA for 400 ft./min airflow for four layer boards changed from 18 to 15 °C/W with
airflow rate specification changed from 400 ft./min to 2 m/sec.
• CBGA package RθJB changed from 8 to 9°C/W.
• HCTE package RθJB changed from 14 to 11°C/W.
• Ta b l e 4 Notes 2 - 4 have been revised and updated; Note 5 is no longer used. Notes on table rows
have been renumbered.
Updated Figure 26 removing optional heat sink clip to package.
Removed references in document to adhesive attached thermal solutions.
Updated thermal solution vendor information in Section 8.8.
Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information to document:
• Added Section 7.2, “Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead Free C5
Spheres).
• Added Figure 18 for HCTE_CBGA Lead Free C5 Spheres package, similar to Figure 17 but with
differences in dimensions A, A1, and b in the figure’s dimension table.
• Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information in Table 17 and Ta b l e 1 9 .
• Changed part marking example in Figure 31 to an HCTE_CBGA device.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 49
Document Revision History
5 4/13/2005 Section numbering revised. In all previous versions, section numbering began with ‘1.’ These extra
‘1’s’ were deleted. For example, previously numbered section 1.8.2 changed to 8.2.
Section 7.1—added CTE value for HCTE package. Corrected minimum module height from 2.65 mm
to 2.72 mm per Figure 17.
Section 3—added HCTE_LGA (VS package descriptor) package description which is the
HCTE_CBGA (HX package descriptor) with the spheres removed.
Table 4—generalized ‘HCTE CBGA’ column to ‘HCTE’ to include both HCTE_CBGA and HCTE_LGA
package thermal characteristics.
Section 5—added HCTE_LGA package. The HCTE_LGA has the same pin assignments as the
CBGA and HCTE_CBGA packages. Added side view Part C for HCTE_LGA.
Section 6—added HCTE_LGA package (VS package descriptor). The HCTE_LGA has the same
pinout listing as the CBGA and HCTE packages.
Section 7.3—added HCTE_LGA package parameters.
Section 7.4—added HCTE_LGA package mechanical dimensions.
Table 17—added HCTE_LGA package (VS package descriptor) to part numbering nomenclature.
4 — Table 5—Changed measurement test condition IOH from -6mA to –5 mA for VOH and IOL from 6 mA
to 5 mA for VOL per Product Bulletin.
Section 1.8.2—revised text regarding AVDD filter selection for the CBGA package.
3 — Table 6—Changed note 1 to specify that OVDD and L2OVDD power is typically <5% of VDD power.
Figure 17—revised diagram and dimensions to specify ‘cap regions’ versus individual cap
measurements. Moved individual capacitor placement to separate figure.
Figure 18—Added this figure to show each individual capacitor placement and value.
Figure 22—updated COP Connector Diagram to recommend a weak pull-up resistor on TCK.
2 — Public release, includes Rev 1.1 changes.
Section 1.7.2—added package capacitor values.
Section 1.8.6—added recommendation that strong pull-up/down resistors be used on the
PLL_CFG[0:3] signals.
Table 8—removed mode input setup and hold times. These inputs adhere to the general input setup
and hold specifications.
Figure 5—revised mode input diagram to show sample points around HRESET negation.
Section 1.3—added HCTE package description.
Figure 22—added note 6 to emphasize that COP emulator and target board need to be able to drive
HRESET and TRST independently to the CPU.
Section 1.8.2—revised section for HCTE package. Added text and figure for AVDD filter for the CBGA
package.
Section 1.8.6—removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST
from snooped transfer attribute list. TBST is an output and is not snooped.
Table 16. Document Revision History (continued)
Revision Date Substantive Change(s)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
50 Freescale Semiconductor
Document Revision History
1.1 — Internal release.
Table 12—added note 16 for ABB/AMON and DBB/DMON signal clarification.
Table 12—changed CHK note 4 reference to note 2, signal is for factory test only. Changed previous
note 4 (CHK related) to now provide additional PLL info.
Table 1—modified maximum value for OVDD from –0.3 to 3.465 to now be –0.3 to 3.6 and L2OVDD
from –0.3 to 2.6 to now be –0.3 to 2.8. Modified note 6, OVDD for revisions prior to Rev. 1.4 have
maximum value for OVDD of –0.3 to 2.8.
Table 8—removed note 12. L2_TSTCLK is for factory use only (see Table 12, note 2).
Section 1.10.2—revised section to include nomenclature tables for part markings not covered by this
spec.
Figure 2—added that under/overshoot for L2OVDD references tL2CLK while OVDD references tSYSCLK.
Table 4—added HCTE package (HX package descriptor) thermal characteristics.
Section 1.5—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same pin assignments.
Section 1.6—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same pinout listings.
Section 1.7—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages
have the same package parameters and dimensions.
Table 17—added HCTE package (HX package descriptor) to part numbering nomenclature.
Table 21—added MPC7410THXnnnLE extended temperature HCTE package part numbers and part
number specification document reference.
Table 16. Document Revision History (continued)
Revision Date Substantive Change(s)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 51
Document Revision History
1.0 — Section 1.3 and Table 3—revised OVDD from 3.3 V ± 100 mV to 3.3 V ± 165 mV.
Table 13—removed unsupported PLL configurations.
Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus
support.
Table 13—revised note 3 to include emulator tool development.
Table 14—removed unsupported Core-to-L2 example frequencies.
Section 1.8.8—updated heat sink vendors list.
Section 1.8.8.2—updated interface vendors list.
Table 1—updated voltage sequencing requirements notes 3 and 4.
Table 4—Updated/added thermal characteristics.
Table 5—removed table and TAU related information, TAU is no longer supported.
Table 6—updated Iin and ITSI leakage current specs.
Section 1.8.3—removed section.
Section 1.10—reformatted section.
Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and
TS to control signals needing pull-ups. Added pull-up resistor value recommendation for
L1_TSTCLK, L2_TSTCLK, and LSSD_MODE factory test signals.
Section 1.8.7—revised text regarding connection of TRST
. Combined Figure 22, Figure 23, and Table
17, into Figure 21.
Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of
350 MHz.
Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OVDD.
Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V
OVDD.
Table 5—added note 8 regarding DC voltage limits for JTAG signals.
Table 16. Document Revision History (continued)
Revision Date Substantive Change(s)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
52 Freescale Semiconductor
Document Revision History
0.3 — Added 3.3 V support on the processor bus (BVSEL).
Table 7—update typical and maximum power numbers for full-on mode in. Removed note 4.
Reworded notes 2 and 3.
Table 9, Note 2—removed reference to application note.
Figure 17—corrected side view datum A to be datum C.
Section 1.8.7—added CI and WT to transfer attribute signals requiring pull-ups.
Section 1.8.7—added 1-kΩ pull-up recommendation to GBL when GBL is not connected.
Table 2— added pull-down resistance necessary for internally pulled-up voltage select pins. Added
3.3-V support for BVSEL.
Table 13—added note 14 for BVSEL, L2VSEL, and TRST pins to address pull-down resistance
necessary for these internally pulled-up pins to recognize a low signal.
Table 6—lowered 2.5 V CVIH from 2.2 to 2.0 V to be compatible with VOH of the MPC107. Added
support for 3.3-V processor bus.
Table 15—modified note 1, use L2CR[L2SL] for L2CLK frequency less than 150 MHz.
Table 8—revised note 2 discussing for 3.3-V bus voltage support.
Table 14—added note 5, do not use PL off during power-up sequence.
Table 1—update output hold times (tL2CHOX).
0.2 — Corrected Section 1.3—technology from 0.13 µm to 0.18 µm.
Updated Table 7—adds power consumption numbers; adds note on estimated decrease w/o AltiVec.
Updated Table 8—adds minimum values for processor frequency and VCO frequency.
Updated Table 9—input setup, output valid times, output hold times, SYSCLK to output high
impedance.
Updated Table 11—L2SYNC_IN to high impedance.
Updated Figure 17—mechanical dimensions, adds capacitor pad dimensions.
0.1 — Minor updates.
0 — Initial release.
Table 16. Document Revision History (continued)
Revision Date Substantive Change(s)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 53
Ordering Information
10 Ordering Information
Ordering infor mation for the parts fully covered by this specif ication doc ument is provided in Section 10.1, “Part
Numbers Addre ssed by This Specificati on.” Section 10.2, “Part Numbers Not Full y Addressed by This Doc ument,”
lists the part numbers whic h do not fully con form to the speci ficati ons of this document. These special pa rt numbers
require an additional document called a part num ber specification.
10.1 Part Numbers Addressed by This Specification
Table 17 provides the Free scale part numberi ng nomenclature fo r the MPC7410 Note that the individua l part
numbers correspond to a maximum processor core frequency . For available frequencies, contact your local Freescale
sales of fice. In addition to the proc essor fr equency , the part numbering s cheme also in cludes an appl icati on modifier
which may specify specia l applicati on cond itions. Each part number also contains a rev ision code which refers t o
the die mask revision number.
Table 17. Part Numbering Nomenclature
Mxx 7410
xx nnn x x
Product
Code
Part
Identifier Package 1Processor
Frequency 2Application
Modifier Revision Level
MPC 7410 RX = CBGA 400
450
500
L: 1.8 V ± 100 mV
0° to 105°C
C: 1.2; PVR = 800C 1102
D: 1.3; PVR = 800C 1103
E: 1.4; PVR = 800C 1104
HX = HCTE_CBGA E: 1.4; PVR = 800C 1104
VS = HCTE_LGA
MC VU = HCTE_CBGA
(Lead Free C5
Solder Spheres)
400
500
Notes:
1. See Section 7, “Package Description,” for more information on available package types and Ta b le 4 for more
information on thermal characteristics.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may
support other maximum core frequencies.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
54 Freescale Semiconductor
Ordering Information
10.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification doc ument are described
in se parate part number s pecifications which supple ment and s upersede thi s document, as descr ibed in the f ollowing
tables.
Table 18. Part Numbers Addressed by MPC7410RXnnnPx Series Part Number Specifications
MPC 7410 RX
nnn
P
x
Product
Code
Part
Identifier Package Processor
Frequency1
Application
Modifier Revision Level
MPC 7410 RX = CBGA 450
500
550
P: 2.0 V ± 50 mV
0° to 65°C
C: 1.2; PVR = 800C 1102 1
D: 1.3; PVR = 800C 1103 2
E: 1.4; PVR = 800C 1104 3
Notes: Document order numbers:
1. MPC7410PCPNS.
2. MPC7410PDPNS.
3. MPC7410PEPNS.
Table 19. Part Numbers Addressed by MPC7410 RISC Microprocessor HardwareSpecifications Addendum
for the MPC7410xxnnnNE Series
Mxx 7410 xx
nnn
NE
Product
Code
Part
Identifier Package Processor
Frequency 1
Application
Modifier Revision Level
MPC 7410 RX = CBGA 400
450
500
N: 1.5 V ± 50 mV E: 1.4; PVR = 800C 1104
HX = HCTE_CBGA
VS = HCTE_LGA
400
450
MC VU = HCTE_CBGA
(Lead Free C5 Solder
Spheres)
Note: Document order number: MPC7410ECS02AD
Table 20. Part Numbers Addressed by MPC7410TRXnnnNE Part Number Specification
MPC 7410 T RX
nnn
NE
Product
Code
Part
Identifier
Process
Descriptor Package Processor
Frequency1Application
Modifier Revision Level
MPC 7410 T: –40° to 105°CRX=CBGA 400
450
N: 1.5 V ±50 mV E: 1.4; PVR = 800C 1104
Note: Document order number: MPC7410TRXNEPNS.
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor 55
Ordering Information
10.3 Part Marking
Parts are marked as the example shown in Figure 31.
Figure 31. Part Marking for HCTE_CBGA Device
HCTE_CBGA
MPC7410
HXnnnLE
MMMMMM
AWLYYWWA
7410
Notes:
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
MMMMMM is the 6-digit mask number.
AWLYYWWA is the traceability code.
MPC7410EC
Rev. 6.1
11/2007
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