256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Features DDR2 SDRAM RDIMM MT9HTF3272 - 256MB MT9HTF6472(P) - 512MB MT9HTF12872(P) - 1GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * 240-pin, registered dual in-line memory module (RDIMM) * Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 * 256MB (32 Meg x 72), 512MB (64 Meg x 72), 1GB (128 Meg x 72) * Supports ECC error detection and correction * VDD = VDDQ = +1.8V * VDDSPD = +1.7V to +3.6V * JEDEC-standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * Single rank * Multiple internal device banks for concurrent operation * Programmable CAS# latency (CL) * Posted CAS# additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths: 4 or 8 * Adjustable data-output drive strength * 64ms, 8,192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Gold edge contacts Table 1: 240-Pin RDIMM (MO-237 R/C A Non-Parity, R/C F Parity) PCB height: 30mm (1.18in) Options Marking P * Parity * Operating temperature1 None - Commercial (0C TA +70C) I - Industrial (-40C TA +85C) * Package Y - 240-pin DIMM (Lead-free) * Frequency/CAS latency2 -80E - 2.5ns @ CL = 5 (DDR2-800)3 -800 - 2.5ns @ CL = 6 (DDR2-800)3 -667 - 3.0ns @ CL = 5 (DDR2-667) -53E - 3.75ns @ CL = 4 (DDR2-533) -40E - 5.0ns @ CL = 3 (DDR2-400) * PCB height - 30mm (1.18in) Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. 3. Not available in 256MB module density. Key Timing Parameters Data Rate (MT/s) tRCD Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 -80E -800 -667 -53E -40E PC2-6400 PC2-6400 PC2-5300 PC2-4200 PC2-3200 - 800 - - - 800 667 667 - - 533 533 533 533 400 - - 400 400 400 PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 1 tRP tRC (ns) (ns) (ns) 12.5 12.5 15 15 15 12.5 12.5 15 15 15 55 55 55 55 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: 256MB 512MB 1GB 8K 8K A[12:0] 4 BA[1:0] 1KB 256Mb (32 Meg x 8) 1K A[9:0] 1 S0# 8K 16K A[13:0] 4 BA[1:0] 1KB 512Mb (64 Meg x 8) 1K A[9:0] 1 S0# 8K 16K A[13:0] 8 BA[2:0] 1KB 1Gb (128 Meg x 8) 1K A[9:0] 1 S0# Part Numbers and Timing Parameters - 256MB Modules Base device: MT47H32M8,1 256Mb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT9HTF3272I(I)Y-667__ MT9HTF3272(I)Y-53E__ MT9HTF3272(I)Y-40E__ 256MB 256MB 256MB 32 Meg x 72 32 Meg x 72 32 Meg x 72 5.3 GB/s 4.3 GB/s 3.2 GB/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 4-4-4 3-3-3 Table 4: Part Numbers and Timing Parameters - 512MB Modules Base device: MT47H64M8,1 512Mb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT9HTF6472(P)(I)Y-80E__ MT9HTF6472(P)(I)Y-800__ MT9HTF6472(P)(I)Y-667__ MT9HTF6472(P)(I)Y-53E__ MT9HTF6472(P)(I)Y-40E__ 512MB 512MB 512MB 512MB 512MB 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 6.2 GB/s 6.2 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Table 5: Part Numbers and Timing Parameters - 1GB Modules Base device: MT47H128M8,1 1Gb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL - tRCD - tRP) MT9HTF12872(P)(I)Y-80E__ MT9HTF12872(P)(I)Y-800__ MT9HTF12872(P)(I)Y-667__ MT9HTF12872(P)(I)Y-53E__ MT9HTF12872(P)(I)Y-40E__ 1GB 1GB 1GB 1GB 1GB 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 6.2 GB/s 6.2 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800 MT/s 2.5ns/800 MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 Notes: PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) designating component and PCB revisions. Consult factory for current revision codes. Example: MT9HTF6472Y-667D2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignments 240-Pin DDR2 RDIMM Front 240-Pin DDR2 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin 1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 3 4 5 DQ0 DQ1 VSS 33 34 35 DQ24 DQ25 VSS 63 64 65 A2 VDD VSS 93 94 95 DQS5 VSS DQ42 123 124 125 153 154 155 A1 VDD CK0 213 214 215 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 186 CK0# 216 VSS 7 8 DQS0 VSS 37 38 DQS3 VSS 67 682 97 98 VSS DQ48 127 128 157 158 187 188 VDD A0 217 218 DQ52 DQ53 9 10 11 12 13 DQ2 DQ3 VSS DQ8 DQ9 39 40 41 42 43 DQ26 DQ27 VSS CB0 CB1 69 70 71 72 73 VDD NC/ PAR_IN VDD A10 BA0 VDDQ WE# DQ29 VSS DM3/ DQS12 NC/ DQS12# VSS DQ30 183 184 185 6 DQ5 VSS DM0/ DQS9 NC/ DQS9# VSS DQ6 DM5/ DQS14 NC/ DQS14# VSS DQ46 DQ47 99 100 101 102 103 DQ49 VSS SA2 NC VSS 129 130 131 132 133 DQ7 VSS DQ12 DQ13 VSS 159 160 161 162 163 DQ31 VSS CB4 CB5 VSS 189 190 191 192 193 VDD BA1 VDDQ RAS# S0# 219 220 221 222 223 14 VSS 44 VSS 74 CAS# 104 DQS6# 134 164 VDDQ 224 DQS1# 45 DQS8# 75 VDDQ 105 DQS6 135 195 ODT0 225 16 17 18 19 20 21 22 DQS1 VSS RESET# NC VSS DQ10 DQ11 46 47 48 49 50 51 52 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 76 77 78 79 80 81 82 S1# ODT1 VDDQ VSS DQ32 DQ33 VSS 106 107 108 109 110 111 112 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS 136 137 138 139 140 141 142 DM8/ DQS17 NC/ DQS17# VSS CB6 CB7 VSS VDDQ CKE1 VDD 194 15 DM1/ DQS10 NC/ DQS10# VSS RFU RFU VSS DQ14 DQ15 VSS VSS RFU RFU VSS DM6/ DQS15 NC/ DQS15# VSS 196 197 198 199 200 201 202 226 227 228 229 230 231 232 23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC/A154 203 24 25 DQ16 DQ17 54 551 84 85 DQS4 VSS 114 115 DQS7 VSS 144 145 DQ21 VSS 174 NC/A144 175 VDDQ 204 205 234 235 DQ54 DQ55 VSS DQ60 DQ61 Vss DM7/ DQS16 NC/ DQS16# VSS DQ62 26 VSS 56 NC/BA2 NC/ ERR_OUT VDDQ NC/A133 VDD VSS DQ36 DQ37 VSS DM4/ DQS13 NC/ DQS13# VSS DQ38 86 DQ34 116 DQ58 146 176 A12 206 DQ39 236 DQ63 27 DQS2# 57 A11 87 DQ35 117 DQ59 147 177 A9 207 VSS 237 VSS 28 29 30 DQS2 VSS DQ18 58 59 60 A7 VDD A5 88 89 90 VSS DQ40 DQ41 118 119 120 VSS SDA SCL 148 149 150 DM2/ DQS11 NC/ DQS11# VSS DQ22 DQ23 178 179 180 VDD A8 A6 208 209 210 DQ44 DQ45 VSS 238 239 240 VDDSPD SA0 SA1 Notes: PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 1. 2. 3. 4. 156 165 166 167 168 169 170 171 172 Symbol Pin Symbol 233 Pin 55 is NC for non-parity and ERR_OUT for parity. Pin 68 is NC for non-parity and PAR_IN for parity. Pin 196 is NC for 512MB or A13 for 1GB, 2GB and parity. Pins 173 and 174 are NC or A15 and A14 for parity. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information Symbol Type Description A[15:0] Input BA[2:0] Input CK0, CK0# Input CKE0 Input DM[8:0]/ DQS[17:9] Input ODT0 Input PAR_IN RAS#, CAS#, WE# Input Input RESET# Input S0# Input SA[2:0] Input SCL Input CB[7:0] DQ[63:0] DQS[8:0], DQS#[8:0] I/O I/O I/O SDA I/O Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2/1:0]) or all device banks (A10 HIGH). A[12:0] (256MB) and A[13:0] (512MB 1GB). A[15:14] are connected for parity. Bank address inputs: BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR, EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (256MB, 512MB) and BA[2:0] (1GB). Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with the input data, during a write access. DM is sampled on both edges of DQS. Although the DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. If RDQS is disabled, RDQS[8:0] become DM[8:0] and RDQS#[8:0] are not used. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Parity input: Parity bit for the address, RAS#, CAS#, and WE#. Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. Serial address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the SPD EEPROM. Check bits. Data input/output: Bidirectional data bus. Data strobe: DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module on the I2C bus. Parity error output: Parity error found on the command and address bus. ERR_OUT EVENT# VDD/VDDQ VDDSPD Output (open drain) Output Temperature event: The EVENT# pin is asserted by the temperature sensor when critical (open drain) temperature thresholds have been exceeded. Supply Power supply: 1.8V 0.1V. The component VDD and VDDQ are connected to the module VDD. Supply SPD EEPROM power supply: +1.7V to +3.6V. PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions (continued) Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information Symbol Type VREF VSS NC RFU Supply Supply - - PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN Description Reference voltage: VDD/2. Ground. No connect: These pins are not connected on the module. Reserved for future use. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Functional Block Diagrams Functional Block Diagrams Figure 2: Functional Block Diagram - Raw Card A Non-Parity RS0# DQS4 DQS4# DM4/DQS13 NC/DQS13# DQS0 DQS0# DM0/DQS9 NC/DQS9# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 DQS1 DQS1# DM1/DQS10 NC/DQS10# DQ DQ DQ DQ DQ DQ DQ DQ U9 DQS5 DQS5# DM5/DQS14 NC/DQS14# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U2 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U10 DQS6 DQS6# DM6/DQS15 NC/DQS15# DQS2 DQS2# DM2/DQS11 NC/DQS11# DM/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U3 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U11 DQS7 DQS7# DM7/DQS16 NC/DQS16# DQS3 DQS3# DM3/DQS12 NC/DQS12# DM/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U4 DQ DQ DQ DQ DQ DQ DQ DQ DQS8 DQS8# DM8/DQS17 NC/DQS17# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ R E G I S T E R NU/ CS# DQS DQS# RDQS# U12 U8 NU/ CS# DQS DQS# RDQS# CK0 CK0# U5 PLL RESET# U7 SPD EEPROM SCL WP A0 A1 SDA DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM Register A2 VSS SA0 SA1 SA2 U6 S0# BA[2/1:0] A[13/12:0] RAS# CAS# WE# CKE0 ODT0 NU/ CS# DQS DQS# RDQS# RS0#: DDR2 SDRAM RBA[2/1:0]: DDR2 SDRAM RA[13/12:0]: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: DDR2 SDRAM RODT0: DDR2 SDRAM VDDSPD SPD EEPROM VDD/VDDQ DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM RESET# PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Functional Block Diagrams Figure 3: Functional Block Diagram - Raw Card F Parity RS0# DQS4 DQS4# DM4/DQS13 NC/DQS13# DQS0 DQS0# DM0/DQS9 NC/DQS9# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 DQS1 DQS1# DM1/DQS10 NC/DQS10# DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U2 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U9 DQS6 DQS6# DM6/DQS15 NC/DQS15# DQS2 DQS2# DM2/DQS11 NC/DQS11# DM/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U3 DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# RDQS# U10 DQS7 DQS7# DM7/DQS16 NC/DQS16# DQS3 DQS3# DM3/DQS12 NC/DQS12# DM/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DM/ RDQS NU/ CS# DQS DQS# RDQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U4 DQ DQ DQ DQ DQ DQ DQ DQ DQS8 DQS8# DM8/DQS17 NC/DQS17# CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ R E G I S T E R PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN NU/ CS# DQS DQS# RDQS# U11 U12 NU/ CS# DQS DQS# RDQS# CK0 CK0# U5 PLL RESET# U7 SPD EEPROM SCL WP A0 A1 SDA DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM Register A2 VSS SA0 SA1 SA2 U6 RESET# U8 DQS5 DQS5# DM5/DQS14 NC/DQS14# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 PAR_IN S0# BA[2:0] A[15:0] RAS# CAS# WE# CKE0 ODT0 NU/ CS# DQS DQS# RDQS# ERR_OUT RS0#: DDR2 SDRAM RBA[2/1:0]: DDR2 SDRAM RA[13/12:0]: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: DDR2 SDRAM RODT0: DDR2 SDRAM VDDSPD 7 SPD EEPROM VDD/VDDQ DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM General Description General Description The MT9HTF3272, MT9HTF6472(P), and MT9HTF12872(P) DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules organized in x72 configurations. These DDR2 SDRAM modules use internally configured 4-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Register and PLL Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address, command, control, and clock signal loading by isolating DRAM from the system controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions above those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 8: Symbol VDD/VDDQ VIN, VOUT II IOZ IVREF TA TC1 Absolute Maximum Ratings Parameter Min Max Units VDD/VDDQ supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE#, S#, test = 0V) CKE, ODT, BA CK, CK# DM Output leakage current; 0V VOUT VDDQ; DQs and DQ, DQS, DQS# ODT are disabled VREF leakage current; VREF = valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial -0.5 -0.5 -5 +2.3 +2.3 +5 V V A -250 -5 -5 +250 +5 +5 A -18 0 -40 0 -40 +18 +70 +85 +85 +95 A C C C C Notes: 1. The refresh rate is required to double when 85C < TC 95C. 2. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron's Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 9. Table 9: Module and Component Speed Grades Module Speed Grade Component Speed Grade -80E -800 -667 -53E -40E -25E -25 -3 -37E -5E PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications IDD Specifications Table 10: DDR2 IDD Specifications and Conditions - 256MB Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), t RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address bus MR[12] = 0 inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 10 Symbol -667 -53E -40E Units IDD0 810 720 675 mA IDD1 900 810 765 mA IDD2P 45 45 45 mA IDD2Q 360 315 225 mA IDD2N 360 315 270 mA IDD3P 270 225 180 mA 54 54 54 mA IDD3N 450 360 270 mA IDD4W 1,710 1,440 1,125 mA IDD4R 1,620 1,350 1,035 mA IDD5 1,620 1,530 1,485 mA IDD6 45 45 45 mA IDD7 2,250 2,160 2,070 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Table 11: DDR2 IDD Specifications and Conditions - 512MB Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition t t t Operating one bank active-precharge current: CK = CK (IDD), RC = t RC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), t RAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0 bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 11 Symbol -80E -800 -667 -53E -40E Units IDD0 900 810 720 720 mA IDD1 1,035 945 855 810 mA IDD2P 63 63 63 63 mA IDD2Q 450 405 360 315 mA IDD2N 495 450 405 360 mA IDD3P 360 315 270 225 mA 108 108 108 108 mA IDD3N 630 585 495 405 mA IDD4W 1,755 1,530 1,260 1,035 mA IDD4R 1,845 1,620 1,305 1,035 mA IDD5 2,070 1,620 1,530 1,485 mA IDD6 63 63 63 63 mA IDD7 2,700 2,160 2,025 1,980 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Table 12: DDR2 IDD Specifications and Conditions (Die Revision A) - 1GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), t RAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0 bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS= tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -80E -800 -667 -53E -40E Units IDD0 900 810 720 630 mA IDD1 990 900 855 720 mA IDD2P 63 63 63 63 mA IDD2Q 585 495 369 315 mA IDD2N 630 540 405 360 mA IDD3P 405 360 315 315 mA 126 126 126 126 mA IDD3N 675 630 495 405 mA IDD4W 1,665 1,440 1,170 990 mA IDD4R 1,710 1,440 1,305 990 mA IDD5 2,520 2,340 2,250 1,980 mA IDD6 63 63 63 63 mA IDD7 3,015 2,700 2,610 2,340 mA t PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Table 13: DDR2 IDD Specifications and Conditions (Die Revision E) - 1GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), t RAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (IDD); CKE is LOW; Other control and address MR[12] = 0 bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching Symbol -80E -800 -667 -53E -40E Units IDD0 810 765 630 630 mA IDD1 990 900 855 810 mA IDD2P 63 63 63 63 mA IDD2Q 450 360 360 315 mA IDD2N 450 360 360 315 mA IDD3P 360 270 270 270 mA 90 90 90 90 mA IDD3N 540 495 405 360 mA IDD4W 1,440 1,215 1,125 945 mA IDD4R 1,440 1,215 1,125 945 mA IDD5 2,115 1,935 1,890 1,845 mA IDD6 63 63 63 63 mA IDD7 3,015 2,520 2,430 2,340 mA t PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Register and PLL Specifications Table 14: Register Specifications SSTU32864 (non-parity) or SSTU32866 (parity) devices or equivalent JESD82-7A/JESD82-16 Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) SSTL_18 VREF(DC) + 125 VDDQ + 250 mV DC low-level input voltage VIL(DC) SSTL_18 0 VREF(DC) - 125 mV AC high-level input voltage VIH(AC) SSTL_18 VREF(DC) + 250 VDD mV AC low-level input voltage VIL(AC) Address, control, command Address, control, command Address, control, command Address, control, command Parity output Parity output All pins All pins All pins SSTL_18 0 VREF(DC) - 250 mV 1.2 - -5 - - - 0.5 +5 100 40 V V A A mA - Varies by manufacturer A - Varies by manufacturer A 2.5 3.5 pF - Varies by manufacturer pF Output high voltage Output low voltage Input current Static standby Static operating VOH VOL II IDD IDD Dynamic operating (clock tree) IDDD Dynamic operating (per each input) IDDD Input capacitance (per device, per pin) Input capacitance (per device, per pin) CI Notes: PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN CI LVCMOS LVCMOS VI = VDDQ or VSSQ RESET# = VSSQ (IO = 0) RESET# = VSSQ; VI = VIH(AC) or VIL(DC) IO = 0 n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle n/a RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle; One data input switching at tCK/2, 50% duty cycle All inputs VI = VREF 250mV; except RESET# VDDQ = 1.8V RESET# VI = VDDQ or VSSQ 1. Timing and switching specifications for the registers listed above are critical for proper operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Electrical Specifications Table 15: PLL Specifications CU877 device or equivalent JESD82-8.18 Parameter Symbol Pins Condition Min Max Units DC high-level input voltage DC low-level input voltage Input voltage (limits) VIH RESET# LVCMOS 0.65 x VDD - V VIL RESET# LVCMOS - 0.35 x VDD V VIN -0.3 VDDQ + 0.3 V DC high-level input voltage DC low-level input voltage Input differential-pair cross voltage Input differential voltage Input differential voltage Input current VIH RESET#, CK, CK# CK, CK# Differential input 0.65 x VDD - V VIL CK, CK# Differential input - 0.35 x VDD V VIX CK, CK# Differential input VID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V VID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V II RESET# CK, CK# VI = VDDQ or VSSQ VI = VDDQ or VSSQ RESET# = VSSQ; VI = VIH(AC) or VIL(DC) CK = CK# = LOW CK, CK# = 410 MHz, all outputs open (not connected to PCB) VI = VDDQ or VSSQ -10 -250 100 +10 +250 - A A A - - 500 300 A mA 2 3 pF Output disabled current Static supply current Dynamic supply IODL IDDLD IDD n/a CIN Each input Input capacitance Table 16: (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Stabilization time Input clock slew rate SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (-3dB from unity gain) Notes: PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN Symbol Min Max Units tL - 1.0 30 0.0 2.0 15 4 33 -0.50 - s V/ns kHz % MHz slr(i) 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC standard JESD82. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Serial Presence-Detect Serial Presence-Detect Table 17: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Table 18: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD x 0.7 -0.6 - 0.10 0.05 1.6 0.4 2 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3 3 4 1 3 V V V V A A A mA mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Notes: Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s kHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT tSU:STA t SU:STO tWRC 2 2 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. 256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM Module Dimensions Module Dimensions Figure 4: 240-Pin DDR2 RDIMM Front view 2.70 (0.106) MAX 133.50 (5.256) 133.20 (5.244) U7 2.00 (0.079) R (4X) U6 U1 U2 U3 U4 U5 U9 U10 U11 U12 30.15 (1.185) 29.85 (1.175) 17.78 (0.700) TYP U8 2.50 (0.098) D (2X) 2.30 (0.091) TYP 0.76 (0.030) R PIN 1 2.2 (0.087) TYP 1.0 (0.039) TYP 10.00 (0.394) TYP 0.80 (0.031) TYP 1.0 (0.039) TYP 1.37 (0.054) 1.17 (0.046) PIN 120 70.67 (2.78) TYP 123.0 (4.840) TYP Back view No components this side of module 3.05 (0.12) TYP PIN 240 PIN 121 5.0 (0.197) TYP 55.0 (2.165) TYP Notes: 63.0 (2.48) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions. 3. Dimensional diagram shows Raw Card A PCB. Raw Card F PCB has identical dimensions. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82250868/Source: 09005aef82250815 HTF9C32_64_128x72.fm - Rev. E 6/08 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.