Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 1©2003 Micron Technology, Inc. All rights reserved.
DDR2 SDRAM RDIMM
MT9HTF3272 – 256MB
MT9HTF6472(P) – 512MB
MT9HTF12872(P) – 1GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 240-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 256MB (32 Meg x 72), 512MB (64 Meg x 72),
1GB (128 Meg x 72)
• Supports ECC error detection and correction
•V
DD = VDDQ = +1.8V
•V
DDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
•4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1: 240-Pin RDIMM (MO-237
R/C A Non-Parity, R/C F Parity)
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not available in 256MB module density.
Options Marking
•Parity P
• Operating temperature1
–Commercial (0°C ≤ TA ≤ +70°C) None
–Industrial (–40°C ≤ TA ≤ +85°C) I
•Package
–240-pin DIMM (Lead-free) Y
• Frequency/CAS latency2
–2.5ns @ CL = 5 (DDR2-800)3-80E
–2.5ns @ CL = 6 (DDR2-800)3-800
–3.0ns @ CL = 5 (DDR2-667) -667
–3.75ns @ CL = 4 (DDR2-533) -53E
–5.0ns @ CL = 3 (DDR2-400) -40E
•PCB height
–30mm (1.18in)
PCB height: 30mm (1.18in)
Table 1: Key Timing Parameters
Speed
Grade
Industry
Nomenclature
Data Rate (MT/s) tRCD
(ns)
tRP
(ns)
tRC
(ns)CL = 6 CL = 5 CL = 4 CL = 3
-80E PC2-6400 – 800 533 – 12.5 12.5 55
-800 PC2-6400 800 667 533 – 12.5 12.5 55
-667 PC2-5300 – 667 533 400 15 15 55
-53E PC2-4200 – – 533 400 15 15 55
-40E PC2-3200 – – 400 400 15 15 55
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 2©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9HTF6472Y-667D2.
Table 2: Addressing
Parameter 256MB 512MB 1GB
Refresh count 8K 8K 8K
Row address 8K A[12:0] 16K A[13:0] 16K A[13:0]
Device bank address 4 BA[1:0] 4 BA[1:0] 8 BA[2:0]
Device page size per bank 1KB 1KB 1KB
Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8)
Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0# 1 S0#
Table 3: Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H32M8,1 256Mb DDR2 SDRAM
Part Number2Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Latency
(CL - tRCD - tRP)
MT9HTF3272I(I)Y-667__ 256MB 32 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT9HTF3272(I)Y-53E__ 256MB 32 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT9HTF3272(I)Y-40E__ 256MB 32 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 4: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8,1 512Mb DDR2 SDRAM
Part Number2Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Latency
(CL - tRCD - tRP)
MT9HTF6472(P)(I)Y-80E__ 512MB 64 Meg x 72 6.2 GB/s 2.5ns/800 MT/s 5-5-5
MT9HTF6472(P)(I)Y-800__ 512MB 64 Meg x 72 6.2 GB/s 2.5ns/800 MT/s 6-6-6
MT9HTF6472(P)(I)Y-667__ 512MB 64 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT9HTF6472(P)(I)Y-53E__ 512MB 64 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT9HTF6472(P)(I)Y-40E__ 512MB 64 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
Table 5: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8,1 1Gb DDR2 SDRAM
Part Number2Module
Density Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Latency
(CL - tRCD - tRP)
MT9HTF12872(P)(I)Y-80E__ 1GB 128 Meg x 72 6.2 GB/s 2.5ns/800 MT/s 5-5-5
MT9HTF12872(P)(I)Y-800__ 1GB 128 Meg x 72 6.2 GB/s 2.5ns/800 MT/s 6-6-6
MT9HTF12872(P)(I)Y-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5
MT9HTF12872(P)(I)Y-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4
MT9HTF12872(P)(I)Y-40E__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 3©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Notes: 1. Pin 55 is NC for non-parity and ERR_OUT for parity.
2. Pin 68 is NC for non-parity and PAR_IN for parity.
3. Pin 196 is NC for 512MB or A13 for 1GB, 2GB and parity.
4. Pins 173 and 174 are NC or A15 and A14 for parity.
Table 6: Pin Assignments
240-Pin DDR2 RDIMM Front 240-Pin DDR2 RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ211DM5/
DQS14
2V
SS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC/
DQS14#
3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS
4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46
5V
SS 35 VSS 65 VSS 95 DQ42 125 DM0/
DQS9
155 DM3/
DQS12
185 CK0 215 DQ47
6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NC/
DQS9#
156 NC/
DQS12#
186 CK0# 216 VSS
7 DQS037DQS367 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52
8V
SS 38 VSS 682NC/
PAR_IN
98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53
9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS
10 DQ3 40DQ2770 A10 100 VSS 130 VSS 160 VSS 190 BA1 220 RFU
11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 CB4 191 VDDQ221 RFU
12 DQ8 42 CB0 72 VDDQ 102 NC 132 DQ13 162 CB5 192 RAS# 222 VSS
13 DQ9 43 CB1 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6/
DQS15
14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1/
DQS10
164 DM8/
DQS17
194 VDDQ224 NC/
DQS15#
15DQS1#45DQS8#75 V
DDQ105DQS6 135 NC/
DQS10#
165 NC/
DQS17#
195 ODT0 225 VSS
16 DQS1 46 DQS8 76 S1# 106 VSS 136 VSS 166 VSS 196 NC/A133226 DQ54
17 VSS 47 VSS 77 ODT1 107 DQ50 137 RFU 167 CB6 197 VDD 227 DQ55
18 RESET# 48 CB2 78 VDDQ 108 DQ51 138 RFU 168 CB7 198 VSS 228 VSS
19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60
20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61
21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 CKE1 201 VSS 231 Vss
22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4/
DQS13
232 DM7/
DQS16
23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC/A154203 NC/
DQS13#
233 NC/
DQS16#
24 DQ16 54 NC/BA2 84 DQS4 114 DQS7 144 DQ21 174 NC/A144204 VSS 234 VSS
25 DQ17 551NC/
ERR_OUT
85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62
26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2/
DQS11
176 A12 206 DQ39 236 DQ63
27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC/
DQS11#
177 A9 207 VSS 237 VSS
28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD
29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0
30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 4©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information
Symbol Type Description
A[15:0] Input Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one device bank (A10 LOW,
device bank selected by BA[2/1:0]) or all device banks (A10 HIGH). A[12:0] (256MB) and
A[13:0] (512MB 1GB). A[15:14] are connected for parity.
BA[2:0] Input Bank address inputs: BA[2/1:0] define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA[2/1:0] define which mode register
(MR, EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0]
(256MB, 512MB) and BA[2:0] (1GB).
CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
CKE0 Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
DM[8:0]/
DQS[17:9]
Input Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to
match that of the DQ and DQS pins. If RDQS is disabled, RDQS[8:0] become DM[8:0] and
RDQS#[8:0] are not used.
ODT0 Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
PAR_INInput Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA[2:0] Input Serial address inputs: These pins are used to configure the SPD EEPROM address range
on the I2C bus.
SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from
the SPD EEPROM.
CB[7:0] I/O Check bits.
DQ[63:0] I/O Data input/output: Bidirectional data bus.
DQS[8:0],
DQS#[8:0]
I/O Data strobe: DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the SPD EEPROM on the module on the I2C bus.
ERR_OUT Output
(open drain)
Parity error output: Parity error found on the command and address bus.
EVENT# Output
(open drain)
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module
VDD.
VDDSPD Supply SPD EEPROM power supply: +1.7V to +3.6V.
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 5©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
VREF Supply Reference voltage: VDD/2.
VSS Supply Ground.
NC – No connect: These pins are not connected on the module.
RFU – Reserved for future use.
Table 7: Pin Descriptions (continued)
Pin numbers may not correlate with symbols; refer to Table 6 on page 3 for more information
Symbol Type Description
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 6©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram – Raw Card A Non-Parity
U1
A0
SPD EEPROM
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS# DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
RS0#
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
U9
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DQS1
DQS1#
DM1/DQS10
NC/DQS10#
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
DQS6
DQS6#
DM6/DQS15
NC/DQS15#
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
DQS7
DQS7#
DM7/DQS16
NC/DQS16#
DQS8
DQS8#
DM8/DQS17
NC/DQS17#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U10
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U3
U4
U5
U12
U11
PLL
U7
CK0
CK0#
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
Register
RESET#
U8
U6
V
REF
V
SS
DDR2 SDRAM
DDR2 SDRAM
V
DD
/
V
DD
Q
V
DDSPD
SPD EEPROM
DDR2 SDRAM
R
E
G
I
S
T
E
R
S0#
BA[2/1:0]
A[13/12:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
RS0#: DDR2 SDRAM
RBA[2/1:0]: DDR2 SDRAM
RA[13/12:0]: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: DDR2 SDRAM
RODT0: DDR2 SDRAM
V
SS
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 7©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Functional Block Diagrams
Figure 3: Functional Block Diagram – Raw Card F Parity
U1
A0
SPD EEPROM
A1 A2
SA0 SA1 SA2
SDA
SCL
WP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM/ NU/ CS# DQS DQS#
RDQS RDQS# DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
RS0#
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
U8
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DQS1
DQS1#
DM1/DQS10
NC/DQS10#
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
DQS6
DQS6#
DM6/DQS15
NC/DQS15#
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
DQS7
DQS7#
DM7/DQS16
NC/DQS16#
DQS8
DQS8#
DM8/DQS17
NC/DQS17#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM/ NU/ CS# DQS DQS#
RDQS RDQS# DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U9
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM/ NU/ CS# DQS DQS#
RDQS RDQS# DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM/ NU/ CS# DQS DQS#
RDQS RDQS# DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM/ NU/ CS# DQS DQS#
RDQS RDQS#
U3
U4
U5
U11
U10
PLL
U7
CK0
CK0#
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
Register
RESET#
U12
U6
V
REF
V
SS
DDR2 SDRAM
DDR2 SDRAM
V
DD
/V
DD
Q
V
DDSPD
SPD EEPROM
DDR2 SDRAM
R
E
G
I
S
T
E
R
P
AR
_I
N
S0#
BA[2:0]
A[15:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
ERR_OUT
RS0#: DDR2 SDRAM
RBA[2/1:0]: DDR2 SDRAM
RA[13/12:0]: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: DDR2 SDRAM
RODT0: DDR2 SDRAM
V
SS
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 8©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
General Description
General Description
The MT9HTF3272, MT9HTF6472(P), and MT9HTF12872(P) DDR2 SDRAM modules are
high-speed, CMOS, dynamic random-access 256MB, 512MB, and 1GB memory modules
organized in x72 configurations. These DDR2 SDRAM modules use internally configured
4-bank (256Mb, 512Mb) or 8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0],
which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected
to VSS, permanently disabling hardware write protect.
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 9©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 8 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions above those indicated in each device’s data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Notes: 1. The refresh rate is required to double when 85°C < TC ≤ 95°C.
2. For further information, refer to technical note TN-00-08: Thermal Applications, available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades, as shown in Table 9.
Table 8: Absolute Maximum Ratings
Symbol Parameter Min Max Units
VDD/VDDQVDD/VDDQ supply voltage relative to VSS –0.5 +2.3 V
VIN, VOUT Voltage on any pin relative to VSS –0.5 +2.3 V
IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;
VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under
test = 0V)
Address inputs
RAS#, CAS#, WE#, S#,
CKE, ODT, BA
–5 +5 µA
CK, CK# –250 +250
DM –5 +5
IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and
ODT are disabled
DQ, DQS, DQS# –5 +5 µA
IVREF VREF leakage current; VREF = valid VREF level –18 +18 µA
TAModule ambient operating temperature Commercial 0+70°C
Industrial –40 +85 °C
TC1DDR2 SDRAM component case operating
temperature2Commercial 0+85°C
Industrial –40 +95 °C
Table 9: Module and Component Speed Grades
Module Speed Grade Component Speed Grade
-80E -25E
-800 -25
-667 -3
-53E -37E
-40E -5E
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256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current: tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 810 720 675 mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as IDD4W
IDD1 900 810 765 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
IDD2P 45 45 45 mA
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
IDD2Q 360 315 225 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N 360 315 270 mA
Active power-down current: All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 270 225 180 mA
Slow PDN exit
MR[12] = 1
54 54 54 mA
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N 450 360 270 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
IDD4W 1,710 1,440 1,125 mA
Operating burst read current: All device banks open; Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD4R 1,620 1,350 1,035 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD5 1,620 1,530 1,485 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD6 454545mA
Operating bank interleave read current: All device banks interleaving
reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7 2,250 2,160 2,070 mA
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 11 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Table 11: DDR2 IDD Specifications and Conditions – 512MB
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition Symbol
-80E
-800 -667 -53E -40E Units
Operating one bank active-precharge current: tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0 900 810 720 720 mA
Operating one bank active-read-precharge current: IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH
between valid commands; Address bus inputs are switching; Data
pattern is same as IDD4W
IDD1 1,035 945 855 810 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P 63 63 63 63 mA
Precharge quiet standby current: All device banks idle;
tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
IDD2Q 450 405 360 315 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD2N 495 450 405 360 mA
Active power-down current: All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 360 315 270 225 mA
Slow PDN exit
MR[12] = 1
108 108 108 108 mA
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD3N 630 585 495 405 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4W 1,755 1,530 1,260 1,035 mA
Operating burst read current: All device banks open; Continuous
burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4R 1,845 1,620 1,305 1,035 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD5 2,070 1,620 1,530 1,485 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD663636363mA
Operating bank interleave read current: All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
IDD7 2,700 2,160 2,025 1,980 mA
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 12 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Table 12: DDR2 IDD Specifications and Conditions (Die Revision A) – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
Parameter/Condition Symbol
-80E
-800 -667 -53E -40E Units
Operating one bank active-precharge current: tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0 900 810 720 630 mA
Operating one bank active-read-precharge current: IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH
between valid commands; Address bus inputs are switching; Data
pattern is same as IDD4W
IDD1 990 900 855 720 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P 63 63 63 63 mA
Precharge quiet standby current: All device banks idle;
tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
IDD2Q 585 495 369 315 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD2N 630 540 405 360 mA
Active power-down current: All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 405 360 315 315 mA
Slow PDN exit
MR[12] = 1
126 126 126 126 mA
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD3N 675 630 495 405 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4W 1,665 1,440 1,170 990 mA
Operating burst read current: All device banks open; Continuous
burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS= tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4R 1,710 1,440 1,305 990 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every
tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD5 2,520 2,340 2,250 1,980 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD663636363mA
Operating bank interleave read current: All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
IDD7 3,015 2,700 2,610 2,340 mA
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 13 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Table 13: DDR2 IDD Specifications and Conditions (Die Revision E) – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
Parameter/Condition Symbol
-80E
-800 -667 -53E -40E Units
Operating one bank active-precharge current: tCK = tCK (IDD),
tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0 810 765 630 630 mA
Operating one bank active-read-precharge current: IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH
between valid commands; Address bus inputs are switching; Data
pattern is same as IDD4W
IDD1 990 900 855 810 mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
IDD2P 63 63 63 63 mA
Precharge quiet standby current: All device banks idle;
tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus
inputs are stable; Data bus inputs are floating
IDD2Q 450 360 360 315 mA
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD2N 450 360 360 315 mA
Active power-down current: All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P 360 270 270 270 mA
Slow PDN exit
MR[12] = 1
90 90 90 90 mA
Active standby current: All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD3N 540 495 405 360 mA
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4W 1,440 1,215 1,125 945 mA
Operating burst read current: All device banks open; Continuous
burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4R 1,440 1,215 1,125 945 mA
Burst refresh current: tCK = tCK (IDD); REFRESH command at every
tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD5 2,115 1,935 1,890 1,845 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
IDD663636363mA
Operating bank interleave read current: All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
IDD7 3,015 2,520 2,430 2,340 mA
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 14 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Register and PLL Specifications
Notes: 1. Timing and switching specifications for the registers listed above are critical for proper
operation of the DDR2 SDRAM registered DIMMs. These are meant to be a subset of the
parameters for the specific device used on the module. Detailed information for this regis-
ter is available in JEDEC standard JESD82.
Table 14: Register Specifications
SSTU32864 (non-parity) or SSTU32866 (parity) devices or equivalent JESD82-7A/JESD82-16
Parameter Symbol Pins Condition Min Max Units
DC high-level
input voltage
VIH(DC) Address,
control,
command
SSTL_18 VREF(DC) + 125 VDDQ + 250 mV
DC low-level
input voltage
VIL(DC) Address,
control,
command
SSTL_18 0 VREF(DC) - 125 mV
AC high-level
input voltage
VIH(AC) Address,
control,
command
SSTL_18 VREF(DC) + 250 VDD mV
AC low-level
input voltage
VIL(AC) Address,
control,
command
SSTL_18 0 VREF(DC) - 250 mV
Output high voltage VOH Parity output LVCMOS 1.2 – V
Output low voltage VOL Parity output LVCMOS – 0.5 V
Input current IIAll pins VI = VDDQ or VSSQ–5 +5µA
Static standby IDD All pins RESET# = VSSQ (IO = 0) – 100 µA
Static operating IDD All pins RESET# = VSSQ;
VI = VIH(AC) or VIL(DC)
IO = 0
–40mA
Dynamic operating
(clock tree)
IDDD n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle
–Varies by
manufacturer
µA
Dynamic operating
(per each input)
IDDD n/a RESET# = VDD, VI = VIH(AC) or
VIL(AC), IO = 0; CK and CK#
switching 50% duty cycle;
One data input switching at
tCK/2, 50% duty cycle
–Varies by
manufacturer
µA
Input capacitance
(per device, per pin)
CIAll inputs
except RESET#
VI = VREF ±250mV;
VDDQ = 1.8V
2.5 3.5 pF
Input capacitance
(per device, per pin)
CIRESET# VI = VDDQ or VSSQ–Varies by
manufacturer
pF
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256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Notes: 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM.
This is a subset of parameters for the specific PLL used. Detailed PLL information is available
in JEDEC standard JESD82.
Table 15: PLL Specifications
CU877 device or equivalent JESD82-8.18
Parameter Symbol Pins Condition Min Max Units
DC high-level input
voltage
VIH RESET# LVCMOS 0.65 × VDD –V
DC low-level input
voltage
VIL RESET# LVCMOS – 0.35 × VDD V
Input voltage (limits) VIN RESET#, CK,
CK#
–0.3 VDDQ + 0.3 V
DC high-level input
voltage
VIH CK, CK# Differential input 0.65 × VDD –V
DC low-level input
voltage
VIL CK, CK# Differential input – 0.35 × VDD V
Input differential-pair
cross voltage
VIX CK, CK# Differential input (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V
Input differential
voltage
VID(DC) CK, CK# Differential input 0.3 VDDQ + 0.4 V
Input differential
voltage
VID(AC) CK, CK# Differential input 0.6 VDDQ + 0.4 V
Input current IIRESET# VI = VDDQ or VSSQ –10 +10 µA
CK, CK# VI = VDDQ or VSSQ–250 +250µA
Output disabled
current
IODL RESET# = VSSQ; VI = VIH(AC)
or VIL(DC)
100 – µA
Static supply current IDDLD CK = CK# = LOW – 500 µA
Dynamic supply IDD n/a CK, CK# = 410 MHz, all
outputs open
(not connected to PCB)
–300mA
Input capacitance CIN Each input VI = VDDQ or VSSQ2 3pF
Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics
Parameter Symbol Min Max Units
Stabilization time tL– 15µs
Input clock slew rate slr(i) 1.0 4 V/ns
SSC modulation frequency 30 33 kHz
SSC clock input frequency deviation 0.0 –0.50 %
PLL loop bandwidth (–3dB from unity gain) 2.0 – MHz
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HTF9C32_64_128x72.fm - Rev. E 6/08 EN 16 ©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron's SPD page:
www.micron.com/SPD.
Table 17: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS
Parameter/Condition Symbol Min Max Units
Supply voltage VDDSPD 1.7 3.6 V
Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V
Input low voltage: Logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V
Output low voltage: IOUT = 3mA VOL –0.4V
Input leakage current: VIN = GND to VDD ILI 0.10 3 µA
Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA
Standby current ISB 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz ICCR0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW23mA
Table 18: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start tBUF 1.3 – µs
Data-out hold time tDH 200 – ns
SDA and SCL fall time tF – 300 ns 2
Data-in hold time tHD:DAT 0 – µs
Start condition hold time tHD:STA 0.6 – µs
Clock HIGH period tHIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs tI–50ns
Clock LOW period tLOW 1.3 – µs
SDA and SCL rise time tR–0.3µs2
SCL clock frequency fSCL – 400 kHz
Data-in setup time tSU:DAT 100 – ns
Start condition setup time tSU:STA 0.6 – µs 3
Stop condition setup time tSU:STO 0.6 – µs
WRITE cycle time tWRC – 10 ms 4
®
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prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Module Dimensions
PDF: 09005aef82250868/Source: 09005aef82250815 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF9C32_64_128x72.fm - Rev. E 6/08 EN 17 ©2003 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 4: 240-Pin DDR2 RDIMM
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for com-
plete design dimensions.
3. Dimensional diagram shows Raw Card A PCB. Raw Card F PCB has identical dimensions.
30.15 (1.185)
29.85 (1.175)
PIN 1
17.78 (0.700)
TYP
2.50 (0.098) D (2X)
2.30 (0.091) TYP
5.0 (0.197) TYP
123.0 (4.840)
TYP
1.0 (0.039)
TYP
0.80 (0.031)
TYP
2.00 (0.079) R (4X)
0.76 (0.030) R
PIN 120
Front view
133.50 (5.256)
133.20 (5.244)
55.0 (2.165)
TYP
63.0 (2.48)
TYP
10.00 (0.394)
TYP
Back view
PIN 240 PIN 121
1.37 (0.054)
1.17 (0.046)
2.70 (0.106)
MAX
No components this side of module
U1 U2 U3 U4 U5
U6
U7
U8
U9 U10 U11 U12
1.0 (0.039)
TYP
2.2 (0.087)
TYP
3.05 (0.12)
TYP
70.67 (2.78)
TYP
