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FAN501A Offline DCM / CCM Flyback PWM Controller for Charger Applications Features Description WSaver(R) Technology Provides Ultra-Low Standby Power Consumption for Energy Star's 5-Star Level (<30 mW) Constant-Current (CC) Control without Secondary-Side Feedback Circuitry for Discontinuous Conduction Mode (DCM) and Continuous Conduction Mode (CCM) Dual-Frequency Function Changes Switching Frequency (140 kHz / 85 kHz) According to Input Voltage to Maximize Transformer Utilization and Improve Efficiency The advanced PWM controller, FAN501A, simplifies isolated power supply design that requires CC regulation of the output. The output current is precisely estimated with only the information in the primary side of the transformer and controlled with an internal compensation circuit, removing the output current-sensing loss and eliminating external CC control circuitry. With an extremely low operating current (250 A), Burst Mode maximizes light-load efficiency, allowing conformance to worldwide Standby Mode efficiency guidelines. High Power Density and High Conversion Efficiency in CCM Compact Charger Applications Frequency Hopping to Reduce EMI Noise Peak-Current-Mode Control with Slope Compensation to Avoid Sub-Harmonic Oscillation High-Voltage Startup Vo Precise Maximum Output Power Limit by CC Regulation through External Resistor Adjustment Programmable Over-Temperature Protection with Latch Mode through External NTC Resistor Two-Level UVLO Reduces Input Power in Output Short Situation Compared with a conventional approach using external control circuit in the secondary side for CC regulation, the FAN501A can reduce total cost, component count, size, and weight; while increasing efficiency, productivity, and system reliability. VS Over-Voltage Protection with Latch Mode Maximum Typical Minimum Io Figure 1. Typical Output V-I Characteristic VDD Over-Voltage Protection with Auto Restart Available in MLP 4 X 3 Package Applications Battery Chargers for Smart Phones, Feature Phones, and Tablet PCs AC-DC Adapters for Portable Devices or Battery Chargers that Require CV / CC Control Ordering Information Part Number Operating Temperature Range Package Packing Method FAN501AMPX -40C to +125C 10-Lead, MLP, QUAD, JEDEC MO-220 4 mm x 3 mm, 0.8 mm Pitch, Single DAP Tape & Reel (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications April 2014 RSNS LF CSNS TX + DR RSNP Bridge CSNP NP CBLK1 AC IN CBLK2 NS CO Vo - DSNP RHV Choke Fuse DG RBias1 FAN501A RG2 RF1 Photo coupler RG1 CComp2 HV FB RComp1 GATE COMP CFB RCOMP RSD CComp1 Shunt regulator DVDD RF2 VS RVS1 PGND CVDD Figure 2. RCS VDD SGND NTC RCSF CS SD Photo coupler RBias2 CVS NA RVS2 Typical Application Internal Block Diagram VDD HV SD Fault OTP Fault VSOVP Fault 8 Latch Protection 1 PWM Control Block GATE VDD OVP Fault 7.5V Latch released VDD VDD UVLO 17.5V / 6V 2 10 PGND Internal bias 5V VDD OVP Fault OCP Fault Burst / Green Mode 5V ZFB Slope Compensation COMV VSAW FB VCS-LIM 6 COMI AV LEB 9 CS IO Estimator 5V Frequency Hopping CC Control Correction 4 COMP ISD SD 7 VSD-TH SD Fault VSH VSOVP Fault S/H Zero Current Detector Line Voltage Detector VVS-OVP S/H = Sample and Hold 5 3 SGND VS Figure 3. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 Function Block Diagram www.fairchildsemi.com 2 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Application Diagram F- Fairchild Logo Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (MP=MLP) M: Manufacture Flow Code ZXYTT FAN501A TM Figure 4. Top Mark HV SD 8 7 Pin Configuration CS 9 PGND 10 FAN501A 1 2 3 GATE VDD VS Figure 5. 6 FB 5 SGND 4 COMP Pin Assignments Pin Definitions Pin # Name Description 1 GATE 2 VDD 3 VS 4 COMP CC Control Correction. This pin connects to external resistor to program the CC control correction weighting. 5 SGND Signal Ground 6 FB Feedback. An opto-coupler is typically connected to this pin to provide feedback information to the internal PWM comparator. This feedback is used to control the duty cycle in ConstantVoltage (CV) regulation. 7 SD Shut Down. This pin is implemented for external over-temperature protection by connecting to an NTC thermistor. 8 HV High Voltage. This pin connects to a DC bus for high-voltage startup. 9 CS Current Sense. This pin connects to a current-sense resistor to detect the MOSFET current for Peak-Current-Mode control for output regulation. The current-sense information is also used to estimate the output current for CC regulation. 10 PGND PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. The gate driving voltage is internally clamped at 7.5 V. Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external capacitor. Voltage Sense. This pin detects the output voltage information and diode current discharge time based on the voltage of the auxiliary winding. It also senses sink current through the auxiliary winding to detect input voltage information. Power Ground (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 3 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Marking Information Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VHV HV Pin Input Voltage 500 V VVDD DC Supply Voltage 30 V VVS VS Pin Input Voltage -0.3 6.0 V VCS CS Pin Input Voltage -0.3 6.0 V VFB FB Pin Input Voltage -0.3 6.0 V COMP Pin Input Voltage -0.3 6.0 V VSD SD Pin Input Voltage -0.3 6.0 V PD Power Dissipation (TA=25C) 850 mW JA Thermal Resistance (Junction-to-Air) 150 C/W JC Thermal Resistance (Junction-to-Case) 10 C/W TJ Operating Junction Temperature -40 +150 C Storage Temperature Range -40 +150 C +260 C VCOMP TSTG TL ESD Lead Temperature (Wave soldering or IR, 10 Seconds) Electrostatic Discharge (3) Capability Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 (Except HV Pin) 5.0 Charged Device Model, JEDEC:JESD22_C101 (Except HV Pin) 2.0 kV Notes: 1. All voltage values, except differential voltages, are given with respect to the GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD ratings including HV pin: HBM=3.5 kV, CDM=1.25 kV. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 4 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Absolute Maximum Ratings VDD=15 V and TJ=-40~125C unless noted. Symbol Parameter Conditions Min. Typ. Max. Unit 30 V 2.0 5.0 mA 0.8 10.0 A HV Section VHV-MIN Minimum Startup Voltage on HV Pin IHV Supply Current Drawn from HV Pin VHV=120 V, VDD=0 V Leakage Current Drawn from HV Pin VHV=500 V, VDD=VDD-OFF+1 V VDD-ON Turn-On Threshold Voltage VDD Rising 16.0 17.5 18.5 V VDD Falling 5.5 6.0 6.5 V 3.4 4.4 5.1 V IHV-LC 1.2 VDD Section VDD-OFF Turn-Off Threshold Voltage VDD-HVON Threshold Voltage for HV Startup VDD-DLH Threshold Voltage for Latch Release 2.50 V IDD-ST Startup Current VDD=VDD-ON-0.16 V 150 250 A IDD-OP Operating Supply Current VCS=5.0 V, VS=3 V, VFB=3 V, VDD=15 V, CGATE=1 nF 3.5 4.0 mA IDD-Burst Burst Mode Operating Supply Current VCS=0.3 V, VS=0 V, VFB=0 V VDD=VDD-ONVDD-OVP10 V, CGATE=1 nF 250 300 A VDD-OVP VDD Over-Voltage Protection Level 26.5 28.0 29.5 V Oscillator Section fOSC--H Operating Frequency, IVS Below (4) Threshold IVS-L(Low Line) VCS=5 V, VS=2.5 V, VFB=6 V 133 140 147 kHz fOSC--L Operating Frequency, IVS Over (4) Threshold IVS-H(High Line) VCS=5 V, VS=2.5 V, VFB=4 V 79 85 91 kHz fHopping-H Frequency Hopping Range, High Line VCS=0.5 V, VS=0.7 V, VFB=3 V 5.5 7.0 8.5 kHz fHopping-L Frequency Hopping Range, Low Line VCS=0.5 V, VS=0.0 V, VFB=3 V 2.5 4.0 5.5 kHz tHopping Frequency Hopping Period 2.54 ms Feedback Input Section ZFB FB Pin Input Impedance AV Internal Voltage Attenuator of FB Pin VFB-Open 36 41 48 1/2.5 k V/V FB Pin Pull-Up Voltage FB Pin Open 5.00 5.50 5.90 V VFB-Burst-H FB Threshold to Enable Gate Drive in (4) Burst Mode VFB Rising with VCS=0.3 V, VS=0 V 1.60 1.70 1.80 V VFB-Burst-L FB Threshold to Disable Gate Drive in (4) Burst Mode VFB Falling with VCS=0.3 V, VS=0 V 1.55 1.65 1.75 V Over-Temperature Protection Section TOTP Threshold Temperature for Over-Temperature Protection C 140 Shutdown Function Section ISD VSD-TH SD Pin Source Current VCS=0.3 V 85 100 115 A Threshold Voltage for Shutdown Function Enable VCS=0.3 V 0.85 1.00 1.15 V Continued on the following page... (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 5 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Electrical Characteristics VDD=15 V and TJ=-40~125C unless noted. Symbol Parameter Conditions Min. Typ. Max. Unit 8.75 10.00 11.25 A Voltage-Sense Section ITC Temperature-Independent Bias Current VCS=5 V, VFB=3 V IVS-H VS Source Current Threshold to fOSC-L Operation 750 A IVS-L VS Source Current Threshold to fOSC-H Operation 680 A IVS-Brownout VS Source Current Threshold to Enable Brownout 160 A VVS-OVP Output Over-Voltage Protection with VS Sampling Voltage NVS-OVP Output Over-Voltage Protection Debounce Cycle Counts (4) 3.10 (4) 3.20 3.30 V 8 Cycle Current-Sense Section VVR Internal Reference Voltage for CC Regulation 2.460 2.500 2.540 V VCCR Variation Test Voltage on CS Pin for (4) CC Regulation 2.405 2.430 2.455 V KCCM Design Parameter in CC Regulation 12.0 V/V VCS-LIM VCS=0.375 V, VCOMP= 1.59 V, VS= 6 V 0.85 0.90 V tPD GATE Output Turn-Off Delay 100 200 ns tLEB Leading-Edge Blanking Time 150 200 ns VSlope Current Limit Threshold Voltage Slope Compensation 0.80 Maximum Duty Cycle 66.6 mV/s Constant Current Correction VCS=0.3 V, VFB=2.5 V, VS=0.3 V 25 35 45 A Minimum On Time VCS=0.6 V, VS=0.3 V, VFB=1.7 V 450 550 650 ns Limited Minimum On Time VCS=0.6 V, VS=0.5 V, VFB=1.7 V 0.95 1.20 1.45 s DCYMAX Maximum Duty Cycle VCS=0.6 V, VS=0 V, VFB=4 V 60.0 68.5 77.0 % VGATE-L Gate Output Voltage Low 1.5 V ICOMP-H COMP Pin Source Current as VS=0.3 V GATE Section tON-MIN tON-MIN-Limit 0 VDD-PMOS-ON Internal Gate PMOS Driver ON 7.0 7.5 8.0 V VDD-PMOS-OFF Internal Gate PMOS Driver OFF 9.0 9.5 10.0 V tr Rising Time VCS=0 V, VS=0 V, CGATE=1 nF 100 140 180 ns tf Falling Time VCS=0 V, VS=0 V, CGATE=1 nF 30 50 70 ns VDD=25 V 7.0 7.5 8.0 V VGATE-CLAMP Gate Output Clamping Voltage Notes: 4. TJ guaranteed range at 25C. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 6 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Electrical Characteristics 6.05 17.8 6.00 17.5 5.95 VDD-OFF (V) VDD-ON (V) 18.1 17.2 16.9 5.75 16.3 -40 -30 Figure 6. -15 0 25 50 75 Temperature ( C) 85 100 -40 125 Figure 7. VDD Turn-On Threshold Voltage (VDD-ON) vs. Temperature 3.9 280 3.7 270 3.5 260 IDD-Burst (A) IDD-OP (mA) 5.85 5.80 16.6 3.3 3.1 2.9 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 VDD Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 250 240 230 2.7 220 -40 -30 Figure 8. -15 0 25 50 75 Temperature ( C) 85 100 125 -40 Figure 9. Operating Supply Current (IDD-OP) vs. Temperature 149 94 146 91 143 88 fOSC-L (kHZ) fOSC-H (kHZ) 5.90 140 137 134 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 Burst Mode Operating Supply Current (IDD-Burst) vs. Temperature 85 82 79 131 76 -40 Figure 10. -30 -15 0 25 50 75 Temperature ( C) 85 100 125 -40 -15 0 25 50 75 Temperature ( C) 85 100 125 Figure 11. Operating Frequency while IVS < IVS-H Threshold (fOSC-L) vs. Temperature Operating Frequency, IVS < IVS-L Threshold (fOSC-H) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 -30 www.fairchildsemi.com 7 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Typical Performance Characteristics 2.56 3.30 2.54 3.25 2.52 VVR (V) VVS-OVP (V) 3.35 3.20 3.15 2.48 3.10 2.46 2.44 3.05 -40 -30 -15 0 25 50 75 Temperature ( C) 85 100 -40 125 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 Figure 13. Internal Reference Voltage for CC Regulation (VVR) vs. Temperature Output OVP with VS Sampling Voltage (VVS-OVP) vs. Temperature 2.49 10.9 2.47 10.6 2.45 10.3 ITC (A) VCCR (V) Figure 12. 2.43 10.0 2.41 9.7 2.39 9.4 9.1 2.37 -40 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 -40 Figure 14. Variation Test Voltage on CS Pin for CC Regulation (VCCR) vs. Temperature Figure 15. 0.88 79 0.87 76 0.86 73 DCYMAX (%) VCS-LIM (V) 2.50 0.85 0.84 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 Temperature-Independent Bias Current (ITC) vs. Temperature 70 67 64 0.83 61 0.82 -40 Figure 16. -30 -15 0 25 50 75 Temperature ( C) 85 100 -40 125 -30 Figure 17. Current Limit Threshold Voltage (VCS-LIM) vs. Temperature -15 0 25 50 75 Temperature ( C) 85 100 125 Maximum Duty Cycle (DCYMAX) vs. Temperature 8.1 VGATE-Clamp (V) 7.9 7.7 7.5 7.3 7.1 6.9 -40 -30 -15 0 25 50 75 Temperature ( C) 85 100 125 Figure 18. Gate Output Clamping Voltage (VGATE-Clamp) vs. Temperature (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 8 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Typical Performance Characteristics (Continued) FAN501A is an offline flyback converter controller that offers constant output voltage (CV) regulation through opto-coupler feedback circuitry and constant output current (CC) regulation with primary-side control. Advanced output current estimation technology allows stable CC regulation regardless of the power stage operation mode: Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM). while COMI is saturated to HIGH level. During CC regulation, COMI determines the duty cycle while COMV is saturated to HIGH level. VBLK Vo PWM Control Block GATE ZCOMP Dual-switching-frequency operation adaptively selects the operational frequency between 85 kHz and 140 kHz according to the line voltage. As a result, the transformer can be fully utilized and high efficiency is maintained over entire line range. A frequency-hopping function is incorporated to reduce EMI noise. Slope Compenastion COMV CS VSAW AV COMI FB IO Estimator Line voltage information through transformer auxiliary winding is used for dual-switching frequency selection and line voltage CC correction. VS Zero Current Detector Figure 19. mWSaver(R) technology, including high-voltage startup and ultra-low operating current in Burst Mode, enables system compliance with Energy Star's 5-star requirement of <30 mW standby power consumption. Simplified CV / CC PWM Control Circuit CV CC COMI Protections such as VDD Over-Voltage Protection (VDD OVP), VS Over-Voltage Protection (VS OVP), internal Over-Temperature Protection (OTP), and brownout protection improve reliability. COMV VSAW All these innovative technologies allow the FAN501A to offer low total cost, reduced component counts, small size / weight, high conversion efficiency, and high power density for compact charger / adapter applications requiring CV / CC control. GATE Figure 20. PWM Operation for CV / CC Regulation CV / CC PWM Operation Principle Primary-Side Constant Current Operation Figure 19 shows a simplified CV / CC PWM control circuit of the FAN501A. The Constant Voltage (CV) regulation is implemented in the same manner as the conventional isolated power supply, where the output voltage is sensed using a voltage divider and compared with the internal reference of the shunt regulator to generate a compensation signal. The compensation signal is transferred to the primary side through an optocoupler and scaled down by attenuator AV to generate a COMV signal. This COMV signal is applied to the PWM comparator to determine the duty cycle. Figure 21 and Figure 22 show the key waveforms of a flyback converter operating in DCM and CCM, respectively. The output current of each mode is estimated by calculating the average of output diode current over one switching cycle: =< > = = [ ] (1) The area of output diode current in both DCM and CCM operation can be expressed in a same form, as a product of diode current discharge time (tDIS) and diode current at the middle of diode discharge (ID-Mid), such as: The Constant Current (CC) regulation is implemented internally with primary-side control. The output current estimator calculates the output current using the transformer primary-side current and diode current discharge time. By comparing the estimated output current with internal reference signal, a COMI signal is generated to determine the duty cycle. [ ] = - (2) In steady state, ID_Mid can be expressed as: (3) where IDS_Mid is primary-side current at the middle of MOSFET conduction time and NP/NS is primary-tosecondary turn ratio. - = _ These two control signals, COMV and COMI, are compared with an internal sawtooth waveform (VSAW) by two PWM comparators to determine the duty cycle. Figure 20 illustrates the outputs of two comparators ,combined with an OR gate, to determine the MOSFET turn-off instant. Of COMV and COMI, the lower signal determines the duty cycle. As shown in Figure 20, during CV regulation, COMV determines the duty cycle (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 0 www.fairchildsemi.com 9 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Functional Description _ = _ = tDIS(n) 0.85tDIS(n-1) 200mV (4) VS VCS_Mid is obtained by sampling the current-sense voltage at the middle of the MOSFET conduction time. The diode current discharge time is obtained by detecting the diode current zero-crossing instant. Since the diode current cannot be sensed directly in the primary side, Zero-Crossing Detection (ZCD) is accomplished indirectly by monitoring the auxiliary winding voltage in the primary side. When the diode current reaches zero, the transformer winding voltage begins to drop sharply. To detect the corner voltage, the VS is sampled, called VSH, at 85% of diode current discharge time (tDIS) of the previous switching cycle and compared with the instantaneous V S voltage. When instantaneous voltage of the VS pin drops below VSH by more than 200 mV, the ZCD of diode current is obtained, as shown in Figure 23. VSH ZCD Figure 23. Line Voltage Detection and its Utilization The FAN501A indirectly senses line voltage using the current flowing out of the VS pin while the MOSFET is turned on, as illustrated in Figure 25 and Figure 26. During the MOSFET turn-on period, auxiliary winding voltage, VAux, reflects input bulk capacitor voltage, V BLK, by the transformer coupling between primary and auxiliary. During MOSFET conduction time, the line voltage detector clamps the VS pin voltage ~0.5 V and the current, IVS, flowing from the VS pin is expressed as: The output current can be programmable by setting current sensing resistor as: RCS 1 N P VCCR I O N S KCC Operation Waveform for ZCD Function (5) where VCCR is the internal voltage for CC control and KCC is the IC design parameter, 12 for the FAN501A. IVS DCM Waveform N A / N P VBLK 0.5 + RVS1 RVS1 / / RVS 2 (6) IDS-Mid Typically, the second term in Equation (6) can be ignored because it is much smaller than the first term. The current, IVS, is approximately proportional to the line voltage, calculated as: IDS 1/2 tON ID-Mid = NPSIDS-Mid IO = <ID>Ts ID IVS 1/2 tDIS N A / NP VBLK RVS1 (7) The IVS current, reflecting the line voltage information, is used for dual switching frequency operation, CC control correction weighting, and brownout protection; as illustrated in Figure 25. VS tON Dual Switching Frequency The FAN501A changes the switching frequency between 85 kHz and 140 kHz according to the line voltage. It is typical to design the flyback converter to operate in CCM for low line and DCM in high line. Therefore, the peak transformer current decreases as the operation mode changes from CCM to DCM, as shown in Figure 24(a), for single-frequency operation. The transformer is not fully utilized at high line when a single switching frequency is used. The peak transformer current can be maintained almost constant when the flyback converter operates at lower frequency at high line, as illustrated in Figure 24(b). This allows full transformer utilization and improves the efficiency by decreasing the switching losses at high line. tDIS tS Figure 21. Waveforms of DCM Flyback Converter CCM Waveform IDS-Mid IDS 1/2 tON ID-Mid = NPSIDS-Mid IO = <ID>Ts ID 1/2 tDIS VS tON When IVS is larger than IVS-H (750 A), the switching frequency is set at fOSC-L (85 kHz) in CV Mode. When IVS is less than IVS-L (680 A), the switching frequency is set at fOSC-H (140 kHz) in CV Mode. For the universal line range, the frequency change should occur between 132 ~ 180 VAC to avoid the transition within the actual tDIS tS Figure 22. Waveforms of CCM Flyback Converter (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 10 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications The unified output current equation both for DCM and CCM operation is obtained as: RVS1 N A / NP 240 IVS - H (8) GATE With the value of RVS1 determined from Equation (8), the switching frequency drops to 85 kHz as line voltage increases above 170 VAC, while switching frequency increases to 140 kHz, as line voltage drops <155 VAC. VAux IDS IDS - VDS NA VBLK NS VDS 1/140kHz 1/140kHz High line Low line (a) Single frequency operation 0.5V VS IDS IDS tON tS VDS VDS 1/140kHz Figure 26. Waveforms for Line Voltage Detection 1/85kHz High line Low line Maximum Power Limit by Precision CC Control Primary-side current-sensing voltage is used to estimate the output current for CC regulation. However, the actual output current regulation is also affected by the turn-off delay of the MOSFET, as illustrated in Figure 27. While FAN501A samples the CS pin voltage at the half on-time of gate drive signal, the actual turn-off is delayed by the MOSFET gate charge and driving current resulting in peak current detection error as: (b) Dual frequency operation Figure 24. Peak Switch Current, Single- and Dual-Frequency Operation Brownout Protection Line voltage information is also used for brownout protection. When the IVS current out of the VS pin during the MOSFET conduction time is less than 160 A for longer than 30 ms, the brownout protection is triggered. When setting RVS1 as calculated in Equation (8), the brownout level is set at 30 VAC. I DS PK Pri. VBLK As can be seen, the error is proportional to the line voltage. FAN501A has an internal correction function to improve CC regulation, as shown in Figure 28. Line information is obtained through the line voltage detector as shown in Figure 25 and Figure 26 and this information is used for the CC regulation correction. The correction gain can be programmed using external resistor RCOMP on the COMP pin. This correction current, ILVF, flows through internal resistor, RLVF, and external resistor, RCSF, to introduce offset voltage on current sensing voltage. Thus, the primary current detection error affected by line voltage and turn-off delay is corrected for better CC regulation. The R COMP resistor can be calculated as: NP IVS GATE VAux Line Voltage Detector VS IVS Aux. RVS1 NA VS_Offset RVS2 Figure 25. (9) where Lm is the primary side magnetic inductance. 5V Line signal VDL tOFF .DLY Lm RCOMP Line Voltage Detection Circuit RCS t NP RVS1 OFF .DLY KCOMP (10) N A RLVF + RCSF Lm where RLVF is the internal resistor on the IC, which is 2.0 k, and KCOMP is the design factor of the IC, which is 3.745 M. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 11 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications operation range. It is typical to design the voltage divider for the VS pin such that frequency change occurs at 170 VAC (VDC-170 VAC = 240 V); calculated as: tOFF .DLY VO I DS RCS VFB-Burst-H VFB-Burst-L RCS I DS I DS .SH RCS I DS PK RCS VFB I D PK Actual diode current NP NS Estimated diode current I DS .SH GATE NP NS Figure 29. t DIS GATE (# 2) Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth of the EMI test equipment, allowing compliance with EMI limitations. VGS Figure 27. CC Control Correction Concept Slope Compensation Pri. VBLK 5V The sensed voltage across the current-sense resistor is used for current-mode control and pulse-by-pulse current limiting. A synchronized ramp signal with a positive slope is added to the current-sense information at each switching cycle, improving noise immunity during current mode control and avoiding sub-harmonic oscillation during CCM operation. NP COMP RCOMP CC Control Correction ILVF Line Signal RLVF Line Voltage Detector Aux. GATE RCSF CS RVS1 NA Burst-Mode Operation Zero Current Detector RCS IO Estimator Leading-Edge Blanking (LEB) RVS2 VS Figure 28. Each time the power MOSFET is switched on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse by the spike, a 150 ns leading-edge blanking time is incorporated. Conventional RC filtering can therefore be omitted. During this blanking period, the current-limit comparator is disabled and it cannot switch off the gate driver. CC Correction Circuit Pulse-by-Pulse Current Limit Since the peak transformer current is controlled by a feedback loop, the peak transformer current is not properly controlled when the feedback loop is saturated to HIGH, which typically occurs under startup or overload conditions. To limit the current, a pulse-bypulse current limit forces the gate drive signal to turn off when the CS pin voltage reaches the current-limit threshold (VCS-LIM) in normal operation. Noise Immunity Noise from the current sense or the control signal can cause significant pulse-width jitter. Though slope compensation helps alleviate this problem, precautions should be taken to improve the noise immunity. Good placement and layout practices are important. Avoid long PCB traces and component leads and locate bypass capacitor as close to the PWM IC as possible. Burst Mode Operation The power supply enters Burst Mode at no-load or extremely light-load condition. As shown in Figure 29, when VFB drops below VFB-Burst-L, the PWM output shuts off and the output voltage drops at a rate dependent on load current. This causes the feedback voltage to rise. Once VFB exceeds VFB-Burst-H, the internal circuit starts to provide a switching pulse. The feedback voltage then falls and the process repeats. In this manner, Burst Mode alternately enables and disables switching of the MOSFET to reduce the switching losses in Standby Mode. In Burst Mode, the operating current is reduced from 3.5 mA to 250 A to minimize power consumption. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 High Voltage (HV) Startup Figure 30 shows the high-voltage (HV) startup circuit for FAN501A applications. The JFET is used to internally implement the high-voltage current source (see Figure 31 for characteristics). Technically, the HV pin can be directly connected to voltage (VBLK) on an input bulk capacitor. To improve reliability and surge immunity, however, it is typical to use a ~100 k resistor between the HV pin and bulk capacitor voltage. The actual HV current with a given bulk capacitor voltage and startup resistor is determined by the intersection of V-I characteristics line and load line, as shown in Figure 31. www.fairchildsemi.com 12 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications The turn-off delay should be obtained by measuring the time between the falling edge and actual turn-off instant of MOSFET, as illustrated in Figure 27. VBLK The supply current drawn from the HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 17.5 V, normal operation resumes. In this manner, Auto-Restart Mode alternately enables and disables MOSFET switching until the abnormal condition is eliminated, as shown in Figure 32. VDS Power On Primary-Side Fault Occurs VDD VDD-OVP NP Fault Removed RHV CBLK VDD-ON IHV VDD-OFF VDD-HV-ON HV Operating Current Aux. DVDD VDD IDD-OP IDD-Brust IDD-ST NA CVDD 6V/17V Figure 30. Figure 32. Auto-Restart Mode Operation When a Latch Mode protection is triggered, PWM switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5.8 V, the internal startup circuit is enabled without resetting the protection and the supply current drawn from HV pin charges the hold-up capacitor. Since the protection is not reset, the IC does not resume PWM switching even when VDD reaches the turn-on voltage of 17.5 V, disabling HV startup circuit. Then V DD drops again down to 5.8 V. In this manner, Latch Mode protection alternately charges and discharges V DD until there is no more energy in DC link capacitor. The protection is reset when VDD drops to 2.5 V, which is allowed only after power supply is unplugged from the AC line, as shown in Figure 33. HV Startup Circuit IHV 5.0mA VBLK RHV 2.0mA 1.2mA AC Disconnected 100V 200V VBLK Figure 31. 300V 400V VDS 500V Power On Power On Again VHV V-I Characteristic of HV Pin VDD Protections The protection functions include VDD over-voltage protection (VDD OVP), brownout protection, VS overvoltage protection (VS OVP), internal over-temperature protection (OTP), and externally triggered shutdown (SD) protection. The VDD OVP and brownout protection are implemented as Auto-Restart Mode. VS OVP, OTP, and SD protections are implemented as Latch Mode. VDD-ON Protection Reset VDD-OFF VDD-Burst VDD-LH Operating Current IDD-OP When an Auto-Restart Mode protection is triggered, switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5.8 V; the protection is reset, and next step to reduced operation current until startup circuit is enabled. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 Protection Triggered IDD-Burst IDD-ST Figure 33. Latch Mode Operation www.fairchildsemi.com 13 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications During startup, the internal startup circuit is enabled and the bulk capacitor voltage supplies the current, IHV, to charge the hold-up capacitor, CVDD, through RHV. When VDD reaches VDD-ON, the internal HV startup circuit is disabled and the IC starts PWM switching. Once the HV startup circuit is disabled, the energy stored in C VDD should supply the IC operating current until the transformer auxiliary winding voltage reaches the nominal value. Therefore, CVDD should be designed to prevent VDD from dropping to VDD-OFF before the auxiliary winding builds up enough voltage to supply V DD. RVS1 NA PWM VSOVP Dedounce time Latch Protection Counter Figure 34. VS OVP Protection Circuit Externally Triggered Shutdown By pulling the SD pin voltage below threshold voltage, VSD-TH (1.0 V); shutdown can be externally triggered and the FAN501A enters Latch Mode protection. It can be also used for external OTP protection by connecting an NTC thermistor between the shutdown (SD) programming pin and ground. An internal constant current source, ISD (100 A), introduces voltage drop across the thermistor. Resistance of the NTC thermistor becomes smaller as the ambient temperature increases, which reduces the voltage drops across the thermistor. When the voltage of the SD pin is less than threshold voltage VSD-TH (1.0 V), OTP protection is triggered. Fold-Back Point and Over-Voltage Protection (VS OVP) Generally, the fold-back point in CC regulation as output drops is determined by the VDD-OFF level. Thus, the foldback level mainly depends on the characteristics of the VDD diode and transformer. For VS pin voltage divider design, RVS1 is obtained from Equation (8), and RVS2 is determined by the VSOVP function as: 5V -1 100A (11) where VO-OVP is the output over-voltage protection threshold level. NTC Thermistor VS over-voltage protection prevents damage caused by output over-voltage condition. Figure 34 shows the internal circuit of VS OVP. When abnormal system conditions occur that cause VS sampling voltage to exceed VVS-OVP (3.2 V) for more than debounce switching cycles (NVS-OVP), PWM pulses are disabled and the FAN501A enters Latch Mode protection. VS over-voltage conditions are usually caused by an open circuit in the secondary-side feedback network or a fault condition in the VS pin voltage divider resistors. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 Q RVS2 Over-Temperature Protection (OTP) If the junction temperature exceeds 140C (TOTP), the internal temperature-sensing circuit shuts down PWM output and enters Latch Mode protection. - -1 - D S/H Brownout Protection Brownout protection is implemented through line voltage detection circuit using the auxiliary winding, as shown in Figure 25 and Figure 26. When the current flowing out of the VS pin during the MOSFET conduction time is smaller than 160 A for longer than 30 ms, the brownout protection is triggered. 2 = 1 3.20V Figure 35. 1.0V Latch Protection Thermal Shutdown Using SD Pin www.fairchildsemi.com 14 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Aux. VDD Over-Voltage-Protection VDD over-voltage protection prevents damage from overvoltage exceeding the IC voltage rating. When VDD exceeds 28 V due to an abnormal condition, protection is triggered. This protection is typically caused by an open circuit in the secondary-side feedback network. 4.60 A 4.0 0.10 C 1.80 0.80 B 10 PIN#1 QUADRANT 9 0.40 (10X) 0.30 8 1 0.80 3.60 3.0 1.58 2 3 0.36 0.10 C 1.60 7 0.65 (10X) 4 5 6 0.80 TOP VIEW 0.45 RECOMMENDED LAND PATTERN 0.10 C 0.80 MAX (0.20) 0.08 C 0.05 0.00 C SEATING PLANE FRONT VIEW 1.85 1.75 0.45 0.30 0.80 4 5 6 7 3 0.80 1.63 1.53 2 8 1 0.36 10 SIDE VIEW PIN #1 IDENT CHAMFER 0.25 mm 9 0.35(10X) SIDE VIEW 0.30(10X) 0.10 0.05 A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO-220. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY E. DRAWING FILE NAME : MKT-MLP10Hrev1 C A B C BOTTOM VIEW Figure 36. 10-Lead, MLP, QUAD, JEDEC MO-220 4 mm X 3 mm, 0.8 mm Pitch, Single DAP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/ML/MLP10H.pdf. For current packing container specifications, visit Fairchild Semiconductor's online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-MLP10H.pdf. (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 15 FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications Physical Dimensions FAN501A -- Offline DCM / CCM Flyback PWM Controller for Charger Applications (c) 2014 Fairchild Semiconductor Corporation FAN501A * Rev. 1.0.0 www.fairchildsemi.com 16 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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