SN74LVC2G32-Q1 www.ti.com SCES842 - AUGUST 2012 DUAL TWO-INPUT POSITIVE-OR GATE Check for Samples: SN74LVC2G32-Q1 FEATURES * 1 * * 2 * * * * Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device HBM ESD Classification Level H2 - Device CDM ESD Classification Level C3B Inputs Accept Voltages to 5.5 V Max Propagation (Delay) Time of 3.8 ns at 3.3 V Low Power Consumption, 10-A Max Supply Current 24-mA Output Drive at 3.3 V * * Typical Voltage Output Low Peak (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Typical Voltage Output High Valley (VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25C Ioff State Current Supports Partial-Power-Down Mode Operation APPLICATIONS * * Automotive Logic and Gates DCU PACKAGE (TOP VIEW) 1A 1B 2Y GND 1 8 2 7 3 6 4 5 VCC 1Y 2B 2A DESCRIPTION This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation. The SN74LVC2G32-Q1 performs the Boolean function Y + A ) B or Y + A * B in positive logic. NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) TA -40C to 125C (1) (2) PACKAGE (2) VSSOP - DCU Reel of 3000 ORDERABLE PART NUMBER TOP-SIDE MARKING SN74LVC2G32QDCURQ1 SUCQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012, Texas Instruments Incorporated SN74LVC2G32-Q1 SCES842 - AUGUST 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTION TABLE (EACH GATE) INPUTS B OUTPUT Y H X H X H H L L L A LOGIC DIAGRAM (POSITIVE LOGIC) 1A 1B 2A 2B 1 7 2 5 3 6 1Y 2Y ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) -0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) -0.5 VCC + 0.5 V IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA (3) Continuous current through VCC or GND Tstg Storage temperature range ESD Rating (1) (2) (3) -65 Human body model (HBM) AEC-Q100 classification level H2 Charged device model (CDM) AEC-Q100 classification level C3B 150 C 2 kV 750 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. THERMAL INFORMATION THERMAL METRIC (1) SN74LVC2G32-Q1 DCU (8 PINS) JA Junction-to-ambient thermal resistance JCtop Junction-to-case (top) thermal resistance JB Junction-to-board thermal resistance 83.2 JT Junction-to-top characterization parameter 7.1 JB Junction-to-board characterization parameter 82.7 JCbot Junction-to-case (bottom) thermal resistance N/A (1) 2 UNIT 204.4 77 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Links: SN74LVC2G32-Q1 SN74LVC2G32-Q1 www.ti.com SCES842 - AUGUST 2012 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 UNIT V 0.65 x VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V V 2 VCC = 4.5 V to 5.5 V 0.7 x VCC VCC = 1.65 V to 1.95 V 0.35 x VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 4.5 V to 5.5 V 0.3 x VCC VCC = 1.65 V -4 VCC = 2.3 V IOH High-level output current -8 -16 VCC = 3 V Low-level output current t/v Input transition rise or fall rate -32 VCC = 1.65 V 4 VCC = 2.3 V 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V 0.15 V, 2.5 V 0.2 V 20 VCC = 3.3 V 0.3 V 10 (1) Operating free-air temperature mA 24 VCC = 5 V 0.5 V TA mA -24 VCC = 4.5 V IOL V ns/V 5 -40 125 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Links: SN74LVC2G32-Q1 3 SN74LVC2G32-Q1 SCES842 - AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 A VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 4.5 V IOL = 100 A 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 32 mA A or B inputs 0.4 ICC VI = 5.5 V or GND, IO = 0 ICC One input at VCC - 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 0.6 0 to 5.5 V 5 A 0 10 A 1.65 V to 5.5 V 10 A 3 V to 5.5 V 500 A VI = 5.5 V or GND VI or VO = 5.5 V V 0.6 4.5 V Ioff (1) 3.8 3V IOL = 24 mA II 2.3 IOH = -32 mA IOL = 16 mA UNIT V 2.4 3V IOH = -24 mA MAX VCC - 0.1 IOH = -4 mA IOH = -16 mA VOL MIN TYP (1) VCC 3.3 V 5 pF All typical values are at VCC = 3.3 V, TA = 25C. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.4 11 1 7.5 1 5.8 1 4.7 UNIT ns OPERATING CHARACTERISTICS TA = 25C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 17 17 17 19 Submit Documentation Feedback UNIT pF Copyright (c) 2012, Texas Instruments Incorporated Product Folder Links: SN74LVC2G32-Q1 SN74LVC2G32-Q1 www.ti.com SCES842 - AUGUST 2012 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL 0V VLOAD/2 VM tPZH VM VM VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH - VD VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2012, Texas Instruments Incorporated Product Folder Links: SN74LVC2G32-Q1 5 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) SN74LVC2G32DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCUR ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCUT ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32DCUTG4 ACTIVE US8 DCU 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC2G32YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS & no Sb/Br) SNAGCU (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Aug-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LVC2G32 : * Enhanced Product: SN74LVC2G32-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC2G32DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 SN74LVC2G32YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC2G32DCUR US8 DCU 8 3000 202.0 201.0 28.0 SN74LVC2G32YZPR DSBGA YZP 8 3000 220.0 220.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS049B - MAY 1999 - REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM CCCCC CCCCC CCCCC CCCCC 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0 - 8 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. 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