1 of 26 052302
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, click here: http://www.maxim-ic.com/errata.
FEATURES
§ 8051-compatible microprocessor adapts to its
task
– Accesses up to 128kB of nonvolatile
SRAM
– In-system programming through on-chip
serial port
– Can modify its own program or data
memory
– Accesses memory on a separate byte-wide
bus
– Performs CRC-16 check of NV RAM
memory
– Decodes memory and peripheral chip
enables
§ High-reliability operation
– Maintains all nonvolatile resources for
over 10 years
– Power-fail reset
– Early warning power-fail interrupt
– Watchdog timer
– Lithium backs user SRAM for
program/data storage
– Precision bandgap reference for power
monitor
§ Fully 8051-compatible
– 128kB scratchpad RAM
– Two timer/counters
– On-chip serial port
– 32 parallel I/O port pins
§ Software security available with DS5002FP
secure microprocessor
PIN ASSIGNMENT (Top View)
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
BA15
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
DS5001FP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
PROG
BA2
RST
BA1
P3.0/RXD
BA0
P3.1/TXD
P3.2/INT0
P3.3/INT1
BA11
P0.5/AD5
PE1
P0.6/AD6
BA10
P0.7/AD7
CE1
NC
CE1N
BD7
A
LE
BD6
PSEN
BD5
P2.7/A15
BD4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DS5001FP
128k Soft Microprocessor Chip
www.maxim-ic.com
80-Pin MQFP
44-Pin MQFP
DS5001FP
2 of 26
DESCRIPTION
The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM
technology and designed for systems that need large quantities of nonvolatile memory. It provides full
compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM
instead of ROM, the user can program and then reprogram the microprocessor while in-system. The
application software can even change its own operation, which allows frequent software upgrades,
adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for
data logging applications. It also connects easily to a Dallas real-time clock.
The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed
byte-wide address and data bus for memory access. This bus performs all memory access and provides
decoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The
DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room
temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh
environments. These features include the ability to save the operating state, power-fail reset, power-fail
interrupt, and watchdog timer.
A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader
supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user.
Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning,
the DS5001FP can divide a common RAM into user-selectable program and data segments. This partition
can be selected at program loading time, but can then be modified later at any time. The microprocessor
decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions
designated code or ROM are automatically write-protected by the microprocessor. Combining program
and data storage in one device saves board space and cost.
The DS5001FP offers several bank switches for access to even more memory. In addition to the primary
data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip
enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can
also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space.
Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAM
program space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB
of data memory.
The DS2251T is available (Refer to the data sheet at www.maxim-ic.com/microcontrollers.) for users
who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. For
more details, refer to the Secure Microcontroller User’s Guide. For users desiring software security, the
DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin
version of the device is functionally identical to the 80-pin version but sports a reduced pin count and
footprint.
Refer to the Secure Microcontroller User’s Guide for operating details. This data sheet provides ordering
information, pinout, and electrical specifications.
ORDERING INFORMATION
PART PIN-PACKAGE MAX. CLOCK SPEED (MHz) TEMP. RANGE (°C)
DS5001FP-16 80-MQFP 16 0 to +70
DS5001FP-16N 80-MQFP 16 -40 to +85
DS5001FP-12-44 44-MQFP 12 0 to +70
DS5001FP
3 of 26
Figure 1. BLOCK DIAGRAM
DS5001FP
4 of 26
PIN DESCRIPTION
80-PIN
MQFP
44-PIN
MQFP SIGNAL DESCRIPTION
11, 9, 7,
5, 1, 79,
77, 75
31
(P0.5) P0.0–P0.7
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires
external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
15, 17,
19, 21,
25, 27,
29, 31
44
(P1.3) P1.0–P1.7 General-Purpose I/O Port 1
49, 50,
51, 56,
58, 60,
64, 66
N/A P2.0–P2.7 General-Purpose I/O Port 2. Also serves as the MSB of the address in expanded memory
accesses, and as pins of the RPC mode when used.
36 8 P3.0 RXD General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on board
UART. This pin should not be connected directly to a PC COM port.
38 10 P3.1 TXD General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on board
UART. This pin should not be connected directly to a PC COM port.
39 N/A P3.2 INT0 General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0.
40 11 P3.3 INT1 General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1.
41 N/A P3.4 T0 General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input.
44 12 P3.5 T1 General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input.
45 13 P3.6 WR General-Purpose I/O Port Pin. Also serves as the write strobe for expanded bus
operation.
46 N/A P3.7 RD General-Purpose I/O Port Pin. Also serves as the read strobe for expanded bus operation.
68 25 PSEN
Program Store Enable. This active-low signal is used to enable an external program
memory when using the expanded bus. It is normally an output and should be unconnected
if not used. PSEN also is used to invoke the bootstrap loader. At this time, PSEN is pulled
down externally. This should only be done once the DS5001FP is already in a reset state.
The device that pulls down should be open drain since it must not interfere with PSEN
under normal operation.
34 6 RST
Active-High Reset Input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally so this pin can be left unconnected if not used. An RC power-on
reset circuit is not needed and is not recommended.
70 27 ALE
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus
on port 0. This pin is normally connected to the clock input on a ’373 type transparent
latch.
47, 48 14, 15 XTAL2,
XTAL1
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
52 16 GND Logic Ground
13 39 VCC VCC - +5V
12 38 VCCO
VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on the
level of VCC. When power is above the lithium input, power will be drawn from VCC. The
lithium cell remains isolated from a load. When VCC is below VLI, the VCCO switches to the
VLI source. VCCO should be connected to the VCC pin of an SRAM.
54 17 VLI Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than
VLImax as shown in the electrical specifications. Nominal value is +3V.
53, 16,
8, 18,
80, 76,
4, 6, 20,
24, 26,
28, 30,
41, 36,
42, 32,
30, 34,
35, 43,
1, 2, 3,
4, 5, 7,
BA14–0
Byte-Wide Address-Bus Bits 14–0. This bus is combined with the nonmultiplexed data
bus (BD7–0) to access NV SRAM. Decoding is performed using CE1 through CE4 .
Therefore, BA15 is not actually needed. Read/write access is controlled by R/ W. BA14–0
connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are
unconnected. If a 128k SRAM is used, the micro converts CE2 and CE3 to serve as A16
DS5001FP
5 of 26
33, 35,
37
9 and A15 respectively.
71, 69,
67, 65,
61, 59,
57, 55
28, 26,
24, 23,
21, 20,
19, 18
BD7–0
Byte-Wide Data-Bus Bits 7–0. This 8-bit, bidirectional bus is combined with the
nonmultiplexed address bus (BA14–0) to access NV SRAM. Decoding is performed on
CE1 and CE2 . Read/write access is controlled by R/ W. BD7–0 connect directly to an
SRAM, and optionally to a real-time clock or other peripheral.
10 37 R/ W
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It
is controlled by the memory map and partition. The blocks selected as program (ROM) are
write-protected.
74 29 CE1
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-
wide bus. It connects to the chip enable input of one SRAM. CE1 is lithium-backed. It
remains in a logic high inactive state when VCC falls below VLI.
72 N/A CE1N Non-battery-backed version of chip enable 1. This can be used with a 32kB EPROM. It
should not be used with a battery-backed chip.
233
CE2
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE2
into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when
VCC falls below VLI.
63 22 CE3
Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It
connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE3
into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when
VCC falls below VLI.
62 N/A CE4
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused.
CE4 is lithium-backed and remains at a logic high when VCC < VLI.
78 N/A PE1
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when
the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock
such as the DS1283. PE1 is lithium-backed and remains at a logic high when VCC falls
below VLI. Connect PE1 to battery-backed functions only.
3N/APE2
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when
the PES bit is set to a logic 1. PE2 is lithium-backed and remains at a logic high when VCC
falls below VLI. Connect PE2 to battery-backed functions only.
22 N/A PE3
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when
the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
23 N/A PE4
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected to any type
of peripheral function. If connected to a battery-backed chip, it needs additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
32 N/A PROG
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that
only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
42 N/A VRST
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC)
has fallen below the VCCmin level and the micro is in a reset state. When this occurs, the
DS5001FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled
low externally. This allows multiple parts to synchronize their power-down resets.
43 N/A PF
This output goes to a logic 0 to indicate that VCC < VLI and the micro has switched to
lithium backup. Because the micro is lithium-backed, this signal is guaranteed even when
VCC = 0V. The normal application of this signal is to control lithium powered current to
isolate battery-backed functions from non-battery-backed functions.
14 40 MSEL
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
DS5001FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5001FP expects to
use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
73 NC No Connect.
DS5001FP
6 of 26
INSTRUCTION SET
The DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User’s Guide. Also note that the DS5001FP
is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32k and 128k
of SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module.
MEMORY ORGANIZATION
Figure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of
data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The
user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program
range and data range. Any area not mapped into the NV RAM is reached by the expanded bus on ports 0
and 2. An alternate configuration allows dynamic partitioning of a 64k space as shown in Figure 3.
Selecting PES=1 provides another 64k of potential data storage or memory-mapped peripheral space as
shown in Figure 4. These selections are made using special function registers. The memory map and its
controls are covered in detail in the Secure Microcontroller User’s Guide.
Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE (PM = 1)
DS5001FP
7 of 26
Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0)
Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode).
DS5001FP
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Figure 4. MEMORY MAP WITH PES = 1
DS5001FP
9 of 26
Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this
configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system
with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The
bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
Figure 5. CONNECTION TO 128k x 8 SRAM
DS5001FP
10 of 26
Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAM
POWER MANAGEMENT
The DS5001FP monitors VCC to provide power-fail reset, early warning power-fail interrupt, and switch
over to lithium backup. It uses an internal bandgap reference in determining the switch points. These are
called VPFW, VCCMIN, and VLI, respectively. When VCC drops below VPFW, the DS5001FP performs an
interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues
regardless. When power falls further to VCCMIN, the DS5001FP invokes a reset state. No further code
execution is performed unless power rises back above VCCMIN. All decoded chip enables and the R/ W
signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further
to below VLI, internal circuitry switches to the lithium cell for power. The majority of internal circuits are
disabled and the remaining nonvolatile states are retained. Any devices connected VCCO are powered by
the lithium cell at this time. VCCO is at the lithium battery voltage minus approximately 0.45V. This drop
varies depending on the load. Low power SRAMs should be used for this reason. When using the
DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the
desired backup lifetime. Note that the lithium cell is only loaded when VCC < VLI. The User’s Guide has
more information on this topic. The trip points VCCMIN and VPFW are listed in Electrical Specifications.
DS5001FP
11 of 26
ABSOLUTE MAXIMUM RATINGS*
Voltage Range on Any Pin Relative to Ground -0.3V to (VCC + 0.5V)
Voltage Range on VCC Related to Ground -0.3 °C to 6.0°C
Operating Temperature Range -40°C to +85°C
Storage Temperature Range1-55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020A
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
1Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this
state, the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS (TA = 0°C to +70°C; VCC = 5V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Low Voltage VIL -0.3 +0.8 V 1
Input High Voltage VIH1 2.0 VCC + 0.3 V 1
Input High Voltage
(RST, XTAL1, PROG )VIH2 3.5 VCC + 0.3 V 1
Output Low Voltage
at IOL = 1.6mA (Ports 1, 2, 3, PF )VOL1 0.15 0.45 V 1, 11
Output Low Voltage
at IOL = 3.2mA (Ports 0, ALE, PSEN ,
BA15–0, BD7–0, R/ W, CE1N ,
CE 1–4, PE 1–4, VRST)
VOL2 0.15 0.45 V 1
Output High Voltage
at IOH = -80µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1
Output High Voltage
at IOH = -400µA (Ports 0, ALE, PSEN ,
PF , BA15–0, BD7–0, R/ W, CE1N ,
CE 1–4, PE 1–4, VRST)
VOH2 2.4 4.8 V 1
Input Low Current
VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(0°C to +70°C)
ITL -500 µA
Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3)
(-40°C to +85°C)
ITL -600 µA 10
DS5001FP
12 of 26
DC CHARACTERISTICS (continued) (TA = 0°C to +70°C; VCC = 5V ±10%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current
0.45 < VIN < VCC (Port 0, MSEL) IIL +10 µA
RST Pulldown Resistor
(0°C to +70°C) RRE 40 150 kW
RST Pulldown Resistor
(-40°C to +85°C) RRE 30 180 kW10
VRST Pullup Resistor RVR 4.7 kW
PROG Pullup Resistor RPR 40 kW
Power-Fail Warning Voltage
(0°C to +70°C) VPFW 4.25 4.37 4.50 V 1
Power-Fail Warning Voltage
(-40°C to +85°C) VPFW 4.1 4.37 4.6 V 1, 10
Minimum Operating Voltage
(0°C to +70°C) VCCMIN 4.00 4.12 4.25 V 1
Minimum Operating Voltage
(-40°C to +85°C) VCCMIN 3.85 4.09 4.25 V 1, 10
Lithium Supply Voltage VLI 2.5 4.0 V 1
Operating Current at 16MHz ICC 36 mA 2
Idle Mode Current at 12MHz
(0°C to +70°C) IIDLE 7.0 mA 3
Idle Mode Current at 12MHz
(-40°C to +85°C) IIDLE 8.0 mA 3, 10
Stop Mode Current ISTOP 80 µA 4
Pin Capacitance CIN 10 pF 5
Output Supply Voltage (VCCO)VCCO1
VCC
-0.45 V 1, 2
Output Supply Battery-Backed Mode
(VCCO, CE 1-4, PE 1-2)
(0°C to +70°C)
VCCO2
VLI
-0.65 V 1, 8
Output Supply Battery-Backed Mode
(VCCO, CE 1-4, PE 1-2)
(-40°C to +85°C)
VCCO2
VLI
-0.9 V 1, 8, 10
Output Supply Current
at VCCO = VCC - 0.45V ICCO1 75 mA 6
Lithium-Backed Quiescent Current
(0°C to +70°C) ILI 575 nA 7
Lithium-Backed Quiescent Current
(-40°C to +85°C) ILI 75 500 nA 7
Reset Trip Point in Stop Mode
With BAT = 3.0V (0°C to +70°C)
With BAT = 3.0V (-40°C to +85°C)
With BAT = 3.0V (0°C to +70°C)
4.0
3.85
4.4
4.25
4.25
4.65
1
1, 10
1
DS5001FP
13 of 26
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
1 Oscillator Frequency 1/ tCLK 1.0 16 MHz
2 ALE Pulse Width tALPW 2tCLK - 40 ns
3 Address Valid to ALE Low tAVALL tCLK - 40 ns
4 Address Hold After ALE Low tAVAAV tCLK - 35 ns
5
ALE Low to Valid Instruction In
at 12MHz
at 16MHz
tALLVI 4tCLK - 150
4tCLK - 90
ns
ns
6ALE Low to PSEN Low tALLPSL tCLK - 25 ns
7PSEN Pulse Width tPSPW 3tCLK - 35 ns
8
PSEN Low to Valid Instruction In
at 12MHz
at 16MHz
tPSLVI 3tCLK - 150
3tCLK - 90
ns
ns
9Input Instruction Hold After PSEN Going
High tPSIV 0ns
10 Input Instruction Float After PSEN Going
High tPSIX tCLK - 20 ns
11 Address Hold After PSEN Going High tPSAV tCLK - 8 ns
12
Address Valid to Valid Instruction In
at 12MHz
at 16MHz
tAVVI 5tCLK - 150
5tCLK - 90
ns
ns
13 PSEN Low to Address Float tPSLAZ 0ns
14 RD Pulse Width tRDPW 6tCLK - 100 ns
15 WR Pulse Width tWRPW 6tCLK - 100 ns
16 RD Low to Valid Data In at 12MHz
at 16MHz tRDLDV 5tCLK - 165
5tCLK - 105
ns
ns
17 Data Hold After RD High tRDHDV 0ns
18 Data Float After RD High tRDHDZ 2tCLK - 70 ns
19 ALE Low to Valid Data In at 12MHz
at 16MHz tALLVD
8tCLK - 150
8tCLK - 90 ns
20 Valid Address to Valid Data In at 12MHz
at 16MHz tAVDV
9tCLK - 165
9tCLK - 105 ns
21 ALE Low to RD or WR Low tALLRDL 3tCLK - 50 3tCLK + 50 ns
22 Address Valid to RD or WR Low tAVRDL 4tCLK - 130 ns
23 Data Valid to WR Going Low tDVWRL tCLK - 60 ns
24 Data Valid to WR High at 12MHz
at 16MHz tDVWRH
7tCLK - 150
7tCLK - 90 ns
25 Data Valid After WR High tWRHDV tCLK - 50 ns
26 RD Low to Address Float tRDLAZ 0ns
27 RD or WR High to ALE High tRDHALH tCLK - 40 tCLK + 50 ns
DS5001FP
14 of 26
EXPANDED PROGRAM-MEMORY READ CYCLE
EXPANDED DATA-MEMORY READ CYCLE
DS5001FP
15 of 26
EXPANDED DATA-MEMORY WRITE CYCLE
DS5001FP
16 of 26
AC CHARACTERISTICS (continued)
EXTERNAL CLOCK DRIVE (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
28
External Clock-High Time
at 12MHz
at 16MHz
tCLKHPW 20
15
ns
29
External Clock-Low Time
at 12MHz
at 16MHz
tCLKLPW 20
15
ns
30
External Clock-Rise Time
at 12MHz
at 16MHz
tCLKR 20
15
ns
31
External Clock-Fall Time
at 12MHz
at 16MHz
tCLKF 20
15
ns
EXTERNAL CLOCK TIMING
DS5001FP
17 of 26
AC CHARACTERISTICS (continued)
POWER CYCLE TIME (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
32 Slew Rate from VCCMIN to VLI tF130 µs
33 Crystal Startup Time tCSU (Note 9)
34 Power-On Reset Delay tPOR 21,504 tCLK
POWER CYCLE TIMING
DS5001FP
18 of 26
AC CHARACTERISTICS (continued)
SERIAL PORT TIMING, MODE 0 (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
35 Serial-Port Clock-Cycle Time tSPCLK 12tCLK µs
36 Output-Data Setup to Rising-Clock Edge tDOCH 10tCLK - 133 ns
37 Output-Data Hold After Rising-Clock Edge tCHDO 2tCLK - 117 ns
38 Clock-Rising Edge to Input-Data Valid tCHDV 10tCLK - 133 ns
39 Input-Data Hold After Rising-Clock Edge tCHDIV 0ns
SERIAL PORT TIMING, MODE 0
DS5001FP
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AC CHARACTERISTICS (continued)
BYTE-WIDE ADDRESS/DATA BUS TIMING
(TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
40
Delay to Byte-Wide Address Valid from
CE1 , CE2 , or CE1N Low During Op Code
Fetch
tCE1LPA 30 ns
41 Pulse Width of CE 1-4, PE 1-4 or CE1N tCEPW 4tCLK - 35 ns
42 Byte-Wide Address Hold After CE1 , CE2 , or
CE1N High During Op Code Fetch tCE1HPA 2tCLK - 20 ns
43 Byte-Wide Data Setup to CE1 , CE2 , or CE1N
High During Op Code Fetch tOVCE1H 1tCLK + 40 ns
44 Byte-Wide Data Hold After CE1 , CE2 or
CE1N High During Op Code Fetch tCE1HOV 0ns
45 Byte-Wide Address Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX tCEHDA 4tCLK - 30 ns
46 Delay from Byte-Wide Address Valid
CE 1-4, PE 1-4, or CE1N Low During MOVX tCELDA 4tCLK - 35 ns
47 Byte-Wide Data Setup to CE 1-4, PE 1-4, or
CE1N High During MOVX (read) tDACEH 1tCLK + 40 ns
48 Byte-Wide Data Hold After CE 1-4,
PE 1-4, or CE1N High During MOVX (read) tCEHDV 0ns
49 Byte-Wide Address Valid to R/ W Active
During MOVX (write) tAVRWL 3tCLK - 35 ns
50 Delay from R/ W Low to Valid Data Out
During MOVX (write) tRWLDV 20 ns
51 Valid Data-Out Hold Time from CE 1-4,
PE 1-4, or CE1N High tCEHDV 1tCLK - 15 ns
52 Valid Data-Out Hold Time from R/ W High tRWHDV 0ns
53 Write Pulse Width (R/ W Low Time) tRWLPW 6tCLK - 20 ns
DS5001FP
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BYTE-WIDE BUS TIMING
RPC AC CHARACTERISTICS, DBB READ (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
54 CS , A0 Setup to RD tAR 0ns
55 CS , A0 Hold After RD tRA 0ns
56 RD Pulse Width tRR 160 ns
57 CS , A0 to Data-Out Delay tAD 130 ns
58 RD to Data-Out Delay tRD 0 130 ns
59 RD to Data-Float Delay tRDZ 85 ns
DS5001FP
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RPC AC CHARACTERISTICS, DBB WRITE (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
60 CS , A0 Setup to WR tAW 0ns
61A CS , Hold After WR tWA 0ns
61B A0, Hold After WR tWA 20 ns
62 WR Pulse Width tWW 160 ns
63 Data Setup to WR tDW 130 ns
64 Data Hold After WR tWD 20 ns
AC CHARACTERISTICS, DMA (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
65 DACK to WR or RD tACC 0ns
66 RD or WR to DACK tCAC 0ns
67 DACK to Data Valid tACD 0 130 ns
68 RD or WR to DRQ Cleared tCRQ 110 ns
AC CHARACTERISTICS, PROG (TA = 0°C to +70°C; VCC = 5V ±10%)
# PARAMETER SYMBOL MIN MAX UNITS
69 PROG Low to Active tPRA 48 CLKS
70 PROG High to Inactive tPRI 48 CLKS
DS5001FP
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RPC TIMING MODE
DS5001FP
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NOTES:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1) All voltages are referenced to ground.
2) Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR,
tCLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC, MSEL = VSS.
3) Idle mode, IIDLE, is measured with all output pins disconnected; XTAL1 driven with tCLKR,
tCLKF = 10ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = MSEL = VSS.
4) Stop mode, ISTOP, is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not
connected; RST = MSEL = XTAL1 = VSS.
5) Pin capacitance is measured with a test frequency: 1MHz, TA = +25°C.
6) ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation.
7) ILI is the current drawn from VLI input when VCC = 0V and VCCO is disconnected.
8) VCCO2 is measured with VCC < VLI, and a maximum load of 10µA on VCCO.
9) Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the
time that power is first applied to the circuit until the first clock pulse is produced by the on-chip
oscillator. The user should check with the crystal vendor for a worst-case specification on this time.
10) This parameter applies to industrial temperature operation.
11) PF pin operation is specified with VBAT ³ 3.0V.
DS5001FP
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80-PIN MQFP
MM
DIM MIN MAX
A-3.40
A1 0.25 -
A2 2.55 2.87
B0.30 0.50
C0.13 0.23
D23.70 24.10
D1 19.90 20.10
E17.70 18.10
E1 13.90 14.10
e0.80 BSC
L0.65 0.95
56-G4005-001
DS5001FP
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44-PIN MQFP
DS5001FP
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REVISION HISTORY
The following represent the key differences between 112795 and 073096 version of the DS5001FP data
sheet. Please review this summary carefully.
1) Change VCC02 specification from VLI - 0.5 to VLI - 0.65 (PCN F62501).
2) Update mechanical specifications.
The following represent the key differences between 073096 and 111996 version of the DS5001FP data
sheet. Please review this summary carefully.
1) Change VCC01 from VCC - 0.3 to VCC - 0.35.
The following represent the key differences between 111996 and 061297 version of the DS5001FP data
sheet. Please review this summary carefully.
1) PF signal moved from VOL2 test specification to VOL1. PCN No. (D72502)
2) AC characteristics for battery-backed SDI pulse specification added.
The following represent the key differences between 061297 and 051099 version of the DS5001FP data
sheet. Please review this summary carefully.
1) Reduced absolute maximum voltage to VCC + 0.5V.
2) Added note clarifying storage temperature specification is for non-battery-backed state.
3) Changed RRE min (industrial temp range) from 40kW to 30kW.
4) Changed VPFW max (industrial temp range) from 4.5V to 4.6V.
5) Added industrial specification for ILI.
6) Reduced tCE1HOV and tCEHDV from 10ns to 0ns.
The following represent the key differences between 051099 and 052499 version of the DS5001FP data
sheet. Please review this summary carefully.
1) Minor markups and ready for approval.
