CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1996 1
SEMICONDUCTOR
HI1396, CXA1396
8-Bit, 125 MSPS Flash A/D Converter
Description
The HI1396, CXA1396 is an 8-bit ultra high speed flash ana-
log-to-digital converter IC capable of digitizing analog signals
at the maximum rate of 125 MSPS. The digital I/O levels of
the converter are compatible with ECL 100K/10KH/10K.
The HI1396, CXA1396 is available in the Commercial and
Industrial temperature ranges and is supplied in a 68 lead
ceramic LCC, 42 lead ceramic DIP and plastic DIP packages.
Ordering Information
PART
NUMBER TEMPERATURE
RANGE PACKAGE
HI1396JCJ,
CXA1396D -20oC to +75oC 42 Lead Ceramic DIP
HI1396AIL,
CXA1396K -20oC to +100oC 68 Lead Ceramic LCC
HI1396JCP,
CXA1396P -20oC to +75oC 42 Lead Plastic DIP
February 1996
Pinouts
HI1396, CXA1396 (CDIP, PDIP)
TOP VIEW HI1396, CXA1396 (LCC)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
AVEE
NC
LINV
DVEE
DGND1
DGND2
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
DGND2
DGND2
DVEE
MINV
NC
CLK
30
42
41
40
39
38
37
36
35
34
33
32
31
29
28
27
26
25
24
NC
VRT
NC
AVEE
AVEE
NC
NC
AGND
VIN
AGND
VRM
AGND
VIN
AGND
NC
NC
AVEE
AVEE
NC
VRB
21 22
23
NCCLK
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
2610 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
NC
AVEE
AVEE
NC
VRB
NC
NC
NC
CLK
CLK
NC
MINV
NC
DVEE
NC
NC
NC
AVEE
AVEE
NC
VRT
NC
AVEE
NC
NC
NC
LINV
NC
DVEE
NC
DGND1
DGND2
NC
NC
NC
NC
NC
AGND
VIN
AGND
VRM
AGND
VIN
AGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
(LSB) D0
D1
D2
D3
D4
D5
D6
(MSB) D7
NC
DGND2
DGND1
NC
NC
NC
NC
Features
• Differential Linearity Error ±0.5 LSB (Typ) or Less
• Integral Linearity Error ±0.5 LSB (Typ) or Less
• Built-In Integral Linearity Compensation Circuit
• Ultra High Speed Operation with Maximum
Conversion Rate of 125 MSPS (Min)
• Low Input Capacitance 18pF (Typ)
• Wide Analog Input Bandwidth 200MHz (Min for Full-
Scale Input)
• Single Power Supply -5.2V
• Low Power Consumption 870mW (Typ)
• Low Error Rate
• Operable at 50% Clock Duty Cycle
• Capable of Driving 50Ω Loads
• Evaluation Board Available
Applications
• Video Digitizing • Communication Systems
• HDTV (High Definition TV) • Radar Systems
• Direct RF Down-Conversion • Digital Oscilloscopes
File Number 3576.2
2
HI1396, CXA1396
Functional Block Diagram
255
254
R/2
R
R
R3
193
R
191
R
192
R
129
R128
R127
R126
R
R2
VRM
VIN
VRB
CLOCK
DRIVER
65
R
63
R
64
R
2
R1
VIN
R
R/2
VRT
R1 COMPARATOR
MINV
ENCODE
LOGIC
LINV
OUTPUT
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
CLK
CLK
3
Specifications HI1396, CXA1396
Absolute Maximum Ratings TA = +25oCThermal Information
Supply Voltage (AVEE, DVEE). . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V
Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
Reference Input Voltage
VRT, VRB, VRM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V
|VRT-VRB| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V
Digital Input Voltage
CLK, CLK, MINV, LINV. . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V
|CLK-CLK| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V
VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . .-3mA to +3mA
Digital Output Current (ID0 to ID7). . . . . . . . . . . . . . . -30mA to 0mA
Storage Temperature Range (TSTG). . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance θJA θJC
HI1396JCP, CXA1396P. . . . . . . . . . . . . . 52oC/W -
HI1396JCJ, CXA1396D. . . . . . . . . . . . . . 36oC/W 12oC/W
HI1396AIL, CXA1396K . . . . . . . . . . . . . . 38oC/W 10oC/W
Maximum Power Dissipation
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.61W
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.44W
Operating Temperature (Note 4)
HI1396JCP, CXA1396P TA . . . . . . . . . . . . . . . . . .-20oC to +75oC
HI1396JCJ, CXA1396D TA . . . . . . . . . . . . . . . . . .-20oC to +75oC
HI1396AIL, CXA1396K TC. . . . . . . . . . . . . . . . . .-20oC to +100oC
Maximum Junction Temperature
HI1396JCP, CXA1396P. . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
HI1396JCJ, CXA1396D HI1396AIL, CXA1396K. . . . . . . . +175oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions (Note 1)
Supply Voltage
AVEE, DVEE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V
AVEE-DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
AGND-DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V
Reference Input Voltage
VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V
VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V
Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT
Pulse Width of Clock
TPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0ns Min.
TPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.0ns Min.
Electrical Specifications TA = +25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PERFORMANCE
Resolution 8 - - Bits
Integral Linearity Error, (INL)
HI1396JCJ, CXA1396D
HI1396AIL, CXA1396K FC = 125MHz - - ±0.5 LSB
HI1396JCP, CXA1396P - - ±0.8 LSB
Differential Linearity Error, (DNL)
HI1396JCJ, CXA1396D
HI1396AIL, CXA1396K FC = 125MHz - - ±0.5 LSB
HI1396JCP, CXA1396P - - ±0.7 LSB
ANALOG INPUT
Input Bandwidth VIN = 2VP-P 200 - - MHz
Analog Input Capacitance, CIN VIN = 1V + 0.07VRMS -18-pF
Analog Input Resistance, RIN 50 190 - kΩ
Input Bias Current, IIN VIN = -1V 20 130 400 µA
REFERENCE INPUTS
Reference Resistance, RREF 75 110 155 Ω
Offset Voltage
EOT VRT 81932mV
E
OB VRB 0 9 24 mV
4
Specifications HI1396, CXA1396
DIGITAL INPUTS
Logic H Level, VIH -1.13 - - V
Logic L Level, VIL - - -1.50 V
Logic H Current, IIH Input Connected to -0.8V 0 - 50 µA
Logic L Current, IIL Input Connected to -1.6V 0 - 50 µA
Input Capacitance - 7 - pF
DIGITAL OUTPUTS
Logic H Level, VOH RL = 50Ω to -2V -1.10 - - V
Logic L Level, VOL RL = 50Ω to -2V - - -1.62 V
TIMING CHARACTERISTICS
Output Rise Time, TRRL = 50Ω to -2V, 20% to 80% 0.5 0.9 1.2 ns
Output Fall Time, TFRL = 50Ω to -2V, 20% to 80% 0.5 1.0 1.3 ns
Output Delay, TOD 3.0 3.6 4.2 ns
H Pulse Width of Clock, TPW1 4.0 - - ns
L Pulse Width of Clock, TPW0 4.0 - - ns
DYNAMIC CHARACTERISTICS
Maximum Conversion Rate, FCError Rate 10-9 TPS (Note 2) 125 - - MSPS
Aperture Jitter, TAJ -10-ps
Sampling Delay, TDS - 1.5 - ns
Signal to Noise Ratio (SINAD) Input = 1MHz, Full Scale
FC = 125MHz -46-dB
Input = 31.5MHz, Full Scale
FC = 125MHz -40-dB
Error Rate Input = 31.249MHz, Full Scale
Error > 16 LSB, FC = 125MHz --10
-9 TPS
(Note 2)
Differential Gain Error, DG NTSC 40IRE Mod.
Ramp, FC = 125 MSPS - 1.0 - %
Differential Phase Error, DP - 0.5 - Degree
POWER SUPPLY CHARACTERISTICS
Supply Current, IEE -230 -160 - mA
Power Consumption Note 3 - 870 - mW
NOTES:
1. Electrical Specifications guaranteed within stated operating conditions.
2. TPS: Times Per Sample.
3.
4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Electrical Specifications TA = +25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RMS Signal
RMS Noise Distortion+
------------------------------------------------------------------
=
PDIEE VEE
•VRT-VRB


2
R
REF
------------------------------------------
+=
5
HI1396, CXA1396
Timing Diagram
FIGURE 1.
Pin Descriptions and I/O Pin Equivalent Circuit
PIN NUMBER
SYMBOL I/O
STAN-
DARD
VOLTAGE
LEVEL EQUIVALENT CIRCUIT DESCRIPTIONDIP LCC
29, 31,
33, 35 49, 51,
53, 55 AGND - 0V Analog GND. Used as GND for
input buffers and latches of com-
parators. Isolated from DGND1,
DGND2.
1, 25,
26, 38,
39
41, 42,
62, 63,
67
AVEE - -5.2V Analog VEE -5.2V (Typ). Internal-
ly connected to DVEE (Resis-
tance: 4Ω to 6Ω). Bypass with
0.1µF to AGND.
21 35 CLK I ECL CLK Input
20 34 CLK Input complementary to CLK.
When left open pulled down to
-1.3V. Device is operable without
CLK input, but use of comple-
mentary inputs of CLK and CLK
is recommended to obtain stable
high speed operation.
NN + 1
N + 2
N + 1
NN - 1 20% 80%
TR
TOD TF
TPW1 TPW0
20% 80%
ANALOG IN
CLK
CLK
DIGITAL OUT
DVEE
CLK
CLK
DGND1
R
R
R
R
RR
6
HI1396, CXA1396
5, 16 7, 24 DGND1 - 0V Digital GND for internal circuits.
6, 15 8, 23 DGND2 - 0V Digital GND for output transis-
tors.
4, 17 5, 30 DVEE - -5.2V Digital VEE. Internally connected
to AVEE (resistance: 4Ω to 6Ω).
Bypass with 0.1µF to DGND
7 14 D0 O ECL LSB of data outputs. External
pull-down resistor is required.
815D1 Data outputs. External pull-down
resistors are required.
916D2
10 17 D3
11 18 D4
12 19 D5
13 20 D6
14 21 D7 MSB of data outputs. External
pull-down resistor is required.
3 3 LINV I ECL Input pin for D0 (LSB) to D6 out-
put polarity inversion (see A/D
Output Code Table). Pulled low
when left open.
18 32 MINV I ECL Input pin for D7 (MSB) output po-
larity inversion (see A/D Output
Code Table). Pulled low when left
open.
30, 34 50, 54 VIN IV
RT to VRB Analog input pins. These two pins
must be connected externally,
since they are not internally con-
nected.
Pin Descriptions and I/O Pin Equivalent Circuit
(Continued)
PIN NUMBER
SYMBOL I/O
STAN-
DARD
VOLTAGE
LEVEL EQUIVALENT CIRCUIT DESCRIPTIONDIP LCC
DVEE
DGND2
DI
R
R
R
R
-1.3V
DVEE
DGND1
LINV
OR
MINV
VIN
VIN
AVEE
AGND
7
HI1396, CXA1396
23 39 VRB I -2V Reference voltage (bottom). Typ-
ically -2V. Bypass with a 0.1µF
and 10µF to AGND.
32 52 VRM IV
RB/2 Reference voltage mid point. Can
be used as a pin for integral lin-
earity compensation. Reference
voltage (top) typically 0V. When a
voltage different from AGND is
applied to this pin, bypass with a
0.1µF and 10µF to AGND.
41 65 VRT I0V
2, 19,
22, 24,
27, 28,
36, 37,
40, 42
1, 2, 4,
6, 9-13,
25-29,
31, 33,
36-38,
40,
43-48,
56-61,
64, 66,
68
NC - - Unused pins. No internal connec-
tions have been made to these
pins. Connecting them to AGND
or DGND on PC board is recom-
mended.
A/D OUTPUT CODE TABLE
VIN (Note 1) STEP
MINV 1, LINV 1 0, 1 1, 0 0, 0
D7 D0 D7 D0 D7 D0 D7 D0
0V 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11
0 000 • • • • • 00 100 • • • • • 00 011 • • • • • 11 111 • • • • • 11
1 000 • • • • • 01 100 • • • • • 01 011 • • • • • 10 111 • • • • • 10
•
•
•
•
•
•
•
•
•
•
•
•
-1V 127 011 • • • • • 11 111 • • • • • 11 000 • • • • • 00 100 • • • • • 00
128 100 • • • • • 00 000 • • • • • 00 111 • • • • • 11 011 • • • • • 11
•
•
•
•
•
•
•
•
•
•
•
•
254 111 • • • • • 10 011 • • • • • 10 100 • • • • • 01 000 • • • • • 01
255 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00
-2V 111 • • • • • 11 011 • • • • • 11 100 • • • • • 00 000 • • • • • 00
NOTE:
1. VRT = 0V, VRB = -2V.
Pin Descriptions and I/O Pin Equivalent Circuit
(Continued)
PIN NUMBER
SYMBOL I/O
STAN-
DARD
VOLTAGE
LEVEL EQUIVALENT CIRCUIT DESCRIPTIONDIP LCC
R
R
R
VRT
R/2
R1
COMPARATOR 1
COMPARATOR 2
COMPARATOR 127
R
COMPARATOR 128
R2
VRM
R
COMPARATOR 129
R
COMPARATOR 130
R
COMPARATOR 255
R/2
VRB R3
8
HI1396, CXA1396
Test Circuits
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
VIN 8COMPARATOR
A>B PULSE
COUNTER
ECL LATCH
SIGNAL
SOURCE
SIGNAL
SOURCE
fCLK
4-1kHz
2VP-P SINEWAVE
CLK CLK
FCLK/4
ECL LATCH
HI1396,
+
DATA 16
A
B
fCLK
CXA1396
SIGNAL
SOURCE
NTSC
SG (CW)
AMP VIN HI1396,
DUT 8LATCH
ECL 8D/A
10 BIT
SCOPE
VECTOR
CLK CLK
DELAY
50 VBB
DG.DP
HI20201
CXA1396
-
VIN HI1396,
DUT 8
CLK (125MHz)
+
A<B A>B
COMPARATOR
A8
A1
A0
B8
B1
B0
“0” “1”
8
S1
S2
-V
+V
S1 : A < B : ON
S2 : A > B : ON
BUFFER
DVM
CONTROLLER
8TO
11111110
00000000
CXA1396
9
HI1396, CXA1396
FIGURE 5A. FIGURE 5B.
FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS
Aperture jitter is defined as follows:
FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD
Where σ (unit: LSB) is the deviation of the output codes when the
input frequency is exactly the same as the clock and is sampled at
the largest slew rate point.
FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
Test Circuits
(Continued)
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
30
42
41
40
39
38
37
36
35
34
33
32
31
29
28
27
26
25
24
21 22
23
A
-1V
IIN
-2V
AIEE
-5.2V
HI1396JCJ
CXA1396D/P
HI1396JCP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
2610 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
AIEE
-5.2V
-2V
A
IIN -1V
HI1396AIL
CXA1396K
VIN HI1396, 8
CLK
LOGIC
ANALYZER
1024
SAMPLES
ECL
BUFFER
AMP
OSC1
φ: VARIABLE
OSC2
67.5MHz
67.5MHz
fRCXA1396
APERTURE JITTER
σ (LSB)
129
128
127
126
125
0V
-1V
-2V
VIN
CLK
VIN
CLK
∆υ
∆tt
TAJ σ∆υ
∆t
-------
⁄σ256
2
---------- 2πf×


⁄==
10
HI1396, CXA1396
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
S S
-D-
-A-
-C-
eA
-B-
aaa C A - B
MD
S S
ccc C A - B
MD
S S
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
S2
M
A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
D42.6
42 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.142 0.225 3.60 5.72 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.022 0.36 0.56 3
b2 0.035 0.043 1.90 1.10 -
b3----4
c 0.009 0.015 0.23 0.38 2
c1 0.009 0.012 0.23 0.30 3
D 2.083 2.122 52.9 53.9 -
E 0.510 0.620 12.95 15.75 -
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.130 - 3.30 - -
Q 0.039 - 1.00 - 5
S1 0.005 - 0.13 - 6
S2 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2
N42 428
Rev. 0 4/94
11
HI1396, CXA1396
D
j x 45o
D3
B
h x 45o
AA1
E
LL3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010 E H
S S
0.010 E F
S S
-E-
0.007 E F
MSHS
B1
-H-
-F-
Ceramic Leadless Chip Carrier Packages (CLCC)
J68.A
68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.067 0.087 1.70 2.20 6, 7
A1 0.058 0.072 1.47 1.83 -
B-----
B1 0.033 0.039 0.85 0.99 2 , 4
B3 0.006 0.022 0.15 0.56 -
D 0.940 0.965 23.88 24.51 -
D1 0.800 BSC 20.32 BSC -
D2 0.400 BSC 10.16 BSC -
D3 0.616 0.632 15.65 16.05 2
E 0.940 0.965 23.88 24.51 -
E1 0.800 BSC 20.32 BSC -
E2 0.400 BSC 10.16 BSC -
E3 0.616 0.632 15.65 16.05 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
j 0.040 Ref 1.00 Ref 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.91 2.41 -
L3 0.003 0.015 0.08 0.38 -
ND 17 17 3
NE 17 17 3
N68 683
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
12
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Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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NORTH AMERICA
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TEL: 1-800-442-7747
(407) 729-4984
FAX: (407) 729-5321
EUROPE
Harris Semiconductor
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Harris Semiconductor PTE Ltd.
No. 1 Tannery Road
Cencon 1, #09-01
Singapore 1334
TEL: (65) 748-4200
FAX: (65) 748-0400
SEMICONDUCTOR
HI1396, CXA1396
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C A
MBS
eA-C-
Dual-In-Line Plastic Packages (PDIP)
E42.6
42 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8, 10
C 0.008 0.015 0.204 0.381 -
D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N42 429
Rev. 0 12/93