DS07-13705-3E
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90595/595G Series
MB90598/F598/F598G/V595/V595G
■
■■
■DESCRIPTION
The MB90595/595G series with FULL-CAN*1 interface and FLASH ROM is especially designed for automotive
and industrial applications. Its main f eatures are two on board CAN Interf aces , which conf orm to V2.0 Part A and
P art B, while supporting a very fle xib le message buffer scheme and so offering more functions than a normal full
CAN approach.
The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions,
and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word data.
The MB90595/595G series has peripheral resources of 8/10-bit A/D con verters, U AR T (SCI), e xtended I/O serial
interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)) and stepping motor controller.
*1: Controller Area Network (CAN) - License of Robert Bosch GmbH
*2: F2MC stands for FUJITSU Flexible Microcontroller.
■
■■
■FEATURES
•Clock
Embedded PLL clock multiplication circuit
Operating cloc k (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz, 4 MHz to 16 MHz).
Minimum instruction ex ecution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
VCC of 5.0 V)
(Continued)
■
■■
■PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90595/595G Series
2
(Continued)
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4-byte instruction queue
• Enhanced interrupt function: 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS): Up to 10 channels
• Embedded ROM size and types
Mask ROM: 128 Kbytes
Flash ROM: 128 Kbytes
Embedded RAM size: 4 Kbytes (MB90V595/595G : 6 Kbytes)
•Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Hardware stand-by mode
• Process: 0.5 µm CMOS technology
• I/O port
General-pur pose I/O ports: 78 ports
Push-pull output and Schmitt trigger input.
Programmable on each bit as I/O or signal for peripherals.
•Timer
Watchdog timer: 1 channel
8/16-bit PPG timer: 8/16-bit × 6 channels
16-bit re-load timer: 2 channels
• 16-bit I/O timer
Input capture: 4 channels
Output compare: 4 channels
• Extended I/O serial interface: 1 channel
•UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
MB90595/595G Series
3
•UART1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial transmission (I/O extended transmission) can be selectively
used.
• Stepping motor controller (4 channels)
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI2OS) and generating an exter nal interr upt which
is triggered by an external input.
• Delayed interrupt generation module: Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
• FULL-CAN interface: 1 channel
Conforming to Version 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can be mixed)
• 18-bit Time-base counter
• External bus interface: Maximum address space 16 Mbytes
*: Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
MB90595/595G Series
4
■
■■
■PRODUCT LINEUP
(Continued)
Features MB90598 MB90F598/F598G MB90V595/V595G
Classification Mask ROM product Flash ROM product Evaluation product
ROM size 128 Kbytes 128 Kbytes
Boot block
Hard-wired reset vector None
RAM size 4 Kbytes 4 Kbytes 6 Kbytes
Emulator-specific power
supply *1None
CPU functions
The number of instructions: 351
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)
Interrupt processing time: 1.5 µs
(at machine clock frequency of 16 MHz, minimum value)
UART0
Clock synchronized transmission (500 K/1 M/2 Mbps)
Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500
/500000 bps at machine clock frequency of 16 MHz)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
UART1(SCI)
Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps)
Clock asynchronized transmission (1202/2404/4808/9615/31250 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
8/10-bit A/D converter
Conversion precision: 8/10-bit can be selectively used.
Number of inputs: 8
One-shot conversion mode (converts selected channel once only)
Scan conversion mode (converts two or more successive channels and can program
up to 8 channels)
Continuous conversion mode (converts selected channel continuously)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8/16-bit PPG timers
(6 channels)
Number of channels: 6 (8/16-bit × 6 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24 ( fsys = system clock frequency )
128µs ( fosc = 4MHz : oscillation clock frequency)
16-bit Reload timer Number of channels: 2
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
16-bit
I/O
timer
16-bit
Output compares Number of channels: 4
Pin input factor: A match signal of compare register
Input captures Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
MB90595/595G Series
5
(Continued)
*1:It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*2:Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
Features MB90598 MB90F598/F598G MB90V595/V595G
CAN Interface
Number of channels: 1
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
CAN bit timing setting:
MB90xxx:TSEG2 ≥ RSJW+2TQ
MB90xxxG:TSEG2 ≥ RSJW
Stepping motor controller
(4 channels) Four high current outputs for each channel
Synchronized two 8-bit PWM’s for each channel
External interrupt circuit Number of inputs: 8
Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
Serial IO Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock
frequency of 16 MHz)
LSB first/MSB first
Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
Flash Memory
Supports automatic programming, Embedded Algorithm TM and
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Writer from Minato Electronics Inc.
Low-power consumption
(stand-by) mode Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by
Process CMOS
Power supply voltage for
operation*2+5 V±10 %
Package QFP-100 PGA-256
MB90595/595G Series
6
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■■
■PIN ASSIGNMENT
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 Vss
P17/TOT1
P16/TIN1
P15/PPG5
P14/PPG4
P13/PPG3
P12/PPG2
P11/PPG1
P07/OUT3
P06/OUT2
P05/OUT1
P04/OUT0
P03/IN3
P02/IN2
P01/IN1
P00/IN0
Vcc
X1
X0
P10/PPG0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
9
8
MD1
MD0
P57/TOT0
P56/TIN0
P67/AN7
P66/AN6
P65/AN5
P64/AN4
Vss
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVss
AVRL
AVRH
AVcc
P55/ADTG
P54/INT7
P53/INT6
P95/INT3
P94/INT2
P93/INT1
RST
P92/INT0
P91/RX
P90/TX
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
HST
MD2
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P52/INT5
P51/INT4
P50/SIN2
C
P47/SCK2
P46/SOT2
P45/SOT1
Vcc
P44/SCK1
P43/SIN1
P42/SIN0
P41/SCK0
P40/SOT0
P37
P36
P35
P34
P33
P32
Vss
(Top view)
(FPT-100P-M06)
MB90595/595G Series
7
■
■■
■PIN DESCRIPTION
(Continued)
Pin no. Pin name Circuit type Function
82 X0 A Oscillator pin
83 X1
77 RST B Reset input
52 HST C Hardware standby input
85 to 88 P00 to P03 GGeneral purpose IO
IN0 to IN3 Inputs for the Input Captures
89 to 92 P04 to P07 GGeneral purpose IO
OUT0 to OUT3 Outputs for the Output Compares.
93 to 98 P10 to P15 DGeneral purpose IO
PPG0 to PPG5 Outputs for the Programmable Pulse Generators
99 P16 DGeneral purpose IO
TIN1 TIN input for the 16-bit Reload Timer 1
100 P17 DGeneral purpose IO
TOT1 TOT output for the 16-bit Reload Timer 1
1 to 8 P20 to P27 G General purpose IO
9 to 10 P30 to P31 G General purpose IO
12 to 16 P32 to P36 G General purpose IO
17 P37 D General purpose IO
18 P40 GGeneral purpose IO
SOT0 SOT output for UART 0
19 P41 GGeneral purpose IO
SCK0 SCK input/output for UART 0
20 P42 GGeneral purpose IO
SIN0 SIN input for UART 0
21 P43 GGeneral purpose IO
SIN1 SIN input for UART 1
22 P44 GGeneral purpose IO
SCK1 SCK input/output for UART 1
24 P45 GGeneral purpose IO
SOT1 SOT output for UART 1
25 P46 GGeneral purpose IO
SOT2 SOT output for the Serial IO
26 P47 GGeneral purpose IO
SCK2 SCK input/output for the Serial IO
MB90595/595G Series
8
(Continued)
Pin no. Pin name Circuit type Function
28 P50 DGeneral purpose IO
SIN2 SIN Input for the Serial IO
29 to 32 P51 to P54 DGeneral purpose IO
INT4 to INT7 External interrupt input for INT4 to INT7
33 P55 DGeneral purpose IO
ADTG Input for the external trigger of the A/D Converter
38 to 41 P60 to P63 EGeneral purpose IO
AN0 to AN3 Inputs for the A/D Converter
43 to 46 P64 to P67 EGeneral purpose IO
AN4 to AN7 Inputs for the A/D Converter
47 P56 DGeneral purpose IO
TIN0 TIN input for the 16-bit Reload Timer 0
48 P57 DGeneral purpose IO
TOT0 TOT output for the 16-bit Reload Timer 0
54 to 57
P70 to P73
F
General purpose IO
PWM1P0
PWM1M0
PWM2P0
PWM2M0
Output for Stepper Motor Controller channel 0
59 to 62
P74 to P77
F
General purpose IO
PWM1P1
PWM1M1
PWM2P1
PWM2M1
Output for Stepper Motor Controller channel 1
64 to 67
P80 to P83
F
General purpose IO
PWM1P2
PWM1M2
PWM2P2
PWM2M2
Output for Stepper Motor Controller channel 2
69 to 72
P84 to P87
F
General purpose IO
PWM1P3
PWM1M3
PWM2P3
PWM2M3
Output for Stepper Motor Controller channel 3
74 P90 DGeneral purpose IO
TX TX output for CAN Interface
75 P91 DGeneral purpose IO
RX RX input for CAN Interface
MB90595/595G Series
9
(Continued)
Pin no. Pin name Circuit type Function
76 P92 DGeneral purpose IO
INT0 External interrupt input for INT0
78 to 80 P93 to P95 DGeneral purpose IO
INT1 to INT3 External interrupt input for INT1 to INT3
58, 68 DVCC Dedicated power supply pins for the high current output buffers
(Pin No. 54 to 72)
53, 63, 73 DVSS Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)
34 AVCC Power supply Dedicated power supply pin for the A/D Converter
37 AVSS Power supply Dedicated ground pin for the A/D Converter
35 AVRH Power supply Upper reference voltage input for the A/D Converter
36 AVRL Power supply Lower reference voltage input for the A/D Converter
49, 50 MD0
MD1 COperating mode selection input pins. These pins should be con-
nected to VCC or VSS.
51 MD2 H Operating mode selection input pin. This pin should be connected
to VCC or VSS.
27 C External capacitor pin. A capacitor of 0.1µF should be
connected to this pin and VSS.
23, 84 VCC Power supply Power supply pins (5.0 V).
11, 42, 81 VSS Power supply Ground pins (0.0 V).
MB90595/595G Series
10
■
■■
■I/O CIRCUIT TYPE
(Continued)
Circuit Type Circuit Remarks
A
• Oscillation feedback resistor:
1 MΩ approx.
B
• Hysteresis input with pull-up
Resistor: 50 kΩ approx.
C• Hysteresis input
D
•CMOS output
• CMOS Hysteresis input
E
•CMOS output
• CMOS Hysteresis input
• Analog input
X1
X0
Standby control
signal
HYS
R
R
HYS
R
HYS
R
P-ch
N-ch
VCC
Analog input
HYS
R
P-ch
N-ch
VCC
MB90595/595G Series
11
Circuit Type Circuit Remarks
F
• CMOS high current output
• CMOS Hysteresis input
G
•CMOS output
• CMOS Hysteresis input
• TTL input
(MB90F598/F598G, only in Flash mode)
H
• Hysteresis input
Pull-down Resistor: 50 Ω approx.
(except MB90F598/F598G)
HYS
High current
R
P-ch
N-ch
VCC
HYS
TTL
T
R
R
P-ch
N-ch
VCC
HYS
R
R
MB90595/595G Series
12
■
■■
■HANDLING DEVICES
(1) Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up).
In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is
applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS.
When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal
break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating.
In turning on/turning off the analog power supply, make sure the analog pow er v oltage (AVCC, AVRH, DVCC) and
analog input voltages not exceed the digital voltage (VCC).
(2) Treatment of Unused Pins
Unused input pins left open ma y cause abnormal operation, or latch-up leading to permanent damage. Unused
input pins should be pulled up or pulled down through at least 2 kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
(3) Using external clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected.
(4) Power supply pins (Vcc/Vss)
In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to
avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a
ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused
by the rise in the ground level, and to conform to the total current rating (See the figure below.)
Make sure to connect Vcc and Vss pins via lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between Vcc and Vss pins near the device.
X0
X1 MB90595/595G Series
Using external clock
Open
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90595/595G
Series
Vcc Vss
Vcc
Vss
MB90595/595G Series
13
(5) Pull-up/down resistors
The MB90595 Series does not support internal pull-up/down resistors. Use e xternal components where needed.
(6) Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via
shor test distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure
that lines of oscillation circuit not cross the lines of other circuits.
A printed circuit board artwork surrounding the X0 and X1 pins with ground area f or stabilizing the operation is
highly recommended.
(7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D conver ter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7)
after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the vo ltage does not exceed AVRH or AVCC (tur ning on/off the analog and digital power supplies simulta-
neously is acceptable).
(8) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
(9) N.C. Pin
The N.C. (internally connected) pin must be opened for use.
(10) Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time dur ing energization at 50
µs or more (0.2 V to 2.7 V).
(11) Indeterminate outputs from ports 0 and 1
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the
outputs from ports 0 and 1 become following state.
•If RST
pin is “H”, the outputs become indeterminate.
•If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow. Oscillation setting time∗2
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal Period of indeterminated
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
RST pin is “H”
MB90595/595G Series
14
(12) Initialization
The de vice contains internal registers which are initialized only by a power-on reset. To initialize these registers,
please turn on the pow e r again.
(13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”), the value of the corre-
sponding bank register (DTB, ADB, USB, SSB) is set in “00H”.
If the v alues of the corresponding bank register (DTB,ADB ,USB,SSB) are set to other than “00H”, the remainder
by the execution result of the instruction is not stored in the register of the instruction operand.
(14) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
Oscillation setting time∗2
Power-on reset∗1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal High-impedance
*1:Power-on reset time: Period of “clock frequency × 217” (Clock frequency of 16 MHz: 8.19 ms)
*2:Oscillation setting time: Period of “clock frequency × 218” (Clock frequency of 16 MHz: 16.38ms)
RST pin is “L”
MB90595/595G Series
15
■
■■
■BLOCK DIAGRAM
RAM 4 K
ROM/Flash
UART0
Prescaler
Serial I/O
Prescaler
10-bit ADC
8 ch
16-bit Reload
Timer 2 ch
16-bit
Clock
Controller
16-bit Input
Capture
4 ch
16-bit Output
Compare
4 ch
CAN
Controller
External
Interrupt
8/16-bit
PPG
6 ch
F2MC-16LX
CPU
F2MC-16 Bus
X0,X1
RST
HST
SOT0
SCK0
SIN0
SCK2
SOT2
SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
TIN0, TIN1
TOT0, TOT1
IN0 to IN3
OUT0 to OUT3
PPG0 to PPG5
RX
TX
INT0 to INT7
UART1
Prescaler
SOT1
SCK1
SIN1 (SCI)
128 K
SMC
4ch
PWM1M0 to PWM1M3
PWM1P0 to PWM1P3
PWM2M0 to PWM2M3
PWM2P0 to PWM2P3
DVCC0, DVCC1
DVSS0 to DVSS2
IO Timer
8 ch
MB90595/595G Series
16
■
■■
■MEMORY SPACE
The memory space of the MB90595 Series is shown below
Memory space map
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C
compiler small model. The low er 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same
address, enabling reference of the table on the ROM without stating “far”.
For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are
accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in
the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image
f or 004000H to 00FFFFH. Thus, it is recommended that the ROM data tab le be stored in the area of FF4000H
to FFFFFFH.
MB90V595/V595G MB90598/F598/F598G
FFFFFFH
FF0000HROM (FF bank) FFFFFFH
FF0000HROM (FF bank)
FEFFFFH
FE0000HROM (FE bank) FEFFFFH
FE0000HROM (FE bank)
FDFFFFH
FD0000HROM (FD bank)
FCFFFFH
FC0000HROM (FC bank)
00FFFFH
004000H
ROM
(Image of FF bank) 00FFFFH
004000H
ROM
(Image of FF bank)
001FFFH
001900HPeripheral 001FFFH
001900HPeripheral
0018FFH
000100H
RAM 6 K 0010FFH
000100H
RAM 4 K
0000BFH
000000HPeripheral 0000BFH
000000HPeripheral
MB90595/595G Series
17
■
■■
■I/O MAP
(Continued)
Address Register Abbreviation Access Peripheral Initial value
00HPort 0 Data Register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 Data Register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 Data Register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 Data Register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 Data Register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 Data Register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 Data Register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 Data Register PDR7 R/W Port 7 XXXXXXXXB
08HPort 8 Data Register PDR8 R/W Port 8 XXXXXXXXB
09HPort 9 Data Register PDR9 R/W Port 9 _ _ XXXXXXB
0AH to 0FHReserved
10HPort 0 Direction Register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
11HPort 1 Direction Register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12HPort 2 Direction Register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13HPort 3 Direction Register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14HPort 4 Direction Register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15HPort 5 Direction Register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16HPort 6 Direction Register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17HPort 7 Direction Register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
18HPort 8 Direction Register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19HPort 9 Direction Register DDR9 R/W Port 9 _ _ 0 0 0 0 0 0B
1AHReserved
1BHAnalog Input Enable Register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B
1CH to 1FHReserved
20HSerial Mode Control Register 0 UMC0 R /W
UART0
0 0 0 0 0 1 0 0B
21HSerial status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B
22HSerial Input/Output Data Register 0 UIDR0/
UODR0 R/W XXXXXXXXB
23HRate and Data Register 0 URD0 R/W 0 0 0 0 0 0 0 XB
24HSerial Mode Register 1 SMR1 R/W
UART1
0 0 0 0 0 0 0 0B
25HSerial Control Register 1 SCR1 R/W 0 0 0 0 0 1 0 0B
26HSerial Input/Output Data Register 1 SIDR1/
SODR1 R/W XXXXXXXXB
27HSerial Status Register 1 SSR1 R/W 0 0 0 0 1 _ 0 0B
28HUART1 Prescaler Control Register U1CDCR R/W 0 _ _ _ 1 1 1 1B
MB90595/595G Series
18
(Continued)
Address Register Abbreviation Access Peripheral Initial value
29H to 2AHReserved
2BHSerial IO Prescaler SCDCR R/W
Serial IO
0 _ _ _ 1 1 1 1B
2CHSerial Mode Control Register (low-order) SMCS R/W _ _ _ _ 0 0 0 0B
2DHSerial Mode Control Register (high-order) SMCS R/W 0 0 0 0 0 0 1 0B
2EHSerial Data Register SDR R/W XXXXXXXXB
2FHEdge Selector SES R/W _ _ _ _ _ _ _ 0B
30HExternal Interrupt Enable Register ENIR R/W
External Interrupt
0 0 0 0 0 0 0 0B
31HExternal Interrupt Request Register EIRR R/W XXXXXXXXB
32HExternal Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
33HExternal Interrupt Level Register ELVR R/W 0 0 0 0 0 0 0 0B
34HA/D Control Status Register 0 ADCS0 R/W
A/D Converter
0 0 0 0 0 0 0 0B
35HA/D Control Status Register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B
36HA/D Data Register 0 ADCR0 R XXXXXXXXB
37HA/D Data Register 1 ADCR1 R/W 0 0 0 0 1 _ XXB
38HPPG0 Operation Mode Control Register PPGC0 R/W 16-bit Program-
mable Pulse
Generator 0/1
0 _ 0 0 0 _ _ 1B
39HPPG1 Operation Mode Control Register PPGC1 R/W 0 _ 0 0 0 0 0 1B
3AHPPG0, 1 Output Pin Control Register PPG01 R/W 0 0 0 0 0 0 _ _B
3BHReserved
3CHPPG2 Operation Mode Control Register PPGC2 R/W 16-bit Program-
mable Pulse
Generator 2/3
0 _ 0 0 0 _ _ 1B
3DHPPG3 Operation Mode Control Register PPGC3 R/W 0 _ 0 0 0 0 0 1B
3EHPPG2, 3 Output Pin Control Register PPG23 R/W 0 0 0 0 0 0 _ _B
3FHReserved
40HPPG4 Operation Mode Control Register PPGC4 R/W 16-bit Program-
mable Pulse
Generator 4/5
0 _ 0 0 0 _ _ 1B
41HPPG5 Operation Mode Control Register PPGC5 R/W 0 _ 0 0 0 0 0 1B
42HPPG4, 5 Output Pin Control Register PPG45 R/W 0 0 0 0 0 0 _ _B
43HReserved
44HPPG6 Operation Mode Control Register PPGC6 R/W 16-bit Program-
mable Pulse
Generator 6/7
0 _ 0 0 0 _ _ 1B
45HPPG7 Operation Mode Control Register PPGC7 R/W 0 _ 0 0 0 0 0 1B
46HPPG6, 7 Output Pin Control Register PPG67 R/W 0 0 0 0 0 0 _ _B
47HReserved
48HPPG8 Operation Mode Control Register PPGC8 R/W 16-bit Program-
mable Pulse
Generator 8/9
0 _ 0 0 0 _ _ 1B
49HPPG9 Operation Mode Control Register PPGC9 R/W 0 _ 0 0 0 0 0 1B
4AHPPG8, 9 Output Pin Control Register PPG89 R/W 0 0 0 0 0 0 _ _B
4BHReserved
MB90595/595G Series
19
(Continued)
Address Register Abbreviation Access Peripheral Initial value
4CHPPGA Operation Mode Control Register PPGCA R/W 16-bit
Programmable
Pulse
Generator A/B
0 _ 0 0 0 _ _ 1B
4DHPPGB Operation Mode Control Register PPGCB R/W 0 _ 0 0 0 0 0 1B
4EHPPGA, B Output Pin Control Register PPGAB R/W 0 0 0 0 0 0 _ _B
4FHReserved
50HTimer Control Status Register 0 TMCSR0 R/W
16-bit
Reload Timer 0
0 0 0 0 0 0 0 0B
51HTimer Control Status Register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B
52HTimer 0/Reload Register 0 TMR0/
TMRLR0 R/W XXXXXXXXB
53HTimer 0/Reload Register 0 TMR0/
TMRLR0 R/W XXXXXXXXB
54HTimer Control Status Register 1 TMCSR1 R/W
16-bit
Reload Timer 1
0 0 0 0 0 0 0 0B
55HTimer Control Status Register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B
56HTimer Register 1/Reload Register 1 TMR1/
TMRLR1 R/W XXXXXXXXB
57HTimer Register 1/Reload Register 1 TMR1/
TMRLR1 R/W XXXXXXXXB
58HOutput Compare Control Status Register 0 OCS0 R/W Output
Compare 0/1 0 0 0 0 _ _ 0 0B
59HOutput Compare Control Status Register 1 OCS1 R/W _ _ _ 0 0 0 0 0B
5AHOutput Compare Control Status Register 2 OCS2 R/W Output
Compare 2/3 0 0 0 0 _ _ 0 0B
5BHOutput Compare Control Status Register 3 OCS3 R/W _ _ _ 0 0 0 0 0B
5CHInput Capture Control Status Register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B
5DHInput Capture Control Status Register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B
5EHPWM Control Register 0 PWC0 R/W Stepping Motor
Controller 0 0 0 0 0 0 _ _ 0B
5FHReserved
60HPWM Control Register 1 PWC1 R/W Stepping Motor
Controller 1 0 0 0 0 0 _ _ 0B
61HReserved
62HPWM Control Register 2 PWC2 R/W Stepping Motor
Controller 2 0 0 0 0 0 _ _ 0B
63HReserved
64HPWM Control Register 3 PWC3 R/W Stepping Motor
Controller 3 0 0 0 0 0 _ _ 0B
65HReserved
66HTimer Data Register (low-order) TCDT R/W
IO Timer
0 0 0 0 0 0 0 0B
67HTimer Data Register (high-order) TCDT R/W 0 0 0 0 0 0 0 0B
68HTimer Control Status Register TCCS R/W 0 0 0 0 0 0 0 0B
69H to 6EHReserved
MB90595/595G Series
20
(Continued)
Address Register Abbreviation Access Peripheral Initial v alue
6FHROM Mirror Function Selection Register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B
70HPWM1 Compare Register 0 PWC10 R/W
Stepping Motor
Controller 0
XXXXXXXXB
71HPWM2 Compare Register 0 PWC20 R/W XXXXXXXXB
72HPWM1 Select Register 0 PWS10 R/W _ _ 0 0 0 0 0 0B
73HPWM2 Select Register 0 PWS20 R/W _ 0 0 0 0 0 0 0B
74HPWM1 Compare Register 1 PWC11 R/W
Stepping Motor
Controller 1
XXXXXXXXB
75HPWM2 Compare Register 1 PWC21 R/W XXXXXXXXB
76HPWM1 Select Register 1 PWS11 R/W _ _ 0 0 0 0 0 0B
77HPWM2 Select Register 1 PWS21 R/W _ 0 0 0 0 0 0 0B
78HPWM1 Compare Register 2 PWC12 R/W
Stepping Motor
Controller 2
XXXXXXXXB
79HPWM2 Compare Register 2 PWC22 R/W XXXXXXXXB
7AHPWM1 Select Register 2 PWS12 R/W _ _ 0 0 0 0 0 0B
7BHPWM2 Select Register 2 PWS22 R/W _ 0 0 0 0 0 0 0B
7CHPWM1 Compare Register 3 PWC13 R/W
Stepping Motor
Controller 3
XXXXXXXXB
7DHPWM2 Compare Register 3 PWC23 R/W XXXXXXXXB
7EHPWM1 Select Register 3 PWS13 R/W _ _ 0 0 0 0 0 0B
7FHPWM2 Select Register 3 PWS23 R/W _ 0 0 0 0 0 0 0B
80H to 8FHCAN Controller. Refer to section about CAN Controller
90H to 9DHReserved
9EHProgram Address Detection Control
Status Register PACSR R/W Address Match
Detection Function 0 0 0 0 0 0 0 0B
9FHDelayed Interrupt/Request Register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B
A0HLow-Power Mode Control Register LPMCR R/W Low Power
Controller 0 0 0 1 1 0 0 0B
A1HClock Selection Register CKSCR R/W Low Power
Controller 1 1 1 1 1 1 0 0B
A2H to A7HReserved
A8HWatchdog Timer Control Register WDTC R/W Watchdog Timer XXXXX 1 1 1B
A9HTime Base Timer Control Register TBTC R/W Time Base Timer 1 _ _ 0 0 1 0 0B
AAH to ADHReserved
AEHFlash Memory Control Status Register
(MB90F598/F598G only.
Otherwise reserved) FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B
AFHReserved
MB90595/595G Series
21
(Continued)
Address Register Abbreviation Access Peripheral Initial value
B0HInterrupt Control Register 00 ICR00 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
B1HInterrupt Control Register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2HInterrupt Control Register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3HInterrupt Control Register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4HInterrupt Control Register 04 ICR04 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
B5HInterrupt Control Register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6HInterrupt Control Register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7HInterrupt Control Register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
B8HInterrupt Control Register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
B9HInterrupt Control Register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAHInterrupt Control Register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBHInterrupt Control Register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCHInterrupt Control Register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDHInterrupt Control Register 13 ICR13 R/W 0 0 0 0 0 1 1 1B
BEHInterrupt Control Register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
BFHInterrupt Control Register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
C0H to FFHReserved
1900HReload Register L PRLL0 R/W 16-bit Programmable
Pulse
Generator 0/1
XXXXXXXXB
1901HReload Register H PRLH0 R/W XXXXXXXXB
1902HReload Register L PRLL1 R/W XXXXXXXXB
1903HReload Register H PRLH1 R/W XXXXXXXXB
1904HReload Register L PRLL2 R/W 16-bit Programmable
Pulse
Generator 2/3
XXXXXXXXB
1905HReload Register H PRLH2 R/W XXXXXXXXB
1906HReload Register L PRLL3 R/W XXXXXXXXB
1907HReload Register H PRLH3 R/W XXXXXXXXB
1908HReload Register L PRLL4 R/W 16-bit Programmable
Pulse
Generator 4/5
XXXXXXXXB
1909HReload Register H PRLH4 R/W XXXXXXXXB
190AHReload Register L PRLL5 R/W XXXXXXXXB
190BHReload Register H PRLH5 R/W XXXXXXXXB
190CHReload Register L PRLL6 R/W 16-bit Programmable
Pulse
Generator 6/7
XXXXXXXXB
190DHReload Register H PRLH6 R/W XXXXXXXXB
190EHReload Register L PRLL7 R/W XXXXXXXXB
190FHReload Register H PRLH7 R/W XXXXXXXXB
MB90595/595G Series
22
(Continued)
(Continued)
Address Register Abbreviation Access Peripheral Initial value
1910HReload Register L PRLL8 R/W 16-bit Programmable
Pulse
Generator 8/9
XXXXXXXXB
1911HReload Register H PRLH8 R/W XXXXXXXXB
1912HReload Register L PRLL9 R/W XXXXXXXXB
1913HReload Register H PRLH9 R/W XXXXXXXXB
1914HReload Register L PRLLA R/W 16-bit Programmable
Pulse
Generator A/B
XXXXXXXXB
1915HReload Register H PRLHA R/W XXXXXXXXB
1916HReload Register L PRLLB R/W 16-bit Programmable
Pulse Generator A/B XXXXXXXXB
1917HReload Register H PRLHB R/W XXXXXXXXB
1918H to 191FHReserved
1920HInput Capture Register 0
(low-order) IPCP0 R
Input Capture 0/1
XXXXXXXXB
1921HInput Capture Register 0
(high-order) IPCP0 R XXXXXXXXB
1922HInput Capture Register 1
(low-order) IPCP1 R XXXXXXXXB
1923HInput Capture Register 1
(high-order) IPCP1 R XXXXXXXXB
1924HInput Capture Register 2
(low-order) IPCP2 R
Input Capture 2/3
XXXXXXXXB
1925HInput Capture Register 2
(high-order) IPCP2 R XXXXXXXXB
1926HInput Capture Register 3
(low-order) IPCP3 R XXXXXXXXB
1927HInput Capture Register 3
(high-order) IPCP3 R XXXXXXXXB
1928HOutput Compare Register 0
(low-order) OCCP0 R/W
Output Compare 0/1
XXXXXXXXB
1929HOutput Compare Register 0
(high-order) OCCP0 R/W XXXXXXXXB
192AHOutput Compare Register 1
(low-order) OCCP1 R/W XXXXXXXXB
192BHOutput Compare Register 1
(high-order) OCCP1 R/W XXXXXXXXB
MB90595/595G Series
23
(Continued)
Note: Initial value of “_” represents unused bit; “X” represents unknown value.
Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions
of the MCU . A read access to these reserved addresses results in reading “X”, and an y write access should
not be perform ed.
Address Register Abbreviation Access Peripheral Initial value
192CHOutput Compare Register 2
(low-order) OCCP2 R/W
Output Compare 2/3
XXXXXXXXB
192DHOutput Compare Register 2
(high-order) OCCP2 R/W XXXXXXXXB
192EHOutput Compare Register 3
(low-order) OCCP3 R/W XXXXXXXXB
192FHOutput Compare Register 3
(high-order) OCCP3 R/W XXXXXXXXB
1930H to 19FFHReserved
1A00H to 1AFFHCAN Controller. Refer to section about CAN Controller
1B00H to 1BFFHCAN Controller. Refer to section about CAN Controller
1C00H to 1EFFHReserved
1FF0HProgram Address Detection
Register 0 (low-order)
PADR0 R/W
Address Match
Detection Function
XXXXXXXXB
1FF1HProgram Address Detection
Register 0 (middle-order) XXXXXXXXB
1FF2HProgram Address Detection
Register 0 (high-order) XXXXXXXXB
1FF3HProgram Address Detection
Register 1 (low-order)
PADR1 R/W
XXXXXXXXB
1FF4HProgram Address Detection
Register 1 (middle-order) XXXXXXXXB
1FF5HProgram Address Detection
Register 1 (high-order) XXXXXXXXB
1FF6H to 1FFFHReserved
MB90595/595G Series
24
■
■■
■CAN CONTROLLER
The CAN controller has the following features:
• Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
(Continued)
Address Register Abbreviation Access Initial Va lue
000080HMessage buffer valid register BVALR R/W 00000000 00000000B
000081H
000082HTransmit request register TREQR R/W 00000000 00000000B
000083H
000084HTransmit cancel register TCANR W 00000000 00000000B
000085H
000086HTransmit complete register TCR R/W 00000000 00000000B
000087H
000088HReceive complete register RCR R/W 00000000 00000000B
000089H
00008AHRemote request receiving register RRTRR R/W 00000000 00000000B
00008BH
00008CHReceive overrun register ROVRR R/W 00000000 00000000B
00008DH
00008EHReceive interrupt enable register RIER R/W 00000000 00000000B
00008FH
001B00HControl status register CSR R/W, R 00---000 0----0-1B
001B01H
001B02HLast event indicator register LEIR R/W -------- 000-0000B
001B03H
001B04HReceive/transmit error counter RTEC R 00000000 00000000B
001B05H
001B06HBit timing register BTR R/W -1111111 11111111B
001B07H
MB90595/595G Series
25
(Continued)
Address Register Abbreviation Access Initial Value
001B08HIDE register IDER R/W XXXXXXXX XXXXXXXXB
001B09H
001B0AHTransmit RTR register TRTRR R/W 00000000 00000000B
001B0BH
001B0CHRemote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXXB
001B0DH
001B0EHTransmit interrupt enable register TIER R/W 00000000 00000000B
001B0FH
001B10H
Acceptance mask select register AMSR R/W
XXXXXXXX XXXXXXXXB
001B11H
001B12HXXXXXXXX XXXXXXXXB
001B13H
001B14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXX XXXXXXXXB
001B15H
001B16HXXXXX--- XXXXXXXXB
001B17H
001B18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXX XXXXXXXXB
001B19H
001B1AHXXXXX--- XXXXXXXXB
001B1BH
MB90595/595G Series
26
List of Message Buffers (ID Registers)
(Continued)
Address Register Abbreviation Access Initial Value
001A00H
to
001A1FHGeneral-purpose RAM -- R/W XXXXXXXXB
to
XXXXXXXXB
001A20H
ID register 0 IDR0 R/W
XXXXXXXX XXXXXXXXB
001A21H
001A22HXXXXX--- XXXXXXXXB
001A23H
001A24H
ID register 1 IDR1 R/W
XXXXXXXX XXXXXXXXB
001A25H
001A26HXXXXX--- XXXXXXXXB
001A27H
001A28H
ID register 2 IDR2 R/W
XXXXXXXX XXXXXXXXB
001A29H
001A2AHXXXXX--- XXXXXXXXB
001A2BH
001A2CH
ID register 3 IDR3 R/W
XXXXXXXX XXXXXXXXB
001A2DH
001A2EHXXXXX--- XXXXXXXXB
001A2FH
001A30H
ID register 4 IDR4 R/W
XXXXXXXX XXXXXXXXB
001A31H
001A32HXXXXX--- XXXXXXXXB
001A33H
001A34H
ID register 5 IDR5 R/W
XXXXXXXX XXXXXXXXB
001A35H
001A36HXXXXX--- XXXXXXXXB
001A37H
001A38H
ID register 6 IDR6 R/W
XXXXXXXX XXXXXXXXB
001A39H
001A3AHXXXXX--- XXXXXXXXB
001A3BH
001A3CH
ID register 7 IDR7 R/W
XXXXXXXX XXXXXXXXB
001A3DH
001A3EHXXXXX--- XXXXXXXXB
001A3FH
MB90595/595G Series
27
(Continued)
Address Register Abbreviation Access Initial Value
001A40H
ID register 8 IDR8 R/W
XXXXXXXX XXXXXXXXB
001A41H
001A42HXXXXX--- XXXXXXXXB
001A43H
001A44H
ID register 9 IDR9 R/W
XXXXXXXX XXXXXXXXB
001A45H
001A46HXXXXX--- XXXXXXXXB
001A47H
001A48H
ID register 10 IDR10 R/W
XXXXXXXX XXXXXXXXB
001A49H
001A4AHXXXXX--- XXXXXXXXB
001A4BH
001A4CH
ID register 11 IDR11 R/W
XXXXXXXX XXXXXXXXB
001A4DH
001A4EHXXXXX--- XXXXXXXXB
001A4FH
001A50H
ID register 12 IDR12 R/W
XXXXXXXX XXXXXXXXB
001A51H
001A52HXXXXX--- XXXXXXXXB
001A53H
001A54H
ID register 13 IDR13 R/W
XXXXXXXX XXXXXXXXB
001A55H
001A56HXXXXX--- XXXXXXXXB
001A57H
001A58H
ID register 14 IDR14 R/W
XXXXXXXX XXXXXXXXB
001A59H
001A5AHXXXXX--- XXXXXXXXB
001A5BH
001A5CH
ID register 15 IDR15 R/W
XXXXXXXX XXXXXXXXB
001A5DH
001A5EHXXXXX--- XXXXXXXXB
001A5FH
MB90595/595G Series
28
List of Message Buffers (DLC Registers and Data Registers)
(Continued)
Address Register Abbreviation Access Initial Value
001A60HDLC register 0 DLCR0 R/W ----XXXXB
001A61H
001A62HDLC register 1 DLCR1 R/W ----XXXXB
001A63H
001A64HDLC register 2 DLCR2 R/W ----XXXXB
001A65H
001A66HDLC register 3 DLCR3 R/W ----XXXXB
001A67H
001A68HDLC register 4 DLCR4 R/W ----XXXXB
001A69H
001A6AHDLC register 5 DLCR5 R/W ----XXXXB
001A6BH
001A6CHDLC register 6 DLCR6 R/W ----XXXXB
001A6DH
001A6EHDLC register 7 DLCR7 R/W ----XXXXB
001A6FH
001A70HDLC register 8 DLCR8 R/W ----XXXX
001A71H
001A72HDLC register 9 DLCR9 R/W ----XXXXB
001A73H
001A74HDLC register 10 DLCR10 R/W ----XXXXB
001A75H
001A76HDLC register 11 DLCR11 R/W ----XXXXB
001A77H
001A78HDLC register 12 DLCR12 R/W ----XXXXB
001A79H
001A7AHDLC register 13 DLCR13 R/W ----XXXXB
001A7BH
001A7CHDLC register 14 DLCR14 R/W ----XXXXB
001A7DH
001A7EHDLC register 15 DLCR15 R/W ----XXXXB
001A7FH
001A80H
to
001A87HData register 0 (8 bytes) DTR0 R/W XXXXXXXXB
to
XXXXXXXXB
MB90595/595G Series
29
(Continued)
Address Register Abbreviation Access Initial Value
001A88H
to
001A8FHData register 1 (8 bytes) DTR1 R/W XXXXXXXXB
to
XXXXXXXXB
001A90H
to
001A97HData register 2 (8 bytes) DTR2 R/W XXXXXXXXB
to
XXXXXXXXB
001A98H
to
001A9FHData register 3 (8 bytes) DTR3 R/W XXXXXXXXB
to
XXXXXXXXB
001AA0H
to
001AA7HData register 4 (8 bytes) DTR4 R/W XXXXXXXXB
to
XXXXXXXXB
001AA8H
to
001AAFHData register 5 (8 bytes) DTR5 R/W XXXXXXXXB
to
XXXXXXXXB
001AB0H
to
001AB7HData register 6 (8 bytes) DTR6 R/W XXXXXXXXB
to
XXXXXXXXB
001AB8H
to
001ABFHData register 7 (8 bytes) DTR7 R/W XXXXXXXXB
to
XXXXXXXXB
001AC0H
to
001AC7HData register 8 (8 bytes) DTR8 R/W XXXXXXXXB
to
XXXXXXXXB
001AC8H
to
001ACFHData register 9 (8 bytes) DTR9 R/W XXXXXXXXB
to
XXXXXXXXB
001AD0H
to
001AD7HData register 10 (8 bytes) DTR10 R/W XXXXXXXXB
to
XXXXXXXXB
001AD8H
to
001ADFHData register 11 (8 bytes) DTR11 R/W XXXXXXXXB
to
XXXXXXXXB
001AE0H
to
001AE7HData register 12 (8 bytes) DTR12 R/W XXXXXXXXB
to
XXXXXXXXB
001AE8H
to
001AEFHData register 13 (8 bytes) DTR13 R/W XXXXXXXXB
to
XXXXXXXXB
001AF0H
to
001AF7HData register 14 (8 bytes) DTR14 R/W XXXXXXXXB
to
XXXXXXXXB
001AF8H
to
001AFFHData register 15 (8 bytes) DTR15 R/W XXXXXXXXB
to
XXXXXXXXB
MB90595/595G Series
30
■
■■
■INTERRUPT MAP
Interrupt source EI2OS
clear Interrupt vector Interrupt control register
Number Address Number Address
Reset N/A # 08 FFFFDCH—— ——
INT9 instruction N/A # 09 FFFFD8H—— ——
Exception N/A # 10 FFFFD4H—— ——
CAN RX N/A # 11 FFFFD0HICR00 0000B0H
CAN TX/NS N/A # 12 FFFFCCH
External Interrupt (INT0/INT1) *1 # 13 FFFFC8HICR01 0000B1H
Time Base Timer N/A # 14 FFFFC4H
16-bit Reload Timer 0 *1 # 15 FFFFC0HICR02 0000B2H
8/10-bit A/D Converter *1 # 16 FFFFBCH
I/O Timer N/A # 17 FFFFB8HICR03 0000B3H
External Interrupt (INT2/INT3) *1 # 18 FFFFB4H
Serial I/O *1 # 19 FFFFB0HICR04 0000B4H
External Interrupt (INT4/INT5) *1 # 20 FFFFACH
Input Capture 0 *1 # 21 FFFFA8HICR05 0000B5H
8/16-bit PPG 0/1 N/A # 22 FFFFA4H
Output Compare 0 *1 # 23 FFFFA0HICR06 0000B6H
8/16-bit PPG 2/3 N/A # 24 FFFF9CH
External Interrupt (INT6/INT7) *1 # 25 FFFF98HICR07 0000B7H
Input Capture 1 *1 # 26 FFFF94H
8/16-bit PPG 4/5 N/A # 27 FFFF90HICR08 0000B8H
Output Compare 1 *1 # 28 FFFF8CH
8/16-bit PPG 6/7 N/A # 29 FFFF88HICR09 0000B9H
Input Capture 2 *1 # 30 FFFF84H
8/16-bit PPG 8/9 N/A # 31 FFFF80HICR10 0000BAH
Output Compare 2 *1 # 32 FFFF7CH
Input Capture 3 *1 # 33 FFFF78HICR11 0000BBH
8/16-bit PPG A/B N/A # 34 FFFF74H
Output Compare 3 *1 # 35 FFFF70HICR12 0000BCH
16-bit Reload Timer 1 *1 # 36 FFFF6CH
UART 0 RX *2 # 37 FFFF68HICR13 0000BDH
UART 0 TX *1 # 38 FFFF64H
UART 1 RX *2 # 39 FFFF60HICR14 0000BEH
UART 1 TX *1 # 40 FFFF5CH
Flash Memory N/A # 41 FFFF58HICR15 0000BFH
Delayed interrupt N/A # 42 FFFF54H
MB90595/595G Series
31
*1:The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2:The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Note: • For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
• At the end of EI2OS, the EI2OS clear signal will be asserted f or all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware e v ent, the later event is lost because the flag is cleared b y the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
MB90595/595G Series
32
■
■■
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings (VSS = AVSS = 0 V)
*1:AVCC, AVRL and AVRL does not exceed VCC and AVRL does not exceed AVRH.
*2:VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the
VI rating.
*3:The maximum output current is a peak value for a corresponding pin.
*4:Average output current is an average current value observed for a 100 ms period for a corresponding pin.
*5:Total average current is an average current value observed for a 100 ms period for all corresponding pins.
Note: Average output current = operating current × operating efficiency
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min. Max.
Power supply voltage
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V VCC = AVCC *1
AVRH,
AVRL VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH/L,
AVRH ≥ AVRL *1
DVCC VSS − 0.3 VSS + 6.0 V VCC ≥ DVCC
Input voltage VIVSS − 0.3 VSS + 6.0 V *2
Output voltage VOVSS − 0.3 VSS + 6.0 V *2
Clamp Current ICLAMP −2.0 2.0 mA
“L” level max. output current IOL1 — 15 mA Normal output *3
“L” level avg. output current IOLAV1 — 4 mA Normal output, average value *4
“L” level max. output current IOL2 — 40 mA High current output *3
“L” level avg. output current IOLAV2 — 30 mA High current output, average value*4
“L” level max. overall output current ∑IOL1 — 100 mA Total normal output
“L” level max. overall output current ∑IOL2 330 mA Total high current output
“L” level avg. overall output current ∑IOLAV1 —50mA
Total normal output, average value *5
“L” level avg. overall output current ∑IOLAV2 250 mA Total high current output, average
value *5
“H” level max. output current IOH1 —−15 mA Normal output *3
“H” level avg. output current IOHAV1 —−4 mA Normal output, average value *4
“H” level max. output current IOH2 —−40 mA High current output *3
“H” level avg. output current IOHAV2 —−30 mA High current output, average value*4
“H” level max. overall output current ∑IOH1 —−100 mA Total normal output
“H” level max. overall output current ∑IOH2 —−330 mA Total high current output
“H” level avg. overall output current ∑IOHAV1 —−50 mA Total normal output, average value *5
“H” level avg. overall output current ∑IOHAV2 —−250 mA Total high current output, average
value *5
Power consumption PD— 500 mW MB90F598/F598G
400 mW MB90598
Operating temperature TA−40 +85 °C
Storage temperature TSTG −55 +150 °C
MB90595/595G Series
33
2. Recommended Conditions (VSS = AVSS = 0 V)
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to
be connected to the VCC pin must have a capacitance value higher than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min. Typ. Max.
Power supply voltage VCC
AVCC
4.5 5.0 5.5 V Under normal operation
3.0 5.5 V Maintains RAM data in stop mode
Smooth capacitor CS0.022 0.1 1.0 µF*
Operating temperature TA–40 +85 °C
C
CS
•C Pin Connection Diagram
MB90595/595G Series
34
3. DC Characteristics (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
*: Current values are tentative and subject to change without notice according to improvements in the character-
istics. The power supply current testing conditions are when using the external clock.
Parameter Sym-
bol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Input H voltage VIHS CMOS hysteresis
input pin — 0.8 VCC VCC
+0.3 V
VIHM MD input pin — VCC –
0.3 VCC
+0.3 V
Input L voltage VILS CMOS hysteresis
input pin —VSS –
0.3 0.2 VCC V
VILM MD input pin — VSS –
0.3 VSS
+0.3 V
Output H
voltage VOH1 Output pins except
P70 to P87 VCC = 4.5 V,
IOH1 = –4.0 mA VCC –
0.5 ——V
Output H
voltage VOH2 P70 to P87 VCC = 4.5 V,
IOH2 = –30.0 mA VCC –
0.5 ——V
Output L
voltage VOL1 Output pins except
P70 to P87 VCC = 4.5 V,
IOL1 = 4.0 mA ——0.4V
Output L
voltage VOL2 P70 to P87 VCC = 4.5 V,
IOL2 = 30.0 mA ——0.5V
Input leak
current IIL VCC = 5.5 V,
VSS < VI < VCC –5 — 5 µA
Power supply
current *
ICC
VCC
VCC = 5.0 V±10%,
Internal frequency:
16 MHz,
At normal operating
— 35 60 mA MB90598
—5090mAMB90F598
—4060mA
MB90F598G
ICCS
VCC = 5.0 V±10%,
Internal frequency:
16 MHz,
At sleep
—1118mA
ICTS
VCC = 5.0 V±1%,
Internal frequency:
2 MHz,
At timer mode
—0.30.6mA
ICCH VCC = 5.0 V±10%,
At stop, TA = 25°C——20µA
ICCH2
VCC = 5.0 V±10%,
At Hardware stand-
by mode,
TA = 25°C
——20µAMB90598
MB90F598
—50100µAMB90F598G
Input capacity CIN
Other than C, AVCC,
AVSS, AVRH, AVRL,
VCC, VSS, DVCC,
DVSS, P70 to P87
——515pF
P70 to P87 — — 15 30 pF
MB90595/595G Series
35
4. AC Characteristics
(1) Cloc k Timing (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
*: Frequency deviation indicates the maximum frequency diff erence from the target frequency when using a multi-
plied clock.
Example of Oscillation circuit
Parameter Symbol Pin name Value Unit Remarks
Min. Typ. Max.
Oscillation frequency fCX0, X1 3—5MHz
When using an oscillation circuit
316MHz
When using an external clock
Oscillation cycle time tCYL X0, X1 200 — 333 ns When using an oscillation circuit
62.5 333 ns When using an external clock
Frequency deviation with
PLL * ∆f———5%
Input clock pulse width PWH, PWL X0 10 — — ns Duty ratio is about 30 to 70%.
Input clock rise and fall time tCR, tCF X0 — — 5 ns When using external clock
Machine clock frequency fCP —1.5—16MHz
Machine clock cycle time tCP — 62.5 — 666 ns
+α
Central frequency f
O
−α
∆fα
fo
------ 100%×=
tCYL
PWH
tCF
PWL
tCR
0.8 VCC
0.2 VCC
X0
•Clock Timing
X0 X1
R
C1 C2
MB90595/595G Series
36
AC characteristics are set to the measured reference voltage values below.
16
5.5
4.5
3.0
1.5 8
Power supply voltage
VCC (V)
Machine clock fCP (MHz)
Guaranteed operation range
Guaranteed PLL operation range
• Guaranteed operation range
16
12
4
9
8
3 4 8 16
Machine clock
fCP (MHz)
External clock fC (MHz) *
• External clock frequency and machine clock frequency
×4×3×2×1
×1/2
(PLL off)
*: When using the oscillation circuit, the maximum oscillation clock frequency is 5 MHz.
• Input signal waveform
Hysteresis Input Pin
0.8 VCC
0.2 VCC
• Output signal waveform
Output Pin
2.4 V
0.8 V
MB90595/595G Series
37
(2) Reset and Hardware Standby Input (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
*1:“tcp” represents one cycle time of the machine clock.
No reset can fully initialize the Flash Memory if it is performing the automatic algorithm.
*2:Oscillation time of oscillator is time that the amplitude reached the 90%.
In the crystal oscillator , the oscillation time is between sev eral ms to tens of ms . In FAR / ceramic oscillator, the
oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Parameter Symbol Pin name Value Unit Remarks
Min. Max.
Reset input time tRSTL RST 16 tCP*1— ns Under normal operation
Oscillation time of
oscillator*2 + 16 tCP*1— ms In stop mode
Hardware standby input time tHSTL HST 16 tCP*1— ns Under normal operation
Oscillation time of
oscillator*2 + 16 tCP*1— ms In stop mode
0.2 VCC
RST
HST
tRSTL, tHSTL
0.2 VCC
Under Normal Operation
tRSTL, tHSTL
0.2VCC 0.2VCC
RST
HST
X0
16 tCP
Internal operation clock
Internal reset
Oscillation time of
oscillator Oscillation setting time
Instruction execution
90% of
amplitude
In Stop Mode
MB90595/595G Series
38
(3)Power On Reset (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
*: VCC must be kept lower than 0.2 V before power-on.
Note: • The above values are used for creating a power-on reset.
• Some registers in the de vice are initializ ed only upon a po wer-on reset. To initialize these register, turn on
the power supply using the above values.
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Power on rise time tRVCC —0.05 30 ms *
Power off time tOFF VCC 50 — ms Due to repetitive operation
tR
2.7 V
0.2 V
VCC
0.2 V0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuations as shown below.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1
V or fewer per second, however, you can use the PLL clock.
VCC
VSS
3 V
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
MB90595/595G Series
39
(4) UART0/1, Serial I/O Timing (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
Note: 1.AC characteristic in CLK synchronized mode.
2. CL is load capacity value of pins when testing.
3. tCP is the machine cycle (Unit: ns).
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC SCK0 to SCK2
Internal clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
8 tCP —ns
SCK ↓ ⇒ SOT delay time tSLOV SCK0 to SCK2,
SOT0 to SOT2 –80 80 ns
Valid SIN ⇒ SCK ↑tIVSH SCK0 to SCK2,
SIN0 to SIN2 100 — ns
SCK ↑ ⇒ Valid SIN hold time tSHIX SCK0 to SCK2,
SIN0 to SIN2 60 — ns
Serial clock “H” pulse width tSHSL SCK0 to SCK2
External clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
4 tCP —ns
Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCP —ns
SCK ↓ ⇒ SOT delay time tSLOV SCK0 to SCK2,
SOT0 to SOT2 — 150 ns
Valid SIN ⇒ SCK ↑tIVSH SCK0 to SCK2,
SIN0 to SIN2 60 — ns
SCK ↑ ⇒ Valid SIN hold time tSHIX SCK0 to SCK2,
SIN0 to SIN2 60 — ns
SCK 2.4 V
tSCYC
0.8 V
SOT 0.8 V
2.4 V
0.8 V
tSLOV
SIN 0.2 VCC
0.8 VCC
tIVSH
0.2 VCC
0.8 VCC
tSHIX
• Internal Shift Clock Mode
MB90595/595G Series
40
(5) Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTIWH TIN0, TIN1 —4 t
CP —ns
tTIWL IN0 to IN3
SCK 0.8 VCC
tSLSH
0.2 VCC
SOT 0.8 V
2.4 V
tSLOV
SIN 0.2 VCC
0.8 VCC
tIVSH
0.2 VCC
0.8 VCC
tSHIX
0.8 VCC
0.2 VCC
tSHSL
• External Shift Clock Mode
0.2 VCC
0.8 VCC
tTIWH
0.2 VCC
0.8 VCC
tTIWL
•Timer Input Timing
MB90595/595G Series
41
(6) Trigger Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
(7) Slew Rate High Current Outputs (VCC = 5.0 V±10 %, VSS = AVSS = 0V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Max.
Input pulse width tTRGH
tTRGL INT0 to
INT7, ADTG —5 tCP — ns Under normal operation
1—µs In stop mode
Parameter Symbol Pin name Condition Value Unit Remarks
Min. Typ. Max.
Output Rise/Fall time tR2
tF2 Port P70 to P77,
Port P80 to P87 — 15 40 150 ns
0.2 VCC
0.8 VCC
tTRGH
0.2 VCC
0.8 VCC
tTRGL
• Trigger Input Timing
• Slew Rate Output Timing
VH
VL
tR2
VH
VL
tF2
VH = VOL2 + 0.1 × (VOH2 − VOL2)
VL = VOL2 + 0.9 × (VOH2 − VOL2)
MB90595/595G Series
42
5. A/D Converter (VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0 V,3.0 V ≤ AVRH − AVRL, TA = −40 °C to +85 °C)
*: When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
Parameter Symbol Pin name Value Unit Remarks
Min. Typ. Max.
Resolution — — — 10 bit
Conversion error — — — — ±5.0 LSB
Nonlinearity error — — — — ±2.5 LSB
Differential linearity error — — — — ±1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVRL − 3.5 AVRL +0.5 AVRL + 4.5 mV
Full scale transition voltage VFST AN0 to AN7 AVRH − 6.5 AVRH − 1.5 AVRH + 1.5 mV
Conversion time — — — 352tCP —ns
Sampling time — — — 64tCP —ns
Analog port input current IAIN AN0 to AN7 −10 — 10 µA
Analog input voltage range VAIN AN0 to AN7 AVRL — AVRH V
Reference voltage range —AVRH
AVRL + 2.7 —AVCC V
— AVRL 0 — AVRH − 2.7 V
Power supply current IAAVCC —5—mA
IAH AVCC ——5µA*
Reference voltage current IRAVRH — 400 600 µA
MB90V595
MB90V595G
MB90F598
MB90F598G
— 140 600 µA MB90598
IRH AVRH — — 5 µA*
Offset between input chan-
nels — AN0 to AN7 — — 4 LSB
MB90595/595G Series
43
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter
Linearity error: The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00
0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual
conversion characteristics
Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value
Total error :The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
Total error
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH
Actual conversion
value
Digital output
VNT
(measured value)
0.5 LSB
Actual conversion
characteristics
Theoretical
characteristics
0.5 LSB
{1 LSB × (N – 1) + 0.5 LSB}
[V]
AVRH – AVRL
1024
1 LSB = (Theoretical value)
VOT (Theoretical value) = AVRL + 0.5 LSB[V]
VFST (Theoretical value) = AVRH – 1.5 LSB[V]
Total error for digital output N [LSB]
VNT – {1 LSB × (N – 1) + 0.5 LSB}
1 LSB
=
VNT: Voltage at a transition of digital output from (N – 1) to N
MB90595/595G Series
44
(Continued)
7. Notes on Using A/D Converter
Select the output impedance v alue f or the e xternal circuit of analog input according to the follo wing conditions, :
• Output impedance values of the external circuit of 15 kΩ or lower are recommended.
• When capacitors are connected to external pins, the capacitance of several thousand times the internal
capacitor v alue is recommended to minimized the eff ect of v oltage distribution between the e xternal capacitor
and internal capacitor.
When the output impedance of the external circuit is too high, the sampling period for analog voltages ma y not
be sufficient (sampling period = 4.00 µs @machine clock of 16 MHz).
•Error
The smaller the | AVRH − AVRL |, the greater the error would become relatively.
Linearity error
3FF
3FE
3FD
004
003
002
001
Analog inputAVRL AVRH Analog inputAVRL AVRH
Actual conversion
characteristics
VOT (measured value)
VFST
(measured value)
Actual conversion
value
VNT
{1 LSB × (N – 1)+ VOT}
Theoretical
characteristics
Digital output
Digital output
Differential linearity error
Theoretical characteristics
V(N + 1)T
(measured value)
Actual conversion
value
VNT (measured value)
Actual conversion value
Linearity error of
digital output N
VOT: Voltage at transition of digital output from “000H” to “001H”
VFST: Voltage at transition of digital output from “3FEH” to “3FFH”
[LSB]
VNT – {1 LSB × (N – 1) + VOT}
1 LSB
=
[V]
VFST – VOT
1022
=
1 LSB
– 1 LSB [LSB]
V(N + 1)T – VNT
1 LSB
=
Differential linearity error
of digital N
N + 1
N
N – 1
N – 2
• Equipment of analog input circuit model
Comparator
Analog input
30 pF Max.
3.2 kΩ Max.
MB90595/595G Series
45
■
■■
■ORDERING INFORMATION
Part number Package Remarks
MB90598PF
MB90F598PF
MB90F598GPF
100-pin Plastic QFP
(FPT-100P-M06)
MB90V595CR
MB90V595GCR 256-pin Ceramic PGA
(PGA-256C-A01) For evaluation
MB90595/595G Series
46
■
■■
■PACKAGE DIMENSION
100-pin plastic QFP
(FPT-100P-M06) Note: This package dimension is for the reference. Please consult separately about
a formal version.
Dimensions in mm (inches)
C
2000 FUJITSU LIMITED F100008-3C-3
"A"
"B"
0.53(.021)MAX
0.18(.007)MAX
Details of "A" part
0 10°
Details of "B" part
12.35(.486)
REF 16.30±0.40
(.642±.016)
0.05(.002)MIN
(STAND OFF)
0.15±0.05(.006±.002)
INDEX
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
17.90±0.4014.00±0.20
(.551±.008) (.705±.016)
0.13(.005) M
18.85(.742)REF
22.30±0.40(.878±.016)
130
31
50
5180
81
100
0.25(.010)
0.30(.012)
0.65(.0256)TYP 0.30±0.10
(.012±.004)
LEAD No.
0.80±0.20
(.031±.008)
3.35(.132)MAX
(Mounting height)
0.10(.004)
MB90595/595G Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTR ONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTR ONICS ASIA PTE. LTD .
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTR ONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0101
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
