18-Bit, 1.33 MSPS PulSAR 10.5 mW
ADC in MSOP/LFCSP
Data Sheet AD7984
Rev. B Document Feedback
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FEATURES
18-bit resolution with no missing codes
Throughput: 1.33 MSPS
Low power dissipation: 10.5 mW at 1.33 MSPS
INL: ±2.25 LSB maximum
Dynamic range: 99.7 dB typical
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.9 V to 5.0 V
Allows use of any input range
Easy to drive with the ADA4941
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Proprietary serial interface
SPI/QSPI/MICROWIRE™/DSP compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm
LFCSP, SOT-23 size
APPLICATIONS
Battery-powered equipment
Data acquisition systems
Medical instruments
Seismic data acquisition systems
APPLICATION DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD79841 is an 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 18-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, the AD7984 samples the voltage difference between
the IN+ and IN− pins. The voltages on these pins usually swing
in opposite phases between 0 V and VREF. The reference voltage,
REF, is applied externally and can be set independent of the
supply voltage, VDD.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD7984 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
1 Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 14-/16-/18-Bit PulSAR® ADC
Type 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS ADC Driver
14-Bit AD7940 AD79421 AD79461
16-Bit AD7680 AD76851 AD76861 AD79801 ADA4941-x
AD7683 AD76871 AD76881 AD79831 ADA4841-x
AD7684 AD7694 AD76931
AD7988-1 AD7988-5
18-Bit AD7989-1 AD76911 AD76901 AD79821 ADA4941-x
AD7989-5 AD79841 ADA4841-x
1 Pin-for-pin compatible.
AD7984
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO 5V
ADA4941
3- OR 4-WIRE
INTERFACE
(SPI, CS
DAISY CHAIN)
2.9V TO 5V 2.5V
±
10V, ±5V, ..
0
6973-001
AD7984 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Application Diagram ........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
Circuit Information .................................................................... 12
Converter Operation .................................................................. 12
Typical Connection Diagram.................................................... 13
Analog Inputs .............................................................................. 14
Driver Amplifier Choice ........................................................... 14
Single-to-Differential Driver .................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply ............................................................................... 15
Digital Interface .......................................................................... 16
CS Mode, 3-Wire Without Busy Indicator ............................. 17
CS Mode, 3-Wire with Busy Indicator .................................... 18
CS Mode, 4-Wire Without Busy Indicator ............................. 19
CS Mode, 4-Wire with Busy Indicator .................................... 20
Chain Mode Without Busy Indicator ...................................... 21
Chain Mode with Busy Indicator ............................................. 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7984 Performance ...................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/14—Rev. A to Rev. B
Changed QFN (LFCSP) to LFCSP .............................. Throughout
Changes to Features Section and Table 1 ...................................... 1
Added Patent Note, Note 1 .............................................................. 1
Changes to Power Supply Section ................................................ 15
Changes to Evaluating the AD7984 Performance Section ........ 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
8/10—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
11/07—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet AD7984
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, T A = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range IN+ − IN− −VREF +VREF V
Absolute Input Voltage
IN+, IN−
−0.1
V
REF
+ 0.1
V
Common-Mode Input Range IN+, IN− VREF × 0.475 VREF × 0.5 VREF × 0.525 V
Analog Input CMRR fIN = 450 kHz 67 dB1
Leakage Current at 25°C Acquisition phase 200 nA
Input Impedance See the Analog Inputs section
ACCURACY
No Missing Codes 18 Bits
Differential Linearity Error −1 +1.5 LSB2
Integral Linearity Error −2.25 +2.25 LSB2
Transition Noise
0.95
LSB
2
Gain Error, TMIN to TMAX3 −0.075 ±0.022 +0.075 % of FS
Gain Error Temperature Drift −0.6 ppm/°C
Zero Error, TMIN to TMAX3 −700 ±100 +700 µV
Zero Temperature Drift 0.3 ppm/°C
Power Supply Sensitivity
VDD = 2.5 V ± 5%
90
dB
1
THROUGHPUT
Conversion Rate 0 1.33 MSPS
Transient Response Full-scale step 290 ns
AC ACCURACY
Dynamic Range VREF = 5 V 99.7 dB1
Signal-to-Noise, SNR
f
IN
= 1 kHz, V
REF
= 5 V, T
A
= 25°C
96.5
98.5
dB
1
Spurious-Free Dynamic Range, SFDR fIN = 10 kHz 112.5 dB1
Total Harmonic Distortion4, THD fIN = 10 kHz −110.5 dB1
Signal-to-(Noise + Distortion), SINAD fIN = 10 kHz, VREF = 5 V, TA = 25°C 98 dB1
1 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
2 LSB means least significant bit. With the ±5 V input range, one LSB is 38.15 µV.
3 See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4 Tested fully in production at fIN = 1 kHz.
Rev. B | Page 3 of 24
AD7984 Data Sheet
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, T A = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 2.9 5.1 V
Load Current 1.33 MSPS 520 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 10 MHz
Aperture Delay 2 ns
DIGITAL INPUTS
Logic Levels
VIL VIO > 3 V –0.3 +0.3 × VIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIL VIO ≤ 3 V –0.3 +0.1 × VIO V
VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 18 bits, twos complement
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = +500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD 2.375 2.5 2.625 V
VIO Specified performance 2.3 5.5 V
VIO Range 1.8 5.5 V
Standby Current1, 2 VDD and VIO = 2.5 V 1.1 mA
Power Dissipation
10.5
14
mW
Energy per Conversion 7.9 nJ/sample
TEMPERATURE RANGE3
Specified Performance TMIN to TMAX −40 +85 °C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Rev. B | Page 4 of 24
Data Sheet AD7984
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 300 500 ns
Acquisition Time tACQ 250 ns
Time Between Conversions tCYC 750 ns
CNV Pulse Width (CS Mode) tCNVH 10 ns
SCK Period (CS Mode) tSCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns
SCK Period (Chain Mode) tSCK
VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns
SCK Low Time tSCKL 4.5 ns
SCK High Time tSCKH 4.5 ns
SCK Falling Edge to Data Remains Valid
t
HSDO
3
ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 3 V 10 ns
VIO Above 2.3 V 15 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns
SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns
SDI Valid Hold Time from CNV Rising Edge (
CS
Mode)
t
HSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns
SDI High to SDO High (Chain Mode with Busy Indicator)
t
DSDOSDI
15
ns
1 See Figure 2 and Figure 3 for load conditions.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
500µA IOL
500µA IOH
1.4V
TO SDO CL
20pF
06973-002
X% VIO
1
Y% VIO
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXI MUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
06973-003
Rev. B | Page 5 of 24
AD7984 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+, IN− to GND1 −0.3 V to VREF + 0.3 V
or ±130 mA
Supply Voltage
REF, VIO to GND −0.3 V to +6.0 V
VDD to GND −0.3 V to +3.0 V
VDD to VIO
+3 V to −6 V
Digital Inputs to GND
−0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead LFCSP 48.7°C/W
θJC Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead LFCSP 2.96°C/W
Lead Temperatures
Vapor Phase (60 sec)
215°C
Infrared (15 sec) 220°C
1 See the Analog Inputs section for an explanation of IN+ and IN−.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 6 of 24
Data Sheet AD7984
Rev. B | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 10-Lead MSOP Pin Configuration Figure 5. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 REF AI
Reference Input Voltage. The REF range is 2.9 V to 5.1 V. This pin is referred to the GND pin and
should be decoupled closely to the GND pin with a 10 μF capacitor.
2 VDD P Power Supply.
3 IN+ AI Differential Positive Analog Input.
4 IN− AI Differential Negative Analog Input.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its rising edge, it initiates the conversions
and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The
digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
REF 1
VDD 2
IN+ 3
IN– 4
GND 5
VIO10
SDI9
SCK
8
SDO7
CNV
6
AD7984
TOP VIEW
(Not to Scale)
06973-004
REF
VDD
IN+
IN–
GND
VIO
SDI
SCK
SDO
CNV
06973-005
1
2
3
4
10
9
8
7
56
*EXPOSED PADDLE CAN BE CONNECTED
TO GROUND.
AD7984
(EXPOSED
PAD)*
AD7984 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V.
Figure 6. Integral Nonlinearity vs. Code
Figure 7. Histogram of a DC Input at the Code Center
Figure 8. FFT Plot
Figure 9. Differential Nonlinearity vs. Code
Figure 10. Histogram of a DC Input at the Code Transition
Figure 11. SNR vs. Input Level
2.0
–2.0 0262144
06973-032
CODE
INL (LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
65536 131072 196608
POSITIVE INL: +1.07LSB
NEGATI V E INL: –0.73L S B
60k
01C
06973-041
CODE IN HEX
COUNTS
50k
40k
30k
20k
10k
1D 1E
0 0 7 6 0 0
1F
326
20 21 22 23 24 25
326
26 27 28
5992
32350
55354
31003
5708
0
–180 0
06973-033
FREQUENCY ( kHz )
AMPLITUDE (dB of Full Scale)
–20
–40
–60
–80
–100
–120
–140
–160
100 200 300 400 500 600
f
S
= 1.33M S P S
f
IN
= 10kHz
SNR = 98. 2dB
THD = –110.6d B
SFDR = 112.5d B
SINAD = 98.0d B
2.0
–2.0 0262144
06973-038
CODE
DNL ( LSB)
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
65536 131072 196608
POSITIVE DNL: +0.63LSB
NEGATI V E DNL: –0. 34LSB
60k
01D
06973-042
CODE IN HEX
COUNTS
50k
40k
30k
20k
10k
1E 1F
0 0 2
20
69
21 22 23 24 25 26 27
37
28 29
00
1801 1378
16593 14653
48273 48266
100
90
–10 0
06973-039
INPUT LEVEL (dB of Full Scale)
SNR (dB)
99
98
97
96
95
94
93
92
91
–9 –8 –7 –6 –5 –4 –3 –2 –1
Rev. B | Page 8 of 24
Data Sheet AD7984
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 13. SNR vs. Temperature
Figure 14. SINAD vs. Frequency
Figure 15. THD vs. Reference Voltage
Figure 16. THD vs. Temperature
Figure 17. THD vs. Frequency
100
80
2.5 5.5
REFERENCE VOLTAGE (V)
SNR, S INAD (dB)
95
90
85
18
14
ENOB ( Bits)
17
16
15
3.0 3.5 4.0 4.5 5.0
06973-043
ENOB
SNR
SINAD
100
90
–55 105
06973-044
TEMPERATURE (°C)
SNR (dB)
98
96
94
92
–35 –15 525 45 65 85
100
80 1000
06973-034
FREQUENCY ( kHz )
SINAD ( dB)
110 100
95
90
85
–100
–120
2.5 5.5
REFERENCE VOLTAGE (V)
THD ( dB)
–105
–110
–115
3.0 3.5 4.0 4.5 5.0
06973-045
–100
–120
–55 125
06973-046
TEMPERATURE (°C)
THD ( dB)
–105
–110
–115
–35 –15 525 45 65 85 105
–80
–115 1000
06973-040
FREQUENCY ( kHz )
THD ( dB)
110 100
–85
–90
–95
–100
–105
–110
Rev. B | Page 9 of 24
AD7984 Data Sheet
Figure 18. Operating Currents vs. Supply
Figure 19. Standby Currents vs. Temperature
Figure 20. Operating Currents vs. Temperature
2.5
0
2.375 2.625
06973-035
V
DD
VOLTAGE (V)
OPE RATI NG CURRENT S ( mA)
2.0
1.5
1.0
0.5
2.425 2.475 2.525 2.575
I
VDD
I
REF
I
VIO
1.5
0.5
–55 125
06973-036
TEMPERATURE (°C)
STANDBY CURRE NTS ( mA)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–35 –15 525 45 65 85 105
I
VDD
+ I
VIO
2.5
0
–55 125
06973-037
TEMPERATURE (°C)
OPE RATI NG CURRENT S ( mA)
–35 –15 525 45 65 85 105
2.0
1.5
1.0
0.5
I
VDD
I
REF
I
VIO
Rev. B | Page 10 of 24
Data Sheet AD7984
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the ±5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below
the nominal full scale (+4.999943 V for the ±5 V range). The
gain error is the deviation of the difference between the actual
level of the last transition and the actual level of the first
transition from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels. It is
measured with a signal at −60 dBF so that it includes all noise
sources and DNL artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value of SINAD is expressed in decibels.
Aperture Delay
Aperture delay is the measurement of the acquisition
performance and is the time between the rising edge of the
CNV input and when the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. B | Page 11 of 24
AD7984 Data Sheet
THEORY OF OPERATION
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7984 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture and is
capable of converting 1,330,000 samples per second (1.33 MSPS).
The AD7984 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7984 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead LFCSP
that allows space savings and flexible configurations.
It is pin-for-pin-compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7984 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7984 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
COMPCONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
CC2C
65,536C 4C
131,072C
LSB SW+
MSB
LSB SW–
MSB
CC
2C
65,536C 4C
131,072C
IN+
REF
GND
IN–
06973-011
Rev. B | Page 12 of 24
Data Sheet AD7984
Rev. B | Page 13 of 24
Transfer Functions
The ideal transfer characteristic for the AD7984 is shown in
Figure 22 and Table 7.
Figure 22. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output
Code (Hex)
FSR − 1 LSB +4.999962 V 0x1FFFF1
Midscale + 1 LSB +38.15 μV 0x00001
Midscale 0 V 0x00000
Midscale − 1 LSB −38.15 μV 0x3FFFF
−FSR + 1 LSB −4.999962 V 0x20001
−FSR −5 V 0x200002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 23 shows an example of the recommended connection
diagram for the AD7984 when multiple supplies are available.
Figure 23. Typical Application Diagram with Multiple Supplies
100 ... 000
100 ... 001
100 ... 010
011 ... 101
011 ... 110
011 ... 111
ADC CODE (TWOS COMPLEMENT)
ANALOG INPUT
+FSR – 1.5 LSB
+FSR – 1 LSB
–FSR + 1 LSB
–FSR
–FSR + 0.5 LSB
0
6973-012
2.7nF
15Ω
V–
0 TO VREF
V+
4
2.7nF
15Ω
V–
V
REF TO 0
V+
4
10µF
2
REF
1
REF VDD VIO
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD7984
100nF
100nF
3-WIRE INTERFACE
2.5V
1.8V TO 5V
V+
ADA4841
2, 3
NOTES
1
SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2
C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE RECOMMENDED LAYOUT IN FIGURE 40 AND FIGURE 41.
3
SEE DRIVER AMPLIFIER CHOICE SECTION.
4
OPTIONAL FILTER. SEE ANALOG INPUTS SECTION.
06973-013
AD7984 Data Sheet
ANALOG INPUTS
Figure 24 shows an equivalent circuit of the input structure of
the AD7984.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the reference input
voltage (REF) by more than 0.3 V. If the analog input signal
exceeds this level, the diodes become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 130 mA maximum. However, if the supplies of the
input buffer (for example, the supplies of the ADA4841 in
Figure 23) are different from those of REF, the analog input
signal may eventually exceed the supply rails by more than
0.3 V. In such a case (for example, an input buffer with a short-
circuit), the current limitation can be used to protect the part.
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
Figure 25. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connection
of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component composed of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor.
During the sampling phase, where the switches are closed, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter that reduces undesirable aliasing effects and
limits noise.
When the source impedance of the driving circuit is low, the
AD7984 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The
dc performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7984 is easy to drive, the driver amplifier must
meet the following requirements:
• The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7984. The noise from the driver is
filtered by the AD7984 analog input circuit’s 1-pole, low-
pass filter made by RIN and CIN or by the external filter, if
one is used. Because the typical noise of the AD7984 is
36.24 µV rms, the SNR degradation due to the amplifier is
+
=
−22
)(
2
π
.2463
36.24
log20
N
3dB
LOSS
Nef
SNR
where:
f–3dB is the input bandwidth, in megahertz, of the AD7984
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp, in
nV/√Hz.
• For ac applications, the driver should have a THD perfor-
mance commensurate with the AD7984.
• For multichannel multiplexed applications, the driver
amplifier and the AD7984 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit level
(0.0004%, 4 ppm). In the data sheet of the amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
may differ significantly from the settling time at an 18-bit
level and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4941-x Very low noise, low power single-to-differential
ADA4841-x Very low noise, small, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8655 5 V single supply, low noise
AD8605, AD8615 5 V single supply, low power
CPIN
REF
RIN CIN
D1
D2
IN+ OR I N–
GND
06973-014
90
85
80
75
70
65
60110 100 1000 10000
FREQUENCY ( kHz )
CMRR (dB)
06973-015
Rev. B | Page 14 of 24
Data Sheet AD7984
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either
bipolar or unipolar, the ADA4941-x single-ended-to-
differential driver allows for a differential input into the part.
The schematic is shown in Figure 26.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the ±10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
R3 and R4 set the common mode on the IN− input, and R5 and R6
set the common mode on the IN+ input of the ADC. The common
mode should be close to VREF/2. For example, for the ±10 V range
with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ,
and R6 = 9.76 kΩ.
Figure 26. Single-Ended-to-Differential Driver Circuit
VOLTAGE REFERENCE INPUT
The AD7984 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 µF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference-decoupling capacitor with values as small
as 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
POWER SUPPLY
The AD7984 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.5 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7984 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 27.
Figure 27. PSRR vs. Frequency
15Ω
15Ω
10µF
R1
100nF
+2.5V
+5V REF
+5.2V
–0.2V
CF
R2
R4
R6
±10V,
±5V, ..
R3
R5
REF VDD
GND
IN+
IN–
AD7984
2.7nF
2.7nF
ADA4941
IN
FB
OUTP
OUTN
REF
100nF
06973-016
95
90
85
80
75
70
65
60
PSRR (dB)
110 100 1000
FREQUENCY ( kHz )
06973-017
Rev. B | Page 15 of 24
AD7984 Data Sheet
DIGITAL INTERFACE
Although the AD7984 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7984 is compatible with SPI, QSPI™,
digital hosts, and DSPs. In this mode, the AD7984 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
When in chain mode, the AD7984 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
In either mode, the AD7984 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.
The busy indicator feature is enabled
• In CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 31 and Figure 35).
• In chain mode if SCK is high during the CNV rising edge
(see Figure 39).
Rev. B | Page 16 of 24
Data Sheet AD7984
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 28, and the corresponding timing is given in
Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7984 enters the acquisition phase and goes
into standby mode. When CNV goes low, the MSB is output
onto SDO. The remaining data bits are clocked by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the 18th SCK falling edge or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
Figure 28. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
Figure 29. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
VIO
06973-018
SDO D17 D16 D15 D1 D0
t
DIS
SCK 123 16 17 18
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
06973-019
Rev. B | Page 17 of 24
AD7984 Data Sheet
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 30, and the
corresponding timing is given in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7984 then
enters the acquisition phase and goes into standby mode. The
data bits are then clocked out, MSB first, by subsequent SCK
falling edges. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided it has
an acceptable hold time. After the optional 19th SCK falling edge
or when CNV goes high (whichever occurs first), SDO returns
to high impedance.
If multiple AD7984s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
Figure 30. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High)
Figure 31. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
VIO
IRQ
VIO
47kΩ
06973-020
SDO D17 D16 D1 D0
t
DIS
SCK 123 17 18 19
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSIONACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
06973-021
Rev. B | Page 18 of 24
Data Sheet AD7984
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7984s are connected
to an SPI-compatible digital host.
A connection diagram example using two AD7984s is shown in
Figure 32, and the corresponding timing is given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7984
enters the acquisition phase and goes into standby mode. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be
used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided it has an acceptable
hold time. After the 18th SCK falling edge or when SDI goes
high (whichever occurs first), SDO returns to high impedance
and another AD7984 can be read.
Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
CS1
CS2
AD7984
SDI SDO
CNV
SCK
06973-022
SDO D17 D16 D15 D1 D0
t
DIS
SCK 1 2 334 35 36
t
HSDO
t
DSDO
t
EN
CONVERSIONACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI(CS1)
CNV
t
SSDICNV
t
HSDICNV
D1
16 17
t
SCK
t
SCKL
t
SCKH
D0 D17 D16
19 2018
SDI(CS2)
06973-023
Rev. B | Page 19 of 24
AD7984 Data Sheet
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7984 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This independence is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7984
then enters the acquisition phase and goes into standby mode.
The data bits are then clocked out, MSB first, by subsequent
SCK falling edges. The data is valid on both SCK edges. Although
the rising edge can be used to capture the data, a digital host
using the SCK falling edge allows a faster reading rate, provided
it has an acceptable hold time. After the optional 19th SCK
falling edge or SDI going high (whichever occurs first), SDO
returns to high impedance.
Figure 34. CS Mode, 4-Wire with Busy Indicator Connection Diagram
Figure 35. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
AD7984
SDI SDO
CNV
SCK
CONVERT
DATA I N
CLK
DIGITAL HOST
IRQ
VIO
47kΩ
CS1
06973-024
SDO D17 D16 D1 D0
tDIS
SCK 12 3 17 18 19
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
06973-025
Rev. B | Page 20 of 24
Data Sheet AD7984
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7984s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7984s is shown in
Figure 36, and the corresponding timing is given in Figure 37.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7984 enters the acquisition phase and
goes into standby mode. The remaining data bits stored in the
internal shift register are clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 18 × N clocks are
required to read back the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge will allow a faster
reading rate and consequently more AD7984s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
Figure 36. Chain Mode Without Busy Indicator Connection Diagram
Figure 37. Chain Mode Without Busy Indicator Serial Interface Timing
CONVERT
DATA I N
CLK
DIGITAL HOST
AD7984
SDI SDO
CNV
B
SCK
AD7984
SDI SDO
CNV
A
SCK
06973-026
SDO
A
= SDI
B
D
A
17 D
A
16 D
A
15
SCK 1 2 3 34 35 36
t
SSDISCK
t
HSDISCK
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV
D
A
1
16 17
t
SCK
t
SCKL
t
SCKH
D
A
0
19 2018
SDI
A
= 0
SDO
B
D
B
17 D
B
16 D
B
15 D
A
1
D
B
1D
B
0 D
A
17 D
A
16
t
HSDO
t
DSDO
t
SSCKCNV
t
HSCKCNV
D
A
0
06973-027
Rev. B | Page 21 of 24
AD7984 Data Sheet
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7984s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7984s is shown
in Figure 38, and the corresponding timing is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7984 ADC labeled C in Figure 38) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7984 then enters the acquisition phase and goes into standby
mode. The data bits stored in the internal shift register are clocked
out, MSB first, by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 18 × N + 1 clocks are required to read back the N
ADCs. Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7984s in the chain, provided
the digital host has an acceptable hold time.
Figure 38. Chain Mode with Busy Indicator Connection Diagram
Figure 39. Chain Mode with Busy Indicator Serial Interface Timing
CONVERT
DATA I N
CLK
DIGITAL HOST
AD7984
SDI SDO
CNV
C
SCK
AD7984
SDI SDO
CNV
A
SCK IRQ
AD7984
SDI SDO
CNV
B
SCK
06973-028
SDO
A
= SDI
B
D
A
17 D
A
16 D
A
15
SCK 1 2 3 39 53 54
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
CNV = SDI
A
D
A
1
417
t
SCK
t
SCKH
t
SCKL
D
A
0
19 3818
SDO
B
= SDI
C
D
B
17 D
B
16 D
B
15 D
A
1D
B
1 D
B
0 D
A
17 D
A
16
55
t
SSDISCK
t
HSDISCK
t
HSDO
t
DSDO
SDO
C
D
C
17 D
C
16 D
C
15 D
A
1 D
A
0D
C
1 D
C
0 D
A
16
21 35 3620 37
D
B
1 D
B
0 D
A
17D
B
17 D
B
16
t
DSDOSDI
t
SSCKCNV
t
HSCKCNV
D
A
0
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
t
DSDOSDI
06973-029
Rev. B | Page 22 of 24
Data Sheet AD7984
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7984
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7984, with its analog signals on the left side
and its digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7984 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7984.
The AD7984 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7984
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7984 and connected using short, wide
traces to provide low impedance paths and to reduce the effect
of glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 40 and Figure 41.
EVALUATING THE AD7984 PERFORMANCE
Other recommended layouts for the AD7984 are outlined
in the documentation of the evaluation board for the AD7984
(EVAL-AD7984SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Figure 40. Example Layout of the AD7984 (Top Layer)
Figure 41. Example Layout of the AD7984 (Bottom Layer)
AD7984
06973-030
06973-031
Rev. B | Page 23 of 24
AD7984 Data Sheet
OUTLINE DIMENSIONS
Figure 42. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Figure 43. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option Ordering Quantity Branding
AD7984BRMZ −40°C to +85°C 10-Lead MSOP RM-10 Tube, 50 C60
AD7984BRMZ-RL7 −40°C to +85°C 10-Lead MSOP RM-10 Reel, 1,000 C60
AD7984BCPZ-RL7 −40°C to +85°C 10-Lead LFCSP_WD CP-10-9 Reel, 1,500 C60
AD7984BCPZ-RL −40°C to +85°C 10-Lead LFCSP_WD CP-10-9 Reel, 5,000 C60
EVAL-AD7984SDZ Evaluation Board
EVAL-SDP-CB1Z Evaluation Board
1 Z = RoHS compliant part.
2 The EVAL-AD7984SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
COMPLIANTTO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50BSC
0.30
0.15
1.10MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PI N 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
3.10
3.00 S Q
2.90
PI N 1
INDICATOR
(R 0. 15)
FOR PRO P E R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
02-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 M IN
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registered trademarks are the property of their respective owners.
D06973-0-7/14(B)
Rev. B | Page 24 of 24