LTC2353-18 Buffered Dual, 18-Bit, 550ksps/Ch Differential 10.24V ADC with 30VP-P Common Mode Range DESCRIPTION FEATURES Simultaneous Sampling of 2 Buffered Channels nn 550ksps per Channel Throughput nn 500pA/12nA Max Input Leakage at 85C/125C nn 3.5LSB INL (Maximum, 10.24V Range) nn Guaranteed 18-Bit, No Missing Codes nn Differential, Wide Common Mode Range Inputs nn Per-Channel SoftSpan Input Ranges: nn 10.24V, 0V to 10.24V, 5.12V, 0V to 5.12V nn 12.5V, 0V to 12.5V, 6.25V, 0V to 6.25V nn 96.4dB Single-Conversion SNR (Typical) nn -110dB THD (Typical) at f = 2kHz IN nn 124dB CMRR (Typical) at f = 200Hz IN nn Rail-to-Rail Input Overdrive Tolerance nn Integrated Reference and Buffer (4.096V) nn SPI CMOS (1.8V to 5V) and LVDS Serial I/O nn Internal Conversion Clock, No Cycle Latency nn 162mW Power Dissipation (Typical) nn 48-Lead (7mm x 7mm) LQFP Package The LTC(R)2353-18 is an 18-bit, low noise 2-channel simultaneous sampling successive approximation register (SAR) ADC with buffered differential, wide common mode range picoamp inputs. Operating from a 5V low voltage supply, flexible high voltage supplies, and using the internal reference and buffer, both channels of this SoftSpanTM ADC can be independently configured on a conversion-by-conversion basis to accept 10.24V, 0V to 10.24V, 5.12V, or 0V to 5.12V signals. One channel may also be disabled to increase throughput on the other channel. nn The integrated picoamp-input analog buffers, wide input common mode range and 124dB CMRR of the LTC2353-18 allow the ADC to directly digitize a variety of signals using minimal board space and power. This input signal flexibility, combined with 3.5LSB INL, no missing codes at 18 bits, and 96.4dB SNR, makes the LTC2353-18 an ideal choice for many high voltage applications requiring wide dynamic range. APPLICATIONS The LTC2353-18 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces. Either one or two lanes of data output may be employed in CMOS mode, allowing the user to optimize bus width and throughput. Programmable Logic Controllers Industrial Process Control nn Power Line Monitoring nn Test and Measurement nn nn All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235. TYPICAL APPLICATION 15V 0.1F 5V 0.1F 1.8V TO 5V 0.1F 2.2F Integral Nonlinearity vs Output Code and Channel CMOS OR LVDS I/O INTERFACE FULLY DIFFERENTIAL +5V 0V 0V -10V -5V TRUE BIPOLAR +10V +10V 0V 0V -10V -10V BUFFERS IN0+ IN0- VCC MUX IN1+ IN1- DIFFERENTIAL INPUTS IN+/IN- WITH WIDE INPUT COMMON MODE RANGE VDDLBYP 1.5 SDO0 SDO1 SCKO SCKI SDI CS BUSY CNV S/H REFIN GND 235318 TA01a 0.1F 47F 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) ALL CHANNELS 1.0 18-BIT SAR ADC VEE REFBUF TWO BUFFERED SIMULTANEOUS SAMPLING CHANNELS 2.0 OVDD LVDS/CMOS PD LTC2353-18 S/H UNIPOLAR VDD 0.1F INL ERROR (LSB) +10V ARBITRARY 0.5 0 -0.5 -1.0 SAMPLE CLOCK -1.5 -2.0 -131072 -65536 0 65536 OUTPUT CODE 131072 235318 TA01b -15V 235318f For more information www.linear.com/LTC2353-18 1 LTC2353-18 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) ORDER INFORMATION 48 47 46 45 44 43 42 41 40 39 38 37 GND GND GND VEE GND VDD VDD GND VDDLBYP CS BUSY SDI TOP VIEW 1 2 3 4 GND 5 GND 6 GND 7 GND 8 IN0- 9 IN0+ 10 GND 11 GND 12 36 35 34 33 32 31 30 29 28 27 26 25 GND GND IN1- IN1+ GND SDO- SDO+ SCKO-/SDO1 SCKO+/SCKO OVDD GND SCKI-/SCKI SCKI+/SDO0 SDI- SDI+ GND GND 13 GND 14 GND 15 VCC 16 VEE 17 GND 18 REFIN 19 GND 20 REFBUF 21 PD 22 LVDS/CMOS 23 CNV 24 Supply Voltage (VCC)......................-0.3V to (VEE + 40V) Supply Voltage (VEE)................................. -17.4V to 0.3V Supply Voltage Difference (VCC - VEE).......................40V Supply Voltage (VDD)...................................................6V Supply Voltage (OVDD).................................................6V Internal Regulated Supply Bypass (VDDLBYP).... (Note 3) Analog Input Voltage IN0+, IN1+, IN0-, IN1- (Note 4)............. (VEE - 0.3V) to (VCC + 0.3V) REFIN..................................................... -0.3V to 2.8V REFBUF, CNV (Note 5).............. -0.3V to (VDD + 0.3V) Digital Input Voltage (Note 5)...... -0.3V to (OVDD + 0.3V) Digital Output Voltage (Note 5)... -0.3V to (OVDD + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2353C................................................. 0C to 70C LTC2353I..............................................-40C to 85C LTC2353H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C LX PACKAGE 48-LEAD (7mm x 7mm) PLASTIC LQFP TJMAX = 150C, JA = 53C/W http://www.linear.com/product/LTC2353-18#orderinfo TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2353CLX-18#PBF LTC2353LX-18 48-Lead (7mm x 7mm) Plastic LQFP 0C to 70C LTC2353ILX-18#PBF LTC2353LX-18 48-Lead (7mm x 7mm) Plastic LQFP -40C to 85C LTC2353HLX-18#PBF LTC2353LX-18 48-Lead (7mm x 7mm) Plastic LQFP -40C to 125C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ 235318f 2 For more information www.linear.com/LTC2353-18 LTC2353-18 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 6) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN0+, IN1+) (Note 7) l VEE + 4 VCC - 4 V VIN- Absolute Input Range (IN0-, IN1-) (Note 7) l VEE + 4 VCC - 4 V VIN+ - VIN- Input Differential Voltage Range SoftSpan 7: 2.5 * VREFBUF Range (Note 7) SoftSpan 6: 2.5 * VREFBUF/1.024 Range (Note 7) SoftSpan 5: 0V to 2.5 * VREFBUF Range (Note 7) SoftSpan 4: 0V to 2.5 * VREFBUF/1.024 Range (Note 7) SoftSpan 3: 1.25 * VREFBUF Range (Note 7) SoftSpan 2: 1.25 * VREFBUF/1.024 Range (Note 7) SoftSpan 1: 0V to 1.25 * VREFBUF Range (Note 7) l -2.5 * VREFBUF l -2.5 * VREFBUF/1.024 l 0 l 0 l -1.25 * VREFBUF l -1.25 * VREFBUF/1.024 l 0 2.5 * VREFBUF 2.5 * VREFBUF/1.024 2.5 * VREFBUF 2.5 * VREFBUF/1.024 1.25 * VREFBUF 1.25 * VREFBUF/1.024 1.25 * VREFBUF V V V V V V V VCM (Note 7) l VEE + 4 VCC - 4 V (Note 8) l -(VCC - VEE) (VCC - VEE) V VIN+ > VCC, VIN- > VCC (Note 8) VIN+ < VEE, VIN- < VEE (Note 8) l l 0 C-Grade and I-Grade H-Grade l l l l Input Common Mode Voltage Range VIN+ - VIN- Input Differential Overdrive Tolerance IOVERDRIVE Input Overdrive Current Tolerance IIN Analog Input Leakage Current IIN+ - IIN- Analog Input Leakage Offset Current VIN+ = VIN- VIN+ = VIN-, C-Grade and I-Grade VIN+ = VIN-, H-Grade For Each Pin RIN Analog Input Resistance CIN Analog Input Capacitance CMRR Input Common Mode Rejection Ratio VIHCNV CNV High Level Input Voltage VILCNV CNV Low Level Input Voltage IINCNV CNV Input Current VIN+ = VIN- = 18VP-P 200Hz Sine MIN TYP MAX 10 5 1 -100 -1.2 l 103 l 1.3 500 12 pA pA nA 100 1.2 pA pA nA G 3 pF 124 dB V -10 l mA mA >1000 l VIN = 0V to VDD UNITS 0.5 V 10 A CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN UNITS l 18 Bits No Missing Codes l 18 Bits SoftSpans 7 and 6: 10.24V and 10V Ranges SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges SoftSpans 3 and 2: 5.12V and 5V Ranges SoftSpan 1: 0V to 5.12V Range INL Integral Linearity Error SoftSpans 7 and 6: 10.24V and 10V Ranges (Note 10) SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges (Note 10) SoftSpans 3 and 2: 5.12V and 5V Ranges (Note 10) SoftSpan 1: 0V to 5.12V Range (Note 10) DNL 1.4 2.8 2.1 4.2 LSBRMS LSBRMS LSBRMS LSBRMS l l l l -3.5 -5 -4 -6 1 1.5 1 1 3.5 5 4 6 LSB LSB LSB LSB Differential Linearity Error (Note 11) l -0.9 0.3 0.9 LSB Zero-Scale Error l -700 50 700 (Note 12) Zero-Scale Error Drift FSE MAX Resolution Transition Noise ZSE TYP 4 Full-Scale Error VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) Full-Scale Error Drift VREFBUF = 4.096V (REFBUF Overdriven) (Note 12) l -0.07 0.025 2.5 V V/C 0.07 %FS ppm/C 235318f For more information www.linear.com/LTC2353-18 3 LTC2353-18 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Notes 9, 13) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio l SoftSpans 7 and 6: 10.24V and 10V Ranges, fIN = 2kHz SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz l l SoftSpans 3 and 2: 5.12V and 5V Ranges, fIN = 2kHz l SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz 92.6 86.9 89.3 83.6 96.2 90.3 92.5 86.6 dB dB dB dB SNR Signal-to-Noise Ratio SoftSpans 7 and 6: 10.24V and 10V Ranges, fIN = 2kHz SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz SoftSpans 3 and 2: 5.12V and 5V Ranges, fIN = 2kHz SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz l l l l 92.7 87.0 89.5 83.6 96.4 90.4 92.5 86.6 dB dB dB dB THD Total Harmonic Distortion SoftSpans 7 and 6: 10.24V and 10V Ranges, fIN = 2kHz SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz SoftSpans 3 and 2: 5.12V and 5V Ranges, fIN = 2kHz SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz l l l l SFDR Spurious Free Dynamic Range SoftSpans 7 and 6: 10.24V and 10V Ranges, fIN = 2kHz SoftSpans 5 and 4: 0V to 10.24V and 0V to 10V Ranges, fIN = 2kHz SoftSpans 3 and 2: 5.12V and 5V Ranges, fIN = 2kHz SoftSpan 1: 0V to 5.12V Range, fIN = 2kHz l l l l Channel-to-Channel Crosstalk One Channel Converting 18VP-P 200Hz Sine in 10.24V Range, Crosstalk to Other Channel -110 -110 -113 -114 101 99 101 99 -3dB Input Bandwidth Aperture Delay Aperture Delay Matching Aperture Jitter Transient Response MAX -101 -99 -101 -99 dB dB dB dB 112 111 113 114 dB dB dB dB -121 dB 6 MHz 1 ns 150 ps 3 Full-Scale Step, 0.005% Settling UNITS psRMS 420 ns INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER VREFIN Internal Reference Output Voltage CONDITIONS Internal Reference Temperature Coefficient (Note 14) Internal Reference Line Regulation VDD = 4.75V to 5.25V MIN TYP MAX 2.043 2.048 2.053 5 20 l 0.1 Internal Reference Output Impedance VREFIN REFIN Voltage Range 1.25 V ppm/C mV/V 20 REFIN Overdriven (Note 7) UNITS k 2.2 V REFERENCE BUFFER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS VREFBUF Reference Buffer Output Voltage REFIN Overdriven, VREFIN = 2.048V REFBUF Voltage Range REFBUF Overdriven (Notes 7, 15) REFBUF Input Impedance VREFIN = 0V, Buffer Disabled REFBUF Load Current VREFBUF = 5V, 2 Channels Enabled (Notes 15, 16) VREFBUF = 5V, Acquisition or Nap Mode (Note 15) IREFBUF MIN TYP MAX UNITS l 4.091 4.096 4.101 V l 2.5 5 13 l 1.2 0.36 V k 1.3 mA mA 235318f 4 For more information www.linear.com/LTC2353-18 LTC2353-18 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Digital Inputs and Outputs VIH High Level Input Voltage l 0.8 * OVDD VIL Low Level Input Voltage l IIN Digital Input Current CIN Digital Input Capacitance VOH High Level Output Voltage VIN = 0V to OVDD l IOUT = -500A l OVDD - 0.2 V -10 0.2 * OVDD V 10 A 5 pF V VOL Low Level Output Voltage IOUT = 500A l IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l ISOURCE Output Source Current VOUT = 0V -50 mA ISINK Output Sink Current VOUT = OVDD 50 mA -10 0.2 V 10 A LVDS Digital Inputs and Outputs VID Differential Input Voltage l 200 350 600 mV l RID On-Chip Input Termination Resistance 90 106 10 125 M VICM Common-Mode Input Voltage l IICM Common-Mode Input Current 0.3 1.2 2.2 V VIN+ = VIN- = 0V to OVDD l -10 10 A VOD VOCM Differential Output Voltage RL = 100 Differential Termination l 275 350 425 mV Common-Mode Output Voltage RL = 100 Differential Termination l 1.1 1.2 1.3 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l -10 10 A CS = 0V, VICM = 1.2V CS = OVDD POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VCC Supply Voltage l 7.5 VEE Supply Voltage l -16.5 0 V VCC - VEE Supply Voltage Difference l 10 38 V l 4.75 VDD Supply Voltage IVCC Supply Current 550ksps Sample Rate, 2 Channels Enabled (Note 17) Acquisition Mode (Note 17) Nap Mode Power Down Mode l l l l IVEE Supply Current 550ksps Sample Rate, 2 Channels Enabled (Note 17) Acquisition Mode (Note 17) Nap Mode Power Down Mode l l l l -4.1 -6.1 -1.2 -15 l 1.71 38 UNITS V 5.00 5.25 V 3.2 4.9 0.9 5 3.9 5.9 1.1 15 mA mA mA A -3.2 -4.7 -0.8 -4 mA mA mA A CMOS I/O Mode OVDD Supply Voltage IVDD Supply Current 550ksps Sample Rate, 2 Channels Enabled 550ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 15) Acquisition Mode Nap Mode Power Down Mode (C-Grade and I-Grade) Power Down Mode (H-Grade) l l l l l l 12.4 11.2 1.8 1.6 89 89 5.25 V 14.0 12.7 2.6 2.4 300 750 mA mA mA mA A A 235318f For more information www.linear.com/LTC2353-18 5 LTC2353-18 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN IOVDD Supply Current 550ksps Sample Rate, 2 Channels Enabled (CL = 25pF) Acquisition or Nap Mode Power Down Mode l l l PD Power Dissipation 550ksps Sample Rate, 2 Channels Enabled Acquisition Mode Nap Mode Power Down Mode (C-Grade and I-Grade) Power Down Mode (H-Grade) l l l l l TYP MAX UNITS 1.6 1 1 2.7 20 20 mA A A 162 153 34 0.60 0.60 195 193 47 2 4.3 mW mW mW mW mW 5.25 V LVDS I/O Mode OVDD Supply Voltage IVDD Supply Current 550ksps Sample Rate, 2 Channels Enabled 550ksps Sample Rate, 2 Channels Enabled, VREFBUF = 5V (Note 15) Acquisition Mode Nap Mode Power Down Mode (C-Grade and I-Grade) Power Down Mode (H-Grade) l l l l l l 14.4 13.2 3.5 3.3 89 89 16.1 14.9 4.4 4.2 300 750 mA mA mA mA A A IOVDD Supply Current 550ksps Sample Rate, 2 Channels Enabled (RL = 100) Acquisition or Nap Mode (RL = 100) Power Down Mode l l l 7.4 7 1 8.6 8.2 20 mA mA A PD Power Dissipation 550ksps Sample Rate, 2 Channels Enabled Acquisition Mode Nap Mode Power Down Mode (C-Grade and I-Grade) Power Down Mode (H-Grade) l l l l l 187 179 60 0.60 0.60 221 223 76 2 4.3 mW mW mW mW mW l 2.375 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS fSMPL Maximum Sampling Frequency 2 Channels Enabled 1 Channel Enabled l l tCYC Time Between Conversions 2 Channels Enabled, fSMPL = 550ksps 1 Channel Enabled, fSMPL = 800ksps l l 1815 1250 tCONV Conversion Time N Channels Enabled, 1 N 2 l 450*N 500*N tACQ Acquisition Time (tACQ = tCYC - tCONV - tBUSYLH) 2 Channels Enabled, fSMPL = 550ksps 1 Channel Enabled, fSMPL = 800ksps l l 685 670 795 730 tCNVH CNV High Time l 40 tCNVL CNV Low Time l 750 tBUSYLH CNV to BUSY Delay tQUIET Digital I/O Quiet Time from CNV l 20 ns tPDH PD High Time l 40 ns tPDL PD Low Time l 40 ns tWAKE REFBUF Wake-Up Time CL = 25pF CREFBUF = 47F, CREFIN = 0.1F MIN TYP MAX UNITS 550 800 ksps ksps ns ns 550*N ns ns ns ns ns 30 l 200 ns ms 235318f 6 For more information www.linear.com/LTC2353-18 LTC2353-18 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS I/O Mode tSCKI SCKI Period tSCKIH tSCKIL tSSDISCKI SDI Setup Time from SCKI tHSDISCKI tDSDOSCKI l 10 ns SCKI High Time l 4 ns SCKI Low Time l 4 ns (Note 18) l 2 ns SDI Hold Time from SCKI (Note 18) l 1 SDO Data Valid Delay from SCKI CL = 25pF (Note 18) l tHSDOSCKI SDO Remains Valid Delay from SCKI CL = 25pF (Note 18) l 1.5 tSKEW SDO to SCKO Skew (Note 18) l -1 CL = 25pF (Note 18) l 0 tDSDOBUSYL SDO Data Valid Delay from BUSY (Notes 18, 19) ns 7.5 ns 1 ns ns 0 ns tEN Bus Enable Time After CS (Note 18) l 15 ns tDIS Bus Relinquish Time After CS (Note 18) l 15 ns LVDS I/O Mode tSCKI SCKI Period (Note 20) l 4 ns tSCKIH SCKI High Time (Note 20) l 1.5 ns tSCKIL SCKI Low Time (Note 20) l 1.5 ns tSSDISCKI SDI Setup Time from SCKI (Notes 11, 20) l 1.2 ns tHSDISCKI SDI Hold Time from SCKI (Notes 11, 20) l -0.2 ns tDSDOSCKI SDO Data Valid Delay from SCKI (Notes 11, 20) l tHSDOSCKI SDO Remains Valid Delay from SCKI (Notes 11, 20) l 1 tSKEW SDO to SCKO Skew (Note 11) l -0.4 (Note 11) l 0 tDSDOBUSYL SDO Data Valid Delay from BUSY 6 ns ns 0 0.4 ns ns tEN Bus Enable Time After CS l 50 ns tDIS Bus Relinquish Time After CS l 15 ns 235318f For more information www.linear.com/LTC2353-18 7 LTC2353-18 ADC TIMING CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: VDDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2F ceramic capacitor to bypass the pin to GND, as described in the Pin Functions section. Do not connect this pin to any external circuitry. Note 4: When these pin voltages are taken below VEE or above VCC, they will be clamped by internal diodes. This product can handle input currents of up to 100mA below VEE or above VCC without latch-up. Note 5: When these pin voltages are taken below GND or above VDD or OVDD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below GND or above VDD or OVDD without latch-up. Note 6: -16.5V VEE 0V, 7.5V VCC 38V, 10V (VCC - VEE) 38V, VDD = 5V, unless otherwise specified. Note 7: Recommended operating conditions. Note 8: Exceeding these limits on one channel may corrupt conversion results on the other channel. Driving an analog input above VCC on any channel up to 10mA will not affect conversion results on other channels. Driving an analog input below VEE may corrupt conversion results on other channels. Refer to Applications Information section for further details. Refer to Absolute Maximum Ratings section for pin voltage limits related to device reliability. Note 9: VCC = 15V, VEE = -15V, VDD = 5V, OVDD = 2.5V, fSMPL = 550ksps, internal reference and buffer, true bipolar input signal drive in bipolar SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless otherwise specified. Note 10: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 11: Guaranteed by design, not subject to test. Note 12: For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is the offset voltage measured from -0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full-scale error for these SoftSpan ranges is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. For unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage measured from 0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Fullscale error for these SoftSpan ranges is the worst-case deviation of the last code transition from ideal and includes the effect of offset error. Note 13: All specifications in dB are referred to a full-scale input in the relevant SoftSpan input range, except for crosstalk, which is referred to the crosstalk injection signal amplitude. Note 14: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 15: When REFBUF is overdriven, the internal reference buffer must be disabled by setting REFIN = 0V. Note 16: IREFBUF varies proportionally with sample rate and the number of active channels. Note 17: Portions of the analog input circuitry are powered down during conversion, reducing IVCC and IVEE. Refer to Applications Information section for more details.. Note 18: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, and OVDD = 5.25V. Note 19: A tSCKI period of 10ns minimum allows a shift clock frequency of up to 100MHz for rising edge capture. Note 20: VICM = 1.2V, VID = 350mV for LVDS differential input pairs. CMOS Timings 0.8 * OVDD tWIDTH 0.2 * OVDD tDELAY tDELAY 0.8 * OVDD 0.8 * OVDD 0.2 * OVDD 0.2 * OVDD 50% 50% 235318 F01 LVDS Timings (Differential) +200mV tWIDTH -200mV tDELAY tDELAY +200mV +200mV -200mV -200mV 0V 0V 235318 F01b Figure 1. Voltage Levels for Timing Specifications 235318f 8 For more information www.linear.com/LTC2353-18 LTC2353-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VCC = +15V, VEE = -15V, VDD = 5V, OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 550ksps, unless otherwise noted. Integral Nonlinearity vs Output Code and Channel 2.0 Integral Nonlinearity vs Output Code and Channel 2.0 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) BOTH CHANNELS 1.5 -0.5 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -131072 -2.0 -131072 0 65536 OUTPUT CODE 131072 2.0 -65536 0 65536 OUTPUT CODE INL ERROR (LSB) INL ERROR (LSB) 0.5 0 -0.5 -65536 10.24V AND 10V RANGES -0.5 -65536 0 65536 OUTPUT CODE 90000 10.24V RANGE COUNTS -0.5 -1.0 ARBITRARY DRIVE IN+/IN- COMMON MODE SWEPT -10.24V TO 10.24V 0 65536 OUTPUT CODE 131072 235318 G07 0V TO 10.24V AND 0V TO 10V RANGES 0 65536 131072 196608 OUTPUT CODE DC Histogram (Near Full-Scale) 90000 70000 60000 60000 50000 40000 50000 40000 30000 30000 20000 20000 10000 10000 -6 -4 -2 0 CODE 2 4 6 235318 G08 10.24V RANGE = 1.4 80000 70000 0 262144 235318 G06 10.24V RANGE = 1.35 80000 TRUE BIPOLAR DRIVE (IN- = 0V) -65536 -2.0 131072 DC Histogram (Zero-Scale) 0 -2.0 -131072 -0.5 235318 G05 0.5 -1.5 0 -1.0 COUNTS 1.0 0.5 -1.5 -2.0 -131072 131072 262144 0V TO 5.12V RANGE 1.0 5.12V AND 5V RANGES -1.0 131072 196608 OUTPUT CODE UNIPOLAR DRIVE (IN- = 0V) ONE CHANNEL 1.5 0 Integral Nonlinearity vs Output Code 1.5 2.0 0.5 235318 G04 2.0 65536 235318 G03 -1.5 0 65536 OUTPUT CODE 0 Integral Nonlinearity vs Output Code and Range 10.24V AND 10V RANGES 1.0 -2.0 -131072 -0.5 131072 FULLY DIFFERENTIAL DRIVE (IN- = -IN+) ONE CHANNEL 1.5 1.0 5.12V AND 5V RANGES -0.2 Integral Nonlinearity vs Output Code and Range TRUE BIPOLAR DRIVE (IN- = 0V) ONE CHANNEL 1.5 0.0 -0.1 235318 G02 Integral Nonlinearity vs Output Code and Range 2.0 0.1 -0.4 INL ERROR (LSB) -65536 0.2 -0.3 235318 G01 INL ERROR (LSB) 0.3 DNL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0 ALL RANGES BOTH CHANNELS 0.4 1.0 0.5 -1.5 0.5 10.24V RANGE FULLY DIFFERENTIAL DRIVE (IN- = -IN+) BOTH CHANNELS 1.5 1.0 -1.0 Differential Nonlinearity vs Output Code and Channel 0 131046 131049 131052 CODE 131055 131058 235318 G09 235318f For more information www.linear.com/LTC2353-18 9 LTC2353-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VCC = +15V, VEE = -15V, VDD = 5V, OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 550ksps, unless otherwise noted. 32k Point Arbitrary Two-Tone FFT 32k Point FFT fSMPL = 550ksps, 32k Point FFT fSMPL = 550ksps, fSMPL = 550ksps, IN+ = -7dBFS 2kHz fIN = 2kHz fIN = 2kHz Sine, IN- = -7dBFS 3.1kHz Sine -40 SNR = 96.3dB THD = -111dB SINAD = 96.2dB SFDR = 113dB -60 -80 -100 -120 -40 SNR = 96.3dB THD = -113dB SINAD = 96.3dB SFDR = 116dB -60 -80 -40 -100 -120 -80 -100 -140 -160 -160 220 -180 275 0 55 110 165 FREQUENCY (kHz) 220 235318 G10 32k Point FFT fSMPL = 550ksps, fIN = 2kHz 100 5.12V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) -20 -40 SNR = 92.6dB THD = -114dB SINAD = 92.6dB SFDR = 119dB -60 -80 -100 -120 -100 2.5 * VREFBUF RANGE TRUE BIPOLAR DRIVE (IN- = 0V) 96 SINAD 94 110 165 FREQUENCY (kHz) 220 90 2.5 275 3 3.5 4 4.5 REFBUF VOLTAGE (V) -120 3RD 75 10k SOURCE -90 -100 50 SOURCE -120 100k 235318 G16 3 -130 100 1k 10k FREQUENCY (Hz) 5 THD, Harmonics vs Input Common Mode, fIN = 2kHz -40 COMMON MODE LIMITS -11V VCM 11V -60 -80 -100 THD -120 3RD -140 1k SOURCE 10 3.5 4 4.5 REFBUF VOLTAGE (V) 10.24V RANGE -20 2VP-P FULLY DIFFERENTIAL DRIVE -110 70 65 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) 60 10 100 1k 10k FREQUENCY (Hz) 0 THD, HARMONICS (dBFS) THD (dBFS) SNR, SINAD (dBFS) -80 SINAD 80 2ND 235318 G15 10.24V RANGE - -70 TRUE BIPOLAR DRIVE (IN = 0V) SNR 90 85 -115 -130 2.5 5 -60 95 THD -110 THD vs Input Frequency and Source Resistance 100 275 2.5 * VREFBUF RANGE TRUE BIPOLAR DRIVE (IN- = 0V) 235318 G14 235318 G13 SNR, SINAD vs Input Frequency 220 -125 -160 55 110 165 FREQUENCY (kHz) THD, Harmonics vs VREFBUF, fIN = 2kHz -105 SNR 92 0 55 235318 G12 SNR, SINAD vs VREFBUF, fIN = 2kHz 98 -140 -180 0 235318 G11 SNR, SINAD (dBFS) 0 -180 275 THD, HARMONICS (dBFS) 110 165 FREQUENCY (kHz) 6.2kHz -120 -140 55 SFDR = 121dB SNR = 96.4dB -60 -160 0 10.24V RANGE ARBITRARY DRIVE -20 -140 -180 AMPLITUDE (dBFS) 0 10.24V RANGE FULLY DIFFERENTIAL DRIVE (IN- = -IN+) -20 AMPLITUDE (dBFS) -20 AMPLITUDE (dBFS) 0 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) AMPLITUDE (dBFS) 0 100k 235318 G17 -160 -15 2ND -10 -5 0 5 10 INPUT COMMON MODE (V) 15 235318 G18 235318f 10 For more information www.linear.com/LTC2353-18 LTC2353-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VCC = +15V, VEE = -15V, VDD = 5V, OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 550ksps, unless otherwise noted. 160 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) 10.24V RANGE IN+ = IN- = 18VP-P SINE BOTH CHANNELS 140 96.6 SINAD 96.4 96.2 120 100 80 -30 -20 -10 INPUT LEVEL (dBFS) 60 0 10 100 1k 10k FREQUENCY (Hz) 100k 235318 G19 98.0 96.5 SNR 96.0 SINAD 95.5 95.0 94.5 -105 THD -110 2ND -115 3RD -125 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 0.075 IN = +10V IN = -10V 1 5 25 45 65 85 105 125 TEMPERATURE (C) 5 25 45 65 85 105 125 TEMPERATURE (C) 235318 G25 100k 0.050 10.24V RANGE REFBUF OVERDRIVEN VREFBUF = 4.096V BOTH CHANNELS 0.025 0.000 -0.025 -0.050 -0.100 -55 -35 -15 1M 1.5 1.0 MAX INL 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) BOTH CHANNELS 0.5 MAX DNL 0 -0.5 MIN DNL -1.0 MIN INL -2.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 235318 G24 Zero-Scale Error vs Temperature and Channel -0.075 IN = 0V 0.1 -55 -35 -15 FULL-SCALE ERROR (%) ANALOG INPUT LEAKAGE CURRENT (pA) 0.100 4 ANALOG INPUT PIN TRACES FOR EACH INPUT VOLTAGE 10 1k 10k FREQUENCY (Hz) INL, DNL vs Temperature Positive Full-Scale Error vs Temperature and Channel 100 100 235318 G23 Analog Input Leakage Current vs Temperature 1k 10 2.0 -1.5 235318 G22 10k CH1 235318 G21 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) -120 94.0 -55 -35 -15 -150 1M THD, Harmonics vs Temperature, fIN = 2kHz -100 THD, HARMONICS (dBFS) SNR, SINAD (dBFS) -95 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) 97.0 -130 235318 G20 SNR, SINAD vs Temperature, fIN = 2kHz 97.5 -120 -140 INL, DNL ERROR (LSB) 96.0 -40 10.24V RANGE IN0+ = 0V IN0- = 18VP-P SINE BOTH CHANNELS CONVERTING -110 CROSSTALK (dB) SNR CMRR (dB) SNR, SINAD (dBFS) 96.8 Crosstalk vs Input Frequency -100 5 4 ZERO-SCALE ERROR (LSB) 97.0 CMRR vs Input Frequency and Channel SNR, SINAD vs Input Level, fIN = 2kHz 10.24V RANGE BOTH CHANNELS 3 2 1 0 -1 -2 -3 -4 5 25 45 65 85 105 125 TEMPERATURE (C) 235318 G26 -5 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 235318 G27 235318f For more information www.linear.com/LTC2353-18 11 LTC2353-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VCC = +15V, VEE = -15V, VDD = 5V, OVDD = 2.5V, Internal Reference and Buffer (VREFBUF = 4.096V), fSMPL = 550ksps, unless otherwise noted. Power-Down Current vs Temperature Supply Current vs Temperature 18 150 16 I VDD 10 8 6 I VCC 4 2 I OVDD 0 I VEE -2 100 130 10 1 I VCC -I VEE 110 90 80 I OVDD 0.1 70 0.01 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) Internal Reference Output vs Temperature INTERNAL REFERENCE OUTPUT (V) OFFSET ERROR (LSB) VCC = 38V, VEE = 0V VCM = 4V TO 34V 0.5 0 -0.5 VCC = 21.5V, VEE = -16.5V VCM = -12.5V TO 17.5V -1.0 -1.5 -2.0 -17 0 17 INPUT COMMON MODE (V) 2.050 2.049 2.048 2.047 OUTPUT CODE (LSB) 120 100 80 60 WITH NAP MODE tCNVL = 750ns 40 0 100 200 300 400 500 600 700 800 SAMPLING RATE (ksps) 235318 G34 4 IVCC 2 0 -6 5 25 45 65 85 105 125 TEMPERATURE (C) IOVDD IVEE 0 110 220 330 440 SAMPLING RATE (ksps) Step Response (Fine Settling) 131072 250 98304 200 65536 32768 0 -32768 550 235318 G33 Step Response (Large-Signal Settling) N=1 140 6 235318 G32 200 N=2 IVDD 8 -4 2.045 -55 -35 -15 34 10 -2 2.046 Power Dissipation vs Sampling Rate, N-Channels Enabled 160 100k WITH NAP MODE 14 tCNVL = 780ns 12 15 UNITS 235318 G31 180 1k 10k FREQUENCY (Hz) Supply Current vs Sampling Rate SUPPLY CURRENT (mA) 10.24V RANGE 1.0 100 16 2.051 1.5 10 235318 G30 10.24V RANGE IN+ = 225.00043kHz SQUARE WAVE IN- = 0V -65536 -98304 -131072 -100 0 100 200 300 400 500 600 700 800 900 SETTLING TIME (ns) 235318 G35 DEVIATION FROM FINAL VALUE (LSB) 2.0 50 5 25 45 65 85 105 125 TEMPERATURE (C) 235318 G29 Offset Error vs Input Common Mode POWER DISSIPATION (mW) VDD 60 235318 G28 20 VEE 100 -4 -6 -55 -35 -15 IN+ = IN- = 0V OVDD 120 PSRR (dB) POWER-DOWN CURRENT (A) 12 VCC 140 I VDD 14 SUPPLY CURRENT (mA) PSRR vs Frequency 1000 150 10.24V RANGE IN+ = 225.00043kHz SQUARE WAVE IN- = 0V 100 50 0 -50 -100 -150 -200 -250 -100 0 100 200 300 400 500 600 700 800 900 SETTLING TIME (ns) 235318 G36 235318f 12 For more information www.linear.com/LTC2353-18 LTC2353-18 PIN FUNCTIONS Pins that are the Same for All Digital I/O Modes IN0+/IN0-, IN1+/IN1- (Pins 10/9, 4/3): Positive and Negative Analog Inputs, Channels 0 and 1. The converter simultaneously samples and digitizes (VIN+ - VIN-) for both channels. Wide input common mode range (VEE + 4V VCM VCC - 4V) and high common mode rejection allow the inputs to accept a wide variety of signal swings. Full-scale input range is determined by the channel's SoftSpan configuration. GND (Pins 1, 2, 5, 6, 7, 8, 11, 12, 13, 14, 15, 18, 20, 25, 30, 36, 41, 44, 46, 47, 48): Ground. Solder all GND pins to a solid ground plane. VCC (Pin 16): Positive High Voltage Power Supply. The range of VCC is 7.5V to 38V with respect to GND and 10V to 38V with respect to VEE. Bypass VCC to GND close to the pin with a 0.1F ceramic capacitor. VEE (Pins 17, 45): Negative High Voltage Power Supply. The range of VEE is 0V to -16.5V with respect to GND and -10V to -38V with respect to VCC. Connect Pins 17 and 45 together and bypass the VEE network to GND close to Pin 17 with a 0.1F ceramic capacitor. In applications where VEE is shorted to GND, this capacitor may be omitted. REFIN (Pin 19): Bandgap Reference Output/Reference Buffer Input. An internal bandgap reference nominally outputs 2.048V on this pin. An internal reference buffer amplifies VREFIN to create the converter master reference voltage VREFBUF = 2 * VREFIN on the REFBUF pin. When using the internal reference, bypass REFIN to GND (Pin 20) close to the pin with a 0.1F ceramic capacitor to filter the bandgap output noise. If more accuracy is desired, overdrive REFIN with an external reference in the range of 1.25V to 2.2V. Do not load this pin when internal reference is used. REFBUF (Pin 21): Internal Reference Buffer Output. An internal reference buffer amplifies VREFIN to create the converter master reference voltage VREFBUF = 2 * VREFIN on this pin, nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with a 47F ceramic capacitor. The internal reference buffer may be disabled by grounding its input at REFIN. With the buffer disabled, overdrive REFBUF with an external reference voltage in the range of 2.5V to 5V. When using the internal reference buffer, limit the loading of any external circuitry connected to REFBUF to less than 200A. Using a high input impedance amplifier to buffer VREFBUF to any external circuits is recommended. PD (Pin 22): Power Down Input. When this pin is brought high, the LTC2353-18 is powered down and subsequent conversion requests are ignored. If this occurs during a conversion, the device powers down once the conversion completes. If this pin is brought high twice without an intervening conversion, an internal global reset is initiated, equivalent to a power-on-reset event. Logic levels are determined by OVDD. LVDS/CMOS (Pin 23): I/O Mode Select. Tie this pin to OVDD to select LVDS I/O mode, or to ground to select CMOS I/O mode. Logic levels are determined by OVDD. CNV (Pin 24): Conversion Start Input. A rising edge on this pin puts the internal sample-and-holds into the hold mode and initiates a new conversion. CNV is not gated by CS, allowing conversions to be initiated independent of the state of the serial I/O bus. BUSY (Pin 38): Busy Output. The BUSY signal indicates that a conversion is in progress. This pin transitions lowto-high at the start of each conversion and stays high until the conversion is complete. Logic levels are determined by OVDD. VDDLBYP (Pin 40): Internal 2.5V Regulator Bypass Pin. The voltage on this pin is generated via an internal regulator operating off of VDD. This pin must be bypassed to GND close to the pin with a 2.2F ceramic capacitor. Do not connect this pin to any external circuitry. VDD (Pins 42, 43): 5V Power Supply. The range of VDD is 4.75V to 5.25V. Connect Pins 42 and 43 together and bypass the VDD network to GND with a shared 0.1F ceramic capacitor close to the pins. 235318f For more information www.linear.com/LTC2353-18 13 LTC2353-18 PIN FUNCTIONS CMOS I/O Mode LVDS I/O Mode SDI+, SDI-, SDO+, SDO- (Pins 26, 27, 34, and 35): LVDS Input and Output. In CMOS I/O mode these pins are Hi-Z. SDI+/SDI- (Pins 26/27): LVDS Positive and Negative Serial Data Input. Differentially drive SDI+/SDI- with the desired 6-bit SoftSpan configuration word (see Table 1a), latched on both the rising and falling edges of SCKI+/SCKI-. The SDI+/SDI- input pair is internally terminated with a 100 differential resistor when CS is low. SDO0, SDO1 (Pins 28, 33): CMOS Serial Data Outputs, Channels 0 to 1. The most recent conversion result along with channel configuration information is clocked out onto the SDO pins on each rising edge of SCKI. Output data formatting is described in the Digital Interface section. Leave unused SDO outputs unconnected. Logic levels are determined by OVDD. SCKI (Pin 29): CMOS Serial Clock Input. Drive SCKI with the serial I/O clock. SCKI rising edges latch serial data in on SDI and clock serial data out on SDO0 and SDO1. For standard SPI bus operation, capture output data at the receiver on rising edges of SCKI. SCKI is allowed to idle either high or low. Logic levels are determined by OVDD. OVDD (Pin 31): I/O Interface Power Supply. In CMOS I/O mode, the range of OVDD is 1.71V to 5.25V. Bypass OVDD to GND (Pin 30) close to the pin with a 0.1F ceramic capacitor. SCKO (Pin 32): CMOS Serial Clock Output. SCKI rising edges trigger transitions on SCKO that are skew-matched to the serial output data streams on SDO0 and SDO1. The resulting SCKO frequency is half that of SCKI. Rising and falling edges of SCKO may be used to capture SDO data at the receiver (FPGA) in double data rate (DDR) fashion. For standard SPI bus operation, SCKO is not used and should be left unconnected. SCKO is forced low at the falling edge of BUSY. Logic levels are determined by OVDD. SDI (Pin 37): CMOS Serial Data Input. Drive this pin with the desired 6-bit SoftSpan configuration word (see Table 1a), latched on the rising edges of SCKI. If both channels will be configured to operate only in SoftSpan 7, tie SDI to OVDD. Logic levels are determined by OVDD. CS (Pin 39): Chip Select Input. The serial data I/O bus is enabled when CS is low and is disabled and Hi-Z when CS is high. CS also gates the external shift clock, SCKI. Logic levels are determined by OVDD. SCKI+/SCKI- (Pins 28/29): LVDS Positive and Negative Serial Clock Input. Differentially drive SCKI+/SCKI- with the serial I/O clock. SCKI+/SCKI- rising and falling edges latch serial data in on SDI+/SDI- and clock serial data out on SDO+/SDO-. Idle SCKI+/SCKI- low, including when transitioning CS. The SCKI+/SCKI- input pair is internally terminated with a 100 differential resistor when CS is low. OVDD (Pin 31): I/O Interface Power Supply. In LVDS I/O mode, the range of OVDD is 2.375V to 5.25V. Bypass OVDD to GND (Pin 30) close to the pin with a 0.1F ceramic capacitor. SCKO+/SCKO- (Pins 32/33): LVDS Positive and Negative Serial Clock Output. SCKO+/SCKO- outputs a copy of the input serial I/O clock received on SCKI+/SCKI-, skewmatched with the serial output data stream on SDO+/ SDO-. Use the rising and falling edges of SCKO+/SCKO- to capture SDO+/SDO- data at the receiver (FPGA). The SCKO+/SCKO- output pair must be differentially terminated with a 100 resistor at the receiver (FPGA). SDO+/SDO- (Pins 34/35): LVDS Positive and Negative Serial Data Output. The most recent conversion result along with channel configuration information is clocked out onto SDO+/SDO- on both rising and falling edges of SCKI+/SCKI-, beginning with channel 0. The SDO+/SDO- output pair must be differentially terminated with a 100 resistor at the receiver (FPGA). SDI (Pin 37): CMOS Serial Data. In LVDS I/O mode, this pin is Hi-Z. CS (Pin 39): Chip Select Input. The serial data I/O bus is enabled when CS is low, and is disabled and Hi-Z when CS is high. CS also gates the external shift clock, SCKI+/ SCKI-. The internal 100 differential termination resistors on the SCKI+/SCKI- and SDI+/SDI- input pairs are disabled when CS is high. Logic levels are determined by OVDD. 235318f 14 For more information www.linear.com/LTC2353-18 LTC2353-18 CONFIGURATION TABLES Table 1a. SoftSpan Configuration Table. Use This Table with Table 1b to Choose Independent Binary SoftSpan Codes SS[2:0] for Each Channel Based on Desired Analog Input Range. Combine SoftSpan Codes to Form 6-Bit SoftSpan Configuration Word S[5:0]. Use Serial Interface to Write SoftSpan Configuration Word to LTC2353-18, as shown in Figure 18 BINARY SoftSpan CODE SS[2:0] ANALOG INPUT RANGE FULL SCALE RANGE BINARY FORMAT OF CONVERSION RESULT 111 110 101 100 011 010 001 000 2.5 * VREFBUF 2.5 * VREFBUF/1.024 0V to 2.5 * VREFBUF 0V to 2.5 * VREFBUF/1.024 1.25 * VREFBUF 1.25 * VREFBUF/1.024 0V to 1.25 * VREFBUF Channel Disabled 5 * VREFBUF 5 * VREFBUF/1.024 2.5 * VREFBUF 2.5 * VREFBUF/1.024 2.5 * VREFBUF 2.5 * VREFBUF/1.024 1.25 * VREFBUF Channel Disabled Two's Complement Two's Complement Straight Binary Straight Binary Two's Complement Two's Complement Straight Binary All Zeros Table 1b. Reference Configuration Table. The LTC2353-18 Supports Three Reference Configurations. Analog Input Range Scales with the Converter Master Reference Voltage, VREFBUF REFERENCE CONFIGURATION Internal Reference with Internal Buffer VREFIN VREFBUF 2.048V BINARY SoftSpan CODE SS[2:0] ANALOG INPUT RANGE 4.096V 1.25V (Min Value) 2.5V External Reference with Internal Buffer (REFIN Pin Externally Overdriven) 2.2V (Max Value) 4.4V 111 10.24V 110 10V 101 0V to 10.24V 100 0V to 10V 011 5.12V 010 5V 001 0V to 5.12V 111 6.25V 110 6.104V 101 0V to 6.25V 100 0V to 6.104V 011 3.125V 010 3.052V 001 0V to 3.125V 111 11V 110 10.742V 101 0V to 11V 100 0V to 10.742V 011 5.5V 010 5.371V 001 0V to 5.5V 235318f For more information www.linear.com/LTC2353-18 15 LTC2353-18 CONFIGURATION TABLES Table 1b. Reference Configuration Table (Continued). The LTC2353-18 Supports Three Reference Configurations. Analog Input Range Scales with the Converter Master Reference Voltage, VREFBUF REFERENCE CONFIGURATION VREFIN 0V VREFBUF BINARY SoftSpan CODE SS[2:0] 2.5V (Min Value) External Reference Unbuffered (REFBUF Pin Externally Overdriven, REFIN Pin Grounded) 0V 5V (Max Value) ANALOG INPUT RANGE 111 6.25V 110 6.104V 101 0V to 6.25V 100 0V to 6.104V 011 3.125V 010 3.052V 001 0V to 3.125V 111 12.5V 110 12.207V 101 0V to 12.5V 100 0V to 12.207V 011 6.25V 010 6.104V 001 0V to 6.25V 235318f 16 For more information www.linear.com/LTC2353-18 LTC2353-18 FUNCTIONAL BLOCK DIAGRAM CMOS I/O Mode VCC VDD VDDLBYP OVDD LTC2353-18 2.5V REGULATOR BUFFERS IN0- S/H IN1+ IN1- S/H SDO0 2-CHANNEL MULTIPLEXER IN0+ 18-BIT SAR ADC 18 BITS SDO1 CMOS SERIAL I/O INTERFACE SCKO SDI SCKI CS 20k 2.048V REFERENCE VEE GND REFERENCE BUFFER 2x REFIN REFBUF CONTROL LOGIC BUSY CNV PD LVDS/CMOS 235318 BD01 LVDS I/O Mode VCC VDD VDDLBYP OVDD LTC2353-18 2.5V REGULATOR SDO+ SDO- BUFFERS IN0- S/H IN1+ IN1- S/H SCKO+ 2-CHANNEL MULTIPLEXER IN0+ 18-BIT SAR ADC 18 BITS LVDS SERIAL I/O INTERFACE SCKO- SDI+ SDI- SCKI+ SCKI- CS 2.048V REFERENCE VEE GND 20k REFERENCE BUFFER 2x REFIN REFBUF CONTROL LOGIC BUSY CNV PD LVDS/CMOS 235318 BD02 235318f For more information www.linear.com/LTC2353-18 17 LTC2353-18 TIMING DIAGRAM CMOS I/O Mode CS = PD = 0 SAMPLE N SAMPLE N + 1 CNV CONVERT BUSY ACQUIRE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCKI DON'T CARE SDI S5 S4 S3 S2 S1 S0 SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1 SCKO DON'T CARE SDO0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C0 SS2 SS1 SS0 D17 SoftSpan CONVERSION RESULT CHANNEL ID CHANNEL 0 CONVERSION N SDO1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 DON'T CARE CONVERSION RESULT CHANNEL 1 CONVERSION N 0 C0 SS2 SS1 SS0 D17 CONVERSION RESULT SoftSpan CHANNEL 1 CONVERSION N CONVERSION RESULT CHANNEL ID CHANNEL 0 CONVERSION N 235318 TD01 LVDS I/O Mode CS = PD = 0 SAMPLE N+1 SAMPLE N CNV (CMOS) BUSY (CMOS) CONVERT SCKI (LVDS) SDI DON'T CARE (LVDS) ACQUIRE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 42 43 44 45 46 47 48 S5 S4 S3 S2 S1 S0 SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1 SCKO (LVDS) SDO (LVDS) DON'T CARE D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONVERSION RESULT CHANNEL 0 CONVERSION N 0 0 C0 SS2 SS1 SS0 D17 D16 D15 D0 0 SoftSpan CHANNEL ID CHANNEL 1 CONVERSION N 0 C0 SS2 SS1 SS0 D17 SoftSpan CHANNEL ID CONVERSION RESULT CHANNEL 0 CONVERSION N 235318 TD02 235318f 18 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION OVERVIEW CONVERTER OPERATION The LTC2353-18 is an 18-bit, low noise 2-channel simultaneous sampling successive approximation register (SAR) ADC with buffered differential, wide common mode range picoamp inputs. The ADC operates from a 5V low voltage supply and flexible high voltage supplies, nominally 15V. Using the integrated low-drift reference and buffer (VREFBUF = 4.096V nominal), both channels of this SoftSpan ADC can be independently configured on a conversion-by-conversion basis to accept 10.24V, 0V to 10.24V, 5.12V, or 0V to 5.12V signals. The input signal range may be expanded up to 12.5V using an external 5V reference. One channel may also be disabled to increase throughput on the other channel. The LTC2353-18 operates in two phases. During the acquisition phase, the sampling capacitors in both channels' sample-and-hold (S/H) circuit connect to their respective analog input buffers, which track the differential analog input voltage (VIN+ - VIN-). A rising edge on the CNV pin transitions both channels' S/H circuits from track mode to hold mode, simultaneously sampling the input signals on both channels and initiating a conversion. During the conversion phase, both channels' sampling capacitors are connected, one channel at a time, to an 18-bit charge redistribution capacitor D/A converter (CDAC). The CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input voltage with binary-weighted fractions of the channel's SoftSpan full-scale range (e.g., VFSR/2, VFSR/4 ... VFSR/262144) using a differential comparator. At the end of this process, the CDAC output approximates the channel's sampled analog input. Once both channels have been converted in this manner, the ADC control logic prepares the 18-bit digital output codes from each channel for serial transfer. The integrated picoamp-input analog buffers, wide input common mode range, and 124dB CMRR of the LTC235318 allow the ADC to directly digitize a variety of signals using minimal board space and power. This input signal flexibility, combined with 3.5LSB INL, no missing codes at 18 bits, and 96.4dB SNR, makes the LTC2353-18 an ideal choice for many high voltage applications requiring wide dynamic range. The absolute common mode input range (VEE + 4V to VCC - 4V) is determined by the choice of high voltage supplies. These supplies may be biased asymmetrically around ground and include the ability for VEE to be tied directly to ground. The LTC2353-18 supports pin-selectable SPI CMOS (1.8V to 5V) and LVDS serial interfaces, enabling it to communicate equally well with legacy microcontrollers and modern FPGAs. In CMOS mode, applications may employ either one or two lanes of serial output data, allowing the user to optimize bus width and data throughput. The LTC2353-18 typically dissipates 195mW when converting two channels simultaneously at 550ksps per channel. Optional nap and power down modes may be employed to further reduce power consumption during inactive periods. TRANSFER FUNCTION The LTC2353-18 digitizes each channel's full-scale voltage range into 218 levels. In conjunction with the ADC master reference voltage, VREFBUF, a channel's SoftSpan configuration determines its input voltage range, full-scale range, LSB size, and the binary format of its conversion result, as shown in Tables 1a and 1b. For example, employing the internal reference and buffer (VREFBUF = 4.096V nominal), SoftSpan 7 configures a channel to accept a 10.24V bipolar analog input voltage range, which corresponds to a 20.48V full-scale range with a 78.125V LSB. Other SoftSpan configurations and reference voltages may be employed to convert both larger and smaller bipolar and unipolar input ranges. Conversion results are output in two's complement binary format for all bipolar SoftSpan ranges, and in straight binary format for all unipolar 235318f For more information www.linear.com/LTC2353-18 19 LTC2353-18 APPLICATIONS INFORMATION OUTPUT CODE (TWO'S COMPLEMENT) SoftSpan ranges. The ideal two's complement transfer function is shown in Figure 2, while the ideal straight binary transfer function is shown in Figure 3. 011...111 BIPOLAR ZERO 011...110 000...001 000...000 111...111 111...110 100...001 FSR = +FS - -FS 1LSB = FSR/262144 100...000 -FSR/2 -1 0V 1 FSR/2 - 1LSB LSB LSB INPUT VOLTAGE (V) 235318 F02 OUTPUT CODE (STRAIGHT BINARY) Figure 2. LTC2353-18 Two's Complement Transfer Function 111...111 111...110 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 000...001 FSR = +FS 1LSB = FSR/262144 000...000 0V FSR - 1LSB INPUT VOLTAGE (V) 235318 F03 LTC2353-18 enables it to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudo-differential unipolar, pseudo-differential true bipolar, and fully differential, simplifying signal chain design. For conversion of signals extending to VEE, the unbuffered LTC2348-18 ADC is recommended. The wide operating range of the high voltage supplies offers further input common mode flexibility. As long as the voltage difference limits of 10V (VCC - VEE) 38V are observed, VCC and VEE may be independently biased anywhere within their own individually allowed operating ranges, including the ability for VEE to be tied directly to ground. This feature enables the common mode input range of the LTC2353-18 to be tailored to specific application requirements. In all SoftSpan ranges, each channel's analog inputs can be modeled by the equivalent circuit shown in Figure 4. At the start of acquisition, the sampling capacitors (CSAMP) connect to the integrated buffers BUFFER+/BUFFER- through the sampling switches. The sampled voltage is reset during the conversion process and is therefore re-acquired for each new conversion. The diodes between the inputs and the VCC and VEE supplies provide input ESD protection. While within the supply voltages, the analog inputs of the LTC2353-18 draw only 5pA typical DC leakage current and the ESD protection diodes don't turn on. This offers a significant advantage over external op amp buffers, which often have diode protection that turns on during transients and corrupts the voltage on any filter capacitors at their inputs. Figure 3. LTC2353-18 Straight Binary Transfer Function VCC BUFFER+ BUFFERED ANALOG INPUTS IN+ Each channel of the LTC2353-18 simultaneously samples the voltage difference (VIN+ - VIN-) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode rejection ratio (CMRR) of the ADC. Wide common mode input range coupled with high CMRR allows the IN+/IN- analog inputs to swing with an arbitrary relationship to each other, provided both pins remain between (VEE + 4V) and (VCC - 4V). This feature of the RSAMP 750 CSAMP 30pF VEE VCC BUFFER- IN- RSAMP 750 CSAMP 30pF BIAS VOLTAGE 235318 F04 VEE Figure 4. Equivalent Circuit for Differential Analog Inputs, Single Channel Shown 235318f 20 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION Bipolar SoftSpan Input Ranges For channels configured in SoftSpan ranges 7, 6, 3, or 2, the LTC2353-18 digitizes the differential analog input voltage (VIN+ - VIN-) over a bipolar span of 2.5 * VREFBUF, 2.5 * VREFBUF/1.024, 1.25 * VREFBUF, or 1.25 * VREFBUF/1.024, respectively, as shown in Table 1a. These SoftSpan ranges are useful for digitizing input signals where IN+ and IN- swing above and below each other. Traditional examples include fully differential input signals, where IN+ and IN- are driven 180 degrees outof-phase with respect to each other centered around a common mode voltage (VIN+ + VIN-)/2, and pseudodifferential true bipolar input signals, where IN+ swings above and below a ground reference level, driven on IN-. Regardless of the chosen SoftSpan range, the wide common mode input range and high CMRR of the IN+/IN- analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between (VCC - 4V) and (VEE + 4V). The output data format for all bipolar SoftSpan ranges is two's complement. Unipolar SoftSpan Input Ranges For channels configured in SoftSpan ranges 5, 4, or 1, the LTC2353-18 digitizes the differential analog input voltage (VIN+ - VIN-) over a unipolar span of 0V to 2.5 * VREFBUF, 0V to 2.5 * VREFBUF/1.024, or 0V to 1.25 * VREFBUF, respectively, as shown in Table 1a. These SoftSpan ranges are useful for digitizing input signals where IN+ remains above IN-. A traditional example includes pseudo-differential unipolar input signals, where IN+ swings above a ground reference level, driven on IN-. Regardless of the chosen SoftSpan range, the wide common mode input range and high CMRR of the IN+/IN- analog inputs allow them to swing with an arbitrary relationship to each other, provided each pin remains between (VCC - 4V) and (VEE + 4V). The output data format for all unipolar SoftSpan ranges is straight binary. INPUT DRIVE CIRCUITS The CMOS buffer input stage offers a very high degree of transient isolation from the sampling process. Most sensors, signal conditioning amplifiers and filter networks with less than 10k of impedance can drive the passive 3pF analog input capacitance directly. For higher impedances and slow-settling circuits, add a 680pF capacitor at the pins to maintain the full DC accuracy of the LTC2353-18. The very high input impedance of the unity gain buffers in the LTC2353-18 greatly reduces the input drive requirements and makes it possible to include optional RC filters with k impedance and arbitrarily slow time constants for anti-aliasing or other purposes. Micropower op amps with limited drive capability are also well suited to drive the high impedance analog inputs directly. The LTC2353-18 features proprietary circuitry to achieve exceptional internal crosstalk isolation between channels (-121dB typical). The PC board wiring to the analog inputs should be short and shielded to prevent external capacitive crosstalk between channels. The capacitance between adjacent package pins is 0.16pF. Low source resistance and/or high source capacitance help reduce external capacitively coupled crosstalk. Single ended input drive also enjoys additional external crosstalk isolation because every other input pin is grounded, or at a low impedance DC source, and serves as a shield between channels. INPUT OVERDRIVE TOLERANCE Driving an analog input above VCC on any channel up to 10mA will not affect conversion results on other channels. Approximately 70% of this overdrive current will flow out of the VCC pin and the remaining 30% will flow out of VEE. This current flowing out of VEE will produce heat across the VCC - VEE voltage drop and must be taken into account for the total Absolute Maximum power dissipation of 500mW. Driving an analog input below VEE may corrupt conversion results on other channels. This product can handle input currents of up to 100mA below VEE or above VCC without latch-up. Keep in mind that driving the inputs above VCC or below VEE may reverse the normal current flow from the external power supplies driving these pins. 235318f For more information www.linear.com/LTC2353-18 21 LTC2353-18 APPLICATIONS INFORMATION Input Filtering The true high impedance analog inputs can accommodate a very wide range of passive or active signal conditioning filters. The buffered ADC inputs have an analog bandwidth of 6MHz, and impose no particular bandwidth requirement on external filters. The external input filters can therefore be optimized independent of the ADC to reduce signal chain noise and interference. A common filter configuration is the simple anti-aliasing and noise reducing RC filter with its pole at half the sampling frequency. For example, 275ksps with R=845 and C=680pF as shown in Figure 5. IN+ 0V R = 845 -10V +10V 680pF UNIPOLAR 0V -10V 15V OPTIONAL LOWPASS FILTER TRUE BIPOLAR +10V 0.1F IN0+ IN0- VCC LTC2353-18 IN- VEE REFBUF 0.1F REFIN 47F 0.1F -15V ONLY CHANNEL 0 SHOWN FOR CLARITY 235318 F05 Figure 5. Filtering Single-Ended Input Signals High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO/COG and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Arbitrary and Fully Differential Analog Input Signals The wide common mode input range and high CMRR of the LTC2353-18 allow each channel's IN+ and IN- pins to swing with an arbitrary relationship to each other, provided each pin remains between (VCC - 4V) and (VEE + 4V). This feature of the LTC2353-18 enables it to accept a wide variety of signal swings, simplifying signal chain design. The two-tone test shown in Figure 6b demonstrates the arbitrary input drive capability of the LTC2353-18. This test simultaneously drives IN+ with a -7dBFS 2kHz single-ended sine wave and IN- with a -7dBFS 3.1kHz single-ended sine wave. Together, these signals sweep the analog inputs across a wide range of common mode and differential mode voltage combinations, similar to the more general arbitrary input signal case. They also have a simple spectral representation. An ideal differential converter with no common-mode sensitivity will digitize this signal as two -7dBFS spectral tones, one at each sine wave frequency. The FFT plot in Figure 6b demonstrates the LTC2353-18 response approaches this ideal, with 121dB of SFDR limited by the converter's second harmonic distortion response to the 3.1kHz sine wave on IN-. The ability of the LTC2353-18 to accept arbitrary signal swings over a wide input common mode range with high CMRR can simplify application solutions. In practice, many sensors produce a differential sensor voltage riding on top of a large common mode signal. Figure 7a depicts one way of using the LTC2353-18 to digitize signals of this type. The amplifier stage provides a differential gain of approximately 10V/V to the desired sensor signal while the unwanted common mode signal is attenuated by the ADC CMRR. The circuit employs the 5V SoftSpan range of the ADC. Figure 7b shows measured CMRR performance of this solution, which is competitive with the best commercially available instrumentation amplifiers. Figure 7c shows measured AC performance of this solution. In Figure 8, another application circuit is shown which uses both channels of the LTC2353-18 to simultaneously sense the voltage and bidirectional current through a sense resistor over a wide common mode range. 235318f 22 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION +10V ARBITRARY 0V 0V -10V -5V TRUE BIPOLAR +10V 15V FULLY DIFFERENTIAL +5V +10V 0V 0V -10V -10V 0.1F IN+ UNIPOLAR VCC IN0+ IN0- LTC2353-18 IN- VEE REFBUF REFIN 0.1F 47F 0.1F -15V ONLY CHANNEL 0 SHOWN FOR CLARITY 235318 F06a Figure 6a. Input Arbitrary, Fully Differential, True Bipolar, and Unipolar Signals Arbitrary Drive 0 10.24V RANGE SFDR = 121dB SNR = 96.4dB -20 -60 -80 -100 6.2kHz -120 -40 -60 -80 -100 -120 -140 -140 -160 -160 -180 0 55 110 165 FREQUENCY (kHz) 220 10.24V RANGE SNR = 96.3dB THD = -113dB SINAD = 96.3dB SFDR = 116dB -20 AMPLITUDE (dBFS) -40 AMPLITUDE (dBFS) Fully Differential Drive 0 -180 275 0 55 110 165 FREQUENCY (kHz) 220 235318 F06c 235318 F06b Figure 6b. Two-Tone Test. IN+ = -7dBFS 2kHz Sine, IN- = -7dBFS 3.1kHz Sine, 32k Point FFT, fSMPL = 550ksps. Circuit Shown in Figure 6a Figure 6c. IN+/IN- = -1dBFS 2kHz Fully Differential Sine, VCM = 0V, 32k Point FFT, fSMPL = 550ksps. Circuit Shown in Figure 6a True Bipolar Drive 10.24V RANGE SNR = 96.3dB THD = -111dB SINAD = 96.2dB SFDR = 113dB -20 -40 AMPLITUDE (dBFS) Unipolar Drive -60 -80 -100 -120 0 -40 -60 -80 -100 -120 -140 -140 -160 -160 -180 0 55 110 165 FREQUENCY (kHz) 220 275 0V TO 10.24V RANGE SNR = 90.6dB THD = -114dB SINAD = 90.6dB SFDR = 117dB -20 AMPLITUDE (dBFS) 0 275 -180 0 235318 F06d Figure 6d. IN+ = -1dBFS 2kHz True Bipolar Sine, IN- = 0V, 32k Point FFT, fSMPL = 550ksps. Circuit Shown in Figure 6a 55 110 165 FREQUENCY (kHz) 220 275 235318 F06e Figure 6e. IN+ = -1dBFS 2kHz Unipolar Sine, IN- = 0V, 32k Point FFT, fSMPL = 550ksps. Circuit Shown in Figure 6a 235318f For more information www.linear.com/LTC2353-18 23 LTC2353-18 APPLICATIONS INFORMATION ARBITRARY IN+ 24V + - 31V INTERNAL HI-Z BUFFERS ALLOW OPTIONAL LTC2057HV k PASSIVE FILTERS 3.65k BUFFERED ANALOG INPUTS 2.49k COMMON MODE INPUT RANGE 31V 549 2.2nF GAIN = 10 2.49k 0.1F LTC2353-18 3.65k DIFFERENTIAL MODE INPUT RANGE: 500mV 0V IN- - + VCC IN0+ IN0- VEE REFBUF BW = 10kHz LTC2057HV 0.1F 47F 0.1F -7V ONLY CHANNEL 0 SHOWN FOR CLARITY REFIN 235318 F07a -7V Figure 7a. Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs 160 0 5V RANGE 150 140 AMPLITUDE (dBFS) CMRR (dB) SNR = 91.5dB THD = -105dB SINAD = 91.3dB SFDR = 107dB -40 130 120 110 100 IN+ = IN- = 5VP-P SINE 90 -60 -80 -100 -120 80 -140 70 -160 60 5V RANGE FULLY DIFFERENTIAL DRIVE (IN- = -IN+) -20 10 100 1k FREQUENCY (Hz) -180 10k 0 235318 F07b 55 110 165 FREQUENCY (kHz) 220 275 235318 F07c Figure 7c. IN+/IN- = 450mV 200Hz Fully Differential Sine, 0V VCM 24V, 32k Point FFT, fSMPL = 550ksps. Circuit Shown in Figure 7a Figure 7b. CMRR vs Input Frequency. Circuit Shown in Figure 7a 15V 0.1F VS1 RSENSE ISENSE VCC IN0+ IN0- IN1+ IN1- LTC2353-18 VEE REFBUF VS2 0.1F REFIN 47F -15V V - VS2 ISENSE = S1 RSENSE 0.1F 235318 F08 -10.24V VS1 10.24V -10.24V VS2 10.24V Figure 8. Simultaneously Sense Voltage (CH0) and Current (CH1) Over a Wide Common Mode Range 235318f 24 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION ADC REFERENCE LTC2353-18 REFIN As shown previously in Table 1b, the LTC2353-18 supports three reference configurations. The first uses both the internal bandgap reference and reference buffer. The second externally overdrives the internal reference but retains the internal buffer, which isolates the external reference from ADC conversion transients. This configuration is ideal for sharing a single precision external reference across multiple ADCs. The third disables the internal buffer and overdrives the REFBUF pin externally. REFBUF REFERENCE BUFFER 6.5k 47F 6.5k GND 235318 F09a Figure 9a. Internal Reference with Internal Buffer Configuration LTC2353-18 REFIN 20k BANDGAP REFERENCE 2.7F REFBUF 47F LTC6655-2.048 REFERENCE BUFFER 6.5k 6.5k GND 235318 F09b Figure 9b. External Reference with Internal Buffer Configuration LTC2353-18 REFIN External Reference with Internal Buffer If more accuracy and/or lower drift is desired, REFIN can be easily overdriven by an external reference since 20k of resistance separates the internal bandgap reference output from the REFIN pin, as shown in Figure 9b. The valid range of external reference voltage overdrive on the REFIN pin is 1.25V to 2.2V, resulting in converter master reference voltages VREFBUF between 2.5V and 4.4V, respectively. Analog Devices offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power, and high accuracy, the LTC6655-2.048 is well suited for use with the LTC2353-18 when overdriving the internal BANDGAP REFERENCE 0.1F Internal Reference with Internal Buffer The LTC2353-18 has an on-chip, low noise, low drift (20ppm/C maximum), temperature compensated bandgap reference that is factory trimmed to 2.048V. The reference output connects through a 20k resistor to the REFIN pin, which serves as the input to the on-chip reference buffer, as shown in Figure 9a. When employing the internal bandgap reference, the REFIN pin should be bypassed to GND (Pin 20) close to the pin with a 0.1F ceramic capacitor to filter wideband noise. The reference buffer amplifies VREFIN to create the converter master reference voltage VREFBUF = 2 * VREFIN on the REFBUF pin, nominally 4.096V when using the internal bandgap reference. Bypass REFBUF to GND (Pin 20) close to the pin with at least a 47F ceramic capacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to compensate the reference buffer, absorb transient conversion currents, and minimize noise. 20k REFBUF LTC6655-5 47F 20k BANDGAP REFERENCE REFERENCE BUFFER 6.5k 6.5k GND 235318 F09c Figure 9c. External Reference with Disabled Internal Buffer Configuration 235318f For more information www.linear.com/LTC2353-18 25 LTC2353-18 APPLICATIONS INFORMATION External Reference with Disabled Internal Buffer The internal reference buffer supports VREFBUF = 4.4V maximum. By grounding REFIN, the internal buffer may be disabled allowing REFBUF to be overdriven with an external reference voltage between 2.5V and 5V, as shown in Figure 9c. Maximum input signal swing and SNR are achieved by overdriving REFBUF using an external 5V reference. The buffer feedback resistors load the REFBUF pin with 13k even when the reference buffer is disabled. The LTC6655-5 offers the same small size, accuracy, drift, and extended temperature range as the LTC6655-2.048, and achieves a typical SNR of 97.9dB when paired with the LTC2353-18. Bypass the LTC6655-5 to GND (Pin 20) close to the REFBUF pin with at least a 47F ceramic capacitor (X7R, 10V, 1210 size or X5R, 10V, 0805 size) to absorb transient conversion currents and minimize noise. The LTC2353-18 converter draws a charge (QCONV) from the REFBUF pin during each conversion cycle. On short time scales most of this charge is supplied by the external REFBUF bypass capacitor, but on longer time scales all of the charge is supplied by either the reference buffer, or when the internal reference buffer is disabled, the external reference. This charge draw corresponds to a DC current equivalent of IREFBUF = QCONV * fSMPL, which is proportional to sample rate. In applications where a burst of samples is taken after idling for long periods of time, as shown in Figure 10, IREFBUF quickly transitions from approximately 0.4mA to 1.2mA (VREFBUF = 5V, fSMPL = 550ksps). This current step triggers a transient response in the external reference that must be considered, since any deviation in VREFBUF affects converter accuracy. If an external reference is used to overdrive REFBUF, the fast settling LTC6655 family of references is recommended. Internal Reference Buffer Transient Response For optimum performance in applications employing burst sampling, the external reference with internal reference buffer configuration should be used. The internal reference buffer incorporates a proprietary design that minimizes movements in VREFBUF when responding to a burst of conversions following an idle period. Figure 11 compares the burst conversion response of the LTC235318 with an input near full scale for two reference configurations. The first configuration employs the internal reference buffer with REFIN externally overdriven by an LTC6655-2.048, while the second configuration disables the internal reference buffer and overdrives REFBUF with an external LTC6655-4.096. In both cases REFBUF is bypassed to GND with a 47F ceramic capacitor. 20 DEVIATION FROM FINAL VALUE (LSB) reference. The LTC6655-2.048 offers 0.025% (maximum) initial accuracy and 2ppm/C (maximum) temperature coefficient for high precision applications. The LTC66552.048 is fully specified over the H-grade temperature range, complementing the extended temperature range of the LTC2353-18 up to 125C. Bypassing the LTC66552.048 with a 2.7F to 100F ceramic capacitor close to the REFIN pin is recommended. 10.24V RANGE IN+ = 10V IN- = 0V 15 10 EXTERNAL REFERENCE ON REFBUF 5 0 INTERNAL REFERENCE BUFFER -5 0 100 200 300 TIME (s) 400 500 235318 F11 Figure 11. Burst Conversion Response of the LTC2353-18, fSMPL = 550ksps CNV IDLE PERIOD IDLE PERIOD 235318 F10 Figure 10. CNV Waveform Showing Burst Sampling 235318f 26 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION Fast Fourier transform (FFT) techniques are used to test the ADC's frequency response, distortion, and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. The LTC2353-18 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies below half the sampling frequency, excluding DC. Figure 12 shows that the LTC2353-18 achieves a typical SINAD of 96.2dB in the 10.24V range at a 550ksps sampling rate with a true bipolar 2kHz input signal. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 12 shows that the LTC2353-18 achieves a typical SNR of 96.3dB in the 10.24V range at a 550ksps sampling rate with a true bipolar 2kHz input signal. Total Harmonic Distortion (THD) Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD = 20 log V22 + V32 + V42 ...VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics, respectively. Figure 12 shows that the LTC2353-18 achieves a typical THD of -111dB (N = 6) in the 10.24V range at a 550ksps sampling rate with a true bipolar 2kHz input signal. 0 10.24V RANGE TRUE BIPOLAR DRIVE (IN- = 0V) -20 -40 AMPLITUDE (dBFS) DYNAMIC PERFORMANCE SNR = 96.3dB THD = -111dB SINAD = 96.2dB SFDR = 113dB -60 -80 -100 -120 -140 -160 -180 0 55 110 165 FREQUENCY (kHz) 220 275 235318 F12 Figure 12. 32k Point FFT fSMPL = 550ksps, fIN = 2kHz POWER CONSIDERATIONS The LTC2353-18 requires four power supplies: the positive and negative high voltage power supplies (VCC and VEE), the 5V core power supply (VDD) and the digital input/ output (I/O) interface power supply (OVDD). As long as the voltage difference limits of 10V VCC - VEE 38V are observed, VCC and VEE may be independently biased anywhere within their own individual allowed operating ranges, including the ability for VEE to be tied directly to ground. This feature enables the common mode input range of the LTC2353-18 to be tailored to the specific application's requirements. The flexible OVDD supply allows the LTC2353-18 to communicate with CMOS logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. When using LVDS I/O mode, the range of OVDD is 2.375V to 5.25V. Power Supply Sequencing The LTC2353-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC235318 has an internal power-on-reset (POR) circuit which 235318f For more information www.linear.com/LTC2353-18 27 LTC2353-18 APPLICATIONS INFORMATION resets the converter on initial power-up and whenever VDD drops below 2V. Once the supply voltage re-enters the nominal supply voltage range, the POR reinitializes the ADC. No conversions should be initiated until at least 10ms after a POR event to ensure the initialization period has ended. When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results. TIMING AND CONTROL CNV Timing The LTC2353-18 sampling and conversion is controlled by CNV. A rising edge on CNV transitions both channels' S/H circuits from track mode to hold mode, simultaneously sampling the input signals on both channels and initiating a conversion. Once a conversion has been started, it cannot be terminated early except by resetting the ADC, as discussed in the Reset Timing section. For optimum performance, drive CNV with a clean, low jitter signal and avoid transitions on data I/O lines leading up to the rising edge of CNV. Additionally, to minimize channelto-channel crosstalk, avoid high slew rates on the analog inputs for 100ns before and after the rising edge of CNV. Converter status is indicated by the BUSY output, which transitions low-to-high at the start of each conversion and stays high until the conversion is complete. Once CNV is brought high to begin a conversion, it should be returned low between 40ns and 60ns later or after the falling edge of BUSY to minimize external disturbances during the internal conversion process. The CNV timing required to take advantage of the reduced power nap mode of operation is described in the Nap Mode section. Internal Conversion Clock The LTC2353-18 has an internal clock that is trimmed to achieve a maximum conversion time of 550*N ns with N channels enabled. With a minimum acquisition time of 685ns when converting both channels simultaneously, throughput performance of 550ksps is guaranteed without any external adjustments. Also note that the minimum acquisition time varies with sampling frequency (fSMPL) and the number of enabled channels. Nap Mode The LTC2353-18 can be placed into nap mode after a conversion has been completed to reduce power consumption between conversions. In this mode a portion of the device circuitry is turned off, including circuits associated with sampling the analog input signals. Nap mode is enabled by keeping CNV high between conversions, as shown in Figure 13. To initiate a new conversion after entering nap mode, bring CNV low and hold for at least 750ns before bringing it high again. The converter acquisition time (tACQ) is set by the CNV low time (tCNVL) when using nap mode. Power Down Mode When PD is brought high, the LTC2353-18 is powered down and subsequent conversion requests are ignored. If this occurs during a conversion, the device powers down t CNVL CNV tCONV BUSY NAP NAP MODE tACQ 235318 F13 Figure 13. Nap Mode Timing for the LTC2353-18 235318f 28 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION reduced, as shown in Figure 15. This decrease in average power dissipation occurs because a portion of the LTC2353-18 circuitry is turned off during nap mode, and the fraction of the conversion cycle (tCYC) spent napping increases as the sampling frequency (fSMPL) is decreased. 16 WITH NAP MODE 14 tCNVL = 780ns 12 SUPPLY CURRENT (mA) once the conversion completes. In this mode, the device draws only a small regulator standby current resulting in a typical power dissipation of 0.60mW. To exit power down mode, bring the PD pin low and wait at least 10ms before initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results. Reset Timing A global reset of the LTC2353-18, equivalent to a poweron-reset event, may be executed without needing to cycle the supplies. This feature is useful when recovering from system-level events that require the state of the entire system to be reset to a known synchronized value. To initiate a global reset, bring PD high twice without an intervening conversion, as shown in Figure 14. The reset event is triggered on the second rising edge of PD, and asynchronously ends based on an internal timer. Reset clears all serial data output registers and restores the internal SoftSpan configuration register default state of all channels in SoftSpan 7. If reset is triggered during a conversion, the conversion is immediately halted. The normal power down behavior associated with PD going high is not affected by reset. Once PD is brought low, wait at least 10ms before initiating a conversion. When employing the internal reference buffer, allow 200ms for the buffer to power up and recharge the REFBUF bypass capacitor. Any conversion initiated before these times will produce invalid results. Power Dissipation vs Sampling Frequency When nap mode is employed, the power dissipation of the LTC2353-18 decreases as the sampling frequency is 10 IVDD 8 6 4 IVCC 2 0 IOVDD -2 -4 -6 IVEE 0 110 220 330 440 SAMPLING FREQUENCY (kHz) 550 235318 F15 Figure 15. Power Dissipation of the LTC2353-18 Decreases with Decreasing Sampling Frequency DIGITAL INTERFACE The LTC2353-18 features CMOS and LVDS serial interfaces, selectable using the LVDS/CMOS pin. The flexible OVDD supply allows the LTC2353-18 to communicate with any CMOS logic operating between 1.8V and 5V, including 2.5V and 3.3V systems, while the LVDS interface supports low noise digital designs. In CMOS mode, applications may employ either one or two lanes of serial data output, allowing the user to optimize bus width and data throughput. Together, these I/O interface options enable the LTC2353-18 to communicate equally well with legacy microcontrollers and modern FPGAs. tPDH t WAKE PD CNV BUSY RESET tPDL tCNVH tCONV SECOND RISING EDGE OF PD TRIGGERS RESET RESET TIME SET INTERNALLY 235318 F14 Figure 14. Reset Timing for the LTC2353-18 235318f For more information www.linear.com/LTC2353-18 29 LTC2353-18 APPLICATIONS INFORMATION CS = PD = 0 SAMPLE N tCNVH tCNVL CNV tCONV BUSY tACQ tBUSYLH RECOMMENDED DATA TRANSACTION WINDOW tSSDISCKI SCKI SDI SAMPLE N + 1 tCYC tSCKI 1 S5 DON'T CARE 2 3 4 5 6 7 8 tHSDISCKI tQUIET tSCKIH 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 tSCKIL S4 S3 S2 S1 S0 SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1 tDSDOBUSYL tHSDOSCKI tSKEW SCKO tDSDOSCKI SDO0 DON'T CARE D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C0 SS2 SS1 SS0 D17 CONVERSION RESULT SoftSpan CHANNEL 0 24-BIT PACKET CONVERSION N SDO1 DON'T CARE D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONVERSION RESULT CHANNEL 1 24-BIT PACKET CONVERSION N CONVERSION RESULT CHANNEL ID 0 CHANNEL 1 24-BIT PACKET CONVERSION N 0 C0 SS2 SS1 SS0 D17 SoftSpan CHANNEL ID CONVERSION RESULT CHANNEL 0 24-BIT PACKET CONVERSION N 235318 F16 Figure 16. Serial CMOS I/O Mode Serial CMOS I/O Mode As shown in Figure 16, in CMOS I/O mode the serial data bus consists of a serial clock input, SCKI, serial data input, SDI, serial clock output, SCKO, and two lanes of serial data output, SDO0 and SDO1. Communication with the LTC2353-18 across this bus occurs during predefined data transaction windows. Within a window, the device accepts 6-bit SoftSpan configuration words for the next conversion on SDI and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on SDO0 and SDO1. New data transaction windows open 10ms after powering up or resetting the LTC2353-18, and at the end of each conversion on the falling edge of BUSY. In the recommended use case, the data transaction should be completed with a minimum tQUIET time of 20ns prior to the start of the next conversion, as shown in Figure 16. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. It is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. Just prior to the falling edge of BUSY and the opening of a new data transaction window, SCKO is forced low and SDO0 and SDO1 are updated with the latest conversion results from analog input channels 0 and 1, respectively. Rising edges on SCKI serially clock conversion results and analog input channel configuration information out on SDO0 and SDO1 and trigger transitions on SCKO that are skew-matched to the data on SDO0 and SDO1. The resulting SCKO frequency is half that of SCKI. SCKI rising edges also latch SoftSpan configuration words provided on SDI, 235318f 30 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION which are used to program the internal 6-bit SoftSpan configuration register. See the section Programming the SoftSpan Configuration Register in CMOS I/O Mode for further details. SCKI is allowed to idle either high or low in CMOS I/O mode. As shown in Figure 17, the CMOS bus is enabled when CS is low and is disabled and Hi-Z when CS is high, allowing the bus to be shared across multiple devices. The data on SDO0 and SDO1 are grouped into 24-bit packets consisting of an 18-bit conversion result, followed by two zeros, 1-bit analog channel ID, and 3-bit SoftSpan code, all presented MSB first. As suggested in Figures 16 and 17, each SDO lane outputs these packets for both analog input channels in a sequential, alternating manner. For example, SDO0 first outputs the 24-bit packet corresponding to analog input channel 0, then outputs the packet for channel 1, then continues to alternate between packets for channels 0 and 1. Likewise, SDO1 has the same alternating pattern as SDO0, but starting with the output for channel 1. When interfacing the LTC2353-18 with a standard SPI bus, capture output data at the receiver on rising edges of SCKI. SCKO is not used in this case. Multiple SDO lanes are also usually not useful in this case. In other applications, such as interfacing the LTC2353-18 with an FPGA or CPLD, rising and falling edges of SCKO may be used to capture serial output data on SDO0 and SDO1 in double data rate (DDR) fashion. Capturing data using SCKO adds robustness to delay variations over temperature and supply. Two Lane Serial CMOS Output Data Capture As shown in Table 2, full 550ksps per channel throughput can be achieved with a 25MHz SCKI frequency by capturing the first packet (24 SCKI cycles total) from both serial data output lanes (SDO0 and SDO1). This configuration also allows conversion results from both channels to be captured using as few as 18 SCKI cycles if the 1-bit analog channel ID and 3-bit SoftSpan code are not needed. Two lane data capture is usually best suited for use with FPGA or CPLD capture hardware, but may be useful in other application-specific cases. PD = 0 BUSY CS SCKI DON'T CARE DON'T CARE NEW SoftSpan CONFIGURATION WORD (OVERWRITES INTERNAL CONFIG REGISTER) SDI DON'T CARE SCKO SDO0 TWELVE ALL-ZERO WORDS AND ONE PARTIAL WORD (INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE) DON'T CARE Hi-Z Hi-Z Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET (PARTIAL) tEN SDO1 Hi-Z Hi-Z t DIS CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET (PARTIAL) Hi-Z 235318 F17 Figure 17. Internal SoftSpan Configuration Register Behavior. Serial CMOS Bus Response to CS 235318f For more information www.linear.com/LTC2353-18 31 LTC2353-18 APPLICATIONS INFORMATION One Lane Serial CMOS Output Data Capture Applications that cannot accommodate two lanes of serial data capture may employ just one lane without reconfiguring the LTC2353-18. For example, capturing two packets (48 SCKI cycles total) from SDO0 or SDO1 provides data for both analog input channels. As shown in Table 2, full 550ksps per channel throughput can be achieved with a 74MHz SCKI frequency in the one lane case. The LTC2353-18 supports CMOS SCKI frequencies up to 100MHz. Programming the SoftSpan Configuration Register in CMOS I/O Mode The internal 6-bit SoftSpan configuration register controls the SoftSpan range for both analog input channels of the LTC2353-18. The default state of this register after power-up or resetting the device is all ones, configuring both channels to convert in SoftSpan 7, the 2.5 * VREFBUF range (see Table 1a). The state of this register may be modified by providing a new 6-bit SoftSpan configuration word on SDI during the data transaction window shown in Figure 16. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. Setting a channel's SoftSpan code to SS[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in tCONV on the next conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before starting the next conversion. The mapping between the serial SoftSpan configuration word, the internal SoftSpan configuration register, and each channel's 3-bit SoftSpan code is illustrated in Figure 18. If fewer than 6 SCKI rising edges are provided during a data transaction window, the partial word received on SDI will be ignored and the SoftSpan configuration register will not be updated. If exactly 6 SCKI rising edges are provided, the SoftSpan configuration register will be updated to match the received SoftSpan configuration Table 2. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Two Channels Enabled. Shaded Entries Denote Throughputs That Are Not Achievable in a Given Configuration. Calculated Using fSCKI = (Number of SCKI Cycles)/(t ACQ(MIN) - tQUIET ) I/O MODE CMOS LVDS NUMBER OF SDO LANES NUMBER OF SCKI CYCLES 2 REQUIRED fSCKI (MHz) TO ACHIEVE THROUGHPUT OF 275ksps/CHANNEL 137ksps/CHANNEL 550ksps/CHANNEL (tACQ = 685ns) (tACQ = 2500ns) (tACQ = 6130ns) 16 25 7 3 2 24 37 10 4 1 48 74 20 8 1 24 37 (74Mbps) 10 (20Mbps) 4 (8Mbps) 235318f 32 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION CMOS I/O MODE tSCKI SCKI SDI tSCKIH 1 DON'T CARE tSCKIL 2 S5 tSSDISCKI tHSDISCKI 3 S4 4 S3 5 S2 6 S1 S0 SoftSpan CONFIGURATION WORD LVDS I/O MODE tSCKI SCKI (LVDS) SDI (LVDS) DON'T CARE tHSDISCKI 1 2 tSCKIH tSCKIL S5 S4 3 4 5 6 tSSDISCKI S3 S2 S1 S0 SoftSpan CONFIGURATION WORD INTERNAL 6-BIT SoftSpan CONFIGURATION REGISTER (SAME FOR CMOS AND LVDS) 5 4 3 2 CHANNEL 1 SoftSpan CODE SS[2:0] 1 0 CHANNEL 0 SoftSpan CODE SS[2:0] 235318 F18 Figure 18. Mapping Between Serial SoftSpan Configuration Word, Internal SoftSpan Configuration Register, and SoftSpan Code for Each Analog Input Channel word, S[5:0]. The one exception to this behavior occurs when S[5:0] is all zeros. In this case, the SoftSpan configuration register will not be updated, allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 6 SCKI rising edges are provided during a data transaction window, each complete 6-bit word received on SDI will be interpreted as a new SoftSpan configuration word and applied to the SoftSpan configuration register as described above. Any partial words are ignored. Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 16 and 17. After the opening of a new data transaction window at the falling edge of BUSY, the user supplies a 6-bit SoftSpan configuration word on SDI during the first 6 SCKI cycles. This new word overwrites the internal configuration register contents following the 6th SCKI rising edge. The user then holds SDI low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional SCKI cycles applied. SoftSpan settings may be retained across multiple conversions by holding SDI low for the entire data transaction window, regardless of the number of SCKI cycles applied. Serial LVDS I/O Mode In LVDS I/O mode, information is transmitted using positive and negative signal pairs (LVDS+/LVDS-) with bits differentially encoded as (LVDS+ - LVDS-). These signals are typically routed using differential transmission lines with 100 characteristic impedance. Logical 1's and 0's are nominally represented by differential +350mV and -350mV, respectively. For clarity, all LVDS timing diagrams and interface discussions adopt the logical rather than physical convention. 235318f For more information www.linear.com/LTC2353-18 33 LTC2353-18 APPLICATIONS INFORMATION As shown in Figure 19, in LVDS I/O mode the serial data bus consists of a serial clock differential input, SCKI, serial data differential input, SDI, serial clock differential output, SCKO, and serial data differential output, SDO. Communication with the LTC2353-18 across this bus occurs during predefined data transaction windows. Within a window, the device accepts 6-bit SoftSpan configuration words for the next conversion on SDI and outputs 24-bit packets containing conversion results and channel configuration information from the previous conversion on SDO. New data transaction windows open 10ms after powering up or resetting the LTC2353-18, and at the end of each conversion on the falling edge of BUSY. In the recommended use case, the data transaction should be completed with a minimum tQUIET time of 20ns prior to the start of the next conversion, as shown in Figure 19. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. It is still possible to read conversion data after starting the next conversion, but this will degrade conversion accuracy and therefore is not recommended. Just prior to the falling edge of BUSY and the opening of a new data transaction window, SDO is updated with the latest conversion results from analog input channel 0. Both rising and falling edges on SCKI serially clock conversion results and analog input channel configuration information out on SDO. SCKI is also echoed on SCKO, skew-matched to the data on SDO. Whenever possible, it is recommended that rising and falling edges of SCKO be used to capture DDR serial output data on SDO, as this will yield the best robustness to delay variations over supply and temperature. SCKI rising and falling edges also latch SoftSpan configuration words provided on SDI, which are used to program the internal 6-bit SoftSpan configuration register. See the section Programming the SoftSpan Configuration Register in LVDS I/O Mode for further details. As shown in Figure 20, the LVDS bus is enabled when CS is low and is disabled and Hi-Z when CS = PD = 0 SAMPLE N + 1 SAMPLE N t CYC tCNVH CNV (CMOS) BUSY (CMOS) t CNVL tCONV t ACQ tBUSYLH RECOMMENDED DATA TRANSACTION WINDOW t SCKI SCKI (LVDS) 1 2 3 4 5 t HSDISCKI SDI (LVDS) DON'T CARE 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 41 42 43 44 45 46 47 48 t SCKIL t SSDISCKI S5 S4 S3 S2 S1 S0 t DSDOBUSYL SoftSpan CONFIGURATION WORD FOR CONVERSION N + 1 t SKEW t HSDOSCKI SCKO (LVDS) SDO (LVDS) 6 tQUIET t SCKIH t DSDOSCKI DON'T CARE D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 C0 SS2 SS1 SS0 D17 D16 D15 D0 0 CONVERSION RESULT CHANNEL 0 24-BIT PACKET CONVERSION N SoftSpan CHANNEL ID CHANNEL 1 24-BIT PACKET CONVERSION N 0 C0 SS2 SS1 SS0 D17 SoftSpan CHANNEL ID CONVERSION RESULT CHANNEL 0 24-BIT PACKET CONVERSION N 235318 F19 Figure 19. Serial LVDS I/O Mode 235318f 34 For more information www.linear.com/LTC2353-18 LTC2353-18 APPLICATIONS INFORMATION CS is high, allowing the bus to be shared across multiple devices. Due to the high speeds involved in LVDS signaling, LVDS bus sharing must be carefully considered. Transmission line limitations imposed by the shared bus may limit the maximum achievable bus clock speed. LVDS inputs are internally terminated with a 100 differential resistor when CS is low, while outputs must be differentially terminated with a 100 resistor at the receiver (FPGA). SCKI must idle in the low state in LVDS I/O mode, including when transitioning CS. The data on SDO are grouped into 24-bit packets consisting of an 18-bit conversion result, followed by two zeros, 1-bit analog channel ID, and 3-bit SoftSpan code, all presented MSB first. As suggested in Figures 19 and 20, SDO outputs these packets for both analog input channels in a sequential, alternating manner. For example, SDO first outputs the 24-bit packet corresponding to analog input channel 0, then outputs the packet for channel 1, then continues to alternate between packets for channels 0 and 1. Serial LVDS Output Data Capture As shown in Table 2, full 550ksps per channel throughput can be achieved with a 37MHz SCKI frequency by capturing two packets (24 SCKI cycles total) of DDR data from SDO. The LTC2353-18 supports LVDS SCKI frequencies up to 250MHz. Programming the SoftSpan Configuration Register in LVDS I/O Mode The internal 6-bit SoftSpan configuration register controls the SoftSpan range for both analog input channels of the LTC2353-18. The default state of this register after power-up or resetting the device is all ones, configuring both channels to convert in SoftSpan 7, the 2.5 * VREFBUF range (see Table 1a). The state of this register may be modified by providing a new 6-bit SoftSpan configuration word on SDI during the data transaction window shown in Figure 19. New SoftSpan configuration words are only accepted within this recommended data transaction window, but SoftSpan changes take effect immediately with no additional analog input settling time required before starting the next conversion. Setting a channel's SoftSpan code to SS[2:0] = 000 immediately disables the channel, resulting in a corresponding reduction in tCONV on the next conversion. Similarly, enabling a previously disabled channel requires no additional analog input settling time before starting the next conversion. The mapping between the serial SoftSpan configuration word, the internal PD = 0 BUSY (CMOS) CS (CMOS) tEN tDIS SCKI DON'T CARE (LVDS) SDI DON'T CARE (LVDS) SCKO (LVDS) SDO (LVDS) DON'T CARE NEW SoftSpan CONFIGURATION WORD (OVERWRITES INTERNAL CONFIG REGISTER) TWELVE ALL-ZERO WORDS AND ONE PARTIAL WORD (INTERNAL CONFIG REGISTER RETAINS CURRENT VALUE) DON'T CARE Hi-Z Hi-Z Hi-Z CHANNEL 0 PACKET CHANNEL 1 PACKET CHANNEL 0 PACKET CHANNEL 1 PACKET (PARTIAL) Hi-Z 235318 F20 Figure 20. Internal SoftSpan Configuration Register Behavior. Serial LVDS Bus Response to CS 235318f For more information www.linear.com/LTC2353-18 35 LTC2353-18 APPLICATIONS INFORMATION SoftSpan configuration register, and each channel's 3-bit SoftSpan code is illustrated in Figure 18. If fewer than 6 SCKI edges (rising plus falling) are provided during a data transaction window, the partial word received on SDI will be ignored and the SoftSpan configuration register will not be updated. If exactly 6 SCKI edges are provided, the SoftSpan configuration register will be updated to match the received SoftSpan configuration word, S[5:0]. The one exception to this behavior occurs when S[5:0] is all zeros. In this case, the SoftSpan configuration register will not be updated, allowing applications to retain the current SoftSpan configuration state by idling SDI low. If more than 6 SCKI edges are provided during a data transaction window, each complete 6-bit word received on SDI will be interpreted as a new SoftSpan configuration word and applied to the SoftSpan configuration register as described above. Any partial words are ignored. Typically, applications will update the SoftSpan configuration register in the manner shown in Figures 19 and 20. After the opening of a new data transaction window at the falling edge of BUSY, the user supplies a 6-bit DDR SoftSpan configuration word on SDI during the first 3 SCKI cycles. This new word overwrites the internal configuration register contents following the 3rd SCKI falling edge. The user then holds SDI low for the remainder of the data transaction window causing the register to retain its contents regardless of the number of additional SCKI cycles applied. SoftSpan settings may be retained across multiple conversions by holding SDI low for the entire data transaction window, regardless of the number of SCKI cycles applied. BOARD LAYOUT To obtain the best performance from the LTC2353-18, a four-layer printed circuit board (PCB) is recommended. Layout for the PCB should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Also minimize the length of the REFBUF to GND (Pin 20) bypass capacitor return loop, and avoid routing CNV near signals which could potentially disturb its rising edge. Supply bypass capacitors should be placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. A single solid ground plane is recommended for this purpose. When possible, screen the analog input traces using ground. Reference Design For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer to DC2365, the evaluation kit for the LTC2353-18. 235318f 36 For more information www.linear.com/LTC2353-18 LTC2353-18 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2353-18#packaging for the most recent package drawings. LX Package 48-Lead Plastic LQFP (7mm x 7mm) (Reference LTC DWG # 05-08-1760 Rev A) 7.15 - 7.25 9.00 BSC 5.50 REF 7.00 BSC 48 0.50 BSC 1 2 48 SEE NOTE: 4 1 2 9.00 BSC 5.50 REF 7.00 BSC 7.15 - 7.25 0.20 - 0.30 A A PACKAGE OUTLINE C0.30 - 0.50 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.60 1.35 - 1.45 MAX 11 - 13 R0.08 - 0.20 GAUGE PLANE 0.25 0 - 7 11 - 13 0.09 - 0.20 1.00 REF 0.50 BSC 0.17 - 0.27 0.05 - 0.15 0.45 - 0.75 SECTION A - A COMPONENT PIN "A1" TRAY PIN 1 BEVEL XXYY LTCXXXX LX-ES Q_ _ _ _ _ _ e3 NOTE: 1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE 2. DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT 4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 5. DRAWING IS NOT TO SCALE LX48 LQFP 0113 REV A PACKAGE IN TRAY LOADING ORIENTATION 235318f Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications For more information www.linear.com/LTC2353-18 subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 37 LTC2353-18 TYPICAL APPLICATION Amplify Differential Signals with Gain of 10 Over a Wide Common Mode Range with Buffered Analog Inputs ARBITRARY IN+ 24V + - 31V INTERNAL HI-Z BUFFERS ALLOW OPTIONAL LTC2057HV k PASSIVE FILTERS 3.65k BUFFERED ANALOG INPUTS 2.49k COMMON MODE INPUT RANGE 549 2.2nF GAIN = 10 2.49k 0.1F IN- - + VCC IN0+ IN0- LTC2353-18 3.65k DIFFERENTIAL MODE INPUT RANGE: 500mV 0V 31V VEE REFBUF LTC2057HV BW = 10kHz -7V ONLY CHANNEL 0 SHOWN FOR CLARITY 0.1F -7V 47F REFIN 0.1F 235318 TA02 RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC2358-18/LTC2358-16 Buffered 18-/16-Bit, 200ksps/Ch, 8-Channel Simultaneous Sampling, 3.5LSB/1LSB INL ADC LTC2357-18/LTC2357-16 Buffered 18-/16-Bit, 350ksps/Ch, 4-Channel Simultaneous Sampling, 3.5LSB/1LSB INL ADC LTC2341-18/LTC2341-16 18-/16-Bit, 666ksps/Ch, 2-Channel Simultaneous Sampling, 4LSB/1LSB INL, Serial ADC LTC2333-18/LTC2333-16 Buffered 18-/16-Bit, 800ksps, 8-Channel Multiplexed, 3LSB/1LSB INL, Serial ADC LTC2345-18/LTC2345-16 18-/16-Bit, 200ksps, 8-Channel Simultaneous Sampling, 5LSB/1.25LSB INL, Serial ADC LTC2378-20/LTC2377-20/ 20-Bit, 1Msps/500ksps/250ksps, 0.5ppm INL Serial, Low Power ADC LTC2376-20 LTC2373-18/LTC2372-18 18-Bit, 1Msps/500ksps, 8-Channel, Serial ADC LTC2387-18/LTC2387-16 18-/16-Bit, 15Msps SAR ADC DACs LTC2756/LTC2757 18-Bit, Serial/Parallel IOUT SoftSpan DAC LTC2668 References LTC6655 LT6657 Amplifiers LTC2057/LTC2057HV LT6020 LT1354/LT1355/LT1356 COMMENTS Buffered 10.24V SoftSpan Inputs with 30VP-P Wide Common Mode Range, 96dB/94dB SNR, Serial CMOS and LVDS I/O, 7mm x 7mm LQFP-48 Package Buffered 10.24V SoftSpan Inputs with Wide Common Mode Range, 96dB/94dB SNR, Serial CMOS and LVDS I/O, 7mm x 7mm LQFP-48 Package 4.096V SoftSpan Inputs with Wide Common Mode Range, 95dB/93dB SNR, Serial CMOS and LVDS I/O, 5mm x 5mm QFN-32 Package Buffered 10.24V SoftSpan Inputs with Wide Common Mode Range, 97dB/94dB SNR, Serial CMOS and LVDS I/O, 7mm x 7mm LQFP-48 Package 4.096V SoftSpan Inputs with Wide Common Mode Range, 92dB/91dB SNR, Serial CMOS and LVDS I/O, 7mm x 7mm QFN-48 Package 2.5V Supply, 5V Fully Differential Input, 104dB SNR, MSOP-16 and 4mm x 3mm DFN-16 Packages 5V Supply, 8 Channel Multiplexed, Configurable Input Range, 100dB SNR, DGC, 5mm x 5mm QFN-32 Package 5V Supply, Differential Input, 95.7/93.8dB SNR, 5mm x 5mm QFN Package 1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm x 7mm LQFP-48 Package 16-Channel 16-/12-Bit 10V VOUT SoftSpan DACs 4LSB INL, Precision Reference 10ppm/C Max, 6mm x 6mm QFN-40 Package Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.25V, 2ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package Precision Low Drift Low Noise Buffered Reference 5V/3V/2.5V, 1.5ppm/C, 0.5ppm Peak-to-Peak Noise, MSOP-8 Package High Voltage, Low Noise Zero-Drift Op Amp Maximum Input Offset: 4.5V, Supply Voltage Range: 4.75V to 60V Dual, Micropower, 5V/s, Rail-to-Rail Op Amp Maximum Input Offset: 30V, Maximum Supply Current: 100A/Amplifier Single/Dual/Quad 1mA, 12MHz, 400V/s Op Amp Good DC Precision, Stable with All Capacitive Loads 235318f 38 LT 1217 * PRINTED IN USA www.linear.com/LTC2353-18 ANALOG DEVICES, INC. 2017