Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 LMV431x Low-Voltage (1.24-V) Adjustable Precision Shunt Regulators 1 Features 3 Description * The LMV431, LMV431A and LMV431B are precision 1.24 V shunt regulators capable of adjustment to 30 V. Negative feedback from the cathode to the adjust pin controls the cathode voltage, much like a noninverting op amp configuration (Refer to Symbol and Functional Diagrams). A two-resistor voltage divider terminated at the adjust pin controls the gain of a 1.24 V band-gap reference. Shorting the cathode to the adjust pin (voltage follower) provides a cathode voltage of a 1.24 V. 1 * * * * * * Low-Voltage Operation/Wide Adjust Range (1.24 V/30 V) 0.5% Initial Tolerance (LMV431B) Temperature Compensated for Industrial Temperature Range (39 PPM/C for the LMV431AI) Low Operation Current (55 A) Low Output Impedance (0.25 ) Fast Turn-On Response Low Cost 2 Applications * * * * * * * Shunt Regulator Series Regulator Current Source or Sink Voltage Monitor Error Amplifier 3-V Off-Line Switching Regulator Low Dropout N-Channel Series Regulator The LMV431, LMV431A and LMV431B have respective initial tolerances of 1.5%, 1%, and 0.5%, and functionally lend themselves to several applications that require zener diode type performance at low voltages. Applications include a 3 V to 2.7 V low drop-out regulator, an error amplifier in a 3 V off-line switching regulator and even as a voltage detector. These parts are typically stable with capacitive loads greater than 10 nF and less than 50 pF. The LMV431, LMV431A and LMV431B provide performance at a competitive price. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LMV431 SOT-23 (5) 2.90 mm x 1.60 mm LMV431 TO-92 (3) 4.30 mm x 4.30 mm LMV431 SOT-23 (3) 2.92 mm x 1.30 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Symbol and Functional Diagrams 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Symbol and Functional Diagrams........................ Revision History..................................................... Pin Configurations and Functions ....................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 4 4 4 5 6 7 8 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. LMV431C Electrical Characteristics.......................... LMV431I Electrical Characteristics ........................... LMV431AC Electrical Characteristics ..................... LMV431AI Electrical Characteristics......................... 7.9 LMV431BC Electrical Characteristics ....................... 9 7.10 LMV431BI Electrical Characteristics ..................... 10 7.11 Typical Performance Characteristics .................... 11 8 Detailed Description ............................................ 15 8.1 Functional Block Diagram ....................................... 15 9 Application and Implementation ........................ 16 9.1 Typical Application ................................................. 16 9.2 DC/AC Test Circuit.................................................. 18 10 Device and Documentation Support ................. 18 10.1 10.2 10.3 10.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 19 11 Mechanical, Packaging, and Orderable Information ........................................................... 19 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (May 2005) to Revision G Page * Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings tables, Layout, and Device and Documentation Support sections; reformatted Detailed Description and Application and Implementation sections. ....................................................................................................................................................... 1 * Added spec............................................................................................................................................................................. 4 2 Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 6 Pin Configurations and Functions TO-92: Plastic Package Top View SOT-23 Top View ANODE REF CATHODE SOT-23 Top View *Pin 1 is not internally connected. *Pin 2 is internally connected to Anode pin. Pin 2 should be either floating or connected to Anode pin. Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 3 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Industrial (LMV431AI, LMV431I) Operating temperature Commercial (LMV431AC, LMV431C, LMV431BC) MIN MAX -40 85 0 70 UNIT C Lead temperature TO-92 Package/SOT-23 -5,-3 Package (Soldering, 10 sec.) 265 Internal power dissipation (2) TO-92 0.78 W SOT-23-5, -3 Package 0.28 W 35 V Cathode voltage Continuous cathode current -30 30 Reference input current -.05 3 (1) (2) mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Ratings apply to ambient temperature at 25C. Above this temperature, derate the TO-92 at 6.2 mW/C, and the SOT-23-5 at 2.2 mW/C. See derating curve in Operating Condition section. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) Electrostatic discharge (1) MIN MAX UNIT -65 150 C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 V The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Cathode voltage MAX UNIT 30 V 0.1 15 mA -40 85 C Cathode current Temperature NOM VREF LMV431AI Derating Curve (Slope = -1/RJA) 7.4 Thermal Information THERMAL METRIC (1) RJA (1) (2) 4 Junction-to-ambient thermal resistance (2) LMV431 LMV431 LMV431 SOT-23 SOT-23 TO-92 3 PINS 5 PINS 3 PINS 455 455 161 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. TJ Max = 150C, TJ = TA+ (RJA PD), where PD is the operating power of the device. Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 7.5 LMV431C Electrical Characteristics TA = 25C unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS TA = 25C VREF Reference Voltage VZ = VREF, IZ = 10 mA (See Figure 32 ) VDEV Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10 mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF TA = Full Range MIN TYP MAX 1.222 1.24 1.258 1.21 1.27 UNIT V 4 12 IZ = 10 mA (see Figure 33 ) VZ from VREF to 6 V R1 = 10 k, R2 = and 2.6 k -1.5 -2.7 Reference Input Current R1 = 10 k, R2 = II = 10 mA (see Figure 33) 0.15 0.5 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.05 0.3 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) 55 80 A IZ(OFF) Off-State Current VZ= 6 V, VREF = 0 V (see Figure 34 ) 0.001 0.1 A rZ Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1 mA to 15 mA Frequency = 0 Hz (see Figure 32) 0.25 0.4 'VREF 'VZ (1) mV mV/V Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 V (at 25qC) (c) REF T2 T1 * 6 VDEV r 10 q V (at 25 C) (c) REF T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 'VZ R1 * # rZ 1 'IZ (c) R2 1/4 Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 5 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 7.6 LMV431I Electrical Characteristics TA = 25C unless otherwise specified SYMBOL VREF PARAMETER TEST CONDITIONS Reference Voltage VDEV VZ = VREF, IZ = 10 mA (See Figure 32 ) Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10 mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF MIN TYP MAX TA = 25C 1.222 1.24 1.258 TA = Full Range 1.202 1.278 UNIT V 6 20 IZ = 10mA (see Figure 33 ) VZ from VREF to 6V R1 = 10 k, R2 = and 2.6k -1.5 -2.7 Reference Input Current R1 = 10 k, R2 = II = 10 mA (see Figure 33) 0.15 0.5 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.1 0.4 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) 55 80 A IZ(OFF) Off-State Current VZ = 6 V, VREF = 0V (see Figure 34 ) 0.001 0.1 A rZ Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1 mA to 15 mA Frequency = 0 Hz (see Figure 32) 0.25 0.4 'VREF 'VZ (1) mV mV/V Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 (c) VREF (at 25qC) T2 T1 * 6 VDEV r 10 (c) VREF (at 25q C) T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 6 'VZ R1 * # rZ 1 'IZ (c) R2 1/4 Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com 7.7 SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 LMV431AC Electrical Characteristics TA = 25C unless otherwise specified SYMBOL VREF PARAMETER TEST CONDITIONS Reference Voltage VZ = VREF, IZ = 10 mA (See Figure 32 ) MIN TYP MAX TA = 25C 1.228 1.24 1.252 TA = Full Range 1.221 Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10 mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF VDEV 1.259 UNIT V 4 12 IZ = 10 mA (see Figure 33 ) VZ from VREF to 6 V R1 = 10 k, R2 = and 2.6 k -1.5 -2.7 mV/V Reference Input Current R1 = 1 k, R2 = II = 10 mA (see Figure 33) 0.15 0.50 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.05 0.3 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) IZ(OFF) Off-State Current VZ = 6 V, VREF = 0V (see Figure 34 ) Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1mA to 15mA Frequency = 0 Hz (see Figure 32) 'VREF 'VZ rZ (1) mV 55 80 A 0.001 0.1 A 0.25 0.4 Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 (c) VREF (at 25qC) T2 T1 * 6 VDEV r 10 (c) VREF (at 25q C) T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 'VZ R1 * # rZ 1 'IZ R2 1/4 (c) Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 7 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 7.8 LMV431AI Electrical Characteristics TA = 25C unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25C 1.228 1.24 1.252 V TA = Full Range 1.215 1.265 V VREF Reference Voltage VZ = VREF, IZ = 10mA (See Figure 32 ) VDEV Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF 6 20 IZ = 10mA (see Figure 33 ) VZ from VREF to 6 V R1 = 10 k, R2 = and 2.6 k -1.5 -2.7 Reference Input Current R1 = 10 k, R2 = II = 10 mA (see Figure 33) 0.15 0.5 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.1 0.4 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) IZ(OFF) Off-State Current VZ = 6 V, VREF = 0 V (see Figure 34 ) Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1 mA to 15 mA Frequency = 0 Hz (see Figure 32) 'VREF 'VZ rZ (1) mV mV/V 55 80 A 0.001 0.1 A 0.25 0.4 Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 (c) VREF (at 25qC) T2 T1 * 6 VDEV r 10 (c) VREF (at 25q C) T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 8 'VZ R1 * # rZ 1 'IZ R2 1/4 (c) Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 7.9 LMV431BC Electrical Characteristics TA = 25C unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25C 1.234 1.24 1.246 V TA = Full Range 1.227 1.253 V VREF Reference Voltage VZ = VREF, IZ = 10 mA (See Figure 32 ) VDEV Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10 mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF 4 12 IZ = 10 mA (see Figure 33 ) VZ from VREF to 6 V R1 = 10 k, R2 = and 2.6 k -1.5 -2.7 mV/V Reference Input Current R1 = 10 k, R2 = II = 10 mA (see Figure 33) 0.15 0.50 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.05 0.3 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) IZ(OFF) Off-State Current VZ = 6 V, VREF = 0V (see Figure 34 ) Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1mA to 15mA Frequency = 0 Hz (see Figure 32) 'VREF 'VZ rZ (1) mV 55 80 A 0.001 0.1 A 0.25 0.4 Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 (c) VREF (at 25qC) T2 T1 * 6 VDEV r 10 (c) VREF (at 25q C) T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 'VZ R1 * # rZ 1 'IZ R2 1/4 (c) Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 9 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 7.10 LMV431BI Electrical Characteristics TA = 25C unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25C 1.234 1.24 1.246 V TA = Full Range 1.224 1.259 V VREF Reference Voltage VZ = VREF, IZ = 10 mA (See Figure 32 ) VDEV Deviation of Reference Input Voltage Over Temperature (1) VZ = VREF, IZ = 10 mA, TA = Full Range (See Figure 32) Ratio of the Change in Reference Voltage to the Change in Cathode Voltage IREF 6 20 IZ = 10 mA (see Figure 33 ) VZ from VREF to 6V R1 = 10 k, R2 = and 2.6 k -1.5 -2.7 mV/V Reference Input Current R1 = 10 k, R2 = II = 10 mA (see Figure 33) 0.15 0.50 A IREF Deviation of Reference Input Current over Temperature R1 = 10 k, R2 = , II = 10 mA, TA = Full Range (see Figure 33) 0.1 0.4 A IZ(MIN) Minimum Cathode Current for Regulation VZ = VREF(see Figure 32) IZ(OFF) Off-State Current VZ = 6 V, VREF = 0 V (see Figure 34 ) Dynamic Output Impedance (2) VZ = VREF, IZ = 0.1 mA to 15 mA Frequency = 0 Hz (see Figure 32) 'VREF 'VZ rZ (1) mV 55 80 A 0.001 0.1 A 0.25 0.4 Deviation of reference input voltage, VDEV, is defined as the maximum variation of the reference input voltage over the full temperature range. See the following: The average temperature coefficient of the reference input voltage, VREF, is defined as: v VREF ppm qC V VMin * 6 r Max 10 (c) VREF (at 25qC) T2 T1 * 6 VDEV r 10 (c) VREF (at 25q C) T2 T1 Where: T2 - T1 = full temperature change. VREF can be positive or negative depending on whether the slope is positive or negative. Example: VDEV = 6 mV, VREF = 1240 mV, T2 - T1 = 125C. v VREF (2) 6.0 mV * 6 10 (c) 1240 mV 125qC 39 ppm / qC The dynamic output impedance, rZ, is defined as: rZ 'VZ 'IZ When the device is programmed with two external resistors, R1 and R2, (see Figure 33 ), the dynamic output impedance of the overall circuit, rZ, is defined as: rZ 10 'VZ R1 * # rZ 1 'IZ R2 1/4 (c) Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 7.11 Typical Performance Characteristics Figure 1. Reference Voltage vs. Junction Temperature Figure 2. Reference Input Current vs. Junction Temperature Figure 3. Cathode Current vs. Cathode Voltage 1 Figure 4. Cathode Current vs. Cathode Voltage 2 Figure 5. Off-State Cathode Current vs. Junction Temperature Figure 6. Delta Reference Voltage Per Delta Cathode Voltage vs. Junction Temperature Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 11 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) Figure 7. Input Voltage Noise vs. Frequency Figure 8. Test Circuit For Input Voltage Noise vs. Frequency BW = 0.1 Hz To 10 Hz 12 Figure 9. Low Frequency Peak To Peak Noise Figure 10. Test Circuit For Peak To Peak Noise Figure 11. Small Signal Voltage Gain And Phase Shift vs. Frequency Figure 12. Test Circuit For Voltage Gain And Phase Shift vs. Frequency Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 Typical Performance Characteristics (continued) Figure 13. Reference Impedance vs. Frequency Figure 14. Test Circuit For Reference Impedance vs. Frequency Figure 15. Pulse Response 1 Figure 16. Test Circuit For Pulse Response 1 Figure 18. Test Circuit For Pulse Response 2 Figure 17. Pulse Response 2 Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 13 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com Typical Performance Characteristics (continued) 15 150: VZ CATHODE CURRENT IZ (mA) TA = 25C IZ = 15mA 12 IZ STABLE STABLE VZ=2V UNSTABLE REGION 9 + CL - 6 VSUPPLY VZ=3V 3 FOR VZ = VREF, STABLE FOR CL = 1pF TO 10k nF 0 0.001 0.01 0.1 1 10 100 1k 10k LOAD CAPACITANCE CL (nF) Figure 19. LMV431 Stability Boundary Condition R1 10k: Figure 20. Test Circuit For VZ = VREF 150: VZ IZ + CL - VSUPPLY R2 Extrapolated from life-test data taken at 125C; the activation energy assumed is 0.7eV. Figure 21. Test Circuit For VZ = 2V, 3V 14 Submit Documentation Feedback Figure 22. Percentage Change In VREF vs. Operating Life At 55C Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 8 Detailed Description 8.1 Functional Block Diagram Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 15 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Typical Application R1 * VO | 1 VREF (c) R2 R1 * 1 R2 VREF (c) VO MIN VREF 5 V VO Figure 23. Series Regulator Figure 24. Output Control of a Three-Terminal Fixed Regulator R1 * VO | 1 VREF R2 (c) R1 * VLIMIT | 1 VREF (c) R2 Figure 26. Crow Bar Figure 25. Higher Current Shunt Regulator 16 Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 Typical Application (continued) R1B * LOW LIMIT | VREF 1 VBE (c) R2B R1A * HIGH LIMIT | VREF 1 R2A (c) R1B * LED ON WHEN LOW LIMIT | VREF 1 (c) R2B LOW LIMIT V HIGH LIMIT R1A * HIGH LIMIT | VREF 1 (c) R2A Figure 28. Voltage Monitor Figure 27. Overvoltage/Undervoltage Protection Circuit IO DELAY RCUn VREF RCL V (V ) VREF Figure 29. Delay Timer Figure 30. Current Limiter or Current Source Figure 31. Constant Current Sink Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 17 LMV431, LMV431A, LMV431B SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 www.ti.com 9.2 DC/AC Test Circuit Figure 33. Test Circuit For VZ > VREF Figure 32. Test Circuit For VZ = VREF Figure 34. Test Circuit For Off-State Current 10 Device and Documentation Support 10.1 Documentation Support 10.1.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LMV431 Click here Click here Click here Click here Click here LMV431A Click here Click here Click here Click here Click here LMV431B Click here Click here Click here Click here Click here 10.2 Trademarks All trademarks are the property of their respective owners. 10.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 18 Submit Documentation Feedback Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B LMV431, LMV431A, LMV431B www.ti.com SNVS041G - MAY 2004 - REVISED SEPTEMBER 2014 10.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2004-2014, Texas Instruments Incorporated Product Folder Links: LMV431 LMV431A LMV431B Submit Documentation Feedback 19 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV431ACM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI 0 to 70 N09A LMV431ACM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 N09A LMV431ACM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 N09A LMV431AIM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 N08A LMV431AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 N08A LMV431AIM5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 N08A LMV431AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 N08A LMV431AIMF NRND SOT-23 DBZ 3 1000 TBD Call TI Call TI -40 to 85 RLA LMV431AIMF/NOPB ACTIVE SOT-23 DBZ 3 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 RLA LMV431AIMFX NRND SOT-23 DBZ 3 3000 TBD Call TI Call TI -40 to 85 RLA LMV431AIMFX/NOPB ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 RLA LMV431AIZ/LFT3 ACTIVE TO-92 LP 3 2000 Green (RoHS & no Sb/Br) SN N / A for Pkg Type LMV431AIZ/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS & no Sb/Br) SN N / A for Pkg Type LMV431BCM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM N09C LMV431BCM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM N09C LMV431 AIZ -40 to 85 LMV431 AIZ LMV431BIMF NRND SOT-23 DBZ 3 1000 TBD Call TI Call TI -40 to 85 RLB LMV431BIMF/NOPB ACTIVE SOT-23 DBZ 3 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 RLB LMV431BIMFX/NOPB ACTIVE SOT-23 DBZ 3 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 RLB LMV431CM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI 0 to 70 N09B LMV431CM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 N09B Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV431CM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM 0 to 70 N09B LMV431CZ/NOPB ACTIVE TO-92 LP 3 1800 Green (RoHS & no Sb/Br) SN N / A for Pkg Type 0 to 70 LMV431 CZ LMV431IM5 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 N08B LMV431IM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 N08B LMV431IM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 N08B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMV431ACM5 SOT-23 DBV 5 1000 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 LMV431ACM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431ACM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431AIM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431AIM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431AIM5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431AIM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431AIMF SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431AIMF/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431AIMFX SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431AIMFX/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431BCM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431BCM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431BIMF SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431BIMF/NOPB SOT-23 DBZ 3 1000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431BIMFX/NOPB SOT-23 DBZ 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 Q3 LMV431CM5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV431CM5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMV431CM5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 LMV431IM5 SOT-23 DBV 5 1000 178.0 8.4 LMV431IM5/NOPB SOT-23 DBV 5 1000 178.0 LMV431IM5X/NOPB SOT-23 DBV 5 3000 178.0 W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV431ACM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431ACM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431ACM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV431AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431AIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV431AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV431AIMF SOT-23 DBZ 3 1000 210.0 185.0 35.0 LMV431AIMF/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0 LMV431AIMFX SOT-23 DBZ 3 3000 210.0 185.0 35.0 LMV431AIMFX/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0 LMV431BCM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431BCM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV431BIMF SOT-23 DBZ 3 1000 210.0 185.0 35.0 LMV431BIMF/NOPB SOT-23 DBZ 3 1000 210.0 185.0 35.0 LMV431BIMFX/NOPB SOT-23 DBZ 3 3000 210.0 185.0 35.0 LMV431CM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431CM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431CM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV431IM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431IM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV431IM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE LP0003A TO-92 - 5.34 mm max height SCALE 1.200 SCALE 1.200 TO-92 5.21 4.44 EJECTOR PIN OPTIONAL 5.34 4.32 (1.5) TYP SEATING PLANE (2.54) NOTE 3 2X 4 MAX (0.51) TYP 6X 0.076 MAX SEATING PLANE 2X 2.6 0.2 3X 12.7 MIN 3X 3X 0.55 0.38 0.43 0.35 2X 1.27 0.13 FORMED LEAD OPTION STRAIGHT LEAD OPTION OTHER DIMENSIONS IDENTICAL TO STRAIGHT LEAD OPTION 3X 2.67 2.03 4.19 3.17 3 2 1 3.43 MIN 4215214/B 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Lead dimensions are not controlled within this area. 4. Reference JEDEC TO-226, variation AA. 5. Shipping method: a. Straight lead option available in bulk pack only. b. Formed lead option available in tape and reel or ammo pack. c. Specific products can be offered in limited combinations of shipping medium and lead options. d. Consult product folder for more information on available options. www.ti.com EXAMPLE BOARD LAYOUT LP0003A TO-92 - 5.34 mm max height TO-92 0.05 MAX ALL AROUND TYP FULL R TYP METAL TYP (1.07) 3X ( 0.85) HOLE 2X METAL (1.5) 2X (1.5) 2 1 (R0.05) TYP 3 2X (1.07) (1.27) SOLDER MASK OPENING 2X SOLDER MASK OPENING (2.54) LAND PATTERN EXAMPLE STRAIGHT LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X 0.05 MAX ALL AROUND TYP ( 1.4) 2X ( 1.4) METAL 3X ( 0.9) HOLE METAL (R0.05) TYP 2 1 (2.6) SOLDER MASK OPENING 3 2X SOLDER MASK OPENING (5.2) LAND PATTERN EXAMPLE FORMED LEAD OPTION NON-SOLDER MASK DEFINED SCALE:15X 4215214/B 04/2017 www.ti.com TAPE SPECIFICATIONS LP0003A TO-92 - 5.34 mm max height TO-92 13.7 11.7 32 23 (2.5) TYP 0.5 MIN 16.5 15.5 11.0 8.5 9.75 8.50 19.0 17.5 6.75 5.95 2.9 TYP 2.4 3.7-4.3 TYP 13.0 12.4 FOR FORMED LEAD OPTION PACKAGE 4215214/B 04/2017 www.ti.com 4203227/C PACKAGE OUTLINE DBZ0003A SOT-23 - 1.12 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 2.64 2.10 1.4 1.2 PIN 1 INDEX AREA 1.12 MAX B A 0.1 C 1 0.95 3.04 2.80 1.9 3X 3 0.5 0.3 0.2 2 (0.95) C A B 0.25 GAGE PLANE 0 -8 TYP 0.10 TYP 0.01 0.20 TYP 0.08 0.6 TYP 0.2 SEATING PLANE 4214838/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. www.ti.com EXAMPLE BOARD LAYOUT DBZ0003A SOT-23 - 1.12 mm max height SMALL OUTLINE TRANSISTOR PKG 3X (1.3) 1 3X (0.6) SYMM 3 2X (0.95) 2 (R0.05) TYP (2.1) LAND PATTERN EXAMPLE SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214838/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBZ0003A SOT-23 - 1.12 mm max height SMALL OUTLINE TRANSISTOR PKG 3X (1.3) 1 3X (0.6) SYMM 3 2X(0.95) 2 (R0.05) TYP (2.1) SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X 4214838/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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