Si8902AEDB
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N-Channel 24 V (D-S) MOSFET
Marking Code: 8902AE
Ordering Information:
Si8902AEDB-T2-E1 (Lead (Pb)-free and Halogen-free)
FEATURES
• TrenchFET® power MOSFET
• Small 2.4 mm x 1.6 mm outline
• Thin 0.6 mm max. height
• Typical ESD protection 5000 V (HBM)
• Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
APPLICATIONS
• Battery protection switch
• Bi-directional switch
Notes
a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s.
b. The case is defined as the top surface of the package.
c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering.
d. Maximum under steady state conditions is 120 °C/W.
PRODUCT SUMMARY
VS1S2 (V) RS1S2 (Ω) Max. IS1S2 (A) a
24
0.028 at VGS = 4.5 V 5.9
0.029 at VGS = 3.7 V 5.8
0.031 at VGS = 2.5 V 5.6
0.037 at VGS = 1.8 V 5.1
MICRO FOOT® 2.4 x 1.6
Backside View
1
1.6 mm
2.4 mm
8902AE
xxx
Bump Side View
5
S2
6
G2
1
S1
S2
4
G1
3
S1
2
G
2
S
2
G
1
S
1
N-Channel
R
R
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter Symbol Limit Unit
Source 1-to-Source 2 Voltage VS1S2 24 V
Gate-Source Voltage VGS ± 12
Continuous Source 1-to-Source 2 Current
(TJ = 150 °C)
TC = 25 °C
IS1S2
11 b
A
TC = 85 °C 7.9 b
TA = 25 °C 5.9 a
TA = 85 °C 4.3 a
Pulsed Source 1-to-Source 2 Current (t = 100 μs) ISM 40
Maximum Power Dissipation
TC = 25 °C
PD
5.7 b
W
TC = 85 °C 3 b
TA = 25 °C 1.7 a
TA = 85 °C 0.9 a
Operating Junction and Storage Temperature Range TJ, Tstg -55 to 150 °C
Soldering Recommendations (Peak Temperature) c 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient a, d t ≤ 5 s RthJA 60 75 °C/W
Maximum Junction-to-Case bSteady State RthJC 18 22
Si8902AEDB
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Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Source 1-to-Source 2 Breakdown Voltage VS1S2 VGS = 0 V, IS = 250 μA 24 - - V
VGS(th) Temperature Coefficient ΔVGS(th)/TJIS = 250 μA - 3 - mV/°C
Gate-Source Threshold Voltage VGS(th) VSS = VGS , IS = 250 μA 0.4 - 0.9 V
Gate-Source Leakage IGSS
VSS = 0 V, VGS = ± 4.5 V - - ± 0.2 μA
VSS = 0 V, VGS = ± 12 V - - ± 10 mA
Zero Gate Voltage Source Current IS1S2
VSS = 24 V, VGS = 0 V - - 1 μA
VSS = 24 V, VGS = 0 V, TJ = 85 °C - - 10
On-State Source Current a IS(on) V
SS ≥ 5 V, VGS = 4.5 V 5 - - A
Source1-to-Source 2 On-State Resistance a RS1S2
VGS = 4.5 V, ISS = 1 A - 0.0215 0.0280
Ω
VGS = 3.7 V, ISS = 1 A - 0.0222 0.0290
VGS = 2.5 V, ISS = 1 A - 0.0240 0.0310
VGS = 1.8 V, ISS = 1 A - 0.0260 0.0370
Forward Transconductance a gfs VSS = 10 V, ISS = 1 A - 15 - S
Dynamic b
Gate Resistance Rgf = 1 MHz - 5.3 - kΩ
Turn-On Delay Time td(on)
VSS = 12.5 V, RL = 12.5 Ω
ISS ≅ 1 A, VGEN = 4.5 V, Rg = 1 Ω
-1.53
μs
Rise Time tr -3.57
Turn-Off Delay Time td(off) -2550
Fall Time tf-1225
Turn-On Delay Time td(on)
VSS = 12.5 V, RL = 12.5 Ω
ISS ≅ 1 A, VGEN = 10 V, Rg = 1 Ω
-0.71.4
Rise Time tr -1.32.6
Turn-Off Delay Time td(off) -3570
Fall Time tf-1225
Si8902AEDB
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Gate Current vs. Gate-Source Voltage
Output Characteristics
On-Resistance vs. Drain Current
Gate Current vs. Gate-Source Voltage
Transfer Characteristics
On-Resistance vs. Junction Temperature
0
0.3
0.6
0.9
1.2
1.5
0 3 6 9 12
IGSS - Gate Current (mA)
VGS - Gate-Source Voltage (V)
TJ = 25 °C
0
10
20
30
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
VGS
= 1.5 V
VGS = 2.5 V
VGS
= 5 V thru 3 V
V
GS
= 1 V
0
0.01
0.02
0.03
0.04
0.05
0 5 10 15 20 25 30
RDS(on) - On-Resistance (Ω)
ID - Drain Current (A)
VGS = 1.8 V
VGS = 3.7 V
VGS = 2.5 V
VGS = 4.5 V
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
0 3 6 9 12
IGSS - Gate Current (A)
VGS - Gate-to-Source Voltage (V)
TJ = 150 °C
TJ = 25 °C
0
2
4
6
8
10
0.0 0.2 0.4 0.6 0.8 1.0 1.2
ID - Drain Current (A)
VGS - Gate-to-Source Voltage (V)
TC = 25 °C
TC = 125 °C
T
C
= -
55
°
C
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
- 50 - 25 0 25 50 75 100 125 150
RDS(on) - On-Resistance (Normalized)
TJ - Junction Temperature (°C)
VGS = 4.5 V, 3.7 V, 2.5 V, 1.8V; ID = 1A
Si8902AEDB
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S15-1171-Rev. B, 25-May-15 4Document Number: 62948
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
On-Resistance vs. Gate-to-Source Voltage
Source-Drain Diode Forward Voltage
Threshold Voltage
Single Pulse Power (Junction-to-Ambient)
0
0.01
0.02
0.03
0.04
0.05
0.06
0 1 2 3 4 5
RDS(on) - On-Resistance (Ω)
VGS - Gate-to-Source Voltage (V)
TJ = 125 °C
TJ = 25 °C
ID = 1 A
0.1
1
10
100
0.0 0.3 0.6 0.9 1.2 1.5
IS - Source Current (A)
VSD - Source-to-Drain Voltage (V)
TJ = 150 °C
TJ = 25 °C
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
- 50 - 25 0 25 50 75 100 125 150
VGS(th) (V)
TJ - Temperature (°C)
I
D
= 250 μA
0
5
10
15
20
25
30
0.01 0.1 1 10 100 1000
Power (W)
Time (s)
Si8902AEDB
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Safe Operating Area, Junction-to-Ambient
Current Derating* Power Derating
Note
• When mounted on 1" x 1" FR4 with full copper.
* The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-ambient thermal resistance, and is more useful in
settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating,
when this rating falls below the package limit.
100 µs
DS
(
on
)
1 ms
10 ms
DC
0
1
2
3
4
5
6
0 25 50 75 100 125 150
ID - Drain Current (A)
TA - Ambient Temperature (°C)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 25 50 75 100 125 150
Power (W)
TA - Case Temperature (°C)
Si8902AEDB
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient (On 1" x 1" FR4 board with maximum copper)
Normalized Thermal Transient Impedance, Junction-to-Case (on 1" x 1" FR4 board with minimum copper)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62948.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-
3
10-
2
00601110-
1
10-
4
100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. PER UNIT BASE = R
TH
JA
= 120°C/W
3. T
JM
-
T
A
= P
DM
Z
thJA(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
Normalized Thermal Transient Impedance, Junction-to-Case
10-
310-2 110-1
10-4
2
1
0.1
0.01
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
Single Pulse
Package Information
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Revision: 27-Apr-15 1Document Number: 69350
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MICRO FOOT®: 6-Bumps
(1.6 mm x 2.4 mm, 0.8 mm Pitch, 0.290 mm Bump Height)
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
Note
• Use millimeters as the primary measurement.
DIM. MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.550 0.575 0.600 0.0217 0.0226 0.0236
A1 0.260 0.275 0.290 0.0102 0.0108 0.0114
A2 0.290 0.300 0.310 0.0114 0.0118 0.0122
b 0.370 0.390 0.410 0.0146 0.0153 0.0161
b1 0.300 0.0118
e 0.800 0.0314
s 0.360 0.380 0.400 0.0141 0.0150 0.0157
D 1.520 1.560 1.600 0.0598 0.0614 0.0630
E 2.320 2.360 2.400 0.0913 0.0929 0.0945
K 0.155 0.185 0.215 0.0061 0.0072 0.0084
ECN: T15-0143-Rev. A, 27-Apr-15
DWG: 6036
S1
S1
G2
G1
S2
S2
XXXXXX
XXX
D
E
eS
S e e
6x Ø b1
A2A1
A
b
K
e
e e
6x 0.30 to 0.31
(Note 3)
Solder mask-0.4
Note 2
b Diameter bump
(Note 1)
Mark on backside of die
Recommended land pattern
Note 5
b1
AN824
Vishay Siliconix
Document Number: 71990
06-Jan-03
www.vishay.com
1
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Si8900EDB
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
0.18 ~ 0.25
321
A
B
0.5
1.58
0.5
0.285
0.285
1.08
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Document Number: 71990
06-Jan-03
TABLE 1
Main Parameters of Solder Bumps in MICRO FOOT Designs
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MICRO FOOT CSP
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Bump Material
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Bump Pitch*
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Bump Diameter*
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
Bump Height*
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MICRO FOOT CSP MOSFET
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Eutectic Solder:
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0.37-0.41
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.26-0.29
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MICRO FOOT CSP Analog Switch
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Eutectic Solder:
63Sm
/
37Pb
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0.18-0.25
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.14-0.19
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
MICRO FOOT UCSP Analog Switch
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
63Sm/37Pb
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
0.32-0.34
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
0.21-0.24
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
TABLE 2
MICRO FOOT Reliability Results
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Test Condition C: −65_ to 150_C
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
>500 Cycles
ÁÁÁÁÁÁÁÁÁ
Test condition B: −40_ to 125_C
ÁÁÁÁÁÁÁ
>1000 Cycles
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
121_C @ 15PSI 100% Humidity Test
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
BOARD LAYOUT GUIDELINES
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Copper pads should be finished with an organic solderability
preservative (OSP) coating. For electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
FIGURE 3. SMD FIGURE 4. NSMD
Copper
Solder Mask
Copper
Solder Mask
AN824
Vishay Siliconix
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06-Jan-03
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3
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
ÁÁÁ
Á
Á
Á
ÁÁÁ
Pitch
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Copper Pad
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Solder Mask
Opening
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Stencil
Aperture
ÁÁÁ
ÁÁÁ
0.80 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.30 " 0.01 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.41 " 0.01 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.33 " 0.01 mm
in ciircle aperture
ÁÁÁ
ÁÁÁ
0.50 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.17 " 0.01 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.27 " 0.01 mm
ÁÁÁÁÁ
ÁÁÁÁÁ
0.30 " 0.01 mm
in square aperture
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
FIGURE 5. SMT Assembly Process Flow
Stencil Design
IIncoming Tape and Reel Inspection
Solder Paste Printing
Chip Placement
Reflow
Solder Joint Inspection
Pack and Ship
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
0
50
100
150
200
250
0 100 200 300 400
Thermal Profile
Time (Seconds
FIGURE 6. Reflow Profile
Temperature (_C)
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
1. Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
2. Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3. Resurface the pads using a temperature-controlled
soldering iron.
4. Apply gel flux to the pad.
5. Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
6. Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
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Revision: 08-Feb-17 1Document Number: 91000
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