1
FEATURES APPLICATIONS
ZVS
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
SYN
VIN
5VOUT
SCLK
NCS
MOSI
RST
RDELAY
EN1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NORPWPPACKAGE
(TOPVIEW)
DESCRIPTION/ORDERING INFORMATION
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008www.ti.com
•Electrical Appliances2
•Eight Low-Side Drivers With Internal Clamp forInductive Loads and Current Limiting for Self
– Air Conditioning UnitsProtection
– Ranges– Seven Outputs Rated at 150 mA and
– DishwashersControlled Through Serial Interface
– Refrigerators– One Output Rated at 150 mA and
– MicrowavesControlled Through Serial Interface and
– Washing MachinesDedicated Enable Pin
•General-Purpose Interface Circuits, Allowing•5-V ± 5% Regulated Power Supply With
Microcontroller Interface to Relays, ElectricMotors, LEDs, and Buzzers200-mA Load Capability at V
IN
Max of 18 V•Internal Voltage Supervisory for RegulatedOutput
•Serial Communications for Control of EightLow-Side Drivers•Enable/Disable Input for OUT1•5-V or 3.3-V I/O Tolerant for Interface toMicrocontroller
•Programmable Power-On Reset Delay BeforeRST Asserted High, Once 5 V Is WithinSpecified Range (6 ms Typ)•Programmable Deglitch Timer Before RSTAsserted Low (40 µs Typ)•Zero-Voltage Detection Signal•Thermal Shutdown for Self Protection
The power supply provides regulated 5-V output to power the system microcontroller and drive eight low-sideswitches. The ac zero-detect circuitry is monitoring the crossover voltage of the mains ac supply. The resultantsignal is a low-frequency clock output on the ZVS terminal, based on the ac-line cycle. This information allowsthe microcontroller to reduce in-rush current by powering loads on the ac-line peak voltage.
A serial communications interface controls the eight low-side outputs; each output has an internal snubber circuitto absorb the energy in the inductor at turn OFF. Alternatively, the system can use a fly-back diode to V
IN
to helprecirculate the energy in an inductive load at turn OFF.
ORDERING INFORMATION
(1)
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
PDIP – N Tube of 20 TPL9201N TPL9201N– 40 °C to 125 °C Reel of 2000 TPL9201PWPRPowerPAD™ – PWP PL201Tube of 70 TPL9201PWP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
PINOUT CONFIGURATION
NO. NAME I/O DESCRIPTION
1 ZVS O Zero-voltage synchronization2 OUT1 O Low-side output 13 OUT2 O Low-side output 24 OUT3 O Low-side output 35 OUT4 O Low-side output 46 OUT5 O Low-side output 57 OUT6 O Low-side output 68 OUT7 O Low-side output 79 OUT8 O Low-side output 810
(1)
GND I Ground11
(1)
GND I Ground12 EN1 I Enable/disable for OUT113 R
DELAY
O Power-up reset delay14
(2)
RST I/O Power-on reset output (open drain, active low)15 MOSI I Serial data input16 NCS I Chip select17 SCLK I Serial clock for data synchronization18 5V
OUT
O Regulated output19 V
IN
I Unregulated input voltage source20 SYN I AC zero detect input
(1) Terminals 10 and 11 are fused internally in the lead frame for the 20-pin PDIP package.(2) Terminal 14 can be used as an input or an output.
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OUT1at
150mA
OUT2at150mA
OUT3at150mA
OUT4at150mA
OUT5at150mA
OUT6at150mA
OUT7at150mA
OUT8at150mA
GateDrive
andControl
Voltage
Supervisor
Comp
Bandgap
Ref
Vref
–
+
Vref
GateControl
forOutputs
1Through8
2kΩ
12kΩ
2kΩS
R
Q
EN1
NCS
SCLK
MOSI
7–18V
SYN
RDELAY
ZVS
5VOUT
5V
5kΩ
RST
RDELAY
ZVS
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
OUT5
OUT5
OUT4
OUT4
OUT3
OUT3
OUT2
OUT2
OUT1
OUT1
Enable
NCS
SCLK
MOSI
VIN
SYN
10kΩ
Serial
Register
Parallel
Register
Enables
OUT1
GND GND
10V
Iconst
PMOS
Optional,dependent
onheat-management
implementation
(seeNote A)
RST
20
(2W)
W
100kW
100kW
100kW
100kW
6V
6V
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
FUNCTIONAL BLOCK DIAGRAM
A. The resistor and Zener diode are required if there is insufficient thermal-management allocation.
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DETAILED DESCRIPTION
TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
The 5-V regulator is powered from V
IN
, and the regulated output is within 5 V ± 5% over the operating conditions.The open-drain power-on reset ( RST) pin remains low until the regulator exceeds the set threshold, and the timervalue set by the capacitor on the reset delay (R
DELAY
) pin expires. If both of these conditions are satisfied, RST isasserted high. This signifies to the microcontroller that serial communications can be initiated to the TPL9201.
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from themicrocontroller. A single register controls all the outputs (one bit per output). The default value is zero (OFF). Ifan output requires pulse width modulation (PWM) function, the register must be updated at a rate faster than thedesired PWM frequency. OUT1 can be controlled by serial input from the microcontroller or with the dedicatedenable (EN1) pin. If EN1 is pulled low or left open, the serial input through the shift register controls OUT1. IfEN1 is pulled high, OUT1 always is turned on, and the serial input for OUT1 is ignored.
The SYN input translates the image of the mains voltage through the secondary of the transformer. The SYNinput has a resistor to protect from high currents into the IC. The zero-voltage synchronization output translatesthe ac-line cycle frequency into a low-frequency clock, which can be used for a timing reference and to helppower loads on the ac-line peak voltage (to reduce in-rush currents).
If RST is asserted, all outputs are turned OFF internally, and the input register is reset to all zeroes. Themicrocontroller must write to the register to turn the outputs ON again.
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Absolute Maximum Ratings
(1)
Dissipation Ratings
Recommended Operating Conditions
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
MIN MAX UNIT
V
IN
24V
I(unreg)
Unregulated input voltage
(2) (3)
VSYN 24EN1, MOSI, SCLK, and NCS 7V
I(logic)
Logic input voltage
(2) (3)
VRST and R
DELAY
7V
O
Low-side output voltage OUT1 – OUT8 16.5 VOUTn = ON and shorted to V
INI
LIMIT
Output current limit
(4)
350 mAwith low impedance
N package 69θ
JA
Thermal impedance, junction to ambient
(5)
°C/WPWP package 33N package 54θ
JC
Thermal impedance, junction to case
(5)
°C/WPWP package 20θ
JP
Thermal impedance, junction to thermal pad
(5)
PWP package 1.4 °C/WN package 1.8P
D
Continuous power dissipation
(6)
WPWP package 3.7ESD Electrostatic discharge
(7)
2 kVT
A
Operating ambient temperature range – 40 125 °CT
stg
Storage temperature range – 65 125 °CT
lead
Lead temperature Soldering, 10 s 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to GND.(3) Absolute negative voltage on these pins must not go below – 0.5 V.(4) Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 ms.(5) The thermal data is based on using 1-oz copper trace with JEDEC 51-5 test board for PWP and JEDEC 51-7 test board for N.(6) The data is based on ambient temperature of 25 °C max.(7) The Human-Body Model is a 100-pF capacitor discharged through a 1.5-k Ωresistor into each pin.
T
A
≤25 °C DERATING FACTOR T
A
= 125 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING
N 1812 mW 14.5 mW/ °C 362 mWPWP 3787 mW 30.3 mW/ °C 757 mW
MIN MAX UNIT
V
IN
7 18V
I(unreg)
Unregulated input voltage VSYN 0 18V
I(logic)
Logic input voltage EN1, MOSI, SCLK, NCS, RST, and R
DELAY
0 5.25 VT
A
Operating ambient temperature – 40 125 °C
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
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Electrical Characteristics
TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
T
A
= – 40 °C to 125 °C, V
IN
= 7 V to 18 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
Supply Voltage and Current
V
IN
(2)
Input voltage 7 18 VEnable = ON, OUT1 – OUT8 = Off 3I
VIN
Input supply current mAEnable = ON, OUT1 – OUT8 = On 5
Logic Inputs (MOSI, NCS, SCLK, and EN1)
V
IL
Logic input low level I
IL
= 100 µA 0.8
VV
IH
Logic input high level I
IL
= 100 µA 2.4
Reset ( RST)
V
OL
Low-level logic output I
OL
= 1.6 mA 0.4 VV
OH
(3)
High-level logic output 5-k Ωpullup to V
CC
V
CC
– 0.8 VV
H
Disabling reset threshold 5-V regulator ramps up 4.25 4.5 VV
L
Enabling reset threshold 5-V regulator ramps down 3.3 3.75 VV
HYS
Threshold hysteresis 0.12 0.5 V
Reset Delay (R
DELAY
)
I
OUT
Output current 18 28 48 µAT
DW
Reset delay timer C = 47 nF 3 6 msT
UP
Reset capacitor to low level C = 47 nF 45 µs
Output (OUT1 – OUT8)
V
OL
Output ON I
OUTn
= 150 mA 0.4 0.7 VI
OH
Output leakage V
OH
= Max of 16.5 V 2 µA
Regulator Output (5V
OUT
)
I
5VOUT
= 5 mA to 200 mA, V
IN
= 7 V to 18 V,5V
OUT
Output supply 4.75 5 5.25 VC
5VOUT
= 1 µFI
5VOUT
limit Output short-circuit current 5V
OUT
= 0 V 200 mA
Thermal Shutdown
T
SD
Thermal shutdown 150 °CT
HYS
Hysteresis 20 °C
Zero Voltage Synchronization (ZVS)
V
SYNTH
Transition threshold 0.4 0.75 1.1 VI
SYN
Input activating current R
ZV
= 10 k Ω, V
SYN
= 24 V 2 mAt
D
Transition time Rising and falling 10 µs
(1) All typical values are at T
A
= 25 °C.(2) There are external high-frequency noise-suppression capacitors and filter capacitors on V
IN
.(3) V
CC
is the pullup resistor voltage.
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Output Control Register
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
MSB LSB
IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1
00000000INn = 0: Output OFFINn = 1: Output ON
To operate the output in PWM mode, the output control register must be updated at a rate twice the desiredPWM frequency of the output. Maximum PWM frequency is 5 kHz. The register is updated every 100 µs.
ENABLE TRUTH TABLE
SERIAL INPUTEN1 OUT1FOR OUT1
Open H OnOpen L OffL H OnL L OffH H OnH L On
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Serial Communications Interface
IN1
LSB
IN7 IN6 IN5 IN4 IN3 IN2
IN8
MSB
XXX
T1 T5
T8
T2
T4
T3
T1
NCS
SCLK
MOSI
12345678
T7
T6
TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from themicrocontroller (see Figure 1 ). A single register controls all the outputs. The signal gives the instruction to controlthe output of TPL9201.
The NCS signal enables the SCLK and MOSI data when it is low. After NCS is set low for T
1
, synchronizationclock and data begin to transmit and, after the 8-bit data has been transmitted, NCS is set high again to disableSCLK and MOSI and transfer the serial data to the control register. SCLK must be held low when NCS is in thehigh state.
Figure 1. Serial Communications
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Timing Requirements
Reset Delay (R
DELAY
)
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
T
A
= – 40 °C to 125 °C, V
IN
= 7 V to 18 V (unless otherwise noted)
MIN TYP MAX UNIT
f
SPI
SPI frequency 4 MHzT1 Delay time, NCS falling edge to SCLK rising edge 10 nsT2 Delay time, NCS falling edge to SCLK falling edge 80 nsT3 Pulse duration, SCLK high 60 nsT4 Pulse duration, SCLK low 60 nsT5 Delay time, last SCLK falling edge to NCS rising edge 80 nsT6 Setup time, MOSI valid before SCLK edge 10 nsT7 Hold time, MOSI valid after SCLK edge 10 nsT8 Time between two words for transmitting 170 ns
The R
DELAY
output provides a constant current source to charge an external capacitor to approximately 6.5 V.The external capacitor is selected to provide a delay time, based on the current equation for a capacitor,I = C( Δv/ Δt) and a 28- µA typical output current.
Therefore, the user should select a 47-nF capacitor to provide a 6-ms delay at 3.55 V.I = C( Δv/ Δt)28 µA = C ×(3.55 V/6 ms)C = 47 nF
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
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APPLICATION INFORMATION
TPL9201
MCU/DSP
MOSI
SCLK
NCS
ZVS
RST
5V ±5% at 200 mA
OUT
EN1
Reset Delay
Buzzer Driver
Relay Driver
Relay Driver
Relay Driver
Relay Driver
Fan Driver
Fan Driver
Fan Driver
8 Outputs
SYN (AC Zero-Cross
Detect Input)
DC Input 7 V to 18 V
GND ( 2)×
Filters
AC Water
Supply
Valve
Water
Outlet
Softener
Supply
Driver
SYN ZVS
5VOUT
RST
Power
Switch
M
Zero-Cross
Detection
Cover
Switch
Temperature
Sensor
(Optional)
Optical
Sensor
Water-Level
Sensor
Volume
Sensor
Keypad
Display
(LED/LCD/VFD)
Controller
Regulator
POR/SYS
TPL9201
+
-
~ ~
LED LED
VIN
TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
Figure 2. Typical Application
Figure 3. Washing-Machine Application
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PCB Layout
Application Using a Multilayer PCB
PackageThermalPad
SolderPad(LandPattern)
ThermalVias
PackageOutline
PowerPad
PackageSolderPad
PackageSolderPad
(BottomTrace)
ThermalVia
ComponentTraces
ThermalIsolation
PowerPlaneOnly
1.5748mm
0.0 0.071-mmBoardBase–
andBottomPad
0.5246 0.5606-mm–
PowerPlane
(1-ozCu)
1.0142 1.0502-mm–
GroundPlane
(1-ozCu)
1.5038 1.5748-mm–
ComponentTrace
(2-ozCu)
2Plane
4Plane
Application Using a Single-Layer PCB
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelinesmust be followed when laying out this part on the PCB.
The following information is to be used as a guideline only.
For further information, see the PowerPAD concept implementation document.
In a multilayer board application, the thermal vias are the primary method of heat transfer from the packagethermal pad to the internal ground plane (see Figure 4 and Figure 5 ).
The efficiency of this method depends on several factors: die area, number of thermal vias, thickness of copper,etc. (see the PowerPAD™ Thermally Enhanced Package Technical Brief, literature number SLMA002 ).
Figure 4. Package and PCB Land Configuration for a Multilayer PCB
Figure 5. Multilayer Board (Side View)
In a single-layer board application, the thermal pad is attached to a heat spreader (copper area) by using the lowthermal-impedance attachment method (solder paste or thermal-conductive epoxy). With either method, it isadvisable to use as much copper trace area as possible to dissipate the heat.
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TPL9201
8-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
CAUTION:
If the attachment method is not implemented correctly, the functionality of theproduct cannot be ensured. Power-dissipation capability is adversely affected ifthe device is incorrectly mounted onto the circuit board.
Figure 6. Layout Recommendations for a Single-Layer PCB
12 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPL9201
www.ti.com
Recommended Board Layout
SMOC=SolderMaskOverCopper
SMO=SolderMaskOpening
3,7SMO
0,65
0,27( 20)´
1,2( 20)´
0,33( 8)´
5,85
6,5SMOC
6,92
4,52
3,4SMOC
2,4SMO
1
1
TPL92018-CHANNEL RELAY DRIVERWITH INTEGRATED 5-V LDO AND ZERO-VOLT DETECTION
SLIS123D – JUNE 2006 – REVISED FEBRUARY 2008
Figure 7. Recommended Board Layout for PWP
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPL9201
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPL9201N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TPL9201NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
TPL9201PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPL9201PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPL9201PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPL9201PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jan-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPL9201PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPL9201PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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