FT6164L-12DMLF - Force Technologies Ltd.

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 8/10/12/15/20/25/35/70/100 ns (Commercial)

– 10/12/15/20/25/35/70/100 ns(Industrial)

– 12/15/20/25/35/45/70/100 ns (Military)

Low Power Operation

Output Enable and Dual Chip Enable Control

Functions

Single 5V±10% Power Supply

Data Retention with 2.0V Supply, 10 µA Typical

Current (FT6164L Military)

Common Data I/O

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil Plastic DIP, SOJ

– 28-Pin 600 mil Plastic DIP (70 & 100ns)

– 28-Pin 300 mil SOP (70 & 100ns)

– 28-Pin 300 mil Ceramic DIP

– 28-Pin 600 mil Ceramic DIP

– 28-Pin 350 x 550 mil LCC

– 32-Pin 450 x 550 mil LCC

– 28-Pin CERPACK

DESCRIPTION

The FT6164 is a 65,536-bit ultra high-speed static RAM

organised as 8K x 8. The CMOS memory requires no

clocks or refreshing and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM operates

from a single 5V±10% tolerance power supply. With

battery backup, data integrity is maintained with supply

voltages down to 2.0V. Current drain is typically 10 µA

from a 2.0V supply.

FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS

1519B

DIP (P5, P6, C5, C5-1, D5-1, D5-2),

SOJ (J5), CERPACK (F4), SOP(S6)

SEE PAGE 7 FOR LCC PIN CONFIGURATIONS

Access times as fast as 8 nanoseconds are available,

permitting greatly enhanced system operating speeds.

The FT6164 is available in 28-pin 300 mil DIP and SOJ, 28-

pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil

LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.

The 70ns and 100ns FT6164s are available in the 600 mil

plastic DIP.

FT6164

ULTRA HIGH SPEED 8K x 8

STATIC CMOS RAMS

REV 1.6 1 of 17

MAXIMUM RATINGS(1)

Symbol Parameter Value Unit

VCC Power Supply Pin with –0.5 to +7 V

Respect to GND

Terminal Voltage with –0.5 to

VTERM Respect to GND VCC +0.5 V

(up to 7.0V)

TAOperating Temperature –55 to +125 °C

Symbol Parameter Value Unit

TBIAS Temperature Under –55 to +125 °C

Bias

TSTG Storage Temperature –65 to +150 °C

PTPower Dissipation 1.0 W

IOUT DC Output Current 50 mA

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

ISB

Standby Power Supply

Current (TTL Input Levels)

CE1 ≥ VIH or Mil.

CE2 ≤VIL, Ind./Com’l.

VCC= Max,

f = Max., Outputs Open

___

___ 40

___

n/a

___

CE1 ≥ VHC or Mil.

CE2 ≤VLC, Ind./Com’l.

VCC= Max,

f = 0, Outputs Open

VIN ≤ VLC or VIN ≥ VHC

Standby Power Supply

Current

(CMOS Input Levels)

ISB1

Grade(2) Ambient

Temperature GND VCC

5.0V ± 10%

0V 5.0V ± 10%

–55°C to +125°C

Military

Symbol

CIN

COUT

Parameter

Input Capacitance

Output Capacitance

Conditions

VIN = 0V

VOUT = 0V

Unit

CAPACITANCES(4)

VCC = 5.0V, TA = 25°C, f = 1.0MHz

Symbol

DC ELECTRICAL CHARACTERISTICS

Over recommended operating temperature and supply voltage

(2)

VIH

VIL

VHC

VLC

VCD

VOL

VOH

ILI

ILO

Parameter

Input High Voltage

Input Low Voltage

CMOS Input High Voltage

CMOS Input Low Voltage

Input Clamp Diode Voltage

Output Low Voltage

(TTL Load)

Output High Voltage

(TTL Load)

Input Leakage Current

Output Leakage Current

Test Conditions

VCC = Min., IIN = –18 mA

IOL = +8 mA, VCC = Min.

IOH = –4 mA, VCC = Min.

VCC = Max. Mil.

VIN = GND to VCC Ind./Com’l.

VCC = Max., CE = VIH, Mil.

VOUT = GND to VCC Ind./Com’l.

FT6164

Min

2.2

–0.5(3)

VCC –0.2

–0.5(3)

2.4

–10

–5

–10

–5

Max

VCC +0.5

0.8

VCC +0.5

0.2

–1.2

0.4

+10

FT6164L

Min Max

2.2

–0.5(3)

VCC –0.2

–0.5(3)

2.4

–5

n/a

–5

n/a

VCC +0.5

0.8

VCC +0.5

0.2

0.4

–1.2

n/a

Unit

µA

Notes:

1. Stresses greater than those listed under MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification

is not implied. Exposure to MAXIMUM rating conditions for extended

periods may affect reliability.

2. Extended temperature operation guaranteed with 400 linear feet per

minute of air flow.

3. Transient inputs with VIL and IIL not more negative than –3.0V and

–100mA, respectively, are permissible for pulse widths up to 20 ns.

4. This parameter is sampled and not 100% tested.

Typ.

Industrial

Commercial

–40°C to +85°C

0°C to +70°C

FT6164

REV 1.6 2 of 17

DATA RETENTION CHARACTERISTICS (FT6164L, Military Temperature Only)

Typ.* Max

Symbol Parameter Test Condition Min VCC=V

CC= Unit

2.0V 3.0V 2.0V 3.0V

VDR VCC for Data Retention 2.0 V

ICCDR Data Retention Current 10 15 200 300 µA

tCDR Chip Deselect to 0 ns

Data Retention Time

†Operation Recovery Time tRC

§ns

*TA = +25°C

§tRC = Read Cycle Time

†This parameter is guaranteed but not tested.

*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH

POWER DISSIPATION CHARACTERISTICS VS. SPEED

DATA RETENTION WAVEFORM

CE1 ≥ VCC – 0.2V or

CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V

or VIN ≤ 0.2V

Symbol Parameter Temp erature

Range -8 -10 -12 -15 -20 -25 -35 45 -70 -100 Unit

Commercial 200 180 170 160 155 150 145 N/A 130 125 mA

Industrial N/A 190 180 170 160 155 150 N/A 145 140 mA

Military N/A N/A 180 170 160 155 150 145 145 145 mA

Dynamic Operating Current*ICC

REV 1.6 3 of 17

FT6164

AC ELECTRICAL CHARACTERISTICS—READ CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

Notes:

5. WE is HIGH for READ cycle.

6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE1

transition

LOW and CE2 transition HIGH.

8. Transition is measured ± 200 mV from steady state voltage prior to

change, with loading as specified in Figure 1. This parameter is

sampled and not 100% tested.

TIMING WAVEFORM OF READ CYCLE NO. 1 (OEOE

OEOE

OE CONTROLLED)(5)

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

tRC

Read Cycle

Time 8 1012152025354570100ns

tAA

Address

Access Time 8 1012152025354570100ns

tAC

Chip Enable

Access Time 8 1012152025354570100ns

tOH

Output Hold

from Address

Change

3333333333ns

tLZ

Chip Enable to

Output in Low Z 2222222222ns

tHZ

Chip Disable

to Output in

High Z

567881015203545ns

tOE

Output Enable

Low to Data

Valid

5679101318203545ns

tOLZ

Output Enable

Low to Low Z 2222222222ns

tOHZ

Output Enable

High to High Z 567991215203545ns

tPU

Chip Enable to

Power Up

Time

0000000000ns

tPD

Chip Disable

to Power Down

Time

8 101215202020253545ns

Symbol Parameter -8 -10 -12 -15 -20 -25 Unit

-35 -45 -70 -100

REV 1.6 4 of 17

FT6164

TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)

TIMING WAVEFORM OF READ CYCLE NO. 3 (CECE

CECE

CE1, CE2 CONTROLLED)(5,7,10)

Notes:

9. READ Cycle Time is measured from the last valid address to the first

transitioning address.

10. Transitions caused by a chip enable control have similar delays

irrespective of whether CE1 or CE2 causes them.

AC CHARACTERISTICS—WRITE CYCLE

(VCC = 5V ± 10%, All Temperature Ranges)(2)

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

tWC Write Cycle Time8 1012152025354570100ns

tCW

Chip Enable

Time to End of

Write

6 7 8 12 15 18 25 33 50 70 ns

tAW

Address Valid to

End of Write 7 8 10 12 15 18 25 33 50 70 ns

tAS

Address Set-up

Time 0000000000ns

tWP

Write Pulse

Width 7 8 9 12 15 18 20 25 40 50 ns

tAH

Address Hold

Time 0000000000ns

tDW

Data Valid to

End of Write 6 7 8 9 111315203040 ns

tDH Date Hold Time0000000000ns

tWZ

Write Enable to

Output in High Z 677781014183040ns

tOW

Output Active

from End of

Write

3333333333ns

Symbol Parameter -8 -10 -12 -15 -20 -25 Unit

-35 -45 -70 -100

REV 1.6 5 of 17

FT6164

Notes:

11. CE1 and WE must be LOW, and CE 2 HIGH for WRITE cycle.

12. OE is LOW for this WRITE cycle to show t WZ and tOW.

13. If CE1 goes HIGH, or CE

2 goes LOW, simultaneously with WE HIGH,

the output remains in a high impedance state.

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CECE

CECE

CE CONTROLLED)(11)

14. Write Cycle Time is measured from the last valid address to the first

transitioning address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WEWE

WEWE

WE CONTROLLED)(11)

REV 1.6 6 of 17

FT6164

Mode CECE

CECE

CE1CE2OEOE

OEOE

OE WEWE

WEWE

WE I/O Power

Standby H X X X High Z Standby

Standby X L X X High Z Standby

DOUT

Disabled L H H H High Z Active

Read L H L H DOUT Active

Write L H X L High Z Active

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V

Input Rise and Fall Times 3ns

Input Timing Reference Level 1.5V

Output Timing Reference Level 1.5V

Output Load See Figures 1 and 2

TRUTH TABLE

Figure 1. Output Load Figure 2. Thevenin Equivalent

* including scope and test fixture.

Note:

Because of the high speed of the FT6164/L, care must be taken when

testing this device; an inadequate setup can cause a normal functioning

part to be rejected as faulty. Long high-inductance leads that cause

supply bounce must be avoided by bringing the V

CC and ground planes

directly up to the contactor fingers. A 0.01 µF high frequency capacitor

is also required between V CC and ground. To avoid signal reflections,

proper termination must be used; for example, a 50Ω test environment

should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at

the comparator input, and a 116Ω resistor must be used in series with

DOUT to match 166Ω (Thevenin Resistance).

LCC (L5)

"LS" - SPECIAL PIN-OUT

LCC PIN CONFIGURATIONS

LCC (L6)LCC (L5)

"L" - STANDARD PIN-OUT

REV 1.6 7 of 17

FT6164

N/A = Not available

SELECTION GUIDE

The FT6164 is available in the following temperature, speed and package options. The FT 6164L is available only over

the military temperature range.

ORDERING INFORMATION

8 1012152025354570100

Plastic DIP (300 mil) -8PC -10PC -12PC -15PC -20PC -25PC -35PC N/A N/A N/A

Plastic DIP (600 m il) N/A N/A N/A N/A N/A N/A N/A N/A -70P6C -100P6C

Plastic S OJ -8JC -10JC -12JC -15JC -20JC -25JC -35JC N/A N/A N/A

Plastic SOP N/A N/A N/A N/A N/A N/A N/A N/A -70SNC -100SNC

Industrial Plastic DIP (300 mil) N/A -10PI -12PI -15PI -20PI -25PI -35PI N/A N/A N/A

Plastic DIP (600 m il) N/A N/A N/A N/A N/A N/A N/A N/A -70P6I -100P6I

Plastic SOJ N/A -10JI -12JI -15JI -20JI -25JI -35JI N/A N/A N/A

Plastic SOP N/A N/A N/A N/A N/A N/A N/A N/A -70SNI -100SNI

Speed (ns)

Temperature

Range Package

Commercial

FT6164 L XX XX

M5004

REV 1.6 8 of 17

FT6164

8 1012152025354570100

Side B razed DIP N/A N/A -12CM -15CM -20CM -25CM -35CM -45CM -70CM -100CM

CERDIP (300 mil) N/A N/A -12DM -15DM -20DM -25DM -35DM -45DM -70DM -100DM

CERDIP (600 mil) N/A N/A -12DWM -15DWM -20DWM -25DWM -35DWM -45DWM -70DWM -100DWM

CERPACK N/A N/A -12FM -15FM -20FM -25FM -35FM -45FM -70FM -100FM

28-Pin LCC N/A N/A -12LM -15LM -20LM -25LM -35LM -45LM -70LM -100LM

28-Pin LCC ** N/A N/A -12LSM -15LSM -20LSM -25LSM -35LSM -45LSM -70LSM -100LSM

32-Pin LCC N/A N/A -12L32M -15L32M -20L32M -25L32M -35L32M -45L32M -70L32M -100L32M

Side B razed DIP N/A N/A -12CMB -15CMB -20CMB -25CMB -35CMB -45CMB -70CMB -100CMB

CERDIP (300 mil) N/A N/A -12DMB -15DMB -20DMB -25DMB -35DMB -45DMB -70DMB -100DMB

CERDIP (600 mil) N/A N/A -12DWMB -15DWMB -20DWMB -25DWMB -35DWMB -45DWMB -70DWMB -100DWMB

CERPACK N/A N/A -12FMB -15FMB -20FMB -25FMB -35FMB -45FMB -70FMB -100FMB

28-Pin LCC N/A N/A -12LMB -15LMB -20LMB -25LMB -35LMB -45LMB -70LMB -100LMB

28-Pin LCC ** N/A N/A -12LSMB -15LSMB -20LSMB -25LSMB -35LSMB -45LSMB -70LSMB -100LSMB

32-Pin LCC N/A N/A -12L32MB -15L32MB -20L32MB -25L32MB -35L32MB -45L32MB -70L32MB -100L32MB

Military

Processed *

Speed (ns)

Military

Temperature

Range Package

SELECTION GUIDE (continued)

* Military temperature range with MIL-STD-883 M5004

** SPECIAL PINOUT

N/A = Not available

REV 1.6 9 of 17

FT6164

Pkg #

# Pins

Symbol Min Max

A-0.225

b 0.014 0.026

b2 0.045 0.065

C 0.008 0.018

D-1.485

E 0.240 0.310

L 0.125 0.200

Q 0.015 0.070

S1 0.005 -

S2 0.005 -

28 (300 mil)

0.300 BSC

0.100 BSC

SIDE BRAZED DUAL IN-LINE PACKAGE (300 mils)

Pkg #

# Pins

Symbol Min Max

A-0.232

b 0.014 0.026

b2 0.045 0.065

C 0.008 0.018

D-1.490

E 0.500 0.610

L 0.125 0.200

Q 0.015 0.060

S1 0.005 -

S2 0.005 -

C5-1

28 (600 mil)

0.600 BSC

0.100 BSC

SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)

REV 1.6 10 of 17

FT6164

CERDIP DUAL IN-LINE P ACKAGE

Pkg #

# Pins

Symbol Min Max

A - 0.232

b 0.014 0.026

b2 0.045 0.065

C 0.008 0.018

D - 1.490

E 0.500 0.610

L 0.125 0.200

Q 0.015 0.060

S1 0.005 -

0° 15°

D5-1

28 (600 mil)

0.600 B SC

0.100 B SC

CERDIP DUAL IN-LINE P ACKAGE

Pkg #

# P ins

Symbol Min Max

A - 0.225

b 0.014 0.026

b2 0.045 0.065

C 0.008 0.018

D - 1.485

E 0.240 0.310

L 0.125 0.200

Q 0.015 0.060

S1 0.005 -

0° 15°

D5-2

28 (300 mil)

0.300 BSC

0.100 BSC

REV 1.6 11 of 17

FT6164

Pkg #

# Pins

Symbol Min Max

A 0.120 0.148

A1 0.078 -

b 0.014 0.020

C 0.007 0.011

D 0.700 0.730

E1 0.292 0.300

Q0.025-

28 (300 mil)

0.050 BSC

0.267 BSC

0.335 BSC

SOJ SMALL OUTLINE IC PACKAGE

Pkg #

# Pins

Symbol Min Max

A 0.060 0.090

b 0.015 0.022

c 0.004 0.009

D-0.730

E 0.330 0.380

k 0.005 0.018

L 0.250 0.370

Q 0.026 0.045

S-0.085

S1 0.005 -

0.050 BSC

CERPACK CERAMIC FLAT PACKAGE

REV 1.6 12 of 17

FT6164

Pkg #

# Pins

Symbol Min Max

A 0.060 0.075

A1 0.050 0.065

B1 0.022 0.028

D 0.442 0.458

D3 - 0.458

E 0.540 0.560

E3 - 0.558

L 0.045 0.055

L1 0.045 0.055

L2 0.075 0.095

0.300 BSC

0.150 BSC

0.020 REF

0.400 BSC

0.200 BSC

0.050 BSC

0.040 REF

RECTANGULAR LEADLESS CHIP CARRIER

Pkg #

# Pins

Symbol Min Max

A 0.060 0.075

A1 0.050 0.065

B1 0.022 0.028

D 0.342 0.358

D3 - 0.358

E 0.540 0.560

E3 - 0.558

L 0.045 0.055

L1 0.045 0.055

L2 0.075 0.095

0.020 REF

0.400 B SC

0.200 B SC

0.050 B SC

0.040 REF

0.200 B SC

0.100 B SC

REV 1.6 13 of 17

FT6164

Pkg #

# Pins

Symbol Min Max

A 0.090 0.200

A1 0.000 0.070

b 0.014 0.020

b2 0.015 0.065

C 0.008 0.012

D 1.380 1.480

E1 0.485 0.550

E 0.600 0.625

L 0.100 0.200

0° 15°

28 (600 mil)

0.100 BSC

0.600 TYP

PLASTIC DUAL IN-LINE PACKAGE (600 mils)

Pkg #

# Pins

Symbol Min Max

A-0.210

A1 -

b 0.014 0.023

b2 0.045 0.070

C 0.008 0.014

D 1.345 1.400

E1 0.270 0.300

E 0.300 0.380

eB - 0.430

L 0.115 0.150

0° 15°

0.100 BSC

28 (300 mil)

PLASTIC DUAL IN-LINE PACKAGE (300 mils)

REV 1.6 14 of 17

FT6164

Pkg #

# Pins

Symbol Min Max

A 0.060 0.075

A1 0.050 0.065

B1 0.022 0.028

D 0.442 0.458

D3 - 0.458

E 0.540 0.560

E3 - 0.558

L 0.045 0.055

L1 0.045 0.055

L2 0.075 0.095

0.300 BSC

0.150 BSC

0.020 REF

0.400 BSC

0.200 BSC

0.050 BSC

0.040 REF

RECTANGULAR LEADLESS CHIP CARRIER

Pkg #

# Pins

Symbol Min Max

A 0.060 0.075

A1 0.050 0.065

B1 0.022 0.028

D 0.342 0.358

D3 - 0.358

E 0.540 0.560

E3 - 0.558

L 0.045 0.055

L1 0.045 0.055

L2 0.075 0.095

0.020 REF

0.400 B SC

0.200 B SC

0.050 B SC

0.040 REF

0.200 B SC

0.100 B SC

REV 1.6 15 of 17

FT6164

Ashley Crt, Henley,

Marlborough, Wilts, SN8 3RH UK

Tel: +44(0)1264 731200

Fax:+44(0)1264 731444

E-mail

sales@forcetechnologies.co.uk

www.forcetechnologies.co.uk

Life Support Applications

Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies

product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products

for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such

improper use or sale.

Unless otherwise stated in this SCD/Data sheet , Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ

-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no

responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these

products, and makes no representation or warranties that these products are free f rom patent, copyright or mask work infringement, unless

otherwise specified.

REV 1.6 16 of 17

REVISIONS

DOCUMENT NUMBER: SRAM115

DOCUMENT TITLE: FT6164 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS

REV. ISSUE

DATE ORIG. OF

CHANGE DESCRIPTION OF CHANGE

OR 1997 M.S New Data Sheet

1.1 Oct-05 M.S Data sheet review

1.2 Jun-06 M.S Added 28-pin ceramic DIP

1.3 Aug-06 M.S Added Lead Free Designation

1.4 Aug-06 M.S Added "LS" - SPECIAL PIN-OUT

1.5 Aug-06 M.S Updated SOJ package information

1.6 Jun-07 M.S Corrected SOP package details

REV 1.6 17 of 17