AUGUST 2013
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3834/13
Features
◆◆
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◆64K x 16 advanced high-speed CMOS Static RAM
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◆Equal access and cycle times
— Commercial: 10/12/15/20ns
— Industrial: 10/12/15/20ns
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◆◆
◆One Chip Select plus one Output Enable pin
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◆Bidirectional data inputs and outputs directly
LVTTL-compatible
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◆Low power consumption via chip deselect
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◆Upper and Lower Byte Enable Pins
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◆Single 3.3V power supply
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◆Available in 44-pin Plastic SOJ, 44-pin TSOP, and
48-Ball Plastic FBGA packages
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using high-perfomance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V016 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V016 are LVTTL compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ,
a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A0–A15 Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
8
8
8
I/O8
I/O15
I/O7
I/O0
3834 drw 01
High
Byte
I/O
Buffer
3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) IDT71V016SA
2
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
123456
ABLE OE A
0
A
1
A
2
NC
B I/O
8
BHE A
3
A
4
CS I/O
0
C I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
DV
SS
I/O
11
NC A
7
I/O
3
V
DD
EV
DD
I/O
12
NC NC I/O
4
V
SS
F I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G I/O
15
NC A
12
A
13
WE I/O
7
HNC A
8
A
9
A
10
A
11
NC
3834 tbl 02a
Pin Configurations
SOJ/TSOP
Top View
Pin Description
Truth Table(1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O
7
NC
A
12
A
13
A
14
A
15
WE
I/O
6
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
I/O
1
I/O
0
CS
A
0
A
1
A
2
A
3
A
4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
NC
A
5
NC
SO44-1
SO44-2
3834 drw 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
CS OE WE BLE BHE I/O
0
-I/O
7
I/O
8
-I/O
15
Function
H X X X X High-Z High-Z Deselected – Standby
LLH L H DATA
OUT
High -Z Low Byte Read
L L H H L High-Z DATA
OUT
High Byte Read
LLH L L DATA
OUT
DATA
OUT
Word Read
LXL L L DATA
IN
DATA
IN
Word Write
LXL L H DATA
IN
High-Z Low By te Write
L X L H L High-Z DATA
IN
High Byte Write
L H H X X High-Z High-Z Outputs Disabled
L X X H H High-Z High-Z Outputs Disabled
3834 tbl 02
FBGA (BF48-1)
Top View
3
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Symbol Parameter
71V016SA10 71V016SA12 71V016SA15 71V016SA20
Unit
Com'l Ind'l Com'l Ind'l Com'l Ind'l Com'l Ind'l
I
CC
Dynamic Operating Current
CS ≤ V
LC
, Outp uts Ope n, V
DD
= Max., f = f
MAX
(3)
Max. 160 170 150 160 130 130 120 120 mA
Typ.(4) 65 -- 60 -- 55 -- 50 --
I
SB
Dynamic Standby Po we r Supply Current
CS ≥ V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
45 50 40 45 35 35 30 30 mA
I
SB1
Full Stand b y Po we r Sup pl y Current (static)
CS ≥ V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
10 10 10 10 10 10 10 10 mA
3834 tb l 08
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Recommended DC Operating
Conditions
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. For 71V016SA10 only.
2. For all speed grades except 71V016SA10.
3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are based on characterization data for H step only measured at 3.3V, 25°C and with equal read and write cycles.
Symbol Rating Value Unit
V
DD
Supply Voltag e Relative to V
SS
–0. 5 to + 4. 6 V
V
IN
, V
OUT
Te rminal Voltag e Relative to V
SS
–0.5 to V
DD
+0.5 V
T
BIAS
Temperature Under Bias –55 to +125
o
C
T
STG
Sto rage Te mp e rature –55 to +125
o
C
P
T
Po we r Di ss ip atio n 1.2 5 W
I
OUT
DC O u tp ut Curren t 50 m A
3834 tbl 03
Grade Temperature V
SS
V
DD
Commercial 0°C to +70°C 0V See Be low
Industrial -40°C to +85°C 0V See Below
3834 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
(1)
Supply Voltage 3.15 3.3 3.6 V
V
DD
(2)
Supply Voltage 3.0 3.3 3. 6 V
Vss Ground 0 0 0 V
V
IH
In put High Volt age 2. 0
____
V
DD
+0.3
(3)
V
V
IL
In put Low Volt age –0.3
(4)
____
0.8 V
3834 tbl 05
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inpu t C apacit ance V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
3834 tbl 06
Symbol Parameter Test Condition
IDT71V016SA
UnitMin. Max.
|I
LI
| I nput Le akage Current V
DD
= Max., V
IN
= V
SS
to V
DD
___
5µA
|I
LO
| O utput Leakage Current V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5µA
V
OL
O utput Lo w Volt age I
OL
= 8m A, V
DD
= M in.
___
0.4 V
V
OH
O utput H igh Volt age I
OH
= –4mA, V
DD
= M in. 2.4
___
V
3834 tbl 07
4
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load Figure 2. AC Test Load
(for t CLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
+1.5V
50Ω
I/O Z
0
=50Ω
3834 drw 03
30pF
3834 drw 04
320Ω
350Ω5pF*
DATA OUT
3.3V
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
Δt
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3834 drw 05
•
•
•
•
•
•
•
Input Pulse Lev els
Input Rise/Fall Tim es
Input Tim ing Ref erence Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3834 tbl 09
5
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
71V016SA10 71V016SA12 71V016SA15 71V016SA20
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Re ad Cyc le Ti me 10 ____ 12 ____ 15 ____ 20 ____ ns
t
AA
Address Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns
t
ACS
Chip Select Access Time ____ 10 ____ 12 ____ 15 ____ 20 ns
t
CLZ
(1)
Chip S el e c t Lo w to Outp ut in Lo w-Z 4 ____ 4____ 5____ 5____ ns
t
CHZ
(1)
Chip S el e c t Hi g h to Outp ut i n Hig h-Z ____ 5____ 6____ 6____ 8ns
t
OE
Outp ut Enab l e Lo w to Outp ut Val id ____ 5____ 6____ 7____ 8ns
t
OLZ
(1)
Outp ut Enab l e Lo w to Outp ut in Lo w-Z 0 ____ 0____ 0____ 0____ ns
t
OHZ
(1)
Outp ut E nab l e Hig h to Outp ut in Hi g h-Z ____ 5____ 6____ 6____ 8ns
t
OH
Outp ut Ho l d fro m A d d re ss Chang e 4 — 4 — 4 — 4 — ns
t
BE
Byte E nab le Lo w to Outp ut Vali d — 5 — 6 — 7 ____ 8ns
t
BLZ
(1)
Byte Enable Low to Outp ut in Lo w-Z 0 ____ 0____ 0____ 0____ ns
t
BHZ
(1)
Byte E nab le Hi g h to Outp ut in Hig h-Z ____ 5____ 6____ 6____ 8ns
WRITE CYCLE
t
WC
Write Cycle Time 10 ____ 12 ____ 15 ____ 20 ____ ns
t
AW
Address Valid to End of Write 7 ____ 8____ 10 ____ 12 ____ ns
t
CW
Chip S el e c t Lo w to End o f Wri te 7 ____ 8____ 10 ____ 12 ____ ns
t
BW
Byte Enable Low to End of Write 7 ____ 8____ 10 ____ 12 ____ ns
t
AS
Address Set-up Time 0 ____ 0____ 0____ 0____ ns
t
WR
Address Hold from End of Write 0 ____ 0____ 0____ 0____ ns
t
WP
Write P ulse Width 7 ____ 8____ 10 ____ 12 ____ ns
t
DW
Data Valid to End of Write 5 ____ 6____ 7____ 9____ ns
t
DH
Data Hol d Ti me 0 ____ 0____ 0____ 0____ ns
t
OW
(1)
Write E nab le Hi g h to Outp ut in Lo w-Z 3 ____ 3____ 3____ 3____ ns
t
WHZ
(1)
Write E nable Low to Outp ut in Hig h-Z ____ 5____ 6____ 6____ 8ns
3834 tb l 10
Timing Waveform of Read Cycle No. 1(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DATA
OUT
ADDRESS
3834 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
6
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Wavefor m of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
OE
CS
DATA
OUT
3834 drw 07
(3)
(3)
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
t
CHZ
t
OHZ
OUT
BHE,BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
t
OH
t
BHZ
(3)
(2)
ADDRESS
CS
DATA
IN
3834 drw 08
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
7
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
ADDRESS
CS
DATA
IN
3834 drw 09
DATA
IN
VALID
t
WC
t
AS (2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE,BLE
t
BW
t
WP
ADDRESS
CS
DATA
IN
3834 drw 10
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
8
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Ordering Information
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
9
IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges
CORPORATE HEADQUARTERS for SALES:
6024 Silver Creek Valley Road 800-345-7015 or
San Jose, CA 95138 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
sramhelp@idt.com
408-284-4532
01/07/00 Updated to new format
Pg. 1, 3, 5, 8 Added Industrial Temperature range offerings
Pg. 2 Numbered I/Os and address pins on FBGA Top View
Pg. 6 Revised footnotes on Write Cycle No. 1 diagram
Pg. 7 Revised footnotes on Write Cycle No. 2 and No. 3 diagrams
Pg. 9 Added Datasheet Document History
08/30/00 Pg. 3 Tighten ICC and ISB.
Pg. 5 Tighten tCLZ, tCHZ, tOHZ, tBHZ and tWHZ
08/22/01 Pg. 8 Removed footnote "available in 15ns and 20ns only"
06/20/02 Pg. 8 Added tape and reel field to ordering information
01/30/04 Pg. 8 Added "Restricted hazardous substance device" to ordering information.
09/27/06 Pg. 8 Corrected ordering information, changed position of I and G.
02/14/07 Pg.8 Added H step generation to data sheet ordering information.
06/26/07 Pg.3 Changed typical parameters for ICC, DC electrical characteristics table.
10/13/08 Pg.8 Removed "IDT" from orderable part number
10/11/11 Pg.1,8 Updated datasheet with removal of Obsolete HSA part number.
08/13/13 Pg.1,3,5,8 Added 10ns for Industrial Temperature range offerings.
